RTC_CNTL_FIB_SEL_REG (reference) in projects: hal_espressif-3.6.0

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Searched refs:RTC_CNTL_FIB_SEL_REG (Results 1 – 7 of 7) sorted by relevance

/hal_espressif-3.6.0/components/bootloader_support/src/esp32c3/
D	bootloader_soc.c	`12 REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_SUPER_WDT_RST); in bootloader_ana_super_wdt_reset_config() 23 REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_BOR_RST); in bootloader_ana_bod_reset_config() 34 REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_GLITCH_RST); in bootloader_ana_clock_glitch_reset_config()`
/hal_espressif-3.6.0/components/bootloader_support/src/esp32h2/
D	bootloader_soc.c	`12 REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_SUPER_WDT_RST); in bootloader_ana_super_wdt_reset_config() 23 REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_BOR_RST); in bootloader_ana_bod_reset_config() 34 REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_GLITCH_RST); in bootloader_ana_clock_glitch_reset_config()`
/hal_espressif-3.6.0/components/bootloader_support/src/esp32s3/
D	bootloader_soc.c	`12 REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_SUPER_WDT_RST); in bootloader_ana_super_wdt_reset_config() 23 REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_BOD_RST); in bootloader_ana_bod_reset_config() 34 REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_GLITCH_RST); in bootloader_ana_clock_glitch_reset_config()`
/hal_espressif-3.6.0/zephyr/esp32c3/src/boot/
D	bootloader_init.c	`165 REG_SET_FIELD(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_SEL, RTC_CNTL_FIB_SUPER_WDT_RST); in bootloader_glitch_reset_disable() 167 …REG_SET_FIELD(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_SEL, RTC_CNTL_FIB_SUPER_WDT_RST \| RTC_CNTL_FIB_BO… in bootloader_glitch_reset_disable()`
/hal_espressif-3.6.0/components/soc/esp32c3/include/soc/
D	rtc_cntl_reg.h	`2357 #define RTC_CNTL_FIB_SEL_REG (DR_REG_RTCCNTL_BASE + 0x010C) macro`
/hal_espressif-3.6.0/components/soc/esp32h2/include/soc/
D	rtc_cntl_reg.h	`2731 #define RTC_CNTL_FIB_SEL_REG (DR_REG_RTCCNTL_BASE + 0x0138) macro`
/hal_espressif-3.6.0/components/soc/esp32s3/include/soc/
D	rtc_cntl_reg.h	`3571 #define RTC_CNTL_FIB_SEL_REG (DR_REG_RTCCNTL_BASE + 0x148) macro`

TraceRecorderSource-2.7.6
TraceRecorderSource-3.4.0
Zephyr-Core-2.7.6
Zephyr-Core-3.4.0
Zephyr-Core-3.5.0
Zephyr-Core-3.6.0
Zephyr-Core-3.7.0
acpica-3.5.0
acpica-3.6.0
acpica-3.7.0
babblesim_base-3.4.0
babblesim_base-3.6.0-3.5.0
babblesim_base-3.7.0
babblesim_ext_2G4_channel_NtNcable-3.7.0-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_channel_multiatt-3.4.0
babblesim_ext_2G4_channel_multiatt-3.7.0-3.6.0-3.5.0
babblesim_ext_2G4_device_WLAN_actmod-3.7.0-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_device_burst_interferer-3.7.0-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_device_playback-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_device_playback-3.7.0
babblesim_ext_2G4_libPhyComv1-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_libPhyComv1-3.7.0
babblesim_ext_2G4_modem_BLE_simple-3.4.0
babblesim_ext_2G4_modem_BLE_simple-3.6.0-3.5.0
babblesim_ext_2G4_modem_BLE_simple-3.7.0
babblesim_ext_2G4_modem_magic-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_modem_magic-3.7.0
babblesim_ext_2G4_phy_v1-3.4.0
babblesim_ext_2G4_phy_v1-3.6.0-3.5.0
babblesim_ext_2G4_phy_v1-3.7.0
babblesim_ext_libCryptov1-3.7.0-3.6.0-3.5.0-3.4.0
bsim-3.4.0
bsim-3.6.0-3.5.0
bsim-3.7.0
canopennode-2.7.6
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chre-3.4.0
civetweb-2.7.6
cmsis-2.7.6
cmsis-3.4.0
cmsis-3.5.0
cmsis-3.7.0-3.6.0
cmsis-dsp-3.5.0
cmsis-dsp-3.7.0-3.6.0
cmsis-nn-3.6.0-3.5.0
cmsis-nn-3.7.0
edtt-2.7.6
edtt-3.6.0-3.5.0-3.4.0
edtt-3.7.0
fatfs-2.7.6
fatfs-3.7.0-3.6.0-3.5.0-3.4.0
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hal_nuvoton-2.7.6
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hal_quicklogic-3.7.0
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hal_telink-3.7.0
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hal_wurthelektronik-3.5.0-3.4.0
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