1 // Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 #ifndef _SOC_RTC_CNTL_REG_H_ 15 #define _SOC_RTC_CNTL_REG_H_ 16 17 /* The value that needs to be written to RTC_CNTL_WDT_WKEY to write-enable the wdt registers */ 18 #define RTC_CNTL_WDT_WKEY_VALUE 0x50D83AA1 19 20 /* Possible values for RTC_CNTL_WDT_CPU_RESET_LENGTH and RTC_CNTL_WDT_SYS_RESET_LENGTH */ 21 #define RTC_WDT_RESET_LENGTH_100_NS 0 22 #define RTC_WDT_RESET_LENGTH_200_NS 1 23 #define RTC_WDT_RESET_LENGTH_300_NS 2 24 #define RTC_WDT_RESET_LENGTH_400_NS 3 25 #define RTC_WDT_RESET_LENGTH_500_NS 4 26 #define RTC_WDT_RESET_LENGTH_800_NS 5 27 #define RTC_WDT_RESET_LENGTH_1600_NS 6 28 #define RTC_WDT_RESET_LENGTH_3200_NS 7 29 30 #include "soc.h" 31 #define RTC_CNTL_OPTIONS0_REG (DR_REG_RTCCNTL_BASE + 0x0) 32 /* RTC_CNTL_SW_SYS_RST : WO ;bitpos:[31] ;default: 1'd0 ; */ 33 /*description: SW system reset*/ 34 #define RTC_CNTL_SW_SYS_RST (BIT(31)) 35 #define RTC_CNTL_SW_SYS_RST_M (BIT(31)) 36 #define RTC_CNTL_SW_SYS_RST_V 0x1 37 #define RTC_CNTL_SW_SYS_RST_S 31 38 /* RTC_CNTL_DG_WRAP_FORCE_NORST : R/W ;bitpos:[30] ;default: 1'd0 ; */ 39 /*description: digital core force no reset in deep sleep*/ 40 #define RTC_CNTL_DG_WRAP_FORCE_NORST (BIT(30)) 41 #define RTC_CNTL_DG_WRAP_FORCE_NORST_M (BIT(30)) 42 #define RTC_CNTL_DG_WRAP_FORCE_NORST_V 0x1 43 #define RTC_CNTL_DG_WRAP_FORCE_NORST_S 30 44 /* RTC_CNTL_DG_WRAP_FORCE_RST : R/W ;bitpos:[29] ;default: 1'd0 ; */ 45 /*description: digital wrap force reset in deep sleep*/ 46 #define RTC_CNTL_DG_WRAP_FORCE_RST (BIT(29)) 47 #define RTC_CNTL_DG_WRAP_FORCE_RST_M (BIT(29)) 48 #define RTC_CNTL_DG_WRAP_FORCE_RST_V 0x1 49 #define RTC_CNTL_DG_WRAP_FORCE_RST_S 29 50 /* RTC_CNTL_ANALOG_FORCE_NOISO : R/W ;bitpos:[28] ;default: 1'd1 ; */ 51 /*description: */ 52 #define RTC_CNTL_ANALOG_FORCE_NOISO (BIT(28)) 53 #define RTC_CNTL_ANALOG_FORCE_NOISO_M (BIT(28)) 54 #define RTC_CNTL_ANALOG_FORCE_NOISO_V 0x1 55 #define RTC_CNTL_ANALOG_FORCE_NOISO_S 28 56 /* RTC_CNTL_PLL_FORCE_NOISO : R/W ;bitpos:[27] ;default: 1'd1 ; */ 57 /*description: */ 58 #define RTC_CNTL_PLL_FORCE_NOISO (BIT(27)) 59 #define RTC_CNTL_PLL_FORCE_NOISO_M (BIT(27)) 60 #define RTC_CNTL_PLL_FORCE_NOISO_V 0x1 61 #define RTC_CNTL_PLL_FORCE_NOISO_S 27 62 /* RTC_CNTL_XTL_FORCE_NOISO : R/W ;bitpos:[26] ;default: 1'd1 ; */ 63 /*description: */ 64 #define RTC_CNTL_XTL_FORCE_NOISO (BIT(26)) 65 #define RTC_CNTL_XTL_FORCE_NOISO_M (BIT(26)) 66 #define RTC_CNTL_XTL_FORCE_NOISO_V 0x1 67 #define RTC_CNTL_XTL_FORCE_NOISO_S 26 68 /* RTC_CNTL_ANALOG_FORCE_ISO : R/W ;bitpos:[25] ;default: 1'd0 ; */ 69 /*description: */ 70 #define RTC_CNTL_ANALOG_FORCE_ISO (BIT(25)) 71 #define RTC_CNTL_ANALOG_FORCE_ISO_M (BIT(25)) 72 #define RTC_CNTL_ANALOG_FORCE_ISO_V 0x1 73 #define RTC_CNTL_ANALOG_FORCE_ISO_S 25 74 /* RTC_CNTL_PLL_FORCE_ISO : R/W ;bitpos:[24] ;default: 1'd0 ; */ 75 /*description: */ 76 #define RTC_CNTL_PLL_FORCE_ISO (BIT(24)) 77 #define RTC_CNTL_PLL_FORCE_ISO_M (BIT(24)) 78 #define RTC_CNTL_PLL_FORCE_ISO_V 0x1 79 #define RTC_CNTL_PLL_FORCE_ISO_S 24 80 /* RTC_CNTL_XTL_FORCE_ISO : R/W ;bitpos:[23] ;default: 1'd0 ; */ 81 /*description: */ 82 #define RTC_CNTL_XTL_FORCE_ISO (BIT(23)) 83 #define RTC_CNTL_XTL_FORCE_ISO_M (BIT(23)) 84 #define RTC_CNTL_XTL_FORCE_ISO_V 0x1 85 #define RTC_CNTL_XTL_FORCE_ISO_S 23 86 /* RTC_CNTL_BIAS_CORE_FORCE_PU : R/W ;bitpos:[22] ;default: 1'd1 ; */ 87 /*description: BIAS_CORE force power up*/ 88 #define RTC_CNTL_BIAS_CORE_FORCE_PU (BIT(22)) 89 #define RTC_CNTL_BIAS_CORE_FORCE_PU_M (BIT(22)) 90 #define RTC_CNTL_BIAS_CORE_FORCE_PU_V 0x1 91 #define RTC_CNTL_BIAS_CORE_FORCE_PU_S 22 92 /* RTC_CNTL_BIAS_CORE_FORCE_PD : R/W ;bitpos:[21] ;default: 1'b0 ; */ 93 /*description: BIAS_CORE force power down*/ 94 #define RTC_CNTL_BIAS_CORE_FORCE_PD (BIT(21)) 95 #define RTC_CNTL_BIAS_CORE_FORCE_PD_M (BIT(21)) 96 #define RTC_CNTL_BIAS_CORE_FORCE_PD_V 0x1 97 #define RTC_CNTL_BIAS_CORE_FORCE_PD_S 21 98 /* RTC_CNTL_BIAS_CORE_FOLW_8M : R/W ;bitpos:[20] ;default: 1'd0 ; */ 99 /*description: BIAS_CORE follow CK8M*/ 100 #define RTC_CNTL_BIAS_CORE_FOLW_8M (BIT(20)) 101 #define RTC_CNTL_BIAS_CORE_FOLW_8M_M (BIT(20)) 102 #define RTC_CNTL_BIAS_CORE_FOLW_8M_V 0x1 103 #define RTC_CNTL_BIAS_CORE_FOLW_8M_S 20 104 /* RTC_CNTL_BIAS_I2C_FORCE_PU : R/W ;bitpos:[19] ;default: 1'd1 ; */ 105 /*description: BIAS_I2C force power up*/ 106 #define RTC_CNTL_BIAS_I2C_FORCE_PU (BIT(19)) 107 #define RTC_CNTL_BIAS_I2C_FORCE_PU_M (BIT(19)) 108 #define RTC_CNTL_BIAS_I2C_FORCE_PU_V 0x1 109 #define RTC_CNTL_BIAS_I2C_FORCE_PU_S 19 110 /* RTC_CNTL_BIAS_I2C_FORCE_PD : R/W ;bitpos:[18] ;default: 1'b0 ; */ 111 /*description: BIAS_I2C force power down*/ 112 #define RTC_CNTL_BIAS_I2C_FORCE_PD (BIT(18)) 113 #define RTC_CNTL_BIAS_I2C_FORCE_PD_M (BIT(18)) 114 #define RTC_CNTL_BIAS_I2C_FORCE_PD_V 0x1 115 #define RTC_CNTL_BIAS_I2C_FORCE_PD_S 18 116 /* RTC_CNTL_BIAS_I2C_FOLW_8M : R/W ;bitpos:[17] ;default: 1'd0 ; */ 117 /*description: BIAS_I2C follow CK8M*/ 118 #define RTC_CNTL_BIAS_I2C_FOLW_8M (BIT(17)) 119 #define RTC_CNTL_BIAS_I2C_FOLW_8M_M (BIT(17)) 120 #define RTC_CNTL_BIAS_I2C_FOLW_8M_V 0x1 121 #define RTC_CNTL_BIAS_I2C_FOLW_8M_S 17 122 /* RTC_CNTL_BIAS_FORCE_NOSLEEP : R/W ;bitpos:[16] ;default: 1'd1 ; */ 123 /*description: BIAS_SLEEP force no sleep*/ 124 #define RTC_CNTL_BIAS_FORCE_NOSLEEP (BIT(16)) 125 #define RTC_CNTL_BIAS_FORCE_NOSLEEP_M (BIT(16)) 126 #define RTC_CNTL_BIAS_FORCE_NOSLEEP_V 0x1 127 #define RTC_CNTL_BIAS_FORCE_NOSLEEP_S 16 128 /* RTC_CNTL_BIAS_FORCE_SLEEP : R/W ;bitpos:[15] ;default: 1'b0 ; */ 129 /*description: BIAS_SLEEP force sleep*/ 130 #define RTC_CNTL_BIAS_FORCE_SLEEP (BIT(15)) 131 #define RTC_CNTL_BIAS_FORCE_SLEEP_M (BIT(15)) 132 #define RTC_CNTL_BIAS_FORCE_SLEEP_V 0x1 133 #define RTC_CNTL_BIAS_FORCE_SLEEP_S 15 134 /* RTC_CNTL_BIAS_SLEEP_FOLW_8M : R/W ;bitpos:[14] ;default: 1'b0 ; */ 135 /*description: BIAS_SLEEP follow CK8M*/ 136 #define RTC_CNTL_BIAS_SLEEP_FOLW_8M (BIT(14)) 137 #define RTC_CNTL_BIAS_SLEEP_FOLW_8M_M (BIT(14)) 138 #define RTC_CNTL_BIAS_SLEEP_FOLW_8M_V 0x1 139 #define RTC_CNTL_BIAS_SLEEP_FOLW_8M_S 14 140 /* RTC_CNTL_XTL_FORCE_PU : R/W ;bitpos:[13] ;default: 1'd1 ; */ 141 /*description: crystall force power up*/ 142 #define RTC_CNTL_XTL_FORCE_PU (BIT(13)) 143 #define RTC_CNTL_XTL_FORCE_PU_M (BIT(13)) 144 #define RTC_CNTL_XTL_FORCE_PU_V 0x1 145 #define RTC_CNTL_XTL_FORCE_PU_S 13 146 /* RTC_CNTL_XTL_FORCE_PD : R/W ;bitpos:[12] ;default: 1'b0 ; */ 147 /*description: crystall force power down*/ 148 #define RTC_CNTL_XTL_FORCE_PD (BIT(12)) 149 #define RTC_CNTL_XTL_FORCE_PD_M (BIT(12)) 150 #define RTC_CNTL_XTL_FORCE_PD_V 0x1 151 #define RTC_CNTL_XTL_FORCE_PD_S 12 152 /* RTC_CNTL_BBPLL_FORCE_PU : R/W ;bitpos:[11] ;default: 1'd0 ; */ 153 /*description: BB_PLL force power up*/ 154 #define RTC_CNTL_BBPLL_FORCE_PU (BIT(11)) 155 #define RTC_CNTL_BBPLL_FORCE_PU_M (BIT(11)) 156 #define RTC_CNTL_BBPLL_FORCE_PU_V 0x1 157 #define RTC_CNTL_BBPLL_FORCE_PU_S 11 158 /* RTC_CNTL_BBPLL_FORCE_PD : R/W ;bitpos:[10] ;default: 1'b0 ; */ 159 /*description: BB_PLL force power down*/ 160 #define RTC_CNTL_BBPLL_FORCE_PD (BIT(10)) 161 #define RTC_CNTL_BBPLL_FORCE_PD_M (BIT(10)) 162 #define RTC_CNTL_BBPLL_FORCE_PD_V 0x1 163 #define RTC_CNTL_BBPLL_FORCE_PD_S 10 164 /* RTC_CNTL_BBPLL_I2C_FORCE_PU : R/W ;bitpos:[9] ;default: 1'd0 ; */ 165 /*description: BB_PLL_I2C force power up*/ 166 #define RTC_CNTL_BBPLL_I2C_FORCE_PU (BIT(9)) 167 #define RTC_CNTL_BBPLL_I2C_FORCE_PU_M (BIT(9)) 168 #define RTC_CNTL_BBPLL_I2C_FORCE_PU_V 0x1 169 #define RTC_CNTL_BBPLL_I2C_FORCE_PU_S 9 170 /* RTC_CNTL_BBPLL_I2C_FORCE_PD : R/W ;bitpos:[8] ;default: 1'b0 ; */ 171 /*description: BB_PLL _I2C force power down*/ 172 #define RTC_CNTL_BBPLL_I2C_FORCE_PD (BIT(8)) 173 #define RTC_CNTL_BBPLL_I2C_FORCE_PD_M (BIT(8)) 174 #define RTC_CNTL_BBPLL_I2C_FORCE_PD_V 0x1 175 #define RTC_CNTL_BBPLL_I2C_FORCE_PD_S 8 176 /* RTC_CNTL_BB_I2C_FORCE_PU : R/W ;bitpos:[7] ;default: 1'd0 ; */ 177 /*description: BB_I2C force power up*/ 178 #define RTC_CNTL_BB_I2C_FORCE_PU (BIT(7)) 179 #define RTC_CNTL_BB_I2C_FORCE_PU_M (BIT(7)) 180 #define RTC_CNTL_BB_I2C_FORCE_PU_V 0x1 181 #define RTC_CNTL_BB_I2C_FORCE_PU_S 7 182 /* RTC_CNTL_BB_I2C_FORCE_PD : R/W ;bitpos:[6] ;default: 1'b0 ; */ 183 /*description: BB_I2C force power down*/ 184 #define RTC_CNTL_BB_I2C_FORCE_PD (BIT(6)) 185 #define RTC_CNTL_BB_I2C_FORCE_PD_M (BIT(6)) 186 #define RTC_CNTL_BB_I2C_FORCE_PD_V 0x1 187 #define RTC_CNTL_BB_I2C_FORCE_PD_S 6 188 /* RTC_CNTL_SW_PROCPU_RST : WO ;bitpos:[5] ;default: 1'b0 ; */ 189 /*description: PRO CPU SW reset*/ 190 #define RTC_CNTL_SW_PROCPU_RST (BIT(5)) 191 #define RTC_CNTL_SW_PROCPU_RST_M (BIT(5)) 192 #define RTC_CNTL_SW_PROCPU_RST_V 0x1 193 #define RTC_CNTL_SW_PROCPU_RST_S 5 194 /* RTC_CNTL_SW_APPCPU_RST : WO ;bitpos:[4] ;default: 1'b0 ; */ 195 /*description: APP CPU SW reset*/ 196 #define RTC_CNTL_SW_APPCPU_RST (BIT(4)) 197 #define RTC_CNTL_SW_APPCPU_RST_M (BIT(4)) 198 #define RTC_CNTL_SW_APPCPU_RST_V 0x1 199 #define RTC_CNTL_SW_APPCPU_RST_S 4 200 /* RTC_CNTL_SW_STALL_PROCPU_C0 : R/W ;bitpos:[3:2] ;default: 2'b0 ; */ 201 /*description: {reg_sw_stall_procpu_c1[5:0] reg_sw_stall_procpu_c0[1:0]} == 202 0x86 will stall PRO CPU*/ 203 #define RTC_CNTL_SW_STALL_PROCPU_C0 0x00000003 204 #define RTC_CNTL_SW_STALL_PROCPU_C0_M ((RTC_CNTL_SW_STALL_PROCPU_C0_V)<<(RTC_CNTL_SW_STALL_PROCPU_C0_S)) 205 #define RTC_CNTL_SW_STALL_PROCPU_C0_V 0x3 206 #define RTC_CNTL_SW_STALL_PROCPU_C0_S 2 207 /* RTC_CNTL_SW_STALL_APPCPU_C0 : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ 208 /*description: {reg_sw_stall_appcpu_c1[5:0] reg_sw_stall_appcpu_c0[1:0]} == 209 0x86 will stall APP CPU*/ 210 #define RTC_CNTL_SW_STALL_APPCPU_C0 0x00000003 211 #define RTC_CNTL_SW_STALL_APPCPU_C0_M ((RTC_CNTL_SW_STALL_APPCPU_C0_V)<<(RTC_CNTL_SW_STALL_APPCPU_C0_S)) 212 #define RTC_CNTL_SW_STALL_APPCPU_C0_V 0x3 213 #define RTC_CNTL_SW_STALL_APPCPU_C0_S 0 214 215 #define RTC_CNTL_SLP_TIMER0_REG (DR_REG_RTCCNTL_BASE + 0x4) 216 /* RTC_CNTL_SLP_VAL_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 217 /*description: RTC sleep timer low 32 bits*/ 218 #define RTC_CNTL_SLP_VAL_LO 0xFFFFFFFF 219 #define RTC_CNTL_SLP_VAL_LO_M ((RTC_CNTL_SLP_VAL_LO_V)<<(RTC_CNTL_SLP_VAL_LO_S)) 220 #define RTC_CNTL_SLP_VAL_LO_V 0xFFFFFFFF 221 #define RTC_CNTL_SLP_VAL_LO_S 0 222 223 #define RTC_CNTL_SLP_TIMER1_REG (DR_REG_RTCCNTL_BASE + 0x8) 224 /* RTC_CNTL_MAIN_TIMER_ALARM_EN : R/W ;bitpos:[16] ;default: 1'h0 ; */ 225 /*description: timer alarm enable bit*/ 226 #define RTC_CNTL_MAIN_TIMER_ALARM_EN (BIT(16)) 227 #define RTC_CNTL_MAIN_TIMER_ALARM_EN_M (BIT(16)) 228 #define RTC_CNTL_MAIN_TIMER_ALARM_EN_V 0x1 229 #define RTC_CNTL_MAIN_TIMER_ALARM_EN_S 16 230 /* RTC_CNTL_SLP_VAL_HI : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ 231 /*description: RTC sleep timer high 16 bits*/ 232 #define RTC_CNTL_SLP_VAL_HI 0x0000FFFF 233 #define RTC_CNTL_SLP_VAL_HI_M ((RTC_CNTL_SLP_VAL_HI_V)<<(RTC_CNTL_SLP_VAL_HI_S)) 234 #define RTC_CNTL_SLP_VAL_HI_V 0xFFFF 235 #define RTC_CNTL_SLP_VAL_HI_S 0 236 237 #define RTC_CNTL_TIME_UPDATE_REG (DR_REG_RTCCNTL_BASE + 0xc) 238 /* RTC_CNTL_TIME_UPDATE : WO ;bitpos:[31] ;default: 1'h0 ; */ 239 /*description: Set 1: to update register with RTC timer*/ 240 #define RTC_CNTL_TIME_UPDATE (BIT(31)) 241 #define RTC_CNTL_TIME_UPDATE_M (BIT(31)) 242 #define RTC_CNTL_TIME_UPDATE_V 0x1 243 #define RTC_CNTL_TIME_UPDATE_S 31 244 /* RTC_CNTL_TIME_VALID : RO ;bitpos:[30] ;default: 1'b0 ; */ 245 /*description: To indicate the register is updated*/ 246 #define RTC_CNTL_TIME_VALID (BIT(30)) 247 #define RTC_CNTL_TIME_VALID_M (BIT(30)) 248 #define RTC_CNTL_TIME_VALID_V 0x1 249 #define RTC_CNTL_TIME_VALID_S 30 250 251 #define RTC_CNTL_TIME0_REG (DR_REG_RTCCNTL_BASE + 0x10) 252 /* RTC_CNTL_TIME_LO : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 253 /*description: RTC timer low 32 bits*/ 254 #define RTC_CNTL_TIME_LO 0xFFFFFFFF 255 #define RTC_CNTL_TIME_LO_M ((RTC_CNTL_TIME_LO_V)<<(RTC_CNTL_TIME_LO_S)) 256 #define RTC_CNTL_TIME_LO_V 0xFFFFFFFF 257 #define RTC_CNTL_TIME_LO_S 0 258 259 #define RTC_CNTL_TIME1_REG (DR_REG_RTCCNTL_BASE + 0x14) 260 /* RTC_CNTL_TIME_HI : RO ;bitpos:[15:0] ;default: 16'h0 ; */ 261 /*description: RTC timer high 16 bits*/ 262 #define RTC_CNTL_TIME_HI 0x0000FFFF 263 #define RTC_CNTL_TIME_HI_M ((RTC_CNTL_TIME_HI_V)<<(RTC_CNTL_TIME_HI_S)) 264 #define RTC_CNTL_TIME_HI_V 0xFFFF 265 #define RTC_CNTL_TIME_HI_S 0 266 267 #define RTC_CNTL_STATE0_REG (DR_REG_RTCCNTL_BASE + 0x18) 268 /* RTC_CNTL_SLEEP_EN : R/W ;bitpos:[31] ;default: 1'd0 ; */ 269 /*description: sleep enable bit*/ 270 #define RTC_CNTL_SLEEP_EN (BIT(31)) 271 #define RTC_CNTL_SLEEP_EN_M (BIT(31)) 272 #define RTC_CNTL_SLEEP_EN_V 0x1 273 #define RTC_CNTL_SLEEP_EN_S 31 274 /* RTC_CNTL_SLP_REJECT : R/W ;bitpos:[30] ;default: 1'd0 ; */ 275 /*description: sleep reject bit*/ 276 #define RTC_CNTL_SLP_REJECT (BIT(30)) 277 #define RTC_CNTL_SLP_REJECT_M (BIT(30)) 278 #define RTC_CNTL_SLP_REJECT_V 0x1 279 #define RTC_CNTL_SLP_REJECT_S 30 280 /* RTC_CNTL_SLP_WAKEUP : R/W ;bitpos:[29] ;default: 1'd0 ; */ 281 /*description: sleep wakeup bit*/ 282 #define RTC_CNTL_SLP_WAKEUP (BIT(29)) 283 #define RTC_CNTL_SLP_WAKEUP_M (BIT(29)) 284 #define RTC_CNTL_SLP_WAKEUP_V 0x1 285 #define RTC_CNTL_SLP_WAKEUP_S 29 286 /* RTC_CNTL_SDIO_ACTIVE_IND : RO ;bitpos:[28] ;default: 1'd0 ; */ 287 /*description: SDIO active indication*/ 288 #define RTC_CNTL_SDIO_ACTIVE_IND (BIT(28)) 289 #define RTC_CNTL_SDIO_ACTIVE_IND_M (BIT(28)) 290 #define RTC_CNTL_SDIO_ACTIVE_IND_V 0x1 291 #define RTC_CNTL_SDIO_ACTIVE_IND_S 28 292 /* RTC_CNTL_ULP_CP_SLP_TIMER_EN : R/W ;bitpos:[24] ;default: 1'd0 ; */ 293 /*description: ULP-coprocessor timer enable bit*/ 294 #define RTC_CNTL_ULP_CP_SLP_TIMER_EN (BIT(24)) 295 #define RTC_CNTL_ULP_CP_SLP_TIMER_EN_M (BIT(24)) 296 #define RTC_CNTL_ULP_CP_SLP_TIMER_EN_V 0x1 297 #define RTC_CNTL_ULP_CP_SLP_TIMER_EN_S 24 298 /* RTC_CNTL_TOUCH_SLP_TIMER_EN : R/W ;bitpos:[23] ;default: 1'd0 ; */ 299 /*description: touch timer enable bit*/ 300 #define RTC_CNTL_TOUCH_SLP_TIMER_EN (BIT(23)) 301 #define RTC_CNTL_TOUCH_SLP_TIMER_EN_M (BIT(23)) 302 #define RTC_CNTL_TOUCH_SLP_TIMER_EN_V 0x1 303 #define RTC_CNTL_TOUCH_SLP_TIMER_EN_S 23 304 /* RTC_CNTL_APB2RTC_BRIDGE_SEL : R/W ;bitpos:[22] ;default: 1'd0 ; */ 305 /*description: 1: APB to RTC using bridge 0: APB to RTC using sync*/ 306 #define RTC_CNTL_APB2RTC_BRIDGE_SEL (BIT(22)) 307 #define RTC_CNTL_APB2RTC_BRIDGE_SEL_M (BIT(22)) 308 #define RTC_CNTL_APB2RTC_BRIDGE_SEL_V 0x1 309 #define RTC_CNTL_APB2RTC_BRIDGE_SEL_S 22 310 /* RTC_CNTL_ULP_CP_WAKEUP_FORCE_EN : R/W ;bitpos:[21] ;default: 1'd1 ; */ 311 /*description: ULP-coprocessor force wake up*/ 312 #define RTC_CNTL_ULP_CP_WAKEUP_FORCE_EN (BIT(21)) 313 #define RTC_CNTL_ULP_CP_WAKEUP_FORCE_EN_M (BIT(21)) 314 #define RTC_CNTL_ULP_CP_WAKEUP_FORCE_EN_V 0x1 315 #define RTC_CNTL_ULP_CP_WAKEUP_FORCE_EN_S 21 316 /* RTC_CNTL_TOUCH_WAKEUP_FORCE_EN : R/W ;bitpos:[20] ;default: 1'd1 ; */ 317 /*description: touch controller force wake up*/ 318 #define RTC_CNTL_TOUCH_WAKEUP_FORCE_EN (BIT(20)) 319 #define RTC_CNTL_TOUCH_WAKEUP_FORCE_EN_M (BIT(20)) 320 #define RTC_CNTL_TOUCH_WAKEUP_FORCE_EN_V 0x1 321 #define RTC_CNTL_TOUCH_WAKEUP_FORCE_EN_S 20 322 323 #define RTC_CNTL_TIMER1_REG (DR_REG_RTCCNTL_BASE + 0x1c) 324 /* RTC_CNTL_PLL_BUF_WAIT : R/W ;bitpos:[31:24] ;default: 8'd40 ; */ 325 /*description: PLL wait cycles in slow_clk_rtc*/ 326 #define RTC_CNTL_PLL_BUF_WAIT 0x000000FF 327 #define RTC_CNTL_PLL_BUF_WAIT_M ((RTC_CNTL_PLL_BUF_WAIT_V)<<(RTC_CNTL_PLL_BUF_WAIT_S)) 328 #define RTC_CNTL_PLL_BUF_WAIT_V 0xFF 329 #define RTC_CNTL_PLL_BUF_WAIT_S 24 330 #define RTC_CNTL_PLL_BUF_WAIT_DEFAULT 20 331 /* RTC_CNTL_XTL_BUF_WAIT : R/W ;bitpos:[23:14] ;default: 10'd80 ; */ 332 /*description: XTAL wait cycles in slow_clk_rtc*/ 333 #define RTC_CNTL_XTL_BUF_WAIT 0x000003FF 334 #define RTC_CNTL_XTL_BUF_WAIT_M ((RTC_CNTL_XTL_BUF_WAIT_V)<<(RTC_CNTL_XTL_BUF_WAIT_S)) 335 #define RTC_CNTL_XTL_BUF_WAIT_V 0x3FF 336 #define RTC_CNTL_XTL_BUF_WAIT_S 14 337 #define RTC_CNTL_XTL_BUF_WAIT_DEFAULT 20 338 /* RTC_CNTL_CK8M_WAIT : R/W ;bitpos:[13:6] ;default: 8'h10 ; */ 339 /*description: CK8M wait cycles in slow_clk_rtc*/ 340 #define RTC_CNTL_CK8M_WAIT 0x000000FF 341 #define RTC_CNTL_CK8M_WAIT_M ((RTC_CNTL_CK8M_WAIT_V)<<(RTC_CNTL_CK8M_WAIT_S)) 342 #define RTC_CNTL_CK8M_WAIT_V 0xFF 343 #define RTC_CNTL_CK8M_WAIT_S 6 344 #define RTC_CNTL_CK8M_WAIT_DEFAULT 20 345 /* RTC_CNTL_CPU_STALL_WAIT : R/W ;bitpos:[5:1] ;default: 5'd1 ; */ 346 /*description: CPU stall wait cycles in fast_clk_rtc*/ 347 #define RTC_CNTL_CPU_STALL_WAIT 0x0000001F 348 #define RTC_CNTL_CPU_STALL_WAIT_M ((RTC_CNTL_CPU_STALL_WAIT_V)<<(RTC_CNTL_CPU_STALL_WAIT_S)) 349 #define RTC_CNTL_CPU_STALL_WAIT_V 0x1F 350 #define RTC_CNTL_CPU_STALL_WAIT_S 1 351 /* RTC_CNTL_CPU_STALL_EN : R/W ;bitpos:[0] ;default: 1'd1 ; */ 352 /*description: CPU stall enable bit*/ 353 #define RTC_CNTL_CPU_STALL_EN (BIT(0)) 354 #define RTC_CNTL_CPU_STALL_EN_M (BIT(0)) 355 #define RTC_CNTL_CPU_STALL_EN_V 0x1 356 #define RTC_CNTL_CPU_STALL_EN_S 0 357 358 #define RTC_CNTL_TIMER2_REG (DR_REG_RTCCNTL_BASE + 0x20) 359 /* RTC_CNTL_MIN_TIME_CK8M_OFF : R/W ;bitpos:[31:24] ;default: 8'h1 ; */ 360 /*description: minimal cycles in slow_clk_rtc for CK8M in power down state*/ 361 #define RTC_CNTL_MIN_TIME_CK8M_OFF 0x000000FF 362 #define RTC_CNTL_MIN_TIME_CK8M_OFF_M ((RTC_CNTL_MIN_TIME_CK8M_OFF_V)<<(RTC_CNTL_MIN_TIME_CK8M_OFF_S)) 363 #define RTC_CNTL_MIN_TIME_CK8M_OFF_V 0xFF 364 #define RTC_CNTL_MIN_TIME_CK8M_OFF_S 24 365 /* RTC_CNTL_ULPCP_TOUCH_START_WAIT : R/W ;bitpos:[23:15] ;default: 9'h10 ; */ 366 /*description: wait cycles in slow_clk_rtc before ULP-coprocessor / touch controller 367 start to work*/ 368 #define RTC_CNTL_ULPCP_TOUCH_START_WAIT 0x000001FF 369 #define RTC_CNTL_ULPCP_TOUCH_START_WAIT_M ((RTC_CNTL_ULPCP_TOUCH_START_WAIT_V)<<(RTC_CNTL_ULPCP_TOUCH_START_WAIT_S)) 370 #define RTC_CNTL_ULPCP_TOUCH_START_WAIT_V 0x1FF 371 #define RTC_CNTL_ULPCP_TOUCH_START_WAIT_S 15 372 373 #define RTC_CNTL_TIMER3_REG (DR_REG_RTCCNTL_BASE + 0x24) 374 /* RTC_CNTL_ROM_RAM_POWERUP_TIMER : R/W ;bitpos:[31:25] ;default: 7'd10 ; */ 375 /*description: */ 376 #define RTC_CNTL_ROM_RAM_POWERUP_TIMER 0x0000007F 377 #define RTC_CNTL_ROM_RAM_POWERUP_TIMER_M ((RTC_CNTL_ROM_RAM_POWERUP_TIMER_V)<<(RTC_CNTL_ROM_RAM_POWERUP_TIMER_S)) 378 #define RTC_CNTL_ROM_RAM_POWERUP_TIMER_V 0x7F 379 #define RTC_CNTL_ROM_RAM_POWERUP_TIMER_S 25 380 /* RTC_CNTL_ROM_RAM_WAIT_TIMER : R/W ;bitpos:[24:16] ;default: 9'h16 ; */ 381 /*description: */ 382 #define RTC_CNTL_ROM_RAM_WAIT_TIMER 0x000001FF 383 #define RTC_CNTL_ROM_RAM_WAIT_TIMER_M ((RTC_CNTL_ROM_RAM_WAIT_TIMER_V)<<(RTC_CNTL_ROM_RAM_WAIT_TIMER_S)) 384 #define RTC_CNTL_ROM_RAM_WAIT_TIMER_V 0x1FF 385 #define RTC_CNTL_ROM_RAM_WAIT_TIMER_S 16 386 /* RTC_CNTL_WIFI_POWERUP_TIMER : R/W ;bitpos:[15:9] ;default: 7'h5 ; */ 387 /*description: */ 388 #define RTC_CNTL_WIFI_POWERUP_TIMER 0x0000007F 389 #define RTC_CNTL_WIFI_POWERUP_TIMER_M ((RTC_CNTL_WIFI_POWERUP_TIMER_V)<<(RTC_CNTL_WIFI_POWERUP_TIMER_S)) 390 #define RTC_CNTL_WIFI_POWERUP_TIMER_V 0x7F 391 #define RTC_CNTL_WIFI_POWERUP_TIMER_S 9 392 /* RTC_CNTL_WIFI_WAIT_TIMER : R/W ;bitpos:[8:0] ;default: 9'h8 ; */ 393 /*description: */ 394 #define RTC_CNTL_WIFI_WAIT_TIMER 0x000001FF 395 #define RTC_CNTL_WIFI_WAIT_TIMER_M ((RTC_CNTL_WIFI_WAIT_TIMER_V)<<(RTC_CNTL_WIFI_WAIT_TIMER_S)) 396 #define RTC_CNTL_WIFI_WAIT_TIMER_V 0x1FF 397 #define RTC_CNTL_WIFI_WAIT_TIMER_S 0 398 399 #define RTC_CNTL_TIMER4_REG (DR_REG_RTCCNTL_BASE + 0x28) 400 /* RTC_CNTL_DG_WRAP_POWERUP_TIMER : R/W ;bitpos:[31:25] ;default: 7'h8 ; */ 401 /*description: */ 402 #define RTC_CNTL_DG_WRAP_POWERUP_TIMER 0x0000007F 403 #define RTC_CNTL_DG_WRAP_POWERUP_TIMER_M ((RTC_CNTL_DG_WRAP_POWERUP_TIMER_V)<<(RTC_CNTL_DG_WRAP_POWERUP_TIMER_S)) 404 #define RTC_CNTL_DG_WRAP_POWERUP_TIMER_V 0x7F 405 #define RTC_CNTL_DG_WRAP_POWERUP_TIMER_S 25 406 /* RTC_CNTL_DG_WRAP_WAIT_TIMER : R/W ;bitpos:[24:16] ;default: 9'h20 ; */ 407 /*description: */ 408 #define RTC_CNTL_DG_WRAP_WAIT_TIMER 0x000001FF 409 #define RTC_CNTL_DG_WRAP_WAIT_TIMER_M ((RTC_CNTL_DG_WRAP_WAIT_TIMER_V)<<(RTC_CNTL_DG_WRAP_WAIT_TIMER_S)) 410 #define RTC_CNTL_DG_WRAP_WAIT_TIMER_V 0x1FF 411 #define RTC_CNTL_DG_WRAP_WAIT_TIMER_S 16 412 /* RTC_CNTL_POWERUP_TIMER : R/W ;bitpos:[15:9] ;default: 7'h5 ; */ 413 /*description: */ 414 #define RTC_CNTL_POWERUP_TIMER 0x0000007F 415 #define RTC_CNTL_POWERUP_TIMER_M ((RTC_CNTL_POWERUP_TIMER_V)<<(RTC_CNTL_POWERUP_TIMER_S)) 416 #define RTC_CNTL_POWERUP_TIMER_V 0x7F 417 #define RTC_CNTL_POWERUP_TIMER_S 9 418 /* RTC_CNTL_WAIT_TIMER : R/W ;bitpos:[8:0] ;default: 9'h8 ; */ 419 /*description: */ 420 #define RTC_CNTL_WAIT_TIMER 0x000001FF 421 #define RTC_CNTL_WAIT_TIMER_M ((RTC_CNTL_WAIT_TIMER_V)<<(RTC_CNTL_WAIT_TIMER_S)) 422 #define RTC_CNTL_WAIT_TIMER_V 0x1FF 423 #define RTC_CNTL_WAIT_TIMER_S 0 424 425 #define RTC_CNTL_TIMER5_REG (DR_REG_RTCCNTL_BASE + 0x2c) 426 /* RTC_CNTL_RTCMEM_POWERUP_TIMER : R/W ;bitpos:[31:25] ;default: 7'h9 ; */ 427 /*description: */ 428 #define RTC_CNTL_RTCMEM_POWERUP_TIMER 0x0000007F 429 #define RTC_CNTL_RTCMEM_POWERUP_TIMER_M ((RTC_CNTL_RTCMEM_POWERUP_TIMER_V)<<(RTC_CNTL_RTCMEM_POWERUP_TIMER_S)) 430 #define RTC_CNTL_RTCMEM_POWERUP_TIMER_V 0x7F 431 #define RTC_CNTL_RTCMEM_POWERUP_TIMER_S 25 432 /* RTC_CNTL_RTCMEM_WAIT_TIMER : R/W ;bitpos:[24:16] ;default: 9'h14 ; */ 433 /*description: */ 434 #define RTC_CNTL_RTCMEM_WAIT_TIMER 0x000001FF 435 #define RTC_CNTL_RTCMEM_WAIT_TIMER_M ((RTC_CNTL_RTCMEM_WAIT_TIMER_V)<<(RTC_CNTL_RTCMEM_WAIT_TIMER_S)) 436 #define RTC_CNTL_RTCMEM_WAIT_TIMER_V 0x1FF 437 #define RTC_CNTL_RTCMEM_WAIT_TIMER_S 16 438 /* RTC_CNTL_MIN_SLP_VAL : R/W ;bitpos:[15:8] ;default: 8'h80 ; */ 439 /*description: minimal sleep cycles in slow_clk_rtc*/ 440 #define RTC_CNTL_MIN_SLP_VAL 0x000000FF 441 #define RTC_CNTL_MIN_SLP_VAL_M ((RTC_CNTL_MIN_SLP_VAL_V)<<(RTC_CNTL_MIN_SLP_VAL_S)) 442 #define RTC_CNTL_MIN_SLP_VAL_V 0xFF 443 #define RTC_CNTL_MIN_SLP_VAL_S 8 444 #define RTC_CNTL_MIN_SLP_VAL_MIN 2 445 /* RTC_CNTL_ULP_CP_SUBTIMER_PREDIV : R/W ;bitpos:[7:0] ;default: 8'd1 ; */ 446 /*description: */ 447 #define RTC_CNTL_ULP_CP_SUBTIMER_PREDIV 0x000000FF 448 #define RTC_CNTL_ULP_CP_SUBTIMER_PREDIV_M ((RTC_CNTL_ULP_CP_SUBTIMER_PREDIV_V)<<(RTC_CNTL_ULP_CP_SUBTIMER_PREDIV_S)) 449 #define RTC_CNTL_ULP_CP_SUBTIMER_PREDIV_V 0xFF 450 #define RTC_CNTL_ULP_CP_SUBTIMER_PREDIV_S 0 451 452 #define RTC_CNTL_ANA_CONF_REG (DR_REG_RTCCNTL_BASE + 0x30) 453 /* RTC_CNTL_PLL_I2C_PU : R/W ;bitpos:[31] ;default: 1'd0 ; */ 454 /*description: 1: PLL_I2C power up otherwise power down*/ 455 #define RTC_CNTL_PLL_I2C_PU (BIT(31)) 456 #define RTC_CNTL_PLL_I2C_PU_M (BIT(31)) 457 #define RTC_CNTL_PLL_I2C_PU_V 0x1 458 #define RTC_CNTL_PLL_I2C_PU_S 31 459 /* RTC_CNTL_CKGEN_I2C_PU : R/W ;bitpos:[30] ;default: 1'd0 ; */ 460 /*description: 1: CKGEN_I2C power up otherwise power down*/ 461 #define RTC_CNTL_CKGEN_I2C_PU (BIT(30)) 462 #define RTC_CNTL_CKGEN_I2C_PU_M (BIT(30)) 463 #define RTC_CNTL_CKGEN_I2C_PU_V 0x1 464 #define RTC_CNTL_CKGEN_I2C_PU_S 30 465 /* RTC_CNTL_RFRX_PBUS_PU : R/W ;bitpos:[28] ;default: 1'd0 ; */ 466 /*description: 1: RFRX_PBUS power up otherwise power down*/ 467 #define RTC_CNTL_RFRX_PBUS_PU (BIT(28)) 468 #define RTC_CNTL_RFRX_PBUS_PU_M (BIT(28)) 469 #define RTC_CNTL_RFRX_PBUS_PU_V 0x1 470 #define RTC_CNTL_RFRX_PBUS_PU_S 28 471 /* RTC_CNTL_TXRF_I2C_PU : R/W ;bitpos:[27] ;default: 1'd0 ; */ 472 /*description: 1: TXRF_I2C power up otherwise power down*/ 473 #define RTC_CNTL_TXRF_I2C_PU (BIT(27)) 474 #define RTC_CNTL_TXRF_I2C_PU_M (BIT(27)) 475 #define RTC_CNTL_TXRF_I2C_PU_V 0x1 476 #define RTC_CNTL_TXRF_I2C_PU_S 27 477 /* RTC_CNTL_PVTMON_PU : R/W ;bitpos:[26] ;default: 1'b0 ; */ 478 /*description: 1: PVTMON power up otherwise power down*/ 479 #define RTC_CNTL_PVTMON_PU (BIT(26)) 480 #define RTC_CNTL_PVTMON_PU_M (BIT(26)) 481 #define RTC_CNTL_PVTMON_PU_V 0x1 482 #define RTC_CNTL_PVTMON_PU_S 26 483 /* RTC_CNTL_BBPLL_CAL_SLP_START : R/W ;bitpos:[25] ;default: 1'b0 ; */ 484 /*description: start BBPLL calibration during sleep*/ 485 #define RTC_CNTL_BBPLL_CAL_SLP_START (BIT(25)) 486 #define RTC_CNTL_BBPLL_CAL_SLP_START_M (BIT(25)) 487 #define RTC_CNTL_BBPLL_CAL_SLP_START_V 0x1 488 #define RTC_CNTL_BBPLL_CAL_SLP_START_S 25 489 /* RTC_CNTL_PLLA_FORCE_PU : R/W ;bitpos:[24] ;default: 1'b0 ; */ 490 /*description: PLLA force power up*/ 491 #define RTC_CNTL_PLLA_FORCE_PU (BIT(24)) 492 #define RTC_CNTL_PLLA_FORCE_PU_M (BIT(24)) 493 #define RTC_CNTL_PLLA_FORCE_PU_V 0x1 494 #define RTC_CNTL_PLLA_FORCE_PU_S 24 495 /* RTC_CNTL_PLLA_FORCE_PD : R/W ;bitpos:[23] ;default: 1'b1 ; */ 496 /*description: PLLA force power down*/ 497 #define RTC_CNTL_PLLA_FORCE_PD (BIT(23)) 498 #define RTC_CNTL_PLLA_FORCE_PD_M (BIT(23)) 499 #define RTC_CNTL_PLLA_FORCE_PD_V 0x1 500 #define RTC_CNTL_PLLA_FORCE_PD_S 23 501 502 #define RTC_CNTL_RESET_STATE_REG (DR_REG_RTCCNTL_BASE + 0x34) 503 /* RTC_CNTL_PROCPU_STAT_VECTOR_SEL : R/W ;bitpos:[13] ;default: 1'b1 ; */ 504 /*description: PRO CPU state vector sel*/ 505 #define RTC_CNTL_PROCPU_STAT_VECTOR_SEL (BIT(13)) 506 #define RTC_CNTL_PROCPU_STAT_VECTOR_SEL_M (BIT(13)) 507 #define RTC_CNTL_PROCPU_STAT_VECTOR_SEL_V 0x1 508 #define RTC_CNTL_PROCPU_STAT_VECTOR_SEL_S 13 509 /* RTC_CNTL_APPCPU_STAT_VECTOR_SEL : R/W ;bitpos:[12] ;default: 1'b1 ; */ 510 /*description: APP CPU state vector sel*/ 511 #define RTC_CNTL_APPCPU_STAT_VECTOR_SEL (BIT(12)) 512 #define RTC_CNTL_APPCPU_STAT_VECTOR_SEL_M (BIT(12)) 513 #define RTC_CNTL_APPCPU_STAT_VECTOR_SEL_V 0x1 514 #define RTC_CNTL_APPCPU_STAT_VECTOR_SEL_S 12 515 /* RTC_CNTL_RESET_CAUSE_APPCPU : RO ;bitpos:[11:6] ;default: 0 ; */ 516 /*description: reset cause of APP CPU*/ 517 #define RTC_CNTL_RESET_CAUSE_APPCPU 0x0000003F 518 #define RTC_CNTL_RESET_CAUSE_APPCPU_M ((RTC_CNTL_RESET_CAUSE_APPCPU_V)<<(RTC_CNTL_RESET_CAUSE_APPCPU_S)) 519 #define RTC_CNTL_RESET_CAUSE_APPCPU_V 0x3F 520 #define RTC_CNTL_RESET_CAUSE_APPCPU_S 6 521 /* RTC_CNTL_RESET_CAUSE_PROCPU : RO ;bitpos:[5:0] ;default: 0 ; */ 522 /*description: reset cause of PRO CPU*/ 523 #define RTC_CNTL_RESET_CAUSE_PROCPU 0x0000003F 524 #define RTC_CNTL_RESET_CAUSE_PROCPU_M ((RTC_CNTL_RESET_CAUSE_PROCPU_V)<<(RTC_CNTL_RESET_CAUSE_PROCPU_S)) 525 #define RTC_CNTL_RESET_CAUSE_PROCPU_V 0x3F 526 #define RTC_CNTL_RESET_CAUSE_PROCPU_S 0 527 528 #define RTC_CNTL_WAKEUP_STATE_REG (DR_REG_RTCCNTL_BASE + 0x38) 529 /* RTC_CNTL_GPIO_WAKEUP_FILTER : R/W ;bitpos:[22] ;default: 1'd0 ; */ 530 /*description: enable filter for gpio wakeup event*/ 531 #define RTC_CNTL_GPIO_WAKEUP_FILTER (BIT(22)) 532 #define RTC_CNTL_GPIO_WAKEUP_FILTER_M (BIT(22)) 533 #define RTC_CNTL_GPIO_WAKEUP_FILTER_V 0x1 534 #define RTC_CNTL_GPIO_WAKEUP_FILTER_S 22 535 /* RTC_CNTL_WAKEUP_ENA : R/W ;bitpos:[21:11] ;default: 11'b1100 ; */ 536 /*description: wakeup enable bitmap*/ 537 #define RTC_CNTL_WAKEUP_ENA 0x000007FF 538 #define RTC_CNTL_WAKEUP_ENA_M ((RTC_CNTL_WAKEUP_ENA_V)<<(RTC_CNTL_WAKEUP_ENA_S)) 539 #define RTC_CNTL_WAKEUP_ENA_V 0x7FF 540 #define RTC_CNTL_WAKEUP_ENA_S 11 541 /* RTC_CNTL_WAKEUP_CAUSE : RO ;bitpos:[10:0] ;default: 11'h0 ; */ 542 /*description: wakeup cause*/ 543 #define RTC_CNTL_WAKEUP_CAUSE 0x000007FF 544 #define RTC_CNTL_WAKEUP_CAUSE_M ((RTC_CNTL_WAKEUP_CAUSE_V)<<(RTC_CNTL_WAKEUP_CAUSE_S)) 545 #define RTC_CNTL_WAKEUP_CAUSE_V 0x7FF 546 #define RTC_CNTL_WAKEUP_CAUSE_S 0 547 548 #define RTC_CNTL_INT_ENA_REG (DR_REG_RTCCNTL_BASE + 0x3c) 549 /* RTC_CNTL_MAIN_TIMER_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ 550 /*description: enable RTC main timer interrupt*/ 551 #define RTC_CNTL_MAIN_TIMER_INT_ENA (BIT(8)) 552 #define RTC_CNTL_MAIN_TIMER_INT_ENA_M (BIT(8)) 553 #define RTC_CNTL_MAIN_TIMER_INT_ENA_V 0x1 554 #define RTC_CNTL_MAIN_TIMER_INT_ENA_S 8 555 /* RTC_CNTL_BROWN_OUT_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ 556 /*description: enable brown out interrupt*/ 557 #define RTC_CNTL_BROWN_OUT_INT_ENA (BIT(7)) 558 #define RTC_CNTL_BROWN_OUT_INT_ENA_M (BIT(7)) 559 #define RTC_CNTL_BROWN_OUT_INT_ENA_V 0x1 560 #define RTC_CNTL_BROWN_OUT_INT_ENA_S 7 561 /* RTC_CNTL_TOUCH_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ 562 /*description: enable touch interrupt*/ 563 #define RTC_CNTL_TOUCH_INT_ENA (BIT(6)) 564 #define RTC_CNTL_TOUCH_INT_ENA_M (BIT(6)) 565 #define RTC_CNTL_TOUCH_INT_ENA_V 0x1 566 #define RTC_CNTL_TOUCH_INT_ENA_S 6 567 /* RTC_CNTL_ULP_CP_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ 568 /*description: enable ULP-coprocessor interrupt*/ 569 #define RTC_CNTL_ULP_CP_INT_ENA (BIT(5)) 570 #define RTC_CNTL_ULP_CP_INT_ENA_M (BIT(5)) 571 #define RTC_CNTL_ULP_CP_INT_ENA_V 0x1 572 #define RTC_CNTL_ULP_CP_INT_ENA_S 5 573 /* RTC_CNTL_TIME_VALID_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ 574 /*description: enable RTC time valid interrupt*/ 575 #define RTC_CNTL_TIME_VALID_INT_ENA (BIT(4)) 576 #define RTC_CNTL_TIME_VALID_INT_ENA_M (BIT(4)) 577 #define RTC_CNTL_TIME_VALID_INT_ENA_V 0x1 578 #define RTC_CNTL_TIME_VALID_INT_ENA_S 4 579 /* RTC_CNTL_WDT_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ 580 /*description: enable RTC WDT interrupt*/ 581 #define RTC_CNTL_WDT_INT_ENA (BIT(3)) 582 #define RTC_CNTL_WDT_INT_ENA_M (BIT(3)) 583 #define RTC_CNTL_WDT_INT_ENA_V 0x1 584 #define RTC_CNTL_WDT_INT_ENA_S 3 585 /* RTC_CNTL_SDIO_IDLE_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ 586 /*description: enable SDIO idle interrupt*/ 587 #define RTC_CNTL_SDIO_IDLE_INT_ENA (BIT(2)) 588 #define RTC_CNTL_SDIO_IDLE_INT_ENA_M (BIT(2)) 589 #define RTC_CNTL_SDIO_IDLE_INT_ENA_V 0x1 590 #define RTC_CNTL_SDIO_IDLE_INT_ENA_S 2 591 /* RTC_CNTL_SLP_REJECT_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ 592 /*description: enable sleep reject interrupt*/ 593 #define RTC_CNTL_SLP_REJECT_INT_ENA (BIT(1)) 594 #define RTC_CNTL_SLP_REJECT_INT_ENA_M (BIT(1)) 595 #define RTC_CNTL_SLP_REJECT_INT_ENA_V 0x1 596 #define RTC_CNTL_SLP_REJECT_INT_ENA_S 1 597 /* RTC_CNTL_SLP_WAKEUP_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ 598 /*description: enable sleep wakeup interrupt*/ 599 #define RTC_CNTL_SLP_WAKEUP_INT_ENA (BIT(0)) 600 #define RTC_CNTL_SLP_WAKEUP_INT_ENA_M (BIT(0)) 601 #define RTC_CNTL_SLP_WAKEUP_INT_ENA_V 0x1 602 #define RTC_CNTL_SLP_WAKEUP_INT_ENA_S 0 603 604 #define RTC_CNTL_INT_RAW_REG (DR_REG_RTCCNTL_BASE + 0x40) 605 /* RTC_CNTL_MAIN_TIMER_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */ 606 /*description: RTC main timer interrupt raw*/ 607 #define RTC_CNTL_MAIN_TIMER_INT_RAW (BIT(8)) 608 #define RTC_CNTL_MAIN_TIMER_INT_RAW_M (BIT(8)) 609 #define RTC_CNTL_MAIN_TIMER_INT_RAW_V 0x1 610 #define RTC_CNTL_MAIN_TIMER_INT_RAW_S 8 611 /* RTC_CNTL_BROWN_OUT_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */ 612 /*description: brown out interrupt raw*/ 613 #define RTC_CNTL_BROWN_OUT_INT_RAW (BIT(7)) 614 #define RTC_CNTL_BROWN_OUT_INT_RAW_M (BIT(7)) 615 #define RTC_CNTL_BROWN_OUT_INT_RAW_V 0x1 616 #define RTC_CNTL_BROWN_OUT_INT_RAW_S 7 617 /* RTC_CNTL_TOUCH_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ 618 /*description: touch interrupt raw*/ 619 #define RTC_CNTL_TOUCH_INT_RAW (BIT(6)) 620 #define RTC_CNTL_TOUCH_INT_RAW_M (BIT(6)) 621 #define RTC_CNTL_TOUCH_INT_RAW_V 0x1 622 #define RTC_CNTL_TOUCH_INT_RAW_S 6 623 /* RTC_CNTL_ULP_CP_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ 624 /*description: ULP-coprocessor interrupt raw*/ 625 #define RTC_CNTL_ULP_CP_INT_RAW (BIT(5)) 626 #define RTC_CNTL_ULP_CP_INT_RAW_M (BIT(5)) 627 #define RTC_CNTL_ULP_CP_INT_RAW_V 0x1 628 #define RTC_CNTL_ULP_CP_INT_RAW_S 5 629 /* RTC_CNTL_TIME_VALID_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ 630 /*description: RTC time valid interrupt raw*/ 631 #define RTC_CNTL_TIME_VALID_INT_RAW (BIT(4)) 632 #define RTC_CNTL_TIME_VALID_INT_RAW_M (BIT(4)) 633 #define RTC_CNTL_TIME_VALID_INT_RAW_V 0x1 634 #define RTC_CNTL_TIME_VALID_INT_RAW_S 4 635 /* RTC_CNTL_WDT_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ 636 /*description: RTC WDT interrupt raw*/ 637 #define RTC_CNTL_WDT_INT_RAW (BIT(3)) 638 #define RTC_CNTL_WDT_INT_RAW_M (BIT(3)) 639 #define RTC_CNTL_WDT_INT_RAW_V 0x1 640 #define RTC_CNTL_WDT_INT_RAW_S 3 641 /* RTC_CNTL_SDIO_IDLE_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ 642 /*description: SDIO idle interrupt raw*/ 643 #define RTC_CNTL_SDIO_IDLE_INT_RAW (BIT(2)) 644 #define RTC_CNTL_SDIO_IDLE_INT_RAW_M (BIT(2)) 645 #define RTC_CNTL_SDIO_IDLE_INT_RAW_V 0x1 646 #define RTC_CNTL_SDIO_IDLE_INT_RAW_S 2 647 /* RTC_CNTL_SLP_REJECT_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ 648 /*description: sleep reject interrupt raw*/ 649 #define RTC_CNTL_SLP_REJECT_INT_RAW (BIT(1)) 650 #define RTC_CNTL_SLP_REJECT_INT_RAW_M (BIT(1)) 651 #define RTC_CNTL_SLP_REJECT_INT_RAW_V 0x1 652 #define RTC_CNTL_SLP_REJECT_INT_RAW_S 1 653 /* RTC_CNTL_SLP_WAKEUP_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ 654 /*description: sleep wakeup interrupt raw*/ 655 #define RTC_CNTL_SLP_WAKEUP_INT_RAW (BIT(0)) 656 #define RTC_CNTL_SLP_WAKEUP_INT_RAW_M (BIT(0)) 657 #define RTC_CNTL_SLP_WAKEUP_INT_RAW_V 0x1 658 #define RTC_CNTL_SLP_WAKEUP_INT_RAW_S 0 659 660 #define RTC_CNTL_INT_ST_REG (DR_REG_RTCCNTL_BASE + 0x44) 661 /* RTC_CNTL_MAIN_TIMER_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ 662 /*description: RTC main timer interrupt state*/ 663 #define RTC_CNTL_MAIN_TIMER_INT_ST (BIT(8)) 664 #define RTC_CNTL_MAIN_TIMER_INT_ST_M (BIT(8)) 665 #define RTC_CNTL_MAIN_TIMER_INT_ST_V 0x1 666 #define RTC_CNTL_MAIN_TIMER_INT_ST_S 8 667 /* RTC_CNTL_BROWN_OUT_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ 668 /*description: brown out interrupt state*/ 669 #define RTC_CNTL_BROWN_OUT_INT_ST (BIT(7)) 670 #define RTC_CNTL_BROWN_OUT_INT_ST_M (BIT(7)) 671 #define RTC_CNTL_BROWN_OUT_INT_ST_V 0x1 672 #define RTC_CNTL_BROWN_OUT_INT_ST_S 7 673 /* RTC_CNTL_TOUCH_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ 674 /*description: touch interrupt state*/ 675 #define RTC_CNTL_TOUCH_INT_ST (BIT(6)) 676 #define RTC_CNTL_TOUCH_INT_ST_M (BIT(6)) 677 #define RTC_CNTL_TOUCH_INT_ST_V 0x1 678 #define RTC_CNTL_TOUCH_INT_ST_S 6 679 /* RTC_CNTL_SAR_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ 680 /*description: ULP-coprocessor interrupt state*/ 681 #define RTC_CNTL_SAR_INT_ST (BIT(5)) 682 #define RTC_CNTL_SAR_INT_ST_M (BIT(5)) 683 #define RTC_CNTL_SAR_INT_ST_V 0x1 684 #define RTC_CNTL_SAR_INT_ST_S 5 685 /* RTC_CNTL_TIME_VALID_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ 686 /*description: RTC time valid interrupt state*/ 687 #define RTC_CNTL_TIME_VALID_INT_ST (BIT(4)) 688 #define RTC_CNTL_TIME_VALID_INT_ST_M (BIT(4)) 689 #define RTC_CNTL_TIME_VALID_INT_ST_V 0x1 690 #define RTC_CNTL_TIME_VALID_INT_ST_S 4 691 /* RTC_CNTL_WDT_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ 692 /*description: RTC WDT interrupt state*/ 693 #define RTC_CNTL_WDT_INT_ST (BIT(3)) 694 #define RTC_CNTL_WDT_INT_ST_M (BIT(3)) 695 #define RTC_CNTL_WDT_INT_ST_V 0x1 696 #define RTC_CNTL_WDT_INT_ST_S 3 697 /* RTC_CNTL_SDIO_IDLE_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ 698 /*description: SDIO idle interrupt state*/ 699 #define RTC_CNTL_SDIO_IDLE_INT_ST (BIT(2)) 700 #define RTC_CNTL_SDIO_IDLE_INT_ST_M (BIT(2)) 701 #define RTC_CNTL_SDIO_IDLE_INT_ST_V 0x1 702 #define RTC_CNTL_SDIO_IDLE_INT_ST_S 2 703 /* RTC_CNTL_SLP_REJECT_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ 704 /*description: sleep reject interrupt state*/ 705 #define RTC_CNTL_SLP_REJECT_INT_ST (BIT(1)) 706 #define RTC_CNTL_SLP_REJECT_INT_ST_M (BIT(1)) 707 #define RTC_CNTL_SLP_REJECT_INT_ST_V 0x1 708 #define RTC_CNTL_SLP_REJECT_INT_ST_S 1 709 /* RTC_CNTL_SLP_WAKEUP_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ 710 /*description: sleep wakeup interrupt state*/ 711 #define RTC_CNTL_SLP_WAKEUP_INT_ST (BIT(0)) 712 #define RTC_CNTL_SLP_WAKEUP_INT_ST_M (BIT(0)) 713 #define RTC_CNTL_SLP_WAKEUP_INT_ST_V 0x1 714 #define RTC_CNTL_SLP_WAKEUP_INT_ST_S 0 715 716 #define RTC_CNTL_INT_CLR_REG (DR_REG_RTCCNTL_BASE + 0x48) 717 /* RTC_CNTL_MAIN_TIMER_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */ 718 /*description: Clear RTC main timer interrupt state*/ 719 #define RTC_CNTL_MAIN_TIMER_INT_CLR (BIT(8)) 720 #define RTC_CNTL_MAIN_TIMER_INT_CLR_M (BIT(8)) 721 #define RTC_CNTL_MAIN_TIMER_INT_CLR_V 0x1 722 #define RTC_CNTL_MAIN_TIMER_INT_CLR_S 8 723 /* RTC_CNTL_BROWN_OUT_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */ 724 /*description: Clear brown out interrupt state*/ 725 #define RTC_CNTL_BROWN_OUT_INT_CLR (BIT(7)) 726 #define RTC_CNTL_BROWN_OUT_INT_CLR_M (BIT(7)) 727 #define RTC_CNTL_BROWN_OUT_INT_CLR_V 0x1 728 #define RTC_CNTL_BROWN_OUT_INT_CLR_S 7 729 /* RTC_CNTL_TOUCH_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */ 730 /*description: Clear touch interrupt state*/ 731 #define RTC_CNTL_TOUCH_INT_CLR (BIT(6)) 732 #define RTC_CNTL_TOUCH_INT_CLR_M (BIT(6)) 733 #define RTC_CNTL_TOUCH_INT_CLR_V 0x1 734 #define RTC_CNTL_TOUCH_INT_CLR_S 6 735 /* RTC_CNTL_SAR_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */ 736 /*description: Clear ULP-coprocessor interrupt state*/ 737 #define RTC_CNTL_SAR_INT_CLR (BIT(5)) 738 #define RTC_CNTL_SAR_INT_CLR_M (BIT(5)) 739 #define RTC_CNTL_SAR_INT_CLR_V 0x1 740 #define RTC_CNTL_SAR_INT_CLR_S 5 741 /* RTC_CNTL_TIME_VALID_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ 742 /*description: Clear RTC time valid interrupt state*/ 743 #define RTC_CNTL_TIME_VALID_INT_CLR (BIT(4)) 744 #define RTC_CNTL_TIME_VALID_INT_CLR_M (BIT(4)) 745 #define RTC_CNTL_TIME_VALID_INT_CLR_V 0x1 746 #define RTC_CNTL_TIME_VALID_INT_CLR_S 4 747 /* RTC_CNTL_WDT_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ 748 /*description: Clear RTC WDT interrupt state*/ 749 #define RTC_CNTL_WDT_INT_CLR (BIT(3)) 750 #define RTC_CNTL_WDT_INT_CLR_M (BIT(3)) 751 #define RTC_CNTL_WDT_INT_CLR_V 0x1 752 #define RTC_CNTL_WDT_INT_CLR_S 3 753 /* RTC_CNTL_SDIO_IDLE_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */ 754 /*description: Clear SDIO idle interrupt state*/ 755 #define RTC_CNTL_SDIO_IDLE_INT_CLR (BIT(2)) 756 #define RTC_CNTL_SDIO_IDLE_INT_CLR_M (BIT(2)) 757 #define RTC_CNTL_SDIO_IDLE_INT_CLR_V 0x1 758 #define RTC_CNTL_SDIO_IDLE_INT_CLR_S 2 759 /* RTC_CNTL_SLP_REJECT_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ 760 /*description: Clear sleep reject interrupt state*/ 761 #define RTC_CNTL_SLP_REJECT_INT_CLR (BIT(1)) 762 #define RTC_CNTL_SLP_REJECT_INT_CLR_M (BIT(1)) 763 #define RTC_CNTL_SLP_REJECT_INT_CLR_V 0x1 764 #define RTC_CNTL_SLP_REJECT_INT_CLR_S 1 765 /* RTC_CNTL_SLP_WAKEUP_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ 766 /*description: Clear sleep wakeup interrupt state*/ 767 #define RTC_CNTL_SLP_WAKEUP_INT_CLR (BIT(0)) 768 #define RTC_CNTL_SLP_WAKEUP_INT_CLR_M (BIT(0)) 769 #define RTC_CNTL_SLP_WAKEUP_INT_CLR_V 0x1 770 #define RTC_CNTL_SLP_WAKEUP_INT_CLR_S 0 771 772 #define RTC_CNTL_STORE0_REG (DR_REG_RTCCNTL_BASE + 0x4c) 773 /* RTC_CNTL_SCRATCH0 : R/W ;bitpos:[31:0] ;default: 0 ; */ 774 /*description: 32-bit general purpose retention register*/ 775 #define RTC_CNTL_SCRATCH0 0xFFFFFFFF 776 #define RTC_CNTL_SCRATCH0_M ((RTC_CNTL_SCRATCH0_V)<<(RTC_CNTL_SCRATCH0_S)) 777 #define RTC_CNTL_SCRATCH0_V 0xFFFFFFFF 778 #define RTC_CNTL_SCRATCH0_S 0 779 780 #define RTC_CNTL_STORE1_REG (DR_REG_RTCCNTL_BASE + 0x50) 781 /* RTC_CNTL_SCRATCH1 : R/W ;bitpos:[31:0] ;default: 0 ; */ 782 /*description: 32-bit general purpose retention register*/ 783 #define RTC_CNTL_SCRATCH1 0xFFFFFFFF 784 #define RTC_CNTL_SCRATCH1_M ((RTC_CNTL_SCRATCH1_V)<<(RTC_CNTL_SCRATCH1_S)) 785 #define RTC_CNTL_SCRATCH1_V 0xFFFFFFFF 786 #define RTC_CNTL_SCRATCH1_S 0 787 788 #define RTC_CNTL_STORE2_REG (DR_REG_RTCCNTL_BASE + 0x54) 789 /* RTC_CNTL_SCRATCH2 : R/W ;bitpos:[31:0] ;default: 0 ; */ 790 /*description: 32-bit general purpose retention register*/ 791 #define RTC_CNTL_SCRATCH2 0xFFFFFFFF 792 #define RTC_CNTL_SCRATCH2_M ((RTC_CNTL_SCRATCH2_V)<<(RTC_CNTL_SCRATCH2_S)) 793 #define RTC_CNTL_SCRATCH2_V 0xFFFFFFFF 794 #define RTC_CNTL_SCRATCH2_S 0 795 796 #define RTC_CNTL_STORE3_REG (DR_REG_RTCCNTL_BASE + 0x58) 797 /* RTC_CNTL_SCRATCH3 : R/W ;bitpos:[31:0] ;default: 0 ; */ 798 /*description: 32-bit general purpose retention register*/ 799 #define RTC_CNTL_SCRATCH3 0xFFFFFFFF 800 #define RTC_CNTL_SCRATCH3_M ((RTC_CNTL_SCRATCH3_V)<<(RTC_CNTL_SCRATCH3_S)) 801 #define RTC_CNTL_SCRATCH3_V 0xFFFFFFFF 802 #define RTC_CNTL_SCRATCH3_S 0 803 804 #define RTC_CNTL_EXT_XTL_CONF_REG (DR_REG_RTCCNTL_BASE + 0x5c) 805 /* RTC_CNTL_XTL_EXT_CTR_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ 806 /*description: enable control XTAL by external pads*/ 807 #define RTC_CNTL_XTL_EXT_CTR_EN (BIT(31)) 808 #define RTC_CNTL_XTL_EXT_CTR_EN_M (BIT(31)) 809 #define RTC_CNTL_XTL_EXT_CTR_EN_V 0x1 810 #define RTC_CNTL_XTL_EXT_CTR_EN_S 31 811 /* RTC_CNTL_XTL_EXT_CTR_LV : R/W ;bitpos:[30] ;default: 1'b0 ; */ 812 /*description: 0: power down XTAL at high level 1: power down XTAL at low level*/ 813 #define RTC_CNTL_XTL_EXT_CTR_LV (BIT(30)) 814 #define RTC_CNTL_XTL_EXT_CTR_LV_M (BIT(30)) 815 #define RTC_CNTL_XTL_EXT_CTR_LV_V 0x1 816 #define RTC_CNTL_XTL_EXT_CTR_LV_S 30 817 818 #define RTC_CNTL_EXT_WAKEUP_CONF_REG (DR_REG_RTCCNTL_BASE + 0x60) 819 /* RTC_CNTL_EXT_WAKEUP1_LV : R/W ;bitpos:[31] ;default: 1'b0 ; */ 820 /*description: 0: external wakeup at low level 1: external wakeup at high level*/ 821 #define RTC_CNTL_EXT_WAKEUP1_LV (BIT(31)) 822 #define RTC_CNTL_EXT_WAKEUP1_LV_M (BIT(31)) 823 #define RTC_CNTL_EXT_WAKEUP1_LV_V 0x1 824 #define RTC_CNTL_EXT_WAKEUP1_LV_S 31 825 /* RTC_CNTL_EXT_WAKEUP0_LV : R/W ;bitpos:[30] ;default: 1'b0 ; */ 826 /*description: 0: external wakeup at low level 1: external wakeup at high level*/ 827 #define RTC_CNTL_EXT_WAKEUP0_LV (BIT(30)) 828 #define RTC_CNTL_EXT_WAKEUP0_LV_M (BIT(30)) 829 #define RTC_CNTL_EXT_WAKEUP0_LV_V 0x1 830 #define RTC_CNTL_EXT_WAKEUP0_LV_S 30 831 832 #define RTC_CNTL_SLP_REJECT_CONF_REG (DR_REG_RTCCNTL_BASE + 0x64) 833 /* RTC_CNTL_REJECT_CAUSE : RO ;bitpos:[31:28] ;default: 4'b0 ; */ 834 /*description: sleep reject cause*/ 835 #define RTC_CNTL_REJECT_CAUSE 0x0000000F 836 #define RTC_CNTL_REJECT_CAUSE_M ((RTC_CNTL_REJECT_CAUSE_V)<<(RTC_CNTL_REJECT_CAUSE_S)) 837 #define RTC_CNTL_REJECT_CAUSE_V 0xF 838 #define RTC_CNTL_REJECT_CAUSE_S 28 839 /* RTC_CNTL_DEEP_SLP_REJECT_EN : R/W ;bitpos:[27] ;default: 1'b0 ; */ 840 /*description: enable reject for deep sleep*/ 841 #define RTC_CNTL_DEEP_SLP_REJECT_EN (BIT(27)) 842 #define RTC_CNTL_DEEP_SLP_REJECT_EN_M (BIT(27)) 843 #define RTC_CNTL_DEEP_SLP_REJECT_EN_V 0x1 844 #define RTC_CNTL_DEEP_SLP_REJECT_EN_S 27 845 /* RTC_CNTL_LIGHT_SLP_REJECT_EN : R/W ;bitpos:[26] ;default: 1'b0 ; */ 846 /*description: enable reject for light sleep*/ 847 #define RTC_CNTL_LIGHT_SLP_REJECT_EN (BIT(26)) 848 #define RTC_CNTL_LIGHT_SLP_REJECT_EN_M (BIT(26)) 849 #define RTC_CNTL_LIGHT_SLP_REJECT_EN_V 0x1 850 #define RTC_CNTL_LIGHT_SLP_REJECT_EN_S 26 851 /* RTC_CNTL_SDIO_REJECT_EN : R/W ;bitpos:[25] ;default: 1'b0 ; */ 852 /*description: enable SDIO reject*/ 853 #define RTC_CNTL_SDIO_REJECT_EN (BIT(25)) 854 #define RTC_CNTL_SDIO_REJECT_EN_M (BIT(25)) 855 #define RTC_CNTL_SDIO_REJECT_EN_V 0x1 856 #define RTC_CNTL_SDIO_REJECT_EN_S 25 857 /* RTC_CNTL_GPIO_REJECT_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */ 858 /*description: enable GPIO reject*/ 859 #define RTC_CNTL_GPIO_REJECT_EN (BIT(24)) 860 #define RTC_CNTL_GPIO_REJECT_EN_M (BIT(24)) 861 #define RTC_CNTL_GPIO_REJECT_EN_V 0x1 862 #define RTC_CNTL_GPIO_REJECT_EN_S 24 863 864 #define RTC_CNTL_CPU_PERIOD_CONF_REG (DR_REG_RTCCNTL_BASE + 0x68) 865 /* RTC_CNTL_CPUPERIOD_SEL : R/W ;bitpos:[31:30] ;default: 2'b00 ; */ 866 /*description: CPU period sel*/ 867 #define RTC_CNTL_CPUPERIOD_SEL 0x00000003 868 #define RTC_CNTL_CPUPERIOD_SEL_M ((RTC_CNTL_CPUPERIOD_SEL_V)<<(RTC_CNTL_CPUPERIOD_SEL_S)) 869 #define RTC_CNTL_CPUPERIOD_SEL_V 0x3 870 #define RTC_CNTL_CPUPERIOD_SEL_S 30 871 /* RTC_CNTL_CPUSEL_CONF : R/W ;bitpos:[29] ;default: 1'b0 ; */ 872 /*description: CPU sel option*/ 873 #define RTC_CNTL_CPUSEL_CONF (BIT(29)) 874 #define RTC_CNTL_CPUSEL_CONF_M (BIT(29)) 875 #define RTC_CNTL_CPUSEL_CONF_V 0x1 876 #define RTC_CNTL_CPUSEL_CONF_S 29 877 878 #define RTC_CNTL_SDIO_ACT_CONF_REG (DR_REG_RTCCNTL_BASE + 0x6c) 879 /* RTC_CNTL_SDIO_ACT_DNUM : R/W ;bitpos:[31:22] ;default: 10'b0 ; */ 880 /*description: */ 881 #define RTC_CNTL_SDIO_ACT_DNUM 0x000003FF 882 #define RTC_CNTL_SDIO_ACT_DNUM_M ((RTC_CNTL_SDIO_ACT_DNUM_V)<<(RTC_CNTL_SDIO_ACT_DNUM_S)) 883 #define RTC_CNTL_SDIO_ACT_DNUM_V 0x3FF 884 #define RTC_CNTL_SDIO_ACT_DNUM_S 22 885 886 #define RTC_CNTL_CLK_CONF_REG (DR_REG_RTCCNTL_BASE + 0x70) 887 /* RTC_CNTL_ANA_CLK_RTC_SEL : R/W ;bitpos:[31:30] ;default: 2'd0 ; */ 888 /*description: slow_clk_rtc sel. 0: SLOW_CK 1: CK_XTAL_32K 2: CK8M_D256_OUT*/ 889 #define RTC_CNTL_ANA_CLK_RTC_SEL 0x00000003 890 #define RTC_CNTL_ANA_CLK_RTC_SEL_M ((RTC_CNTL_ANA_CLK_RTC_SEL_V)<<(RTC_CNTL_ANA_CLK_RTC_SEL_S)) 891 #define RTC_CNTL_ANA_CLK_RTC_SEL_V 0x3 892 #define RTC_CNTL_ANA_CLK_RTC_SEL_S 30 893 /* RTC_CNTL_FAST_CLK_RTC_SEL : R/W ;bitpos:[29] ;default: 1'b0 ; */ 894 /*description: fast_clk_rtc sel. 0: XTAL div 4 1: CK8M*/ 895 #define RTC_CNTL_FAST_CLK_RTC_SEL (BIT(29)) 896 #define RTC_CNTL_FAST_CLK_RTC_SEL_M (BIT(29)) 897 #define RTC_CNTL_FAST_CLK_RTC_SEL_V 0x1 898 #define RTC_CNTL_FAST_CLK_RTC_SEL_S 29 899 /* RTC_CNTL_SOC_CLK_SEL : R/W ;bitpos:[28:27] ;default: 2'd0 ; */ 900 /*description: SOC clock sel. 0: XTAL 1: PLL 2: CK8M 3: APLL*/ 901 #define RTC_CNTL_SOC_CLK_SEL 0x00000003 902 #define RTC_CNTL_SOC_CLK_SEL_M ((RTC_CNTL_SOC_CLK_SEL_V)<<(RTC_CNTL_SOC_CLK_SEL_S)) 903 #define RTC_CNTL_SOC_CLK_SEL_V 0x3 904 #define RTC_CNTL_SOC_CLK_SEL_S 27 905 #define RTC_CNTL_SOC_CLK_SEL_XTL 0 906 #define RTC_CNTL_SOC_CLK_SEL_PLL 1 907 #define RTC_CNTL_SOC_CLK_SEL_8M 2 908 #define RTC_CNTL_SOC_CLK_SEL_APLL 3 909 /* RTC_CNTL_CK8M_FORCE_PU : R/W ;bitpos:[26] ;default: 1'd0 ; */ 910 /*description: CK8M force power up*/ 911 #define RTC_CNTL_CK8M_FORCE_PU (BIT(26)) 912 #define RTC_CNTL_CK8M_FORCE_PU_M (BIT(26)) 913 #define RTC_CNTL_CK8M_FORCE_PU_V 0x1 914 #define RTC_CNTL_CK8M_FORCE_PU_S 26 915 /* RTC_CNTL_CK8M_FORCE_PD : R/W ;bitpos:[25] ;default: 1'd0 ; */ 916 /*description: CK8M force power down*/ 917 #define RTC_CNTL_CK8M_FORCE_PD (BIT(25)) 918 #define RTC_CNTL_CK8M_FORCE_PD_M (BIT(25)) 919 #define RTC_CNTL_CK8M_FORCE_PD_V 0x1 920 #define RTC_CNTL_CK8M_FORCE_PD_S 25 921 /* RTC_CNTL_CK8M_DFREQ : R/W ;bitpos:[24:17] ;default: 8'd0 ; */ 922 /*description: CK8M_DFREQ*/ 923 #define RTC_CNTL_CK8M_DFREQ 0x000000FF 924 #define RTC_CNTL_CK8M_DFREQ_M ((RTC_CNTL_CK8M_DFREQ_V)<<(RTC_CNTL_CK8M_DFREQ_S)) 925 #define RTC_CNTL_CK8M_DFREQ_V 0xFF 926 #define RTC_CNTL_CK8M_DFREQ_S 17 927 #define RTC_CNTL_CK8M_DFREQ_DEFAULT 172 928 /* RTC_CNTL_CK8M_FORCE_NOGATING : R/W ;bitpos:[16] ;default: 1'd0 ; */ 929 /*description: CK8M force no gating during sleep*/ 930 #define RTC_CNTL_CK8M_FORCE_NOGATING (BIT(16)) 931 #define RTC_CNTL_CK8M_FORCE_NOGATING_M (BIT(16)) 932 #define RTC_CNTL_CK8M_FORCE_NOGATING_V 0x1 933 #define RTC_CNTL_CK8M_FORCE_NOGATING_S 16 934 /* RTC_CNTL_XTAL_FORCE_NOGATING : R/W ;bitpos:[15] ;default: 1'd0 ; */ 935 /*description: XTAL force no gating during sleep*/ 936 #define RTC_CNTL_XTAL_FORCE_NOGATING (BIT(15)) 937 #define RTC_CNTL_XTAL_FORCE_NOGATING_M (BIT(15)) 938 #define RTC_CNTL_XTAL_FORCE_NOGATING_V 0x1 939 #define RTC_CNTL_XTAL_FORCE_NOGATING_S 15 940 /* RTC_CNTL_CK8M_DIV_SEL : R/W ;bitpos:[14:12] ;default: 3'd2 ; */ 941 /*description: divider = reg_ck8m_div_sel + 1*/ 942 #define RTC_CNTL_CK8M_DIV_SEL 0x00000007 943 #define RTC_CNTL_CK8M_DIV_SEL_M ((RTC_CNTL_CK8M_DIV_SEL_V)<<(RTC_CNTL_CK8M_DIV_SEL_S)) 944 #define RTC_CNTL_CK8M_DIV_SEL_V 0x7 945 #define RTC_CNTL_CK8M_DIV_SEL_S 12 946 /* RTC_CNTL_CK8M_DFREQ_FORCE : R/W ;bitpos:[11] ;default: 1'd0 ; */ 947 /*description: */ 948 #define RTC_CNTL_CK8M_DFREQ_FORCE (BIT(11)) 949 #define RTC_CNTL_CK8M_DFREQ_FORCE_M (BIT(11)) 950 #define RTC_CNTL_CK8M_DFREQ_FORCE_V 0x1 951 #define RTC_CNTL_CK8M_DFREQ_FORCE_S 11 952 /* RTC_CNTL_DIG_CLK8M_EN : R/W ;bitpos:[10] ;default: 1'd0 ; */ 953 /*description: enable CK8M for digital core (no relationship with RTC core)*/ 954 #define RTC_CNTL_DIG_CLK8M_EN (BIT(10)) 955 #define RTC_CNTL_DIG_CLK8M_EN_M (BIT(10)) 956 #define RTC_CNTL_DIG_CLK8M_EN_V 0x1 957 #define RTC_CNTL_DIG_CLK8M_EN_S 10 958 /* RTC_CNTL_DIG_CLK8M_D256_EN : R/W ;bitpos:[9] ;default: 1'd1 ; */ 959 /*description: enable CK8M_D256_OUT for digital core (no relationship with RTC core)*/ 960 #define RTC_CNTL_DIG_CLK8M_D256_EN (BIT(9)) 961 #define RTC_CNTL_DIG_CLK8M_D256_EN_M (BIT(9)) 962 #define RTC_CNTL_DIG_CLK8M_D256_EN_V 0x1 963 #define RTC_CNTL_DIG_CLK8M_D256_EN_S 9 964 /* RTC_CNTL_DIG_XTAL32K_EN : R/W ;bitpos:[8] ;default: 1'd0 ; */ 965 /*description: enable CK_XTAL_32K for digital core (no relationship with RTC core)*/ 966 #define RTC_CNTL_DIG_XTAL32K_EN (BIT(8)) 967 #define RTC_CNTL_DIG_XTAL32K_EN_M (BIT(8)) 968 #define RTC_CNTL_DIG_XTAL32K_EN_V 0x1 969 #define RTC_CNTL_DIG_XTAL32K_EN_S 8 970 /* RTC_CNTL_ENB_CK8M_DIV : R/W ;bitpos:[7] ;default: 1'd0 ; */ 971 /*description: 1: CK8M_D256_OUT is actually CK8M 0: CK8M_D256_OUT is CK8M divided by 256*/ 972 #define RTC_CNTL_ENB_CK8M_DIV (BIT(7)) 973 #define RTC_CNTL_ENB_CK8M_DIV_M (BIT(7)) 974 #define RTC_CNTL_ENB_CK8M_DIV_V 0x1 975 #define RTC_CNTL_ENB_CK8M_DIV_S 7 976 /* RTC_CNTL_ENB_CK8M : R/W ;bitpos:[6] ;default: 1'd0 ; */ 977 /*description: disable CK8M and CK8M_D256_OUT*/ 978 #define RTC_CNTL_ENB_CK8M (BIT(6)) 979 #define RTC_CNTL_ENB_CK8M_M (BIT(6)) 980 #define RTC_CNTL_ENB_CK8M_V 0x1 981 #define RTC_CNTL_ENB_CK8M_S 6 982 /* RTC_CNTL_CK8M_DIV : R/W ;bitpos:[5:4] ;default: 2'b01 ; */ 983 /*description: CK8M_D256_OUT divider. 00: div128 01: div256 10: div512 11: div1024.*/ 984 #define RTC_CNTL_CK8M_DIV 0x00000003 985 #define RTC_CNTL_CK8M_DIV_M ((RTC_CNTL_CK8M_DIV_V)<<(RTC_CNTL_CK8M_DIV_S)) 986 #define RTC_CNTL_CK8M_DIV_V 0x3 987 #define RTC_CNTL_CK8M_DIV_S 4 988 989 #define RTC_CNTL_SDIO_CONF_REG (DR_REG_RTCCNTL_BASE + 0x74) 990 /* RTC_CNTL_XPD_SDIO_REG : R/W ;bitpos:[31] ;default: 1'd0 ; */ 991 /*description: SW option for XPD_SDIO_REG. Only active when reg_sdio_force = 1*/ 992 #define RTC_CNTL_XPD_SDIO_REG (BIT(31)) 993 #define RTC_CNTL_XPD_SDIO_REG_M (BIT(31)) 994 #define RTC_CNTL_XPD_SDIO_REG_V 0x1 995 #define RTC_CNTL_XPD_SDIO_REG_S 31 996 /* RTC_CNTL_DREFH_SDIO : R/W ;bitpos:[30:29] ;default: 2'b00 ; */ 997 /*description: SW option for DREFH_SDIO. Only active when reg_sdio_force = 1*/ 998 #define RTC_CNTL_DREFH_SDIO 0x00000003 999 #define RTC_CNTL_DREFH_SDIO_M ((RTC_CNTL_DREFH_SDIO_V)<<(RTC_CNTL_DREFH_SDIO_S)) 1000 #define RTC_CNTL_DREFH_SDIO_V 0x3 1001 #define RTC_CNTL_DREFH_SDIO_S 29 1002 /* RTC_CNTL_DREFM_SDIO : R/W ;bitpos:[28:27] ;default: 2'b00 ; */ 1003 /*description: SW option for DREFM_SDIO. Only active when reg_sdio_force = 1*/ 1004 #define RTC_CNTL_DREFM_SDIO 0x00000003 1005 #define RTC_CNTL_DREFM_SDIO_M ((RTC_CNTL_DREFM_SDIO_V)<<(RTC_CNTL_DREFM_SDIO_S)) 1006 #define RTC_CNTL_DREFM_SDIO_V 0x3 1007 #define RTC_CNTL_DREFM_SDIO_S 27 1008 /* RTC_CNTL_DREFL_SDIO : R/W ;bitpos:[26:25] ;default: 2'b01 ; */ 1009 /*description: SW option for DREFL_SDIO. Only active when reg_sdio_force = 1*/ 1010 #define RTC_CNTL_DREFL_SDIO 0x00000003 1011 #define RTC_CNTL_DREFL_SDIO_M ((RTC_CNTL_DREFL_SDIO_V)<<(RTC_CNTL_DREFL_SDIO_S)) 1012 #define RTC_CNTL_DREFL_SDIO_V 0x3 1013 #define RTC_CNTL_DREFL_SDIO_S 25 1014 /* RTC_CNTL_REG1P8_READY : RO ;bitpos:[24] ;default: 1'd0 ; */ 1015 /*description: read only register for REG1P8_READY*/ 1016 #define RTC_CNTL_REG1P8_READY (BIT(24)) 1017 #define RTC_CNTL_REG1P8_READY_M (BIT(24)) 1018 #define RTC_CNTL_REG1P8_READY_V 0x1 1019 #define RTC_CNTL_REG1P8_READY_S 24 1020 /* RTC_CNTL_SDIO_TIEH : R/W ;bitpos:[23] ;default: 1'd1 ; */ 1021 /*description: SW option for SDIO_TIEH. Only active when reg_sdio_force = 1*/ 1022 #define RTC_CNTL_SDIO_TIEH (BIT(23)) 1023 #define RTC_CNTL_SDIO_TIEH_M (BIT(23)) 1024 #define RTC_CNTL_SDIO_TIEH_V 0x1 1025 #define RTC_CNTL_SDIO_TIEH_S 23 1026 /* RTC_CNTL_SDIO_FORCE : R/W ;bitpos:[22] ;default: 1'd0 ; */ 1027 /*description: 1: use SW option to control SDIO_REG 0: use state machine*/ 1028 #define RTC_CNTL_SDIO_FORCE (BIT(22)) 1029 #define RTC_CNTL_SDIO_FORCE_M (BIT(22)) 1030 #define RTC_CNTL_SDIO_FORCE_V 0x1 1031 #define RTC_CNTL_SDIO_FORCE_S 22 1032 /* RTC_CNTL_SDIO_PD_EN : R/W ;bitpos:[21] ;default: 1'd1 ; */ 1033 /*description: power down SDIO_REG in sleep. Only active when reg_sdio_force = 0*/ 1034 #define RTC_CNTL_SDIO_PD_EN (BIT(21)) 1035 #define RTC_CNTL_SDIO_PD_EN_M (BIT(21)) 1036 #define RTC_CNTL_SDIO_PD_EN_V 0x1 1037 #define RTC_CNTL_SDIO_PD_EN_S 21 1038 1039 #define RTC_CNTL_BIAS_CONF_REG (DR_REG_RTCCNTL_BASE + 0x78) 1040 /* RTC_CNTL_RST_BIAS_I2C : R/W ;bitpos:[31] ;default: 1'd0 ; */ 1041 /*description: RST_BIAS_I2C*/ 1042 #define RTC_CNTL_RST_BIAS_I2C (BIT(31)) 1043 #define RTC_CNTL_RST_BIAS_I2C_M (BIT(31)) 1044 #define RTC_CNTL_RST_BIAS_I2C_V 0x1 1045 #define RTC_CNTL_RST_BIAS_I2C_S 31 1046 /* RTC_CNTL_DEC_HEARTBEAT_WIDTH : R/W ;bitpos:[30] ;default: 1'd0 ; */ 1047 /*description: DEC_HEARTBEAT_WIDTH*/ 1048 #define RTC_CNTL_DEC_HEARTBEAT_WIDTH (BIT(30)) 1049 #define RTC_CNTL_DEC_HEARTBEAT_WIDTH_M (BIT(30)) 1050 #define RTC_CNTL_DEC_HEARTBEAT_WIDTH_V 0x1 1051 #define RTC_CNTL_DEC_HEARTBEAT_WIDTH_S 30 1052 /* RTC_CNTL_INC_HEARTBEAT_PERIOD : R/W ;bitpos:[29] ;default: 1'd0 ; */ 1053 /*description: INC_HEARTBEAT_PERIOD*/ 1054 #define RTC_CNTL_INC_HEARTBEAT_PERIOD (BIT(29)) 1055 #define RTC_CNTL_INC_HEARTBEAT_PERIOD_M (BIT(29)) 1056 #define RTC_CNTL_INC_HEARTBEAT_PERIOD_V 0x1 1057 #define RTC_CNTL_INC_HEARTBEAT_PERIOD_S 29 1058 /* RTC_CNTL_DEC_HEARTBEAT_PERIOD : R/W ;bitpos:[28] ;default: 1'd0 ; */ 1059 /*description: DEC_HEARTBEAT_PERIOD*/ 1060 #define RTC_CNTL_DEC_HEARTBEAT_PERIOD (BIT(28)) 1061 #define RTC_CNTL_DEC_HEARTBEAT_PERIOD_M (BIT(28)) 1062 #define RTC_CNTL_DEC_HEARTBEAT_PERIOD_V 0x1 1063 #define RTC_CNTL_DEC_HEARTBEAT_PERIOD_S 28 1064 /* RTC_CNTL_INC_HEARTBEAT_REFRESH : R/W ;bitpos:[27] ;default: 1'd0 ; */ 1065 /*description: INC_HEARTBEAT_REFRESH*/ 1066 #define RTC_CNTL_INC_HEARTBEAT_REFRESH (BIT(27)) 1067 #define RTC_CNTL_INC_HEARTBEAT_REFRESH_M (BIT(27)) 1068 #define RTC_CNTL_INC_HEARTBEAT_REFRESH_V 0x1 1069 #define RTC_CNTL_INC_HEARTBEAT_REFRESH_S 27 1070 /* RTC_CNTL_ENB_SCK_XTAL : R/W ;bitpos:[26] ;default: 1'd0 ; */ 1071 /*description: ENB_SCK_XTAL*/ 1072 #define RTC_CNTL_ENB_SCK_XTAL (BIT(26)) 1073 #define RTC_CNTL_ENB_SCK_XTAL_M (BIT(26)) 1074 #define RTC_CNTL_ENB_SCK_XTAL_V 0x1 1075 #define RTC_CNTL_ENB_SCK_XTAL_S 26 1076 /* RTC_CNTL_DBG_ATTEN : R/W ;bitpos:[25:24] ;default: 2'b00 ; */ 1077 /*description: DBG_ATTEN*/ 1078 #define RTC_CNTL_DBG_ATTEN 0x00000003 1079 #define RTC_CNTL_DBG_ATTEN_M ((RTC_CNTL_DBG_ATTEN_V)<<(RTC_CNTL_DBG_ATTEN_S)) 1080 #define RTC_CNTL_DBG_ATTEN_V 0x3 1081 #define RTC_CNTL_DBG_ATTEN_S 24 1082 #define RTC_CNTL_DBG_ATTEN_DEFAULT 3 1083 #define RTC_CNTL_REG (DR_REG_RTCCNTL_BASE + 0x7c) 1084 /* RTC_CNTL_FORCE_PU : R/W ;bitpos:[31] ;default: 1'd1 ; */ 1085 /*description: RTC_REG force power up*/ 1086 #define RTC_CNTL_FORCE_PU (BIT(31)) 1087 #define RTC_CNTL_FORCE_PU_M (BIT(31)) 1088 #define RTC_CNTL_FORCE_PU_V 0x1 1089 #define RTC_CNTL_FORCE_PU_S 31 1090 /* RTC_CNTL_FORCE_PD : R/W ;bitpos:[30] ;default: 1'd0 ; */ 1091 /*description: RTC_REG force power down (for RTC_REG power down means decrease 1092 the voltage to 0.8v or lower )*/ 1093 #define RTC_CNTL_FORCE_PD (BIT(30)) 1094 #define RTC_CNTL_FORCE_PD_M (BIT(30)) 1095 #define RTC_CNTL_FORCE_PD_V 0x1 1096 #define RTC_CNTL_FORCE_PD_S 30 1097 /* RTC_CNTL_DBOOST_FORCE_PU : R/W ;bitpos:[29] ;default: 1'd1 ; */ 1098 /*description: RTC_DBOOST force power up*/ 1099 #define RTC_CNTL_DBOOST_FORCE_PU (BIT(29)) 1100 #define RTC_CNTL_DBOOST_FORCE_PU_M (BIT(29)) 1101 #define RTC_CNTL_DBOOST_FORCE_PU_V 0x1 1102 #define RTC_CNTL_DBOOST_FORCE_PU_S 29 1103 /* RTC_CNTL_DBOOST_FORCE_PD : R/W ;bitpos:[28] ;default: 1'd0 ; */ 1104 /*description: RTC_DBOOST force power down*/ 1105 #define RTC_CNTL_DBOOST_FORCE_PD (BIT(28)) 1106 #define RTC_CNTL_DBOOST_FORCE_PD_M (BIT(28)) 1107 #define RTC_CNTL_DBOOST_FORCE_PD_V 0x1 1108 #define RTC_CNTL_DBOOST_FORCE_PD_S 28 1109 /* RTC_CNTL_DBIAS_WAK : R/W ;bitpos:[27:25] ;default: 3'd4 ; */ 1110 /*description: RTC_DBIAS during wakeup*/ 1111 #define RTC_CNTL_DBIAS_WAK 0x00000007 1112 #define RTC_CNTL_DBIAS_WAK_M ((RTC_CNTL_DBIAS_WAK_V)<<(RTC_CNTL_DBIAS_WAK_S)) 1113 #define RTC_CNTL_DBIAS_WAK_V 0x7 1114 #define RTC_CNTL_DBIAS_WAK_S 25 1115 /* RTC_CNTL_DBIAS_SLP : R/W ;bitpos:[24:22] ;default: 3'd4 ; */ 1116 /*description: RTC_DBIAS during sleep*/ 1117 #define RTC_CNTL_DBIAS_SLP 0x00000007 1118 #define RTC_CNTL_DBIAS_SLP_M ((RTC_CNTL_DBIAS_SLP_V)<<(RTC_CNTL_DBIAS_SLP_S)) 1119 #define RTC_CNTL_DBIAS_SLP_V 0x7 1120 #define RTC_CNTL_DBIAS_SLP_S 22 1121 /* RTC_CNTL_SCK_DCAP : R/W ;bitpos:[21:14] ;default: 8'd0 ; */ 1122 /*description: SCK_DCAP*/ 1123 #define RTC_CNTL_SCK_DCAP 0x000000FF 1124 #define RTC_CNTL_SCK_DCAP_M ((RTC_CNTL_SCK_DCAP_V)<<(RTC_CNTL_SCK_DCAP_S)) 1125 #define RTC_CNTL_SCK_DCAP_V 0xFF 1126 #define RTC_CNTL_SCK_DCAP_S 14 1127 #define RTC_CNTL_SCK_DCAP_DEFAULT 255 1128 /* RTC_CNTL_DIG_DBIAS_WAK : R/W ;bitpos:[13:11] ;default: 3'd4 ; */ 1129 /*description: DIG_REG_DBIAS during wakeup*/ 1130 #define RTC_CNTL_DIG_DBIAS_WAK 0x00000007 1131 #define RTC_CNTL_DIG_DBIAS_WAK_M ((RTC_CNTL_DIG_DBIAS_WAK_V)<<(RTC_CNTL_DIG_DBIAS_WAK_S)) 1132 #define RTC_CNTL_DIG_DBIAS_WAK_V 0x7 1133 #define RTC_CNTL_DIG_DBIAS_WAK_S 11 1134 /* RTC_CNTL_DIG_DBIAS_SLP : R/W ;bitpos:[10:8] ;default: 3'd4 ; */ 1135 /*description: DIG_REG_DBIAS during sleep*/ 1136 #define RTC_CNTL_DIG_DBIAS_SLP 0x00000007 1137 #define RTC_CNTL_DIG_DBIAS_SLP_M ((RTC_CNTL_DIG_DBIAS_SLP_V)<<(RTC_CNTL_DIG_DBIAS_SLP_S)) 1138 #define RTC_CNTL_DIG_DBIAS_SLP_V 0x7 1139 #define RTC_CNTL_DIG_DBIAS_SLP_S 8 1140 /* RTC_CNTL_SCK_DCAP_FORCE : R/W ;bitpos:[7] ;default: 1'd0 ; */ 1141 /*description: N/A*/ 1142 #define RTC_CNTL_SCK_DCAP_FORCE (BIT(7)) 1143 #define RTC_CNTL_SCK_DCAP_FORCE_M (BIT(7)) 1144 #define RTC_CNTL_SCK_DCAP_FORCE_V 0x1 1145 #define RTC_CNTL_SCK_DCAP_FORCE_S 7 1146 1147 /* Approximate mapping of voltages to RTC_CNTL_DBIAS_WAK, RTC_CNTL_DBIAS_SLP, 1148 * RTC_CNTL_DIG_DBIAS_WAK, RTC_CNTL_DIG_DBIAS_SLP values. 1149 * Valid if RTC_CNTL_DBG_ATTEN is 0. 1150 */ 1151 #define RTC_CNTL_DBIAS_0V90 0 1152 #define RTC_CNTL_DBIAS_0V95 1 1153 #define RTC_CNTL_DBIAS_1V00 2 1154 #define RTC_CNTL_DBIAS_1V05 3 1155 #define RTC_CNTL_DBIAS_1V10 4 1156 #define RTC_CNTL_DBIAS_1V15 5 1157 #define RTC_CNTL_DBIAS_1V20 6 1158 #define RTC_CNTL_DBIAS_1V25 7 1159 1160 #define RTC_CNTL_PWC_REG (DR_REG_RTCCNTL_BASE + 0x80) 1161 /* RTC_CNTL_PD_EN : R/W ;bitpos:[20] ;default: 1'd0 ; */ 1162 /*description: enable power down rtc_peri in sleep*/ 1163 #define RTC_CNTL_PD_EN (BIT(20)) 1164 #define RTC_CNTL_PD_EN_M (BIT(20)) 1165 #define RTC_CNTL_PD_EN_V 0x1 1166 #define RTC_CNTL_PD_EN_S 20 1167 /* RTC_CNTL_FORCE_PU : R/W ;bitpos:[19] ;default: 1'd0 ; */ 1168 /*description: rtc_peri force power up*/ 1169 #define RTC_CNTL_PWC_FORCE_PU (BIT(19)) 1170 #define RTC_CNTL_PWC_FORCE_PU_M (BIT(19)) 1171 #define RTC_CNTL_PWC_FORCE_PU_V 0x1 1172 #define RTC_CNTL_PWC_FORCE_PU_S 19 1173 /* RTC_CNTL_FORCE_PD : R/W ;bitpos:[18] ;default: 1'b0 ; */ 1174 /*description: rtc_peri force power down*/ 1175 #define RTC_CNTL_PWC_FORCE_PD (BIT(18)) 1176 #define RTC_CNTL_PWC_FORCE_PD_M (BIT(18)) 1177 #define RTC_CNTL_PWC_FORCE_PD_V 0x1 1178 #define RTC_CNTL_PWC_FORCE_PD_S 18 1179 /* RTC_CNTL_SLOWMEM_PD_EN : R/W ;bitpos:[17] ;default: 1'b0 ; */ 1180 /*description: enable power down RTC memory in sleep*/ 1181 #define RTC_CNTL_SLOWMEM_PD_EN (BIT(17)) 1182 #define RTC_CNTL_SLOWMEM_PD_EN_M (BIT(17)) 1183 #define RTC_CNTL_SLOWMEM_PD_EN_V 0x1 1184 #define RTC_CNTL_SLOWMEM_PD_EN_S 17 1185 /* RTC_CNTL_SLOWMEM_FORCE_PU : R/W ;bitpos:[16] ;default: 1'b1 ; */ 1186 /*description: RTC memory force power up*/ 1187 #define RTC_CNTL_SLOWMEM_FORCE_PU (BIT(16)) 1188 #define RTC_CNTL_SLOWMEM_FORCE_PU_M (BIT(16)) 1189 #define RTC_CNTL_SLOWMEM_FORCE_PU_V 0x1 1190 #define RTC_CNTL_SLOWMEM_FORCE_PU_S 16 1191 /* RTC_CNTL_SLOWMEM_FORCE_PD : R/W ;bitpos:[15] ;default: 1'b0 ; */ 1192 /*description: RTC memory force power down*/ 1193 #define RTC_CNTL_SLOWMEM_FORCE_PD (BIT(15)) 1194 #define RTC_CNTL_SLOWMEM_FORCE_PD_M (BIT(15)) 1195 #define RTC_CNTL_SLOWMEM_FORCE_PD_V 0x1 1196 #define RTC_CNTL_SLOWMEM_FORCE_PD_S 15 1197 /* RTC_CNTL_FASTMEM_PD_EN : R/W ;bitpos:[14] ;default: 1'b0 ; */ 1198 /*description: enable power down fast RTC memory in sleep*/ 1199 #define RTC_CNTL_FASTMEM_PD_EN (BIT(14)) 1200 #define RTC_CNTL_FASTMEM_PD_EN_M (BIT(14)) 1201 #define RTC_CNTL_FASTMEM_PD_EN_V 0x1 1202 #define RTC_CNTL_FASTMEM_PD_EN_S 14 1203 /* RTC_CNTL_FASTMEM_FORCE_PU : R/W ;bitpos:[13] ;default: 1'b1 ; */ 1204 /*description: Fast RTC memory force power up*/ 1205 #define RTC_CNTL_FASTMEM_FORCE_PU (BIT(13)) 1206 #define RTC_CNTL_FASTMEM_FORCE_PU_M (BIT(13)) 1207 #define RTC_CNTL_FASTMEM_FORCE_PU_V 0x1 1208 #define RTC_CNTL_FASTMEM_FORCE_PU_S 13 1209 /* RTC_CNTL_FASTMEM_FORCE_PD : R/W ;bitpos:[12] ;default: 1'b0 ; */ 1210 /*description: Fast RTC memory force power down*/ 1211 #define RTC_CNTL_FASTMEM_FORCE_PD (BIT(12)) 1212 #define RTC_CNTL_FASTMEM_FORCE_PD_M (BIT(12)) 1213 #define RTC_CNTL_FASTMEM_FORCE_PD_V 0x1 1214 #define RTC_CNTL_FASTMEM_FORCE_PD_S 12 1215 /* RTC_CNTL_SLOWMEM_FORCE_LPU : R/W ;bitpos:[11] ;default: 1'b1 ; */ 1216 /*description: RTC memory force no PD*/ 1217 #define RTC_CNTL_SLOWMEM_FORCE_LPU (BIT(11)) 1218 #define RTC_CNTL_SLOWMEM_FORCE_LPU_M (BIT(11)) 1219 #define RTC_CNTL_SLOWMEM_FORCE_LPU_V 0x1 1220 #define RTC_CNTL_SLOWMEM_FORCE_LPU_S 11 1221 /* RTC_CNTL_SLOWMEM_FORCE_LPD : R/W ;bitpos:[10] ;default: 1'b0 ; */ 1222 /*description: RTC memory force PD*/ 1223 #define RTC_CNTL_SLOWMEM_FORCE_LPD (BIT(10)) 1224 #define RTC_CNTL_SLOWMEM_FORCE_LPD_M (BIT(10)) 1225 #define RTC_CNTL_SLOWMEM_FORCE_LPD_V 0x1 1226 #define RTC_CNTL_SLOWMEM_FORCE_LPD_S 10 1227 /* RTC_CNTL_SLOWMEM_FOLW_CPU : R/W ;bitpos:[9] ;default: 1'b0 ; */ 1228 /*description: 1: RTC memory PD following CPU 0: RTC memory PD following RTC state machine*/ 1229 #define RTC_CNTL_SLOWMEM_FOLW_CPU (BIT(9)) 1230 #define RTC_CNTL_SLOWMEM_FOLW_CPU_M (BIT(9)) 1231 #define RTC_CNTL_SLOWMEM_FOLW_CPU_V 0x1 1232 #define RTC_CNTL_SLOWMEM_FOLW_CPU_S 9 1233 /* RTC_CNTL_FASTMEM_FORCE_LPU : R/W ;bitpos:[8] ;default: 1'b1 ; */ 1234 /*description: Fast RTC memory force no PD*/ 1235 #define RTC_CNTL_FASTMEM_FORCE_LPU (BIT(8)) 1236 #define RTC_CNTL_FASTMEM_FORCE_LPU_M (BIT(8)) 1237 #define RTC_CNTL_FASTMEM_FORCE_LPU_V 0x1 1238 #define RTC_CNTL_FASTMEM_FORCE_LPU_S 8 1239 /* RTC_CNTL_FASTMEM_FORCE_LPD : R/W ;bitpos:[7] ;default: 1'b0 ; */ 1240 /*description: Fast RTC memory force PD*/ 1241 #define RTC_CNTL_FASTMEM_FORCE_LPD (BIT(7)) 1242 #define RTC_CNTL_FASTMEM_FORCE_LPD_M (BIT(7)) 1243 #define RTC_CNTL_FASTMEM_FORCE_LPD_V 0x1 1244 #define RTC_CNTL_FASTMEM_FORCE_LPD_S 7 1245 /* RTC_CNTL_FASTMEM_FOLW_CPU : R/W ;bitpos:[6] ;default: 1'b0 ; */ 1246 /*description: 1: Fast RTC memory PD following CPU 0: fast RTC memory PD following 1247 RTC state machine*/ 1248 #define RTC_CNTL_FASTMEM_FOLW_CPU (BIT(6)) 1249 #define RTC_CNTL_FASTMEM_FOLW_CPU_M (BIT(6)) 1250 #define RTC_CNTL_FASTMEM_FOLW_CPU_V 0x1 1251 #define RTC_CNTL_FASTMEM_FOLW_CPU_S 6 1252 /* RTC_CNTL_FORCE_NOISO : R/W ;bitpos:[5] ;default: 1'd1 ; */ 1253 /*description: rtc_peri force no ISO*/ 1254 #define RTC_CNTL_FORCE_NOISO (BIT(5)) 1255 #define RTC_CNTL_FORCE_NOISO_M (BIT(5)) 1256 #define RTC_CNTL_FORCE_NOISO_V 0x1 1257 #define RTC_CNTL_FORCE_NOISO_S 5 1258 /* RTC_CNTL_FORCE_ISO : R/W ;bitpos:[4] ;default: 1'd0 ; */ 1259 /*description: rtc_peri force ISO*/ 1260 #define RTC_CNTL_FORCE_ISO (BIT(4)) 1261 #define RTC_CNTL_FORCE_ISO_M (BIT(4)) 1262 #define RTC_CNTL_FORCE_ISO_V 0x1 1263 #define RTC_CNTL_FORCE_ISO_S 4 1264 /* RTC_CNTL_SLOWMEM_FORCE_ISO : R/W ;bitpos:[3] ;default: 1'b0 ; */ 1265 /*description: RTC memory force ISO*/ 1266 #define RTC_CNTL_SLOWMEM_FORCE_ISO (BIT(3)) 1267 #define RTC_CNTL_SLOWMEM_FORCE_ISO_M (BIT(3)) 1268 #define RTC_CNTL_SLOWMEM_FORCE_ISO_V 0x1 1269 #define RTC_CNTL_SLOWMEM_FORCE_ISO_S 3 1270 /* RTC_CNTL_SLOWMEM_FORCE_NOISO : R/W ;bitpos:[2] ;default: 1'b1 ; */ 1271 /*description: RTC memory force no ISO*/ 1272 #define RTC_CNTL_SLOWMEM_FORCE_NOISO (BIT(2)) 1273 #define RTC_CNTL_SLOWMEM_FORCE_NOISO_M (BIT(2)) 1274 #define RTC_CNTL_SLOWMEM_FORCE_NOISO_V 0x1 1275 #define RTC_CNTL_SLOWMEM_FORCE_NOISO_S 2 1276 /* RTC_CNTL_FASTMEM_FORCE_ISO : R/W ;bitpos:[1] ;default: 1'b0 ; */ 1277 /*description: Fast RTC memory force ISO*/ 1278 #define RTC_CNTL_FASTMEM_FORCE_ISO (BIT(1)) 1279 #define RTC_CNTL_FASTMEM_FORCE_ISO_M (BIT(1)) 1280 #define RTC_CNTL_FASTMEM_FORCE_ISO_V 0x1 1281 #define RTC_CNTL_FASTMEM_FORCE_ISO_S 1 1282 /* RTC_CNTL_FASTMEM_FORCE_NOISO : R/W ;bitpos:[0] ;default: 1'b1 ; */ 1283 /*description: Fast RTC memory force no ISO*/ 1284 #define RTC_CNTL_FASTMEM_FORCE_NOISO (BIT(0)) 1285 #define RTC_CNTL_FASTMEM_FORCE_NOISO_M (BIT(0)) 1286 #define RTC_CNTL_FASTMEM_FORCE_NOISO_V 0x1 1287 #define RTC_CNTL_FASTMEM_FORCE_NOISO_S 0 1288 1289 /* Useful groups of RTC_CNTL_PWC_REG bits */ 1290 #define RTC_CNTL_MEM_FORCE_ISO \ 1291 (RTC_CNTL_SLOWMEM_FORCE_ISO | RTC_CNTL_FASTMEM_FORCE_ISO) 1292 #define RTC_CNTL_MEM_FORCE_NOISO \ 1293 (RTC_CNTL_SLOWMEM_FORCE_NOISO | RTC_CNTL_FASTMEM_FORCE_NOISO) 1294 #define RTC_CNTL_MEM_PD_EN \ 1295 (RTC_CNTL_SLOWMEM_PD_EN | RTC_CNTL_FASTMEM_PD_EN) 1296 #define RTC_CNTL_MEM_FORCE_PU \ 1297 (RTC_CNTL_SLOWMEM_FORCE_PU | RTC_CNTL_FASTMEM_FORCE_PU) 1298 #define RTC_CNTL_MEM_FORCE_PD \ 1299 (RTC_CNTL_SLOWMEM_FORCE_PD | RTC_CNTL_FASTMEM_FORCE_PD) 1300 #define RTC_CNTL_MEM_FOLW_CPU \ 1301 (RTC_CNTL_SLOWMEM_FOLW_CPU | RTC_CNTL_FASTMEM_FOLW_CPU) 1302 #define RTC_CNTL_MEM_FORCE_LPU \ 1303 (RTC_CNTL_SLOWMEM_FORCE_LPU | RTC_CNTL_FASTMEM_FORCE_LPU) 1304 #define RTC_CNTL_MEM_FORCE_LPD \ 1305 (RTC_CNTL_SLOWMEM_FORCE_LPD | RTC_CNTL_FASTMEM_FORCE_LPD) 1306 1307 #define RTC_CNTL_DIG_PWC_REG (DR_REG_RTCCNTL_BASE + 0x84) 1308 /* RTC_CNTL_DG_WRAP_PD_EN : R/W ;bitpos:[31] ;default: 0 ; */ 1309 /*description: enable power down digital core in sleep*/ 1310 #define RTC_CNTL_DG_WRAP_PD_EN (BIT(31)) 1311 #define RTC_CNTL_DG_WRAP_PD_EN_M (BIT(31)) 1312 #define RTC_CNTL_DG_WRAP_PD_EN_V 0x1 1313 #define RTC_CNTL_DG_WRAP_PD_EN_S 31 1314 /* RTC_CNTL_WIFI_PD_EN : R/W ;bitpos:[30] ;default: 0 ; */ 1315 /*description: enable power down wifi in sleep*/ 1316 #define RTC_CNTL_WIFI_PD_EN (BIT(30)) 1317 #define RTC_CNTL_WIFI_PD_EN_M (BIT(30)) 1318 #define RTC_CNTL_WIFI_PD_EN_V 0x1 1319 #define RTC_CNTL_WIFI_PD_EN_S 30 1320 /* RTC_CNTL_INTER_RAM4_PD_EN : R/W ;bitpos:[29] ;default: 0 ; */ 1321 /*description: enable power down internal SRAM 4 in sleep*/ 1322 #define RTC_CNTL_INTER_RAM4_PD_EN (BIT(29)) 1323 #define RTC_CNTL_INTER_RAM4_PD_EN_M (BIT(29)) 1324 #define RTC_CNTL_INTER_RAM4_PD_EN_V 0x1 1325 #define RTC_CNTL_INTER_RAM4_PD_EN_S 29 1326 /* RTC_CNTL_INTER_RAM3_PD_EN : R/W ;bitpos:[28] ;default: 0 ; */ 1327 /*description: enable power down internal SRAM 3 in sleep*/ 1328 #define RTC_CNTL_INTER_RAM3_PD_EN (BIT(28)) 1329 #define RTC_CNTL_INTER_RAM3_PD_EN_M (BIT(28)) 1330 #define RTC_CNTL_INTER_RAM3_PD_EN_V 0x1 1331 #define RTC_CNTL_INTER_RAM3_PD_EN_S 28 1332 /* RTC_CNTL_INTER_RAM2_PD_EN : R/W ;bitpos:[27] ;default: 0 ; */ 1333 /*description: enable power down internal SRAM 2 in sleep*/ 1334 #define RTC_CNTL_INTER_RAM2_PD_EN (BIT(27)) 1335 #define RTC_CNTL_INTER_RAM2_PD_EN_M (BIT(27)) 1336 #define RTC_CNTL_INTER_RAM2_PD_EN_V 0x1 1337 #define RTC_CNTL_INTER_RAM2_PD_EN_S 27 1338 /* RTC_CNTL_INTER_RAM1_PD_EN : R/W ;bitpos:[26] ;default: 0 ; */ 1339 /*description: enable power down internal SRAM 1 in sleep*/ 1340 #define RTC_CNTL_INTER_RAM1_PD_EN (BIT(26)) 1341 #define RTC_CNTL_INTER_RAM1_PD_EN_M (BIT(26)) 1342 #define RTC_CNTL_INTER_RAM1_PD_EN_V 0x1 1343 #define RTC_CNTL_INTER_RAM1_PD_EN_S 26 1344 /* RTC_CNTL_INTER_RAM0_PD_EN : R/W ;bitpos:[25] ;default: 0 ; */ 1345 /*description: enable power down internal SRAM 0 in sleep*/ 1346 #define RTC_CNTL_INTER_RAM0_PD_EN (BIT(25)) 1347 #define RTC_CNTL_INTER_RAM0_PD_EN_M (BIT(25)) 1348 #define RTC_CNTL_INTER_RAM0_PD_EN_V 0x1 1349 #define RTC_CNTL_INTER_RAM0_PD_EN_S 25 1350 /* RTC_CNTL_ROM0_PD_EN : R/W ;bitpos:[24] ;default: 0 ; */ 1351 /*description: enable power down ROM in sleep*/ 1352 #define RTC_CNTL_ROM0_PD_EN (BIT(24)) 1353 #define RTC_CNTL_ROM0_PD_EN_M (BIT(24)) 1354 #define RTC_CNTL_ROM0_PD_EN_V 0x1 1355 #define RTC_CNTL_ROM0_PD_EN_S 24 1356 /* RTC_CNTL_DG_WRAP_FORCE_PU : R/W ;bitpos:[20] ;default: 1'd1 ; */ 1357 /*description: digital core force power up*/ 1358 #define RTC_CNTL_DG_WRAP_FORCE_PU (BIT(20)) 1359 #define RTC_CNTL_DG_WRAP_FORCE_PU_M (BIT(20)) 1360 #define RTC_CNTL_DG_WRAP_FORCE_PU_V 0x1 1361 #define RTC_CNTL_DG_WRAP_FORCE_PU_S 20 1362 /* RTC_CNTL_DG_WRAP_FORCE_PD : R/W ;bitpos:[19] ;default: 1'b0 ; */ 1363 /*description: digital core force power down*/ 1364 #define RTC_CNTL_DG_WRAP_FORCE_PD (BIT(19)) 1365 #define RTC_CNTL_DG_WRAP_FORCE_PD_M (BIT(19)) 1366 #define RTC_CNTL_DG_WRAP_FORCE_PD_V 0x1 1367 #define RTC_CNTL_DG_WRAP_FORCE_PD_S 19 1368 /* RTC_CNTL_WIFI_FORCE_PU : R/W ;bitpos:[18] ;default: 1'd1 ; */ 1369 /*description: wifi force power up*/ 1370 #define RTC_CNTL_WIFI_FORCE_PU (BIT(18)) 1371 #define RTC_CNTL_WIFI_FORCE_PU_M (BIT(18)) 1372 #define RTC_CNTL_WIFI_FORCE_PU_V 0x1 1373 #define RTC_CNTL_WIFI_FORCE_PU_S 18 1374 /* RTC_CNTL_WIFI_FORCE_PD : R/W ;bitpos:[17] ;default: 1'b0 ; */ 1375 /*description: wifi force power down*/ 1376 #define RTC_CNTL_WIFI_FORCE_PD (BIT(17)) 1377 #define RTC_CNTL_WIFI_FORCE_PD_M (BIT(17)) 1378 #define RTC_CNTL_WIFI_FORCE_PD_V 0x1 1379 #define RTC_CNTL_WIFI_FORCE_PD_S 17 1380 /* RTC_CNTL_INTER_RAM4_FORCE_PU : R/W ;bitpos:[16] ;default: 1'd1 ; */ 1381 /*description: internal SRAM 4 force power up*/ 1382 #define RTC_CNTL_INTER_RAM4_FORCE_PU (BIT(16)) 1383 #define RTC_CNTL_INTER_RAM4_FORCE_PU_M (BIT(16)) 1384 #define RTC_CNTL_INTER_RAM4_FORCE_PU_V 0x1 1385 #define RTC_CNTL_INTER_RAM4_FORCE_PU_S 16 1386 /* RTC_CNTL_INTER_RAM4_FORCE_PD : R/W ;bitpos:[15] ;default: 1'b0 ; */ 1387 /*description: internal SRAM 4 force power down*/ 1388 #define RTC_CNTL_INTER_RAM4_FORCE_PD (BIT(15)) 1389 #define RTC_CNTL_INTER_RAM4_FORCE_PD_M (BIT(15)) 1390 #define RTC_CNTL_INTER_RAM4_FORCE_PD_V 0x1 1391 #define RTC_CNTL_INTER_RAM4_FORCE_PD_S 15 1392 /* RTC_CNTL_INTER_RAM3_FORCE_PU : R/W ;bitpos:[14] ;default: 1'd1 ; */ 1393 /*description: internal SRAM 3 force power up*/ 1394 #define RTC_CNTL_INTER_RAM3_FORCE_PU (BIT(14)) 1395 #define RTC_CNTL_INTER_RAM3_FORCE_PU_M (BIT(14)) 1396 #define RTC_CNTL_INTER_RAM3_FORCE_PU_V 0x1 1397 #define RTC_CNTL_INTER_RAM3_FORCE_PU_S 14 1398 /* RTC_CNTL_INTER_RAM3_FORCE_PD : R/W ;bitpos:[13] ;default: 1'b0 ; */ 1399 /*description: internal SRAM 3 force power down*/ 1400 #define RTC_CNTL_INTER_RAM3_FORCE_PD (BIT(13)) 1401 #define RTC_CNTL_INTER_RAM3_FORCE_PD_M (BIT(13)) 1402 #define RTC_CNTL_INTER_RAM3_FORCE_PD_V 0x1 1403 #define RTC_CNTL_INTER_RAM3_FORCE_PD_S 13 1404 /* RTC_CNTL_INTER_RAM2_FORCE_PU : R/W ;bitpos:[12] ;default: 1'd1 ; */ 1405 /*description: internal SRAM 2 force power up*/ 1406 #define RTC_CNTL_INTER_RAM2_FORCE_PU (BIT(12)) 1407 #define RTC_CNTL_INTER_RAM2_FORCE_PU_M (BIT(12)) 1408 #define RTC_CNTL_INTER_RAM2_FORCE_PU_V 0x1 1409 #define RTC_CNTL_INTER_RAM2_FORCE_PU_S 12 1410 /* RTC_CNTL_INTER_RAM2_FORCE_PD : R/W ;bitpos:[11] ;default: 1'b0 ; */ 1411 /*description: internal SRAM 2 force power down*/ 1412 #define RTC_CNTL_INTER_RAM2_FORCE_PD (BIT(11)) 1413 #define RTC_CNTL_INTER_RAM2_FORCE_PD_M (BIT(11)) 1414 #define RTC_CNTL_INTER_RAM2_FORCE_PD_V 0x1 1415 #define RTC_CNTL_INTER_RAM2_FORCE_PD_S 11 1416 /* RTC_CNTL_INTER_RAM1_FORCE_PU : R/W ;bitpos:[10] ;default: 1'd1 ; */ 1417 /*description: internal SRAM 1 force power up*/ 1418 #define RTC_CNTL_INTER_RAM1_FORCE_PU (BIT(10)) 1419 #define RTC_CNTL_INTER_RAM1_FORCE_PU_M (BIT(10)) 1420 #define RTC_CNTL_INTER_RAM1_FORCE_PU_V 0x1 1421 #define RTC_CNTL_INTER_RAM1_FORCE_PU_S 10 1422 /* RTC_CNTL_INTER_RAM1_FORCE_PD : R/W ;bitpos:[9] ;default: 1'b0 ; */ 1423 /*description: internal SRAM 1 force power down*/ 1424 #define RTC_CNTL_INTER_RAM1_FORCE_PD (BIT(9)) 1425 #define RTC_CNTL_INTER_RAM1_FORCE_PD_M (BIT(9)) 1426 #define RTC_CNTL_INTER_RAM1_FORCE_PD_V 0x1 1427 #define RTC_CNTL_INTER_RAM1_FORCE_PD_S 9 1428 /* RTC_CNTL_INTER_RAM0_FORCE_PU : R/W ;bitpos:[8] ;default: 1'd1 ; */ 1429 /*description: internal SRAM 0 force power up*/ 1430 #define RTC_CNTL_INTER_RAM0_FORCE_PU (BIT(8)) 1431 #define RTC_CNTL_INTER_RAM0_FORCE_PU_M (BIT(8)) 1432 #define RTC_CNTL_INTER_RAM0_FORCE_PU_V 0x1 1433 #define RTC_CNTL_INTER_RAM0_FORCE_PU_S 8 1434 /* RTC_CNTL_INTER_RAM0_FORCE_PD : R/W ;bitpos:[7] ;default: 1'b0 ; */ 1435 /*description: internal SRAM 0 force power down*/ 1436 #define RTC_CNTL_INTER_RAM0_FORCE_PD (BIT(7)) 1437 #define RTC_CNTL_INTER_RAM0_FORCE_PD_M (BIT(7)) 1438 #define RTC_CNTL_INTER_RAM0_FORCE_PD_V 0x1 1439 #define RTC_CNTL_INTER_RAM0_FORCE_PD_S 7 1440 /* RTC_CNTL_ROM0_FORCE_PU : R/W ;bitpos:[6] ;default: 1'd1 ; */ 1441 /*description: ROM force power up*/ 1442 #define RTC_CNTL_ROM0_FORCE_PU (BIT(6)) 1443 #define RTC_CNTL_ROM0_FORCE_PU_M (BIT(6)) 1444 #define RTC_CNTL_ROM0_FORCE_PU_V 0x1 1445 #define RTC_CNTL_ROM0_FORCE_PU_S 6 1446 /* RTC_CNTL_ROM0_FORCE_PD : R/W ;bitpos:[5] ;default: 1'b0 ; */ 1447 /*description: ROM force power down*/ 1448 #define RTC_CNTL_ROM0_FORCE_PD (BIT(5)) 1449 #define RTC_CNTL_ROM0_FORCE_PD_M (BIT(5)) 1450 #define RTC_CNTL_ROM0_FORCE_PD_V 0x1 1451 #define RTC_CNTL_ROM0_FORCE_PD_S 5 1452 /* RTC_CNTL_LSLP_MEM_FORCE_PU : R/W ;bitpos:[4] ;default: 1'b1 ; */ 1453 /*description: memories in digital core force no PD in sleep*/ 1454 #define RTC_CNTL_LSLP_MEM_FORCE_PU (BIT(4)) 1455 #define RTC_CNTL_LSLP_MEM_FORCE_PU_M (BIT(4)) 1456 #define RTC_CNTL_LSLP_MEM_FORCE_PU_V 0x1 1457 #define RTC_CNTL_LSLP_MEM_FORCE_PU_S 4 1458 /* RTC_CNTL_LSLP_MEM_FORCE_PD : R/W ;bitpos:[3] ;default: 1'b0 ; */ 1459 /*description: memories in digital core force PD in sleep*/ 1460 #define RTC_CNTL_LSLP_MEM_FORCE_PD (BIT(3)) 1461 #define RTC_CNTL_LSLP_MEM_FORCE_PD_M (BIT(3)) 1462 #define RTC_CNTL_LSLP_MEM_FORCE_PD_V 0x1 1463 #define RTC_CNTL_LSLP_MEM_FORCE_PD_S 3 1464 1465 /* Useful groups of RTC_CNTL_DIG_PWC_REG bits */ 1466 #define RTC_CNTL_CPU_ROM_RAM_PD_EN \ 1467 (RTC_CNTL_INTER_RAM4_PD_EN | RTC_CNTL_INTER_RAM3_PD_EN |\ 1468 RTC_CNTL_INTER_RAM2_PD_EN | RTC_CNTL_INTER_RAM1_PD_EN |\ 1469 RTC_CNTL_INTER_RAM0_PD_EN | RTC_CNTL_ROM0_PD_EN) 1470 #define RTC_CNTL_CPU_ROM_RAM_FORCE_PU \ 1471 (RTC_CNTL_INTER_RAM4_FORCE_PU | RTC_CNTL_INTER_RAM3_FORCE_PU |\ 1472 RTC_CNTL_INTER_RAM2_FORCE_PU | RTC_CNTL_INTER_RAM1_FORCE_PU |\ 1473 RTC_CNTL_INTER_RAM0_FORCE_PU | RTC_CNTL_ROM0_FORCE_PU) 1474 #define RTC_CNTL_CPU_ROM_RAM_FORCE_PD \ 1475 (RTC_CNTL_INTER_RAM4_FORCE_PD | RTC_CNTL_INTER_RAM3_FORCE_PD |\ 1476 RTC_CNTL_INTER_RAM2_FORCE_PD | RTC_CNTL_INTER_RAM1_FORCE_PD |\ 1477 RTC_CNTL_INTER_RAM0_FORCE_PD | RTC_CNTL_ROM0_FORCE_PD 1478 1479 #define RTC_CNTL_DIG_ISO_REG (DR_REG_RTCCNTL_BASE + 0x88) 1480 /* RTC_CNTL_DG_WRAP_FORCE_NOISO : R/W ;bitpos:[31] ;default: 1'd1 ; */ 1481 /*description: digital core force no ISO*/ 1482 #define RTC_CNTL_DG_WRAP_FORCE_NOISO (BIT(31)) 1483 #define RTC_CNTL_DG_WRAP_FORCE_NOISO_M (BIT(31)) 1484 #define RTC_CNTL_DG_WRAP_FORCE_NOISO_V 0x1 1485 #define RTC_CNTL_DG_WRAP_FORCE_NOISO_S 31 1486 /* RTC_CNTL_DG_WRAP_FORCE_ISO : R/W ;bitpos:[30] ;default: 1'd0 ; */ 1487 /*description: digital core force ISO*/ 1488 #define RTC_CNTL_DG_WRAP_FORCE_ISO (BIT(30)) 1489 #define RTC_CNTL_DG_WRAP_FORCE_ISO_M (BIT(30)) 1490 #define RTC_CNTL_DG_WRAP_FORCE_ISO_V 0x1 1491 #define RTC_CNTL_DG_WRAP_FORCE_ISO_S 30 1492 /* RTC_CNTL_WIFI_FORCE_NOISO : R/W ;bitpos:[29] ;default: 1'd1 ; */ 1493 /*description: wifi force no ISO*/ 1494 #define RTC_CNTL_WIFI_FORCE_NOISO (BIT(29)) 1495 #define RTC_CNTL_WIFI_FORCE_NOISO_M (BIT(29)) 1496 #define RTC_CNTL_WIFI_FORCE_NOISO_V 0x1 1497 #define RTC_CNTL_WIFI_FORCE_NOISO_S 29 1498 /* RTC_CNTL_WIFI_FORCE_ISO : R/W ;bitpos:[28] ;default: 1'd0 ; */ 1499 /*description: wifi force ISO*/ 1500 #define RTC_CNTL_WIFI_FORCE_ISO (BIT(28)) 1501 #define RTC_CNTL_WIFI_FORCE_ISO_M (BIT(28)) 1502 #define RTC_CNTL_WIFI_FORCE_ISO_V 0x1 1503 #define RTC_CNTL_WIFI_FORCE_ISO_S 28 1504 /* RTC_CNTL_INTER_RAM4_FORCE_NOISO : R/W ;bitpos:[27] ;default: 1'd1 ; */ 1505 /*description: internal SRAM 4 force no ISO*/ 1506 #define RTC_CNTL_INTER_RAM4_FORCE_NOISO (BIT(27)) 1507 #define RTC_CNTL_INTER_RAM4_FORCE_NOISO_M (BIT(27)) 1508 #define RTC_CNTL_INTER_RAM4_FORCE_NOISO_V 0x1 1509 #define RTC_CNTL_INTER_RAM4_FORCE_NOISO_S 27 1510 /* RTC_CNTL_INTER_RAM4_FORCE_ISO : R/W ;bitpos:[26] ;default: 1'd0 ; */ 1511 /*description: internal SRAM 4 force ISO*/ 1512 #define RTC_CNTL_INTER_RAM4_FORCE_ISO (BIT(26)) 1513 #define RTC_CNTL_INTER_RAM4_FORCE_ISO_M (BIT(26)) 1514 #define RTC_CNTL_INTER_RAM4_FORCE_ISO_V 0x1 1515 #define RTC_CNTL_INTER_RAM4_FORCE_ISO_S 26 1516 /* RTC_CNTL_INTER_RAM3_FORCE_NOISO : R/W ;bitpos:[25] ;default: 1'd1 ; */ 1517 /*description: internal SRAM 3 force no ISO*/ 1518 #define RTC_CNTL_INTER_RAM3_FORCE_NOISO (BIT(25)) 1519 #define RTC_CNTL_INTER_RAM3_FORCE_NOISO_M (BIT(25)) 1520 #define RTC_CNTL_INTER_RAM3_FORCE_NOISO_V 0x1 1521 #define RTC_CNTL_INTER_RAM3_FORCE_NOISO_S 25 1522 /* RTC_CNTL_INTER_RAM3_FORCE_ISO : R/W ;bitpos:[24] ;default: 1'd0 ; */ 1523 /*description: internal SRAM 3 force ISO*/ 1524 #define RTC_CNTL_INTER_RAM3_FORCE_ISO (BIT(24)) 1525 #define RTC_CNTL_INTER_RAM3_FORCE_ISO_M (BIT(24)) 1526 #define RTC_CNTL_INTER_RAM3_FORCE_ISO_V 0x1 1527 #define RTC_CNTL_INTER_RAM3_FORCE_ISO_S 24 1528 /* RTC_CNTL_INTER_RAM2_FORCE_NOISO : R/W ;bitpos:[23] ;default: 1'd1 ; */ 1529 /*description: internal SRAM 2 force no ISO*/ 1530 #define RTC_CNTL_INTER_RAM2_FORCE_NOISO (BIT(23)) 1531 #define RTC_CNTL_INTER_RAM2_FORCE_NOISO_M (BIT(23)) 1532 #define RTC_CNTL_INTER_RAM2_FORCE_NOISO_V 0x1 1533 #define RTC_CNTL_INTER_RAM2_FORCE_NOISO_S 23 1534 /* RTC_CNTL_INTER_RAM2_FORCE_ISO : R/W ;bitpos:[22] ;default: 1'd0 ; */ 1535 /*description: internal SRAM 2 force ISO*/ 1536 #define RTC_CNTL_INTER_RAM2_FORCE_ISO (BIT(22)) 1537 #define RTC_CNTL_INTER_RAM2_FORCE_ISO_M (BIT(22)) 1538 #define RTC_CNTL_INTER_RAM2_FORCE_ISO_V 0x1 1539 #define RTC_CNTL_INTER_RAM2_FORCE_ISO_S 22 1540 /* RTC_CNTL_INTER_RAM1_FORCE_NOISO : R/W ;bitpos:[21] ;default: 1'd1 ; */ 1541 /*description: internal SRAM 1 force no ISO*/ 1542 #define RTC_CNTL_INTER_RAM1_FORCE_NOISO (BIT(21)) 1543 #define RTC_CNTL_INTER_RAM1_FORCE_NOISO_M (BIT(21)) 1544 #define RTC_CNTL_INTER_RAM1_FORCE_NOISO_V 0x1 1545 #define RTC_CNTL_INTER_RAM1_FORCE_NOISO_S 21 1546 /* RTC_CNTL_INTER_RAM1_FORCE_ISO : R/W ;bitpos:[20] ;default: 1'd0 ; */ 1547 /*description: internal SRAM 1 force ISO*/ 1548 #define RTC_CNTL_INTER_RAM1_FORCE_ISO (BIT(20)) 1549 #define RTC_CNTL_INTER_RAM1_FORCE_ISO_M (BIT(20)) 1550 #define RTC_CNTL_INTER_RAM1_FORCE_ISO_V 0x1 1551 #define RTC_CNTL_INTER_RAM1_FORCE_ISO_S 20 1552 /* RTC_CNTL_INTER_RAM0_FORCE_NOISO : R/W ;bitpos:[19] ;default: 1'd1 ; */ 1553 /*description: internal SRAM 0 force no ISO*/ 1554 #define RTC_CNTL_INTER_RAM0_FORCE_NOISO (BIT(19)) 1555 #define RTC_CNTL_INTER_RAM0_FORCE_NOISO_M (BIT(19)) 1556 #define RTC_CNTL_INTER_RAM0_FORCE_NOISO_V 0x1 1557 #define RTC_CNTL_INTER_RAM0_FORCE_NOISO_S 19 1558 /* RTC_CNTL_INTER_RAM0_FORCE_ISO : R/W ;bitpos:[18] ;default: 1'd0 ; */ 1559 /*description: internal SRAM 0 force ISO*/ 1560 #define RTC_CNTL_INTER_RAM0_FORCE_ISO (BIT(18)) 1561 #define RTC_CNTL_INTER_RAM0_FORCE_ISO_M (BIT(18)) 1562 #define RTC_CNTL_INTER_RAM0_FORCE_ISO_V 0x1 1563 #define RTC_CNTL_INTER_RAM0_FORCE_ISO_S 18 1564 /* RTC_CNTL_ROM0_FORCE_NOISO : R/W ;bitpos:[17] ;default: 1'd1 ; */ 1565 /*description: ROM force no ISO*/ 1566 #define RTC_CNTL_ROM0_FORCE_NOISO (BIT(17)) 1567 #define RTC_CNTL_ROM0_FORCE_NOISO_M (BIT(17)) 1568 #define RTC_CNTL_ROM0_FORCE_NOISO_V 0x1 1569 #define RTC_CNTL_ROM0_FORCE_NOISO_S 17 1570 /* RTC_CNTL_ROM0_FORCE_ISO : R/W ;bitpos:[16] ;default: 1'd0 ; */ 1571 /*description: ROM force ISO*/ 1572 #define RTC_CNTL_ROM0_FORCE_ISO (BIT(16)) 1573 #define RTC_CNTL_ROM0_FORCE_ISO_M (BIT(16)) 1574 #define RTC_CNTL_ROM0_FORCE_ISO_V 0x1 1575 #define RTC_CNTL_ROM0_FORCE_ISO_S 16 1576 /* RTC_CNTL_DG_PAD_FORCE_HOLD : R/W ;bitpos:[15] ;default: 1'd0 ; */ 1577 /*description: digital pad force hold*/ 1578 #define RTC_CNTL_DG_PAD_FORCE_HOLD (BIT(15)) 1579 #define RTC_CNTL_DG_PAD_FORCE_HOLD_M (BIT(15)) 1580 #define RTC_CNTL_DG_PAD_FORCE_HOLD_V 0x1 1581 #define RTC_CNTL_DG_PAD_FORCE_HOLD_S 15 1582 /* RTC_CNTL_DG_PAD_FORCE_UNHOLD : R/W ;bitpos:[14] ;default: 1'd1 ; */ 1583 /*description: digital pad force un-hold*/ 1584 #define RTC_CNTL_DG_PAD_FORCE_UNHOLD (BIT(14)) 1585 #define RTC_CNTL_DG_PAD_FORCE_UNHOLD_M (BIT(14)) 1586 #define RTC_CNTL_DG_PAD_FORCE_UNHOLD_V 0x1 1587 #define RTC_CNTL_DG_PAD_FORCE_UNHOLD_S 14 1588 /* RTC_CNTL_DG_PAD_FORCE_ISO : R/W ;bitpos:[13] ;default: 1'd0 ; */ 1589 /*description: digital pad force ISO*/ 1590 #define RTC_CNTL_DG_PAD_FORCE_ISO (BIT(13)) 1591 #define RTC_CNTL_DG_PAD_FORCE_ISO_M (BIT(13)) 1592 #define RTC_CNTL_DG_PAD_FORCE_ISO_V 0x1 1593 #define RTC_CNTL_DG_PAD_FORCE_ISO_S 13 1594 /* RTC_CNTL_DG_PAD_FORCE_NOISO : R/W ;bitpos:[12] ;default: 1'd1 ; */ 1595 /*description: digital pad force no ISO*/ 1596 #define RTC_CNTL_DG_PAD_FORCE_NOISO (BIT(12)) 1597 #define RTC_CNTL_DG_PAD_FORCE_NOISO_M (BIT(12)) 1598 #define RTC_CNTL_DG_PAD_FORCE_NOISO_V 0x1 1599 #define RTC_CNTL_DG_PAD_FORCE_NOISO_S 12 1600 /* RTC_CNTL_DG_PAD_AUTOHOLD_EN : R/W ;bitpos:[11] ;default: 1'd0 ; */ 1601 /*description: digital pad enable auto-hold*/ 1602 #define RTC_CNTL_DG_PAD_AUTOHOLD_EN (BIT(11)) 1603 #define RTC_CNTL_DG_PAD_AUTOHOLD_EN_M (BIT(11)) 1604 #define RTC_CNTL_DG_PAD_AUTOHOLD_EN_V 0x1 1605 #define RTC_CNTL_DG_PAD_AUTOHOLD_EN_S 11 1606 /* RTC_CNTL_CLR_DG_PAD_AUTOHOLD : WO ;bitpos:[10] ;default: 1'd0 ; */ 1607 /*description: wtite only register to clear digital pad auto-hold*/ 1608 #define RTC_CNTL_CLR_DG_PAD_AUTOHOLD (BIT(10)) 1609 #define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_M (BIT(10)) 1610 #define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_V 0x1 1611 #define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_S 10 1612 /* RTC_CNTL_DG_PAD_AUTOHOLD : RO ;bitpos:[9] ;default: 1'd0 ; */ 1613 /*description: read only register to indicate digital pad auto-hold status*/ 1614 #define RTC_CNTL_DG_PAD_AUTOHOLD (BIT(9)) 1615 #define RTC_CNTL_DG_PAD_AUTOHOLD_M (BIT(9)) 1616 #define RTC_CNTL_DG_PAD_AUTOHOLD_V 0x1 1617 #define RTC_CNTL_DG_PAD_AUTOHOLD_S 9 1618 /* RTC_CNTL_DIG_ISO_FORCE_ON : R/W ;bitpos:[8] ;default: 1'd0 ; */ 1619 /*description: */ 1620 #define RTC_CNTL_DIG_ISO_FORCE_ON (BIT(8)) 1621 #define RTC_CNTL_DIG_ISO_FORCE_ON_M (BIT(8)) 1622 #define RTC_CNTL_DIG_ISO_FORCE_ON_V 0x1 1623 #define RTC_CNTL_DIG_ISO_FORCE_ON_S 8 1624 /* RTC_CNTL_DIG_ISO_FORCE_OFF : R/W ;bitpos:[7] ;default: 1'd0 ; */ 1625 /*description: */ 1626 #define RTC_CNTL_DIG_ISO_FORCE_OFF (BIT(7)) 1627 #define RTC_CNTL_DIG_ISO_FORCE_OFF_M (BIT(7)) 1628 #define RTC_CNTL_DIG_ISO_FORCE_OFF_V 0x1 1629 #define RTC_CNTL_DIG_ISO_FORCE_OFF_S 7 1630 1631 /* Useful groups of RTC_CNTL_DIG_ISO_REG bits */ 1632 #define RTC_CNTL_CPU_ROM_RAM_FORCE_ISO \ 1633 (RTC_CNTL_INTER_RAM4_FORCE_ISO | RTC_CNTL_INTER_RAM3_FORCE_ISO |\ 1634 RTC_CNTL_INTER_RAM2_FORCE_ISO | RTC_CNTL_INTER_RAM1_FORCE_ISO |\ 1635 RTC_CNTL_INTER_RAM0_FORCE_ISO | RTC_CNTL_ROM0_FORCE_ISO) 1636 #define RTC_CNTL_CPU_ROM_RAM_FORCE_NOISO \ 1637 (RTC_CNTL_INTER_RAM4_FORCE_NOISO | RTC_CNTL_INTER_RAM3_FORCE_NOISO |\ 1638 RTC_CNTL_INTER_RAM2_FORCE_NOISO | RTC_CNTL_INTER_RAM1_FORCE_NOISO |\ 1639 RTC_CNTL_INTER_RAM0_FORCE_NOISO | RTC_CNTL_ROM0_FORCE_NOISO) 1640 1641 #define RTC_CNTL_WDTCONFIG0_REG (DR_REG_RTCCNTL_BASE + 0x8c) 1642 /* RTC_CNTL_WDT_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */ 1643 /*description: enable RTC WDT*/ 1644 #define RTC_CNTL_WDT_EN (BIT(31)) 1645 #define RTC_CNTL_WDT_EN_M (BIT(31)) 1646 #define RTC_CNTL_WDT_EN_V 0x1 1647 #define RTC_CNTL_WDT_EN_S 31 1648 /* RTC_CNTL_WDT_STG0 : R/W ;bitpos:[30:28] ;default: 3'h0 ; */ 1649 /*description: 1: interrupt stage en 2: CPU reset stage en 3: system reset 1650 stage en 4: RTC reset stage en*/ 1651 #define RTC_CNTL_WDT_STG0 0x00000007 1652 #define RTC_CNTL_WDT_STG0_M ((RTC_CNTL_WDT_STG0_V)<<(RTC_CNTL_WDT_STG0_S)) 1653 #define RTC_CNTL_WDT_STG0_V 0x7 1654 #define RTC_CNTL_WDT_STG0_S 28 1655 /* RTC_CNTL_WDT_STG1 : R/W ;bitpos:[27:25] ;default: 3'h0 ; */ 1656 /*description: 1: interrupt stage en 2: CPU reset stage en 3: system reset 1657 stage en 4: RTC reset stage en*/ 1658 #define RTC_CNTL_WDT_STG1 0x00000007 1659 #define RTC_CNTL_WDT_STG1_M ((RTC_CNTL_WDT_STG1_V)<<(RTC_CNTL_WDT_STG1_S)) 1660 #define RTC_CNTL_WDT_STG1_V 0x7 1661 #define RTC_CNTL_WDT_STG1_S 25 1662 /* RTC_CNTL_WDT_STG2 : R/W ;bitpos:[24:22] ;default: 3'h0 ; */ 1663 /*description: 1: interrupt stage en 2: CPU reset stage en 3: system reset 1664 stage en 4: RTC reset stage en*/ 1665 #define RTC_CNTL_WDT_STG2 0x00000007 1666 #define RTC_CNTL_WDT_STG2_M ((RTC_CNTL_WDT_STG2_V)<<(RTC_CNTL_WDT_STG2_S)) 1667 #define RTC_CNTL_WDT_STG2_V 0x7 1668 #define RTC_CNTL_WDT_STG2_S 22 1669 /* RTC_CNTL_WDT_STG3 : R/W ;bitpos:[21:19] ;default: 3'h0 ; */ 1670 /*description: 1: interrupt stage en 2: CPU reset stage en 3: system reset 1671 stage en 4: RTC reset stage en*/ 1672 #define RTC_CNTL_WDT_STG3 0x00000007 1673 #define RTC_CNTL_WDT_STG3_M ((RTC_CNTL_WDT_STG3_V)<<(RTC_CNTL_WDT_STG3_S)) 1674 #define RTC_CNTL_WDT_STG3_V 0x7 1675 #define RTC_CNTL_WDT_STG3_S 19 1676 /* RTC_CNTL_WDT_EDGE_INT_EN : R/W ;bitpos:[18] ;default: 1'h0 ; */ 1677 /*description: N/A*/ 1678 #define RTC_CNTL_WDT_EDGE_INT_EN (BIT(18)) 1679 #define RTC_CNTL_WDT_EDGE_INT_EN_M (BIT(18)) 1680 #define RTC_CNTL_WDT_EDGE_INT_EN_V 0x1 1681 #define RTC_CNTL_WDT_EDGE_INT_EN_S 18 1682 /* RTC_CNTL_WDT_LEVEL_INT_EN : R/W ;bitpos:[17] ;default: 1'h0 ; */ 1683 /*description: N/A*/ 1684 #define RTC_CNTL_WDT_LEVEL_INT_EN (BIT(17)) 1685 #define RTC_CNTL_WDT_LEVEL_INT_EN_M (BIT(17)) 1686 #define RTC_CNTL_WDT_LEVEL_INT_EN_V 0x1 1687 #define RTC_CNTL_WDT_LEVEL_INT_EN_S 17 1688 /* RTC_CNTL_WDT_CPU_RESET_LENGTH : R/W ;bitpos:[16:14] ;default: 3'h1 ; */ 1689 /*description: CPU reset counter length*/ 1690 #define RTC_CNTL_WDT_CPU_RESET_LENGTH 0x00000007 1691 #define RTC_CNTL_WDT_CPU_RESET_LENGTH_M ((RTC_CNTL_WDT_CPU_RESET_LENGTH_V)<<(RTC_CNTL_WDT_CPU_RESET_LENGTH_S)) 1692 #define RTC_CNTL_WDT_CPU_RESET_LENGTH_V 0x7 1693 #define RTC_CNTL_WDT_CPU_RESET_LENGTH_S 14 1694 /* RTC_CNTL_WDT_SYS_RESET_LENGTH : R/W ;bitpos:[13:11] ;default: 3'h1 ; */ 1695 /*description: system reset counter length*/ 1696 #define RTC_CNTL_WDT_SYS_RESET_LENGTH 0x00000007 1697 #define RTC_CNTL_WDT_SYS_RESET_LENGTH_M ((RTC_CNTL_WDT_SYS_RESET_LENGTH_V)<<(RTC_CNTL_WDT_SYS_RESET_LENGTH_S)) 1698 #define RTC_CNTL_WDT_SYS_RESET_LENGTH_V 0x7 1699 #define RTC_CNTL_WDT_SYS_RESET_LENGTH_S 11 1700 /* RTC_CNTL_WDT_FLASHBOOT_MOD_EN : R/W ;bitpos:[10] ;default: 1'h1 ; */ 1701 /*description: enable WDT in flash boot*/ 1702 #define RTC_CNTL_WDT_FLASHBOOT_MOD_EN (BIT(10)) 1703 #define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_M (BIT(10)) 1704 #define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_V 0x1 1705 #define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_S 10 1706 /* RTC_CNTL_WDT_PROCPU_RESET_EN : R/W ;bitpos:[9] ;default: 1'd0 ; */ 1707 /*description: enable WDT reset PRO CPU*/ 1708 #define RTC_CNTL_WDT_PROCPU_RESET_EN (BIT(9)) 1709 #define RTC_CNTL_WDT_PROCPU_RESET_EN_M (BIT(9)) 1710 #define RTC_CNTL_WDT_PROCPU_RESET_EN_V 0x1 1711 #define RTC_CNTL_WDT_PROCPU_RESET_EN_S 9 1712 /* RTC_CNTL_WDT_APPCPU_RESET_EN : R/W ;bitpos:[8] ;default: 1'd0 ; */ 1713 /*description: enable WDT reset APP CPU*/ 1714 #define RTC_CNTL_WDT_APPCPU_RESET_EN (BIT(8)) 1715 #define RTC_CNTL_WDT_APPCPU_RESET_EN_M (BIT(8)) 1716 #define RTC_CNTL_WDT_APPCPU_RESET_EN_V 0x1 1717 #define RTC_CNTL_WDT_APPCPU_RESET_EN_S 8 1718 /* RTC_CNTL_WDT_PAUSE_IN_SLP : R/W ;bitpos:[7] ;default: 1'd1 ; */ 1719 /*description: pause WDT in sleep*/ 1720 #define RTC_CNTL_WDT_PAUSE_IN_SLP (BIT(7)) 1721 #define RTC_CNTL_WDT_PAUSE_IN_SLP_M (BIT(7)) 1722 #define RTC_CNTL_WDT_PAUSE_IN_SLP_V 0x1 1723 #define RTC_CNTL_WDT_PAUSE_IN_SLP_S 7 1724 /* RTC_CNTL_WDT_STGX : */ 1725 /*description: stage action selection values */ 1726 #define RTC_WDT_STG_SEL_OFF 0 1727 #define RTC_WDT_STG_SEL_INT 1 1728 #define RTC_WDT_STG_SEL_RESET_CPU 2 1729 #define RTC_WDT_STG_SEL_RESET_SYSTEM 3 1730 #define RTC_WDT_STG_SEL_RESET_RTC 4 1731 1732 #define RTC_CNTL_WDTCONFIG1_REG (DR_REG_RTCCNTL_BASE + 0x90) 1733 /* RTC_CNTL_WDT_STG0_HOLD : R/W ;bitpos:[31:0] ;default: 32'd128000 ; */ 1734 /*description: */ 1735 #define RTC_CNTL_WDT_STG0_HOLD 0xFFFFFFFF 1736 #define RTC_CNTL_WDT_STG0_HOLD_M ((RTC_CNTL_WDT_STG0_HOLD_V)<<(RTC_CNTL_WDT_STG0_HOLD_S)) 1737 #define RTC_CNTL_WDT_STG0_HOLD_V 0xFFFFFFFF 1738 #define RTC_CNTL_WDT_STG0_HOLD_S 0 1739 1740 #define RTC_CNTL_WDTCONFIG2_REG (DR_REG_RTCCNTL_BASE + 0x94) 1741 /* RTC_CNTL_WDT_STG1_HOLD : R/W ;bitpos:[31:0] ;default: 32'd80000 ; */ 1742 /*description: */ 1743 #define RTC_CNTL_WDT_STG1_HOLD 0xFFFFFFFF 1744 #define RTC_CNTL_WDT_STG1_HOLD_M ((RTC_CNTL_WDT_STG1_HOLD_V)<<(RTC_CNTL_WDT_STG1_HOLD_S)) 1745 #define RTC_CNTL_WDT_STG1_HOLD_V 0xFFFFFFFF 1746 #define RTC_CNTL_WDT_STG1_HOLD_S 0 1747 1748 #define RTC_CNTL_WDTCONFIG3_REG (DR_REG_RTCCNTL_BASE + 0x98) 1749 /* RTC_CNTL_WDT_STG2_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfff ; */ 1750 /*description: */ 1751 #define RTC_CNTL_WDT_STG2_HOLD 0xFFFFFFFF 1752 #define RTC_CNTL_WDT_STG2_HOLD_M ((RTC_CNTL_WDT_STG2_HOLD_V)<<(RTC_CNTL_WDT_STG2_HOLD_S)) 1753 #define RTC_CNTL_WDT_STG2_HOLD_V 0xFFFFFFFF 1754 #define RTC_CNTL_WDT_STG2_HOLD_S 0 1755 1756 #define RTC_CNTL_WDTCONFIG4_REG (DR_REG_RTCCNTL_BASE + 0x9c) 1757 /* RTC_CNTL_WDT_STG3_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfff ; */ 1758 /*description: */ 1759 #define RTC_CNTL_WDT_STG3_HOLD 0xFFFFFFFF 1760 #define RTC_CNTL_WDT_STG3_HOLD_M ((RTC_CNTL_WDT_STG3_HOLD_V)<<(RTC_CNTL_WDT_STG3_HOLD_S)) 1761 #define RTC_CNTL_WDT_STG3_HOLD_V 0xFFFFFFFF 1762 #define RTC_CNTL_WDT_STG3_HOLD_S 0 1763 1764 #define RTC_CNTL_WDTFEED_REG (DR_REG_RTCCNTL_BASE + 0xa0) 1765 /* RTC_CNTL_WDT_FEED : WO ;bitpos:[31] ;default: 1'd0 ; */ 1766 /*description: */ 1767 #define RTC_CNTL_WDT_FEED (BIT(31)) 1768 #define RTC_CNTL_WDT_FEED_M (BIT(31)) 1769 #define RTC_CNTL_WDT_FEED_V 0x1 1770 #define RTC_CNTL_WDT_FEED_S 31 1771 1772 #define RTC_CNTL_WDTWPROTECT_REG (DR_REG_RTCCNTL_BASE + 0xa4) 1773 /* RTC_CNTL_WDT_WKEY : R/W ;bitpos:[31:0] ;default: 32'h50d83aa1 ; */ 1774 /*description: */ 1775 #define RTC_CNTL_WDT_WKEY 0xFFFFFFFF 1776 #define RTC_CNTL_WDT_WKEY_M ((RTC_CNTL_WDT_WKEY_V)<<(RTC_CNTL_WDT_WKEY_S)) 1777 #define RTC_CNTL_WDT_WKEY_V 0xFFFFFFFF 1778 #define RTC_CNTL_WDT_WKEY_S 0 1779 1780 #define RTC_CNTL_TEST_MUX_REG (DR_REG_RTCCNTL_BASE + 0xa8) 1781 /* RTC_CNTL_DTEST_RTC : R/W ;bitpos:[31:30] ;default: 2'd0 ; */ 1782 /*description: DTEST_RTC*/ 1783 #define RTC_CNTL_DTEST_RTC 0x00000003 1784 #define RTC_CNTL_DTEST_RTC_M ((RTC_CNTL_DTEST_RTC_V)<<(RTC_CNTL_DTEST_RTC_S)) 1785 #define RTC_CNTL_DTEST_RTC_V 0x3 1786 #define RTC_CNTL_DTEST_RTC_S 30 1787 /* RTC_CNTL_ENT_RTC : R/W ;bitpos:[29] ;default: 1'd0 ; */ 1788 /*description: ENT_RTC*/ 1789 #define RTC_CNTL_ENT_RTC (BIT(29)) 1790 #define RTC_CNTL_ENT_RTC_M (BIT(29)) 1791 #define RTC_CNTL_ENT_RTC_V 0x1 1792 #define RTC_CNTL_ENT_RTC_S 29 1793 1794 #define RTC_CNTL_SW_CPU_STALL_REG (DR_REG_RTCCNTL_BASE + 0xac) 1795 /* RTC_CNTL_SW_STALL_PROCPU_C1 : R/W ;bitpos:[31:26] ;default: 6'b0 ; */ 1796 /*description: {reg_sw_stall_procpu_c1[5:0] reg_sw_stall_procpu_c0[1:0]} == 1797 0x86 will stall PRO CPU*/ 1798 #define RTC_CNTL_SW_STALL_PROCPU_C1 0x0000003F 1799 #define RTC_CNTL_SW_STALL_PROCPU_C1_M ((RTC_CNTL_SW_STALL_PROCPU_C1_V)<<(RTC_CNTL_SW_STALL_PROCPU_C1_S)) 1800 #define RTC_CNTL_SW_STALL_PROCPU_C1_V 0x3F 1801 #define RTC_CNTL_SW_STALL_PROCPU_C1_S 26 1802 /* RTC_CNTL_SW_STALL_APPCPU_C1 : R/W ;bitpos:[25:20] ;default: 6'b0 ; */ 1803 /*description: {reg_sw_stall_appcpu_c1[5:0] reg_sw_stall_appcpu_c0[1:0]} == 1804 0x86 will stall APP CPU*/ 1805 #define RTC_CNTL_SW_STALL_APPCPU_C1 0x0000003F 1806 #define RTC_CNTL_SW_STALL_APPCPU_C1_M ((RTC_CNTL_SW_STALL_APPCPU_C1_V)<<(RTC_CNTL_SW_STALL_APPCPU_C1_S)) 1807 #define RTC_CNTL_SW_STALL_APPCPU_C1_V 0x3F 1808 #define RTC_CNTL_SW_STALL_APPCPU_C1_S 20 1809 1810 #define RTC_CNTL_STORE4_REG (DR_REG_RTCCNTL_BASE + 0xb0) 1811 /* RTC_CNTL_SCRATCH4 : R/W ;bitpos:[31:0] ;default: 0 ; */ 1812 /*description: 32-bit general purpose retention register*/ 1813 #define RTC_CNTL_SCRATCH4 0xFFFFFFFF 1814 #define RTC_CNTL_SCRATCH4_M ((RTC_CNTL_SCRATCH4_V)<<(RTC_CNTL_SCRATCH4_S)) 1815 #define RTC_CNTL_SCRATCH4_V 0xFFFFFFFF 1816 #define RTC_CNTL_SCRATCH4_S 0 1817 1818 #define RTC_CNTL_STORE5_REG (DR_REG_RTCCNTL_BASE + 0xb4) 1819 /* RTC_CNTL_SCRATCH5 : R/W ;bitpos:[31:0] ;default: 0 ; */ 1820 /*description: 32-bit general purpose retention register*/ 1821 #define RTC_CNTL_SCRATCH5 0xFFFFFFFF 1822 #define RTC_CNTL_SCRATCH5_M ((RTC_CNTL_SCRATCH5_V)<<(RTC_CNTL_SCRATCH5_S)) 1823 #define RTC_CNTL_SCRATCH5_V 0xFFFFFFFF 1824 #define RTC_CNTL_SCRATCH5_S 0 1825 1826 #define RTC_CNTL_STORE6_REG (DR_REG_RTCCNTL_BASE + 0xb8) 1827 /* RTC_CNTL_SCRATCH6 : R/W ;bitpos:[31:0] ;default: 0 ; */ 1828 /*description: 32-bit general purpose retention register*/ 1829 #define RTC_CNTL_SCRATCH6 0xFFFFFFFF 1830 #define RTC_CNTL_SCRATCH6_M ((RTC_CNTL_SCRATCH6_V)<<(RTC_CNTL_SCRATCH6_S)) 1831 #define RTC_CNTL_SCRATCH6_V 0xFFFFFFFF 1832 #define RTC_CNTL_SCRATCH6_S 0 1833 1834 #define RTC_CNTL_STORE7_REG (DR_REG_RTCCNTL_BASE + 0xbc) 1835 /* RTC_CNTL_SCRATCH7 : R/W ;bitpos:[31:0] ;default: 0 ; */ 1836 /*description: 32-bit general purpose retention register*/ 1837 #define RTC_CNTL_SCRATCH7 0xFFFFFFFF 1838 #define RTC_CNTL_SCRATCH7_M ((RTC_CNTL_SCRATCH7_V)<<(RTC_CNTL_SCRATCH7_S)) 1839 #define RTC_CNTL_SCRATCH7_V 0xFFFFFFFF 1840 #define RTC_CNTL_SCRATCH7_S 0 1841 1842 #define RTC_CNTL_LOW_POWER_ST_REG (DR_REG_RTCCNTL_BASE + 0xc0) 1843 /* RTC_CNTL_RDY_FOR_WAKEUP : R/0; bitpos:[19]; default: 0 */ 1844 /*description: 1 if RTC controller is ready to execute WAKE instruction, 0 otherwise */ 1845 #define RTC_CNTL_RDY_FOR_WAKEUP (BIT(19)) 1846 #define RTC_CNTL_RDY_FOR_WAKEUP_M (BIT(19)) 1847 #define RTC_CNTL_RDY_FOR_WAKEUP_V 0x1 1848 #define RTC_CNTL_RDY_FOR_WAKEUP_S 19 1849 1850 /* Compatibility definition */ 1851 #define RTC_CNTL_DIAG0_REG RTC_CNTL_LOW_POWER_ST_REG 1852 /* RTC_CNTL_LOW_POWER_DIAG0 : RO ;bitpos:[31:0] ;default: 0 ; */ 1853 /*description: */ 1854 #define RTC_CNTL_LOW_POWER_DIAG0 0xFFFFFFFF 1855 #define RTC_CNTL_LOW_POWER_DIAG0_M ((RTC_CNTL_LOW_POWER_DIAG0_V)<<(RTC_CNTL_LOW_POWER_DIAG0_S)) 1856 #define RTC_CNTL_LOW_POWER_DIAG0_V 0xFFFFFFFF 1857 #define RTC_CNTL_LOW_POWER_DIAG0_S 0 1858 1859 #define RTC_CNTL_DIAG1_REG (DR_REG_RTCCNTL_BASE + 0xc4) 1860 /* RTC_CNTL_LOW_POWER_DIAG1 : RO ;bitpos:[31:0] ;default: 0 ; */ 1861 /*description: */ 1862 #define RTC_CNTL_LOW_POWER_DIAG1 0xFFFFFFFF 1863 #define RTC_CNTL_LOW_POWER_DIAG1_M ((RTC_CNTL_LOW_POWER_DIAG1_V)<<(RTC_CNTL_LOW_POWER_DIAG1_S)) 1864 #define RTC_CNTL_LOW_POWER_DIAG1_V 0xFFFFFFFF 1865 #define RTC_CNTL_LOW_POWER_DIAG1_S 0 1866 1867 #define RTC_CNTL_HOLD_FORCE_REG (DR_REG_RTCCNTL_BASE + 0xc8) 1868 /* RTC_CNTL_X32N_HOLD_FORCE : R/W ;bitpos:[17] ;default: 1'b0 ; */ 1869 /*description: */ 1870 #define RTC_CNTL_X32N_HOLD_FORCE (BIT(17)) 1871 #define RTC_CNTL_X32N_HOLD_FORCE_M (BIT(17)) 1872 #define RTC_CNTL_X32N_HOLD_FORCE_V 0x1 1873 #define RTC_CNTL_X32N_HOLD_FORCE_S 17 1874 /* RTC_CNTL_X32P_HOLD_FORCE : R/W ;bitpos:[16] ;default: 1'b0 ; */ 1875 /*description: */ 1876 #define RTC_CNTL_X32P_HOLD_FORCE (BIT(16)) 1877 #define RTC_CNTL_X32P_HOLD_FORCE_M (BIT(16)) 1878 #define RTC_CNTL_X32P_HOLD_FORCE_V 0x1 1879 #define RTC_CNTL_X32P_HOLD_FORCE_S 16 1880 /* RTC_CNTL_TOUCH_PAD7_HOLD_FORCE : R/W ;bitpos:[15] ;default: 1'b0 ; */ 1881 /*description: */ 1882 #define RTC_CNTL_TOUCH_PAD7_HOLD_FORCE (BIT(15)) 1883 #define RTC_CNTL_TOUCH_PAD7_HOLD_FORCE_M (BIT(15)) 1884 #define RTC_CNTL_TOUCH_PAD7_HOLD_FORCE_V 0x1 1885 #define RTC_CNTL_TOUCH_PAD7_HOLD_FORCE_S 15 1886 /* RTC_CNTL_TOUCH_PAD6_HOLD_FORCE : R/W ;bitpos:[14] ;default: 1'b0 ; */ 1887 /*description: */ 1888 #define RTC_CNTL_TOUCH_PAD6_HOLD_FORCE (BIT(14)) 1889 #define RTC_CNTL_TOUCH_PAD6_HOLD_FORCE_M (BIT(14)) 1890 #define RTC_CNTL_TOUCH_PAD6_HOLD_FORCE_V 0x1 1891 #define RTC_CNTL_TOUCH_PAD6_HOLD_FORCE_S 14 1892 /* RTC_CNTL_TOUCH_PAD5_HOLD_FORCE : R/W ;bitpos:[13] ;default: 1'b0 ; */ 1893 /*description: */ 1894 #define RTC_CNTL_TOUCH_PAD5_HOLD_FORCE (BIT(13)) 1895 #define RTC_CNTL_TOUCH_PAD5_HOLD_FORCE_M (BIT(13)) 1896 #define RTC_CNTL_TOUCH_PAD5_HOLD_FORCE_V 0x1 1897 #define RTC_CNTL_TOUCH_PAD5_HOLD_FORCE_S 13 1898 /* RTC_CNTL_TOUCH_PAD4_HOLD_FORCE : R/W ;bitpos:[12] ;default: 1'b0 ; */ 1899 /*description: */ 1900 #define RTC_CNTL_TOUCH_PAD4_HOLD_FORCE (BIT(12)) 1901 #define RTC_CNTL_TOUCH_PAD4_HOLD_FORCE_M (BIT(12)) 1902 #define RTC_CNTL_TOUCH_PAD4_HOLD_FORCE_V 0x1 1903 #define RTC_CNTL_TOUCH_PAD4_HOLD_FORCE_S 12 1904 /* RTC_CNTL_TOUCH_PAD3_HOLD_FORCE : R/W ;bitpos:[11] ;default: 1'b0 ; */ 1905 /*description: */ 1906 #define RTC_CNTL_TOUCH_PAD3_HOLD_FORCE (BIT(11)) 1907 #define RTC_CNTL_TOUCH_PAD3_HOLD_FORCE_M (BIT(11)) 1908 #define RTC_CNTL_TOUCH_PAD3_HOLD_FORCE_V 0x1 1909 #define RTC_CNTL_TOUCH_PAD3_HOLD_FORCE_S 11 1910 /* RTC_CNTL_TOUCH_PAD2_HOLD_FORCE : R/W ;bitpos:[10] ;default: 1'b0 ; */ 1911 /*description: */ 1912 #define RTC_CNTL_TOUCH_PAD2_HOLD_FORCE (BIT(10)) 1913 #define RTC_CNTL_TOUCH_PAD2_HOLD_FORCE_M (BIT(10)) 1914 #define RTC_CNTL_TOUCH_PAD2_HOLD_FORCE_V 0x1 1915 #define RTC_CNTL_TOUCH_PAD2_HOLD_FORCE_S 10 1916 /* RTC_CNTL_TOUCH_PAD1_HOLD_FORCE : R/W ;bitpos:[9] ;default: 1'b0 ; */ 1917 /*description: */ 1918 #define RTC_CNTL_TOUCH_PAD1_HOLD_FORCE (BIT(9)) 1919 #define RTC_CNTL_TOUCH_PAD1_HOLD_FORCE_M (BIT(9)) 1920 #define RTC_CNTL_TOUCH_PAD1_HOLD_FORCE_V 0x1 1921 #define RTC_CNTL_TOUCH_PAD1_HOLD_FORCE_S 9 1922 /* RTC_CNTL_TOUCH_PAD0_HOLD_FORCE : R/W ;bitpos:[8] ;default: 1'b0 ; */ 1923 /*description: */ 1924 #define RTC_CNTL_TOUCH_PAD0_HOLD_FORCE (BIT(8)) 1925 #define RTC_CNTL_TOUCH_PAD0_HOLD_FORCE_M (BIT(8)) 1926 #define RTC_CNTL_TOUCH_PAD0_HOLD_FORCE_V 0x1 1927 #define RTC_CNTL_TOUCH_PAD0_HOLD_FORCE_S 8 1928 /* RTC_CNTL_SENSE4_HOLD_FORCE : R/W ;bitpos:[7] ;default: 1'b0 ; */ 1929 /*description: */ 1930 #define RTC_CNTL_SENSE4_HOLD_FORCE (BIT(7)) 1931 #define RTC_CNTL_SENSE4_HOLD_FORCE_M (BIT(7)) 1932 #define RTC_CNTL_SENSE4_HOLD_FORCE_V 0x1 1933 #define RTC_CNTL_SENSE4_HOLD_FORCE_S 7 1934 /* RTC_CNTL_SENSE3_HOLD_FORCE : R/W ;bitpos:[6] ;default: 1'b0 ; */ 1935 /*description: */ 1936 #define RTC_CNTL_SENSE3_HOLD_FORCE (BIT(6)) 1937 #define RTC_CNTL_SENSE3_HOLD_FORCE_M (BIT(6)) 1938 #define RTC_CNTL_SENSE3_HOLD_FORCE_V 0x1 1939 #define RTC_CNTL_SENSE3_HOLD_FORCE_S 6 1940 /* RTC_CNTL_SENSE2_HOLD_FORCE : R/W ;bitpos:[5] ;default: 1'b0 ; */ 1941 /*description: */ 1942 #define RTC_CNTL_SENSE2_HOLD_FORCE (BIT(5)) 1943 #define RTC_CNTL_SENSE2_HOLD_FORCE_M (BIT(5)) 1944 #define RTC_CNTL_SENSE2_HOLD_FORCE_V 0x1 1945 #define RTC_CNTL_SENSE2_HOLD_FORCE_S 5 1946 /* RTC_CNTL_SENSE1_HOLD_FORCE : R/W ;bitpos:[4] ;default: 1'b0 ; */ 1947 /*description: */ 1948 #define RTC_CNTL_SENSE1_HOLD_FORCE (BIT(4)) 1949 #define RTC_CNTL_SENSE1_HOLD_FORCE_M (BIT(4)) 1950 #define RTC_CNTL_SENSE1_HOLD_FORCE_V 0x1 1951 #define RTC_CNTL_SENSE1_HOLD_FORCE_S 4 1952 /* RTC_CNTL_PDAC2_HOLD_FORCE : R/W ;bitpos:[3] ;default: 1'b0 ; */ 1953 /*description: */ 1954 #define RTC_CNTL_PDAC2_HOLD_FORCE (BIT(3)) 1955 #define RTC_CNTL_PDAC2_HOLD_FORCE_M (BIT(3)) 1956 #define RTC_CNTL_PDAC2_HOLD_FORCE_V 0x1 1957 #define RTC_CNTL_PDAC2_HOLD_FORCE_S 3 1958 /* RTC_CNTL_PDAC1_HOLD_FORCE : R/W ;bitpos:[2] ;default: 1'b0 ; */ 1959 /*description: */ 1960 #define RTC_CNTL_PDAC1_HOLD_FORCE (BIT(2)) 1961 #define RTC_CNTL_PDAC1_HOLD_FORCE_M (BIT(2)) 1962 #define RTC_CNTL_PDAC1_HOLD_FORCE_V 0x1 1963 #define RTC_CNTL_PDAC1_HOLD_FORCE_S 2 1964 /* RTC_CNTL_ADC2_HOLD_FORCE : R/W ;bitpos:[1] ;default: 1'b0 ; */ 1965 /*description: */ 1966 #define RTC_CNTL_ADC2_HOLD_FORCE (BIT(1)) 1967 #define RTC_CNTL_ADC2_HOLD_FORCE_M (BIT(1)) 1968 #define RTC_CNTL_ADC2_HOLD_FORCE_V 0x1 1969 #define RTC_CNTL_ADC2_HOLD_FORCE_S 1 1970 /* RTC_CNTL_ADC1_HOLD_FORCE : R/W ;bitpos:[0] ;default: 1'b0 ; */ 1971 /*description: */ 1972 #define RTC_CNTL_ADC1_HOLD_FORCE (BIT(0)) 1973 #define RTC_CNTL_ADC1_HOLD_FORCE_M (BIT(0)) 1974 #define RTC_CNTL_ADC1_HOLD_FORCE_V 0x1 1975 #define RTC_CNTL_ADC1_HOLD_FORCE_S 0 1976 1977 #define RTC_CNTL_EXT_WAKEUP1_REG (DR_REG_RTCCNTL_BASE + 0xcc) 1978 /* RTC_CNTL_EXT_WAKEUP1_STATUS_CLR : WO ;bitpos:[18] ;default: 1'd0 ; */ 1979 /*description: clear ext wakeup1 status*/ 1980 #define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR (BIT(18)) 1981 #define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR_M (BIT(18)) 1982 #define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR_V 0x1 1983 #define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR_S 18 1984 /* RTC_CNTL_EXT_WAKEUP1_SEL : R/W ;bitpos:[17:0] ;default: 18'd0 ; */ 1985 /*description: Bitmap to select RTC pads for ext wakeup1*/ 1986 #define RTC_CNTL_EXT_WAKEUP1_SEL 0x0003FFFF 1987 #define RTC_CNTL_EXT_WAKEUP1_SEL_M ((RTC_CNTL_EXT_WAKEUP1_SEL_V)<<(RTC_CNTL_EXT_WAKEUP1_SEL_S)) 1988 #define RTC_CNTL_EXT_WAKEUP1_SEL_V 0x3FFFF 1989 #define RTC_CNTL_EXT_WAKEUP1_SEL_S 0 1990 1991 #define RTC_CNTL_EXT_WAKEUP1_STATUS_REG (DR_REG_RTCCNTL_BASE + 0xd0) 1992 /* RTC_CNTL_EXT_WAKEUP1_STATUS : RO ;bitpos:[17:0] ;default: 18'd0 ; */ 1993 /*description: ext wakeup1 status*/ 1994 #define RTC_CNTL_EXT_WAKEUP1_STATUS 0x0003FFFF 1995 #define RTC_CNTL_EXT_WAKEUP1_STATUS_M ((RTC_CNTL_EXT_WAKEUP1_STATUS_V)<<(RTC_CNTL_EXT_WAKEUP1_STATUS_S)) 1996 #define RTC_CNTL_EXT_WAKEUP1_STATUS_V 0x3FFFF 1997 #define RTC_CNTL_EXT_WAKEUP1_STATUS_S 0 1998 1999 #define RTC_CNTL_BROWN_OUT_REG (DR_REG_RTCCNTL_BASE + 0xd4) 2000 /* RTC_CNTL_BROWN_OUT_DET : RO ;bitpos:[31] ;default: 1'b0 ; */ 2001 /*description: brown out detect*/ 2002 #define RTC_CNTL_BROWN_OUT_DET (BIT(31)) 2003 #define RTC_CNTL_BROWN_OUT_DET_M (BIT(31)) 2004 #define RTC_CNTL_BROWN_OUT_DET_V 0x1 2005 #define RTC_CNTL_BROWN_OUT_DET_S 31 2006 /* RTC_CNTL_BROWN_OUT_ENA : R/W ;bitpos:[30] ;default: 1'b0 ; */ 2007 /*description: enable brown out*/ 2008 #define RTC_CNTL_BROWN_OUT_ENA (BIT(30)) 2009 #define RTC_CNTL_BROWN_OUT_ENA_M (BIT(30)) 2010 #define RTC_CNTL_BROWN_OUT_ENA_V 0x1 2011 #define RTC_CNTL_BROWN_OUT_ENA_S 30 2012 /* RTC_CNTL_DBROWN_OUT_THRES : R/W ;bitpos:[29:27] ;default: 3'b010 ; */ 2013 /*description: brown out threshold*/ 2014 #define RTC_CNTL_DBROWN_OUT_THRES 0x00000007 2015 #define RTC_CNTL_DBROWN_OUT_THRES_M ((RTC_CNTL_DBROWN_OUT_THRES_V)<<(RTC_CNTL_DBROWN_OUT_THRES_S)) 2016 #define RTC_CNTL_DBROWN_OUT_THRES_V 0x7 2017 #define RTC_CNTL_DBROWN_OUT_THRES_S 27 2018 /* RTC_CNTL_BROWN_OUT_RST_ENA : R/W ;bitpos:[26] ;default: 1'b0 ; */ 2019 /*description: enable brown out reset*/ 2020 #define RTC_CNTL_BROWN_OUT_RST_ENA (BIT(26)) 2021 #define RTC_CNTL_BROWN_OUT_RST_ENA_M (BIT(26)) 2022 #define RTC_CNTL_BROWN_OUT_RST_ENA_V 0x1 2023 #define RTC_CNTL_BROWN_OUT_RST_ENA_S 26 2024 /* RTC_CNTL_BROWN_OUT_RST_WAIT : R/W ;bitpos:[25:16] ;default: 10'h3ff ; */ 2025 /*description: brown out reset wait cycles*/ 2026 #define RTC_CNTL_BROWN_OUT_RST_WAIT 0x000003FF 2027 #define RTC_CNTL_BROWN_OUT_RST_WAIT_M ((RTC_CNTL_BROWN_OUT_RST_WAIT_V)<<(RTC_CNTL_BROWN_OUT_RST_WAIT_S)) 2028 #define RTC_CNTL_BROWN_OUT_RST_WAIT_V 0x3FF 2029 #define RTC_CNTL_BROWN_OUT_RST_WAIT_S 16 2030 /* RTC_CNTL_BROWN_OUT_PD_RF_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */ 2031 /*description: enable power down RF when brown out happens*/ 2032 #define RTC_CNTL_BROWN_OUT_PD_RF_ENA (BIT(15)) 2033 #define RTC_CNTL_BROWN_OUT_PD_RF_ENA_M (BIT(15)) 2034 #define RTC_CNTL_BROWN_OUT_PD_RF_ENA_V 0x1 2035 #define RTC_CNTL_BROWN_OUT_PD_RF_ENA_S 15 2036 /* RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */ 2037 /*description: enable close flash when brown out happens*/ 2038 #define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA (BIT(14)) 2039 #define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_M (BIT(14)) 2040 #define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_V 0x1 2041 #define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_S 14 2042 2043 #define RTC_MEM_CONF (DR_REG_RTCCNTL_BASE + 0x40 * 4) 2044 #define RTC_MEM_CRC_FINISH (BIT(31)) 2045 #define RTC_MEM_CRC_FINISH_M (BIT(31)) 2046 #define RTC_MEM_CRC_FINISH_V 0x1 2047 #define RTC_MEM_CRC_FINISH_S 31 2048 #define RTC_MEM_CRC_LEN (0x7ff) 2049 #define RTC_MEM_CRC_LEN_M ((RTC_MEM_CRC_LEN_V)<<(RTC_MEM_CRC_LEN_S)) 2050 #define RTC_MEM_CRC_LEN_V 0x7ff 2051 #define RTC_MEM_CRC_LEN_S 20 2052 #define RTC_MEM_CRC_ADDR 0x7ff 2053 #define RTC_MEM_CRC_ADDR_M ((RTC_MEM_CRC_ADDR_V)<<(RTC_MEM_CRC_ADDR_S)) 2054 #define RTC_MEM_CRC_ADDR_V 0x7ff 2055 #define RTC_MEM_CRC_ADDR_S 9 2056 #define RTC_MEM_CRC_START (BIT(8)) 2057 #define RTC_MEM_CRC_START_M (BIT(8)) 2058 #define RTC_MEM_CRC_START_V 0x1 2059 #define RTC_MEM_CRC_START_S 8 2060 #define RTC_MEM_PID_CONF 0xff 2061 #define RTC_MEM_PID_CONF_M 0xff 2062 #define RTC_MEM_PID_CONF_V 0xff 2063 #define RTC_MEM_PID_CONF_S 0 2064 2065 #define RTC_MEM_CRC_RES (DR_REG_RTCCNTL_BASE + 0x41 * 4) 2066 2067 #define RTC_CNTL_DATE_REG (DR_REG_RTCCNTL_BASE + 0x13c) 2068 /* RTC_CNTL_CNTL_DATE : R/W ;bitpos:[27:0] ;default: 28'h1604280 ; */ 2069 /*description: */ 2070 #define RTC_CNTL_CNTL_DATE 0x0FFFFFFF 2071 #define RTC_CNTL_CNTL_DATE_M ((RTC_CNTL_CNTL_DATE_V)<<(RTC_CNTL_CNTL_DATE_S)) 2072 #define RTC_CNTL_CNTL_DATE_V 0xFFFFFFF 2073 #define RTC_CNTL_CNTL_DATE_S 0 2074 #define RTC_CNTL_RTC_CNTL_DATE_VERSION 0x1604280 2075 2076 2077 2078 2079 #endif /*_SOC_RTC_CNTL_REG_H_ */ 2080
