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Searched refs:RSA_MEM_M_BLOCK_BASE (Results 1 – 10 of 10) sorted by relevance

/hal_espressif-3.6.0/components/mbedtls/port/esp32s3/
Dbignum.c144 mpi_to_mem_block(RSA_MEM_M_BLOCK_BASE, M, num_words); in esp_mpi_mul_mpi_mod_hw_op()
162 mpi_to_mem_block(RSA_MEM_M_BLOCK_BASE, M, num_words); in esp_mpi_exp_mpi_mod_hw_op()
203 DPORT_REG_WRITE(RSA_MEM_M_BLOCK_BASE + i * 4, UINT32_MAX); in esp_mpi_mult_mpi_failover_mod_mult_hw_op()
/hal_espressif-3.6.0/components/mbedtls/port/esp32c3/
Dbignum.c151 mpi_to_mem_block(RSA_MEM_M_BLOCK_BASE, M, num_words); in esp_mpi_mul_mpi_mod_hw_op()
169 mpi_to_mem_block(RSA_MEM_M_BLOCK_BASE, M, num_words); in esp_mpi_exp_mpi_mod_hw_op()
210 REG_WRITE(RSA_MEM_M_BLOCK_BASE + i * 4, UINT32_MAX); in esp_mpi_mult_mpi_failover_mod_mult_hw_op()
/hal_espressif-3.6.0/components/mbedtls/port/esp32h2/
Dbignum.c151 mpi_to_mem_block(RSA_MEM_M_BLOCK_BASE, M, num_words); in esp_mpi_mul_mpi_mod_hw_op()
169 mpi_to_mem_block(RSA_MEM_M_BLOCK_BASE, M, num_words); in esp_mpi_exp_mpi_mod_hw_op()
210 REG_WRITE(RSA_MEM_M_BLOCK_BASE + i * 4, UINT32_MAX); in esp_mpi_mult_mpi_failover_mod_mult_hw_op()
/hal_espressif-3.6.0/components/mbedtls/port/esp32s2/
Dbignum.c146 mpi_to_mem_block(RSA_MEM_M_BLOCK_BASE, M, num_words); in esp_mpi_mul_mpi_mod_hw_op()
164 mpi_to_mem_block(RSA_MEM_M_BLOCK_BASE, M, num_words); in esp_mpi_exp_mpi_mod_hw_op()
205 DPORT_REG_WRITE(RSA_MEM_M_BLOCK_BASE + i * 4, UINT32_MAX); in esp_mpi_mult_mpi_failover_mod_mult_hw_op()
/hal_espressif-3.6.0/components/mbedtls/port/esp32/
Dbignum.c147 mpi_to_mem_block(RSA_MEM_M_BLOCK_BASE, M, hw_words); in esp_mpi_mul_mpi_mod_hw_op()
199 mpi_to_mem_block(RSA_MEM_M_BLOCK_BASE, M, hw_words); in esp_mont_hw_op()
250 DPORT_REG_WRITE(RSA_MEM_M_BLOCK_BASE + i * 4, UINT32_MAX); in esp_mpi_mult_mpi_failover_mod_mult_hw_op()
/hal_espressif-3.6.0/components/soc/esp32/include/soc/
Dhwcrypto_reg.h20 #define RSA_MEM_M_BLOCK_BASE ((DR_REG_RSA_BASE)+0x000) macro
/hal_espressif-3.6.0/components/soc/esp32s3/include/soc/
Dhwcrypto_reg.h12 #define RSA_MEM_M_BLOCK_BASE ((DR_REG_RSA_BASE)+0x000) macro
/hal_espressif-3.6.0/components/soc/esp32c3/include/soc/
Dhwcrypto_reg.h20 #define RSA_MEM_M_BLOCK_BASE ((DR_REG_RSA_BASE)+0x000) macro
/hal_espressif-3.6.0/components/soc/esp32h2/include/soc/
Dhwcrypto_reg.h20 #define RSA_MEM_M_BLOCK_BASE ((DR_REG_RSA_BASE)+0x000) macro
/hal_espressif-3.6.0/components/soc/esp32s2/include/soc/
Dhwcrypto_reg.h20 #define RSA_MEM_M_BLOCK_BASE ((DR_REG_RSA_BASE)+0x000) macro