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Searched refs:REG_TIMG_BASE (Results 1 – 10 of 10) sorted by relevance

/hal_espressif-3.6.0/components/soc/esp32/include/soc/
Dtimer_group_reg.h37 #define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + i*0x1000) macro
38 #define TIMG_T0CONFIG_REG(i) (REG_TIMG_BASE(i) + 0x0000)
83 #define TIMG_T0LO_REG(i) (REG_TIMG_BASE(i) + 0x0004)
91 #define TIMG_T0HI_REG(i) (REG_TIMG_BASE(i) + 0x0008)
99 #define TIMG_T0UPDATE_REG(i) (REG_TIMG_BASE(i) + 0x000c)
108 #define TIMG_T0ALARMLO_REG(i) (REG_TIMG_BASE(i) + 0x0010)
116 #define TIMG_T0ALARMHI_REG(i) (REG_TIMG_BASE(i) + 0x0014)
124 #define TIMG_T0LOADLO_REG(i) (REG_TIMG_BASE(i) + 0x0018)
132 #define TIMG_T0LOADHI_REG(i) (REG_TIMG_BASE(i) + 0x001c)
140 #define TIMG_T0LOAD_REG(i) (REG_TIMG_BASE(i) + 0x0020)
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/hal_espressif-3.6.0/components/soc/esp32s3/include/soc/
Dtimer_group_reg.h26 #define TIMG_T0CONFIG_REG(i) (REG_TIMG_BASE(i) + 0x0)
76 #define TIMG_T0LO_REG(i) (REG_TIMG_BASE(i) + 0x4)
89 #define TIMG_T0HI_REG(i) (REG_TIMG_BASE(i) + 0x8)
102 #define TIMG_T0UPDATE_REG(i) (REG_TIMG_BASE(i) + 0xc)
114 #define TIMG_T0ALARMLO_REG(i) (REG_TIMG_BASE(i) + 0x10)
126 #define TIMG_T0ALARMHI_REG(i) (REG_TIMG_BASE(i) + 0x14)
138 #define TIMG_T0LOADLO_REG(i) (REG_TIMG_BASE(i) + 0x18)
151 #define TIMG_T0LOADHI_REG(i) (REG_TIMG_BASE(i) + 0x1c)
164 #define TIMG_T0LOAD_REG(i) (REG_TIMG_BASE(i) + 0x20)
177 #define TIMG_T1CONFIG_REG(i) (REG_TIMG_BASE(i) + 0x24)
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Dsoc.h120 #define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i)*0x1000) macro
/hal_espressif-3.6.0/components/soc/esp32c3/include/soc/
Dsoc.h76 #define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i)*0x1000) macro
Dtimer_group_reg.h14 #define DR_REG_TIMG_BASE(i) REG_TIMG_BASE(i)
/hal_espressif-3.6.0/components/soc/esp32h2/include/soc/
Dsoc.h104 #define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i)*0x1000) macro
Dtimer_group_reg.h14 #define DR_REG_TIMG_BASE(i) REG_TIMG_BASE(i)
/hal_espressif-3.6.0/components/soc/esp32s2/include/soc/
Dsoc.h100 #define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i)*0x1000) macro
Dtimer_group_reg.h14 #define DR_REG_TIMG_BASE(i) REG_TIMG_BASE(i)
/hal_espressif-3.6.0/components/esp_system/port/soc/esp32/
Dhighint_hdl.S73 #define TIMG1_REG_OFFSET(reg) ((reg) - REG_TIMG_BASE(1))