REG_SPI_BASE (reference) in projects: hal_espressif-3.6.0

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Searched refs:REG_SPI_BASE (Results 1 – 5 of 5) sorted by relevance

/hal_espressif-3.6.0/components/soc/esp32/include/soc/
D	spi_reg.h	19 #define REG_SPI_BASE(i) (DR_REG_SPI1_BASE + (((i)>1) ? (((i)* 0x1000) + 0x20000) : (((~(i)) & 1… macro 21 #define SPI_CMD_REG(i) (REG_SPI_BASE(i) + 0x0) 135 #define SPI_ADDR_REG(i) (REG_SPI_BASE(i) + 0x4) 139 #define SPI_CTRL_REG(i) (REG_SPI_BASE(i) + 0x8) 226 #define SPI_CTRL1_REG(i) (REG_SPI_BASE(i) + 0xC) 240 #define SPI_RD_STATUS_REG(i) (REG_SPI_BASE(i) + 0x10) 260 #define SPI_CTRL2_REG(i) (REG_SPI_BASE(i) + 0x14) 328 #define SPI_CLOCK_REG(i) (REG_SPI_BASE(i) + 0x18) 364 #define SPI_USER_REG(i) (REG_SPI_BASE(i) + 0x1C) 533 #define SPI_USER1_REG(i) (REG_SPI_BASE(i) + 0x20) [all …]
/hal_espressif-3.6.0/components/soc/esp32s2/include/soc/
D	spi_reg.h	22 #define REG_SPI_BASE(i) (DR_REG_SPI2_BASE + (((i)>3) ? (((i-2)* 0x1000) + 0x10000) : ((i - 2)* … macro 24 #define SPI_CMD_REG(i) (REG_SPI_BASE(i) + 0x000) 39 #define SPI_ADDR_REG(i) (REG_SPI_BASE(i) + 0x004) 47 #define SPI_CTRL_REG(i) (REG_SPI_BASE(i) + 0x008) 161 #define SPI_CTRL1_REG(i) (REG_SPI_BASE(i) + 0x00C) 197 #define SPI_CTRL2_REG(i) (REG_SPI_BASE(i) + 0x010) 227 #define SPI_CLOCK_REG(i) (REG_SPI_BASE(i) + 0x014) 264 #define SPI_USER_REG(i) (REG_SPI_BASE(i) + 0x018) 476 #define SPI_USER1_REG(i) (REG_SPI_BASE(i) + 0x01C) 492 #define SPI_USER2_REG(i) (REG_SPI_BASE(i) + 0x020) [all …]
/hal_espressif-3.6.0/components/soc/esp32c3/include/soc/
D	spi_reg.h	23 #define SPI_CMD_REG(i) (REG_SPI_BASE(i) + 0x0) 46 #define SPI_ADDR_REG(i) (REG_SPI_BASE(i) + 0x4) 54 #define SPI_CTRL_REG(i) (REG_SPI_BASE(i) + 0x8) 147 #define SPI_CLOCK_REG(i) (REG_SPI_BASE(i) + 0xC) 184 #define SPI_USER_REG(i) (REG_SPI_BASE(i) + 0x10) 320 #define SPI_USER1_REG(i) (REG_SPI_BASE(i) + 0x14) 358 #define SPI_USER2_REG(i) (REG_SPI_BASE(i) + 0x18) 381 #define SPI_MS_DLEN_REG(i) (REG_SPI_BASE(i) + 0x1C) 392 #define SPI_MISC_REG(i) (REG_SPI_BASE(i) + 0x20) 476 #define SPI_DIN_MODE_REG(i) (REG_SPI_BASE(i) + 0x24) [all …]
/hal_espressif-3.6.0/components/soc/esp32h2/include/soc/
D	spi_reg.h	23 #define SPI_CMD_REG(i) (REG_SPI_BASE(i) + 0x0) 46 #define SPI_ADDR_REG(i) (REG_SPI_BASE(i) + 0x4) 54 #define SPI_CTRL_REG(i) (REG_SPI_BASE(i) + 0x008) 147 #define SPI_CLOCK_REG(i) (REG_SPI_BASE(i) + 0xC) 184 #define SPI_USER_REG(i) (REG_SPI_BASE(i) + 0x10) 320 #define SPI_USER1_REG(i) (REG_SPI_BASE(i) + 0x14) 358 #define SPI_USER2_REG(i) (REG_SPI_BASE(i) + 0x18) 381 #define SPI_MS_DLEN_REG(i) (REG_SPI_BASE(i) + 0x1C) 392 #define SPI_MISC_REG(i) (REG_SPI_BASE(i) + 0x20) 476 #define SPI_DIN_MODE_REG(i) (REG_SPI_BASE(i) + 0x24) [all …]
/hal_espressif-3.6.0/components/soc/esp32s3/include/soc/
D	spi_reg.h	23 #define SPI_CMD_REG(i) (REG_SPI_BASE(i) + 0x0) 46 #define SPI_ADDR_REG(i) (REG_SPI_BASE(i) + 0x4) 54 #define SPI_CTRL_REG(i) (REG_SPI_BASE(i) + 0x8) 168 #define SPI_CLOCK_REG(i) (REG_SPI_BASE(i) + 0xC) 205 #define SPI_USER_REG(i) (REG_SPI_BASE(i) + 0x10) 355 #define SPI_USER1_REG(i) (REG_SPI_BASE(i) + 0x14) 393 #define SPI_USER2_REG(i) (REG_SPI_BASE(i) + 0x18) 416 #define SPI_MS_DLEN_REG(i) (REG_SPI_BASE(i) + 0x1C) 427 #define SPI_MISC_REG(i) (REG_SPI_BASE(i) + 0x20) 548 #define SPI_DIN_MODE_REG(i) (REG_SPI_BASE(i) + 0x24) [all …]

TraceRecorderSource-2.7.6
TraceRecorderSource-3.4.0
Zephyr-Core-2.7.6
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Zephyr-Core-3.5.0
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