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Searched refs:PANIC_RSN_INTWDT_CPU0 (Results 1 – 8 of 8) sorted by relevance

/hal_espressif-3.6.0/components/esp_system/port/
Dpanic_handler.c141 BUSY_WAIT_IF_TRUE(panic_get_cause(frame) == PANIC_RSN_INTWDT_CPU0 && core_id == 1);
173 if (panic_get_cause(frame) == PANIC_RSN_INTWDT_CPU0
/hal_espressif-3.6.0/components/xtensa/include/esp_private/
Dpanic_reason.h8 #define PANIC_RSN_INTWDT_CPU0 5 macro
/hal_espressif-3.6.0/components/riscv/include/esp_private/
Dpanic_reason.h18 PANIC_RSN_INTWDT_CPU0, enumerator
/hal_espressif-3.6.0/components/esp_system/port/arch/riscv/
Dpanic_arch.c292 _Static_assert(PANIC_RSN_INTWDT_CPU0 + 1 == PANIC_RSN_INTWDT_CPU1, in panic_soc_fill_info()
295 info->reason = pseudo_reason[PANIC_RSN_INTWDT_CPU0 + core]; in panic_soc_fill_info()
/hal_espressif-3.6.0/components/esp_system/port/arch/xtensa/
Dpanic_arch.c68 && ((core == 0 && frame->exccause == PANIC_RSN_INTWDT_CPU0) || in panic_print_registers()
400 if (frame->exccause == PANIC_RSN_INTWDT_CPU0) { in panic_soc_fill_info()
/hal_espressif-3.6.0/components/esp_system/port/soc/esp32s2/
Dhighint_hdl.S75 movi a0,PANIC_RSN_INTWDT_CPU0
/hal_espressif-3.6.0/components/esp_system/port/soc/esp32s3/
Dhighint_hdl.S103 movi a0,PANIC_RSN_INTWDT_CPU0
/hal_espressif-3.6.0/components/esp_system/port/soc/esp32/
Dhighint_hdl.S277 movi a0,PANIC_RSN_INTWDT_CPU0