Searched refs:I_WR_REG_BIT (Results 1 – 5 of 5) sorted by relevance
| /hal_espressif-3.6.0/components/esp_pm/test/ |
| D | test_pm.c | 199 I_WR_REG_BIT(RTC_CNTL_HOLD_FORCE_REG, RTC_CNTL_PDAC1_HOLD_FORCE_S, 0),
200 I_WR_REG_BIT(RTC_GPIO_OUT_REG, ext_rtc_io + RTC_GPIO_OUT_DATA_S, 1),
202 I_WR_REG_BIT(RTC_GPIO_OUT_REG, ext_rtc_io + RTC_GPIO_OUT_DATA_S, 0),
203 I_WR_REG_BIT(RTC_CNTL_HOLD_FORCE_REG, RTC_CNTL_PDAC1_HOLD_FORCE_S, 1),
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| /hal_espressif-3.6.0/components/ulp/include/esp32s3/ |
| D | ulp.h | 342 #define I_WR_REG_BIT(reg, shift, val) I_WR_REG(reg, shift, shift, val) macro
378 I_WR_REG_BIT(RTC_CNTL_STATE0_REG, RTC_CNTL_ULP_CP_SLP_TIMER_EN_S, 0)
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| /hal_espressif-3.6.0/components/ulp/include/esp32s2/ |
| D | ulp.h | 341 #define I_WR_REG_BIT(reg, shift, val) I_WR_REG(reg, shift, shift, val) macro
377 I_WR_REG_BIT(RTC_CNTL_STATE0_REG, RTC_CNTL_ULP_CP_SLP_TIMER_EN_S, 0)
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| /hal_espressif-3.6.0/components/ulp/include/esp32/ |
| D | ulp.h | 375 #define I_WR_REG_BIT(reg, shift, val) I_WR_REG(reg, shift, shift, val) macro
411 I_WR_REG_BIT(RTC_CNTL_STATE0_REG, RTC_CNTL_ULP_CP_SLP_TIMER_EN_S, 0)
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| /hal_espressif-3.6.0/examples/system/deep_sleep/main/ |
| D | deep_sleep_example_main.c | 396 I_WR_REG_BIT(RTC_CNTL_STATE0_REG, RTC_CNTL_ULP_CP_SLP_TIMER_EN_S, 0), in start_ulp_temperature_monitoring()
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