Searched refs:I_WR_REG (Results 1 – 6 of 6) sorted by relevance
| /hal_espressif-3.6.0/components/ulp/test/esp32/ |
| D | test_ulp.c | 145 I_WR_REG(RTC_CNTL_STORE0_REG, 0, 7, 0x89),
146 I_WR_REG(RTC_CNTL_STORE0_REG, 8, 15, 0xab),
147 I_WR_REG(RTC_CNTL_STORE0_REG, 16, 23, 0xcd),
148 I_WR_REG(RTC_CNTL_STORE0_REG, 24, 31, 0xef),
198 I_WR_REG(RTC_CNTL_STORE0_REG,
202 I_WR_REG(RTC_CNTL_STORE1_REG,
236 I_WR_REG(RTC_GPIO_OUT_REG, 26, 27, 1), // RTC_GPIO12 = 1
239 I_WR_REG(RTC_GPIO_OUT_REG, 26, 27, 0), // RTC_GPIO12 = 0
363 I_WR_REG(SENS_SAR_MEAS_WAIT2_REG, SENS_FORCE_XPD_SAR_S, SENS_FORCE_XPD_SAR_S + 1, 3),
365 I_WR_REG(SENS_SAR_MEAS_WAIT2_REG, SENS_FORCE_XPD_SAR_S, SENS_FORCE_XPD_SAR_S + 1, 0),
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| /hal_espressif-3.6.0/examples/system/deep_sleep/main/ |
| D | deep_sleep_example_main.c | 363 I_WR_REG(SENS_SAR_MEAS_WAIT2_REG, SENS_FORCE_XPD_SAR_S, SENS_FORCE_XPD_SAR_S + 1, 3), in start_ulp_temperature_monitoring()
367 I_WR_REG(SENS_SAR_MEAS_WAIT2_REG, SENS_FORCE_XPD_SAR_S, SENS_FORCE_XPD_SAR_S + 1, 0), in start_ulp_temperature_monitoring()
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| /hal_espressif-3.6.0/components/ulp/include/esp32s3/ |
| D | ulp.h | 314 #define I_WR_REG(reg, low_bit, high_bit, val) {.wr_reg = {\ macro
342 #define I_WR_REG_BIT(reg, shift, val) I_WR_REG(reg, shift, shift, val)
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| /hal_espressif-3.6.0/components/ulp/include/esp32s2/ |
| D | ulp.h | 313 #define I_WR_REG(reg, low_bit, high_bit, val) {.wr_reg = {\ macro
341 #define I_WR_REG_BIT(reg, shift, val) I_WR_REG(reg, shift, shift, val)
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| /hal_espressif-3.6.0/components/ulp/include/esp32/ |
| D | ulp.h | 347 #define I_WR_REG(reg, low_bit, high_bit, val) {.wr_reg = {\ macro
375 #define I_WR_REG_BIT(reg, shift, val) I_WR_REG(reg, shift, shift, val)
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| /hal_espressif-3.6.0/components/ulp/ |
| D | README.rst | 106 .. doxygendefine:: I_WR_REG
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