1 // Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 #ifndef _SOC_I2C_REG_H_ 15 #define _SOC_I2C_REG_H_ 16 17 18 #include "soc.h" 19 20 #define REG_I2C_BASE(i) (DR_REG_I2C_EXT_BASE + (i) * 0x14000 ) 21 22 #define I2C_SCL_LOW_PERIOD_REG(i) (REG_I2C_BASE(i) + 0x0000) 23 /* I2C_SCL_LOW_PERIOD : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ 24 /*description: This register is used to configure the low level width of SCL clock.*/ 25 #define I2C_SCL_LOW_PERIOD 0x00003FFF 26 #define I2C_SCL_LOW_PERIOD_M ((I2C_SCL_LOW_PERIOD_V)<<(I2C_SCL_LOW_PERIOD_S)) 27 #define I2C_SCL_LOW_PERIOD_V 0x3FFF 28 #define I2C_SCL_LOW_PERIOD_S 0 29 30 #define I2C_CTR_REG(i) (REG_I2C_BASE(i) + 0x0004) 31 /* I2C_CLK_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */ 32 /*description: This is the clock gating control bit for reading or writing registers.*/ 33 #define I2C_CLK_EN (BIT(8)) 34 #define I2C_CLK_EN_M (BIT(8)) 35 #define I2C_CLK_EN_V 0x1 36 #define I2C_CLK_EN_S 8 37 /* I2C_RX_LSB_FIRST : R/W ;bitpos:[7] ;default: 1'h0 ; */ 38 /*description: This bit is used to control the storage mode for received datas. 39 1: receive data from most significant bit 0: receive data from least significant bit*/ 40 #define I2C_RX_LSB_FIRST (BIT(7)) 41 #define I2C_RX_LSB_FIRST_M (BIT(7)) 42 #define I2C_RX_LSB_FIRST_V 0x1 43 #define I2C_RX_LSB_FIRST_S 7 44 /* I2C_TX_LSB_FIRST : R/W ;bitpos:[6] ;default: 1'b0 ; */ 45 /*description: This bit is used to control the sending mode for data need to 46 be send. 1: receive data from most significant bit 0: receive data from least significant bit*/ 47 #define I2C_TX_LSB_FIRST (BIT(6)) 48 #define I2C_TX_LSB_FIRST_M (BIT(6)) 49 #define I2C_TX_LSB_FIRST_V 0x1 50 #define I2C_TX_LSB_FIRST_S 6 51 /* I2C_TRANS_START : R/W ;bitpos:[5] ;default: 1'b0 ; */ 52 /*description: Set this bit to start sending data in txfifo.*/ 53 #define I2C_TRANS_START (BIT(5)) 54 #define I2C_TRANS_START_M (BIT(5)) 55 #define I2C_TRANS_START_V 0x1 56 #define I2C_TRANS_START_S 5 57 /* I2C_MS_MODE : R/W ;bitpos:[4] ;default: 1'b0 ; */ 58 /*description: Set this bit to configure the module as i2c master clear this 59 bit to configure the module as i2c slave.*/ 60 #define I2C_MS_MODE (BIT(4)) 61 #define I2C_MS_MODE_M (BIT(4)) 62 #define I2C_MS_MODE_V 0x1 63 #define I2C_MS_MODE_S 4 64 /* I2C_SAMPLE_SCL_LEVEL : R/W ;bitpos:[2] ;default: 1'b0 ; */ 65 /*description: Set this bit to sample data in SCL low level. clear this bit 66 to sample data in SCL high level.*/ 67 #define I2C_SAMPLE_SCL_LEVEL (BIT(2)) 68 #define I2C_SAMPLE_SCL_LEVEL_M (BIT(2)) 69 #define I2C_SAMPLE_SCL_LEVEL_V 0x1 70 #define I2C_SAMPLE_SCL_LEVEL_S 2 71 /* I2C_SCL_FORCE_OUT : R/W ;bitpos:[1] ;default: 1'b1 ; */ 72 /*description: 1: normally ouput scl clock 0: exchange the function of scl_o 73 and scl_oe (scl_o is the original internal output scl signal scl_oe is the enable bit for the internal output scl signal)*/ 74 #define I2C_SCL_FORCE_OUT (BIT(1)) 75 #define I2C_SCL_FORCE_OUT_M (BIT(1)) 76 #define I2C_SCL_FORCE_OUT_V 0x1 77 #define I2C_SCL_FORCE_OUT_S 1 78 /* I2C_SDA_FORCE_OUT : R/W ;bitpos:[0] ;default: 1'b1 ; */ 79 /*description: 1: normally ouput sda data 0: exchange the function of sda_o 80 and sda_oe (sda_o is the original internal output sda signal sda_oe is the enable bit for the internal output sda signal)*/ 81 #define I2C_SDA_FORCE_OUT (BIT(0)) 82 #define I2C_SDA_FORCE_OUT_M (BIT(0)) 83 #define I2C_SDA_FORCE_OUT_V 0x1 84 #define I2C_SDA_FORCE_OUT_S 0 85 86 #define I2C_SR_REG(i) (REG_I2C_BASE(i) + 0x0008) 87 /* I2C_SCL_STATE_LAST : RO ;bitpos:[30:28] ;default: 3'b0 ; */ 88 /*description: This register stores the value of state machine to produce SCL. 89 3'h0: SCL_IDLE 3'h1:SCL_START 3'h2:SCL_LOW_EDGE 3'h3: SCL_LOW 3'h4:SCL_HIGH_EDGE 3'h5:SCL_HIGH 3'h6:SCL_STOP*/ 90 #define I2C_SCL_STATE_LAST 0x00000007 91 #define I2C_SCL_STATE_LAST_M ((I2C_SCL_STATE_LAST_V)<<(I2C_SCL_STATE_LAST_S)) 92 #define I2C_SCL_STATE_LAST_V 0x7 93 #define I2C_SCL_STATE_LAST_S 28 94 /* I2C_SCL_MAIN_STATE_LAST : RO ;bitpos:[26:24] ;default: 3'b0 ; */ 95 /*description: This register stores the value of state machine for i2c module. 96 3'h0: SCL_MAIN_IDLE 3'h1: SCL_ADDRESS_SHIFT 3'h2: SCL_ACK_ADDRESS 3'h3: SCL_RX_DATA 3'h4 SCL_TX_DATA 3'h5:SCL_SEND_ACK 3'h6:SCL_WAIT_ACK*/ 97 #define I2C_SCL_MAIN_STATE_LAST 0x00000007 98 #define I2C_SCL_MAIN_STATE_LAST_M ((I2C_SCL_MAIN_STATE_LAST_V)<<(I2C_SCL_MAIN_STATE_LAST_S)) 99 #define I2C_SCL_MAIN_STATE_LAST_V 0x7 100 #define I2C_SCL_MAIN_STATE_LAST_S 24 101 /* I2C_TXFIFO_CNT : RO ;bitpos:[23:18] ;default: 6'b0 ; */ 102 /*description: This register stores the amount of received data in ram.*/ 103 #define I2C_TXFIFO_CNT 0x0000003F 104 #define I2C_TXFIFO_CNT_M ((I2C_TXFIFO_CNT_V)<<(I2C_TXFIFO_CNT_S)) 105 #define I2C_TXFIFO_CNT_V 0x3F 106 #define I2C_TXFIFO_CNT_S 18 107 /* I2C_RXFIFO_CNT : RO ;bitpos:[13:8] ;default: 6'b0 ; */ 108 /*description: This register represent the amount of data need to send.*/ 109 #define I2C_RXFIFO_CNT 0x0000003F 110 #define I2C_RXFIFO_CNT_M ((I2C_RXFIFO_CNT_V)<<(I2C_RXFIFO_CNT_S)) 111 #define I2C_RXFIFO_CNT_V 0x3F 112 #define I2C_RXFIFO_CNT_S 8 113 /* I2C_BYTE_TRANS : RO ;bitpos:[6] ;default: 1'b0 ; */ 114 /*description: This register changes to high level when one byte is transferred.*/ 115 #define I2C_BYTE_TRANS (BIT(6)) 116 #define I2C_BYTE_TRANS_M (BIT(6)) 117 #define I2C_BYTE_TRANS_V 0x1 118 #define I2C_BYTE_TRANS_S 6 119 /* I2C_SLAVE_ADDRESSED : RO ;bitpos:[5] ;default: 1'b0 ; */ 120 /*description: when configured as i2c slave and the address send by master 121 is equal to slave's address then this bit will be high level.*/ 122 #define I2C_SLAVE_ADDRESSED (BIT(5)) 123 #define I2C_SLAVE_ADDRESSED_M (BIT(5)) 124 #define I2C_SLAVE_ADDRESSED_V 0x1 125 #define I2C_SLAVE_ADDRESSED_S 5 126 /* I2C_BUS_BUSY : RO ;bitpos:[4] ;default: 1'b0 ; */ 127 /*description: 1:I2C bus is busy transferring data. 0:I2C bus is in idle state.*/ 128 #define I2C_BUS_BUSY (BIT(4)) 129 #define I2C_BUS_BUSY_M (BIT(4)) 130 #define I2C_BUS_BUSY_V 0x1 131 #define I2C_BUS_BUSY_S 4 132 /* I2C_ARB_LOST : RO ;bitpos:[3] ;default: 1'b0 ; */ 133 /*description: when I2C lost control of SDA line this register changes to high level.*/ 134 #define I2C_ARB_LOST (BIT(3)) 135 #define I2C_ARB_LOST_M (BIT(3)) 136 #define I2C_ARB_LOST_V 0x1 137 #define I2C_ARB_LOST_S 3 138 /* I2C_TIME_OUT : RO ;bitpos:[2] ;default: 1'b0 ; */ 139 /*description: when I2C takes more than time_out_reg clocks to receive a data 140 then this register changes to high level.*/ 141 #define I2C_TIME_OUT (BIT(2)) 142 #define I2C_TIME_OUT_M (BIT(2)) 143 #define I2C_TIME_OUT_V 0x1 144 #define I2C_TIME_OUT_S 2 145 /* I2C_SLAVE_RW : RO ;bitpos:[1] ;default: 1'b0 ; */ 146 /*description: when in slave mode 1: master read slave 0: master write slave.*/ 147 #define I2C_SLAVE_RW (BIT(1)) 148 #define I2C_SLAVE_RW_M (BIT(1)) 149 #define I2C_SLAVE_RW_V 0x1 150 #define I2C_SLAVE_RW_S 1 151 /* I2C_ACK_REC : RO ;bitpos:[0] ;default: 1'b0 ; */ 152 /*description: This register stores the value of ACK bit.*/ 153 #define I2C_ACK_REC (BIT(0)) 154 #define I2C_ACK_REC_M (BIT(0)) 155 #define I2C_ACK_REC_V 0x1 156 #define I2C_ACK_REC_S 0 157 158 #define I2C_TO_REG(i) (REG_I2C_BASE(i) + 0x000c) 159 /* I2C_TIME_OUT_REG : R/W ;bitpos:[19:0] ;default: 20'b0 ; */ 160 /*description: This register is used to configure the max clock number of receiving a data.*/ 161 #define I2C_TIME_OUT_REG 0x000FFFFF 162 #define I2C_TIME_OUT_REG_M ((I2C_TIME_OUT_REG_V)<<(I2C_TIME_OUT_REG_S)) 163 #define I2C_TIME_OUT_REG_V 0xFFFFF 164 #define I2C_TIME_OUT_REG_S 0 165 166 #define I2C_SLAVE_ADDR_REG(i) (REG_I2C_BASE(i) + 0x0010) 167 /* I2C_ADDR_10BIT_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ 168 /*description: This register is used to enable slave 10bit address mode.*/ 169 #define I2C_ADDR_10BIT_EN (BIT(31)) 170 #define I2C_ADDR_10BIT_EN_M (BIT(31)) 171 #define I2C_ADDR_10BIT_EN_V 0x1 172 #define I2C_ADDR_10BIT_EN_S 31 173 /* I2C_SLAVE_ADDR : R/W ;bitpos:[14:0] ;default: 15'b0 ; */ 174 /*description: when configured as i2c slave this register is used to configure 175 slave's address.*/ 176 #define I2C_SLAVE_ADDR 0x00007FFF 177 #define I2C_SLAVE_ADDR_M ((I2C_SLAVE_ADDR_V)<<(I2C_SLAVE_ADDR_S)) 178 #define I2C_SLAVE_ADDR_V 0x7FFF 179 #define I2C_SLAVE_ADDR_S 0 180 181 #define I2C_RXFIFO_ST_REG(i) (REG_I2C_BASE(i) + 0x0014) 182 /* I2C_TXFIFO_END_ADDR : RO ;bitpos:[19:15] ;default: 5'b0 ; */ 183 /*description: This is the offset address of the last sending data as described 184 in nonfifo_tx_thres register.*/ 185 #define I2C_TXFIFO_END_ADDR 0x0000001F 186 #define I2C_TXFIFO_END_ADDR_M ((I2C_TXFIFO_END_ADDR_V)<<(I2C_TXFIFO_END_ADDR_S)) 187 #define I2C_TXFIFO_END_ADDR_V 0x1F 188 #define I2C_TXFIFO_END_ADDR_S 15 189 /* I2C_TXFIFO_START_ADDR : RO ;bitpos:[14:10] ;default: 5'b0 ; */ 190 /*description: This is the offset address of the first sending data as described 191 in nonfifo_tx_thres register.*/ 192 #define I2C_TXFIFO_START_ADDR 0x0000001F 193 #define I2C_TXFIFO_START_ADDR_M ((I2C_TXFIFO_START_ADDR_V)<<(I2C_TXFIFO_START_ADDR_S)) 194 #define I2C_TXFIFO_START_ADDR_V 0x1F 195 #define I2C_TXFIFO_START_ADDR_S 10 196 /* I2C_RXFIFO_END_ADDR : RO ;bitpos:[9:5] ;default: 5'b0 ; */ 197 /*description: This is the offset address of the first receiving data as described 198 in nonfifo_rx_thres_register.*/ 199 #define I2C_RXFIFO_END_ADDR 0x0000001F 200 #define I2C_RXFIFO_END_ADDR_M ((I2C_RXFIFO_END_ADDR_V)<<(I2C_RXFIFO_END_ADDR_S)) 201 #define I2C_RXFIFO_END_ADDR_V 0x1F 202 #define I2C_RXFIFO_END_ADDR_S 5 203 /* I2C_RXFIFO_START_ADDR : RO ;bitpos:[4:0] ;default: 5'b0 ; */ 204 /*description: This is the offset address of the last receiving data as described 205 in nonfifo_rx_thres_register.*/ 206 #define I2C_RXFIFO_START_ADDR 0x0000001F 207 #define I2C_RXFIFO_START_ADDR_M ((I2C_RXFIFO_START_ADDR_V)<<(I2C_RXFIFO_START_ADDR_S)) 208 #define I2C_RXFIFO_START_ADDR_V 0x1F 209 #define I2C_RXFIFO_START_ADDR_S 0 210 211 #define I2C_FIFO_CONF_REG(i) (REG_I2C_BASE(i) + 0x0018) 212 /* I2C_NONFIFO_TX_THRES : R/W ;bitpos:[25:20] ;default: 6'h15 ; */ 213 /*description: when I2C sends more than nonfifo_tx_thres data it will produce 214 tx_send_empty_int_raw interrupt and update the current offset address of the sending data.*/ 215 #define I2C_NONFIFO_TX_THRES 0x0000003F 216 #define I2C_NONFIFO_TX_THRES_M ((I2C_NONFIFO_TX_THRES_V)<<(I2C_NONFIFO_TX_THRES_S)) 217 #define I2C_NONFIFO_TX_THRES_V 0x3F 218 #define I2C_NONFIFO_TX_THRES_S 20 219 /* I2C_NONFIFO_RX_THRES : R/W ;bitpos:[19:14] ;default: 6'h15 ; */ 220 /*description: when I2C receives more than nonfifo_rx_thres data it will produce 221 rx_send_full_int_raw interrupt and update the current offset address of the receiving data.*/ 222 #define I2C_NONFIFO_RX_THRES 0x0000003F 223 #define I2C_NONFIFO_RX_THRES_M ((I2C_NONFIFO_RX_THRES_V)<<(I2C_NONFIFO_RX_THRES_S)) 224 #define I2C_NONFIFO_RX_THRES_V 0x3F 225 #define I2C_NONFIFO_RX_THRES_S 14 226 /* I2C_TX_FIFO_RST : R/W ;bitpos:[13] ;default: 1'b0 ; */ 227 /*description: Set this bit to reset tx fifo when using apb fifo access.*/ 228 #define I2C_TX_FIFO_RST (BIT(13)) 229 #define I2C_TX_FIFO_RST_M (BIT(13)) 230 #define I2C_TX_FIFO_RST_V 0x1 231 #define I2C_TX_FIFO_RST_S 13 232 /* I2C_RX_FIFO_RST : R/W ;bitpos:[12] ;default: 1'b0 ; */ 233 /*description: Set this bit to reset rx fifo when using apb fifo access.*/ 234 #define I2C_RX_FIFO_RST (BIT(12)) 235 #define I2C_RX_FIFO_RST_M (BIT(12)) 236 #define I2C_RX_FIFO_RST_V 0x1 237 #define I2C_RX_FIFO_RST_S 12 238 /* I2C_FIFO_ADDR_CFG_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */ 239 /*description: When this bit is set to 1 then the byte after address represent 240 the offset address of I2C Slave's ram.*/ 241 #define I2C_FIFO_ADDR_CFG_EN (BIT(11)) 242 #define I2C_FIFO_ADDR_CFG_EN_M (BIT(11)) 243 #define I2C_FIFO_ADDR_CFG_EN_V 0x1 244 #define I2C_FIFO_ADDR_CFG_EN_S 11 245 /* I2C_NONFIFO_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ 246 /*description: Set this bit to enble apb nonfifo access.*/ 247 #define I2C_NONFIFO_EN (BIT(10)) 248 #define I2C_NONFIFO_EN_M (BIT(10)) 249 #define I2C_NONFIFO_EN_V 0x1 250 #define I2C_NONFIFO_EN_S 10 251 /* I2C_TXFIFO_EMPTY_THRHD : R/W ;bitpos:[9:5] ;default: 5'h4 ; */ 252 /*description: Config txfifo empty threhd value when using apb fifo access*/ 253 #define I2C_TXFIFO_EMPTY_THRHD 0x0000001F 254 #define I2C_TXFIFO_EMPTY_THRHD_M ((I2C_TXFIFO_EMPTY_THRHD_V)<<(I2C_TXFIFO_EMPTY_THRHD_S)) 255 #define I2C_TXFIFO_EMPTY_THRHD_V 0x1F 256 #define I2C_TXFIFO_EMPTY_THRHD_S 5 257 /* I2C_RXFIFO_FULL_THRHD : R/W ;bitpos:[4:0] ;default: 5'hb ; */ 258 /*description: */ 259 #define I2C_RXFIFO_FULL_THRHD 0x0000001F 260 #define I2C_RXFIFO_FULL_THRHD_M ((I2C_RXFIFO_FULL_THRHD_V)<<(I2C_RXFIFO_FULL_THRHD_S)) 261 #define I2C_RXFIFO_FULL_THRHD_V 0x1F 262 #define I2C_RXFIFO_FULL_THRHD_S 0 263 264 #define I2C_DATA_APB_REG(i) (0x60013000 + (i) * 0x14000 + 0x001c) 265 266 #define I2C_DATA_REG(i) (REG_I2C_BASE(i) + 0x001c) 267 /* I2C_FIFO_RDATA : RO ;bitpos:[7:0] ;default: 8'b0 ; */ 268 /*description: The register represent the byte data read from rxfifo when use apb fifo access*/ 269 #define I2C_FIFO_RDATA 0x000000FF 270 #define I2C_FIFO_RDATA_M ((I2C_FIFO_RDATA_V)<<(I2C_FIFO_RDATA_S)) 271 #define I2C_FIFO_RDATA_V 0xFF 272 #define I2C_FIFO_RDATA_S 0 273 274 #define I2C_INT_RAW_REG(i) (REG_I2C_BASE(i) + 0x0020) 275 /* I2C_TX_SEND_EMPTY_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */ 276 /*description: The raw interrupt status bit for tx_send_empty_int interrupt.when 277 I2C sends more data than nonfifo_tx_thres it will produce tx_send_empty_int interrupt..*/ 278 #define I2C_TX_SEND_EMPTY_INT_RAW (BIT(12)) 279 #define I2C_TX_SEND_EMPTY_INT_RAW_M (BIT(12)) 280 #define I2C_TX_SEND_EMPTY_INT_RAW_V 0x1 281 #define I2C_TX_SEND_EMPTY_INT_RAW_S 12 282 /* I2C_RX_REC_FULL_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */ 283 /*description: The raw interrupt status bit for rx_rec_full_int interrupt. when 284 I2C receives more data than nonfifo_rx_thres it will produce rx_rec_full_int interrupt.*/ 285 #define I2C_RX_REC_FULL_INT_RAW (BIT(11)) 286 #define I2C_RX_REC_FULL_INT_RAW_M (BIT(11)) 287 #define I2C_RX_REC_FULL_INT_RAW_V 0x1 288 #define I2C_RX_REC_FULL_INT_RAW_S 11 289 /* I2C_ACK_ERR_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */ 290 /*description: The raw interrupt status bit for ack_err_int interrupt. when 291 I2C receives a wrong ACK bit it will produce ack_err_int interrupt..*/ 292 #define I2C_ACK_ERR_INT_RAW (BIT(10)) 293 #define I2C_ACK_ERR_INT_RAW_M (BIT(10)) 294 #define I2C_ACK_ERR_INT_RAW_V 0x1 295 #define I2C_ACK_ERR_INT_RAW_S 10 296 /* I2C_TRANS_START_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */ 297 /*description: The raw interrupt status bit for trans_start_int interrupt. when 298 I2C sends the START bit it will produce trans_start_int interrupt.*/ 299 #define I2C_TRANS_START_INT_RAW (BIT(9)) 300 #define I2C_TRANS_START_INT_RAW_M (BIT(9)) 301 #define I2C_TRANS_START_INT_RAW_V 0x1 302 #define I2C_TRANS_START_INT_RAW_S 9 303 /* I2C_TIME_OUT_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */ 304 /*description: The raw interrupt status bit for time_out_int interrupt. when 305 I2C takes a lot of time to receive a data it will produce time_out_int interrupt.*/ 306 #define I2C_TIME_OUT_INT_RAW (BIT(8)) 307 #define I2C_TIME_OUT_INT_RAW_M (BIT(8)) 308 #define I2C_TIME_OUT_INT_RAW_V 0x1 309 #define I2C_TIME_OUT_INT_RAW_S 8 310 /* I2C_TRANS_COMPLETE_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */ 311 /*description: The raw interrupt status bit for trans_complete_int interrupt. 312 when I2C Master finished STOP command it will produce trans_complete_int interrupt.*/ 313 #define I2C_TRANS_COMPLETE_INT_RAW (BIT(7)) 314 #define I2C_TRANS_COMPLETE_INT_RAW_M (BIT(7)) 315 #define I2C_TRANS_COMPLETE_INT_RAW_V 0x1 316 #define I2C_TRANS_COMPLETE_INT_RAW_S 7 317 /* I2C_MASTER_TRAN_COMP_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ 318 /*description: The raw interrupt status bit for master_tra_comp_int interrupt. 319 when I2C Master sends or receives a byte it will produce master_tran_comp_int interrupt.*/ 320 #define I2C_MASTER_TRAN_COMP_INT_RAW (BIT(6)) 321 #define I2C_MASTER_TRAN_COMP_INT_RAW_M (BIT(6)) 322 #define I2C_MASTER_TRAN_COMP_INT_RAW_V 0x1 323 #define I2C_MASTER_TRAN_COMP_INT_RAW_S 6 324 /* I2C_ARBITRATION_LOST_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ 325 /*description: The raw interrupt status bit for arbitration_lost_int interrupt.when 326 I2C lost the usage right of I2C BUS it will produce arbitration_lost_int interrupt.*/ 327 #define I2C_ARBITRATION_LOST_INT_RAW (BIT(5)) 328 #define I2C_ARBITRATION_LOST_INT_RAW_M (BIT(5)) 329 #define I2C_ARBITRATION_LOST_INT_RAW_V 0x1 330 #define I2C_ARBITRATION_LOST_INT_RAW_S 5 331 /* I2C_SLAVE_TRAN_COMP_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ 332 /*description: The raw interrupt status bit for slave_tran_comp_int interrupt. 333 when I2C Slave detectsthe STOP bit it will produce slave_tran_comp_int interrupt.*/ 334 #define I2C_SLAVE_TRAN_COMP_INT_RAW (BIT(4)) 335 #define I2C_SLAVE_TRAN_COMP_INT_RAW_M (BIT(4)) 336 #define I2C_SLAVE_TRAN_COMP_INT_RAW_V 0x1 337 #define I2C_SLAVE_TRAN_COMP_INT_RAW_S 4 338 /* I2C_END_DETECT_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ 339 /*description: The raw interrupt status bit for end_detect_int interrupt. when 340 I2C deals with the END command it will produce end_detect_int interrupt.*/ 341 #define I2C_END_DETECT_INT_RAW (BIT(3)) 342 #define I2C_END_DETECT_INT_RAW_M (BIT(3)) 343 #define I2C_END_DETECT_INT_RAW_V 0x1 344 #define I2C_END_DETECT_INT_RAW_S 3 345 /* I2C_RXFIFO_OVF_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ 346 /*description: The raw interrupt status bit for receiving data overflow when 347 use apb fifo access.*/ 348 #define I2C_RXFIFO_OVF_INT_RAW (BIT(2)) 349 #define I2C_RXFIFO_OVF_INT_RAW_M (BIT(2)) 350 #define I2C_RXFIFO_OVF_INT_RAW_V 0x1 351 #define I2C_RXFIFO_OVF_INT_RAW_S 2 352 /* I2C_TXFIFO_EMPTY_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ 353 /*description: The raw interrupt status bit for txfifo empty when use apb fifo access.*/ 354 #define I2C_TXFIFO_EMPTY_INT_RAW (BIT(1)) 355 #define I2C_TXFIFO_EMPTY_INT_RAW_M (BIT(1)) 356 #define I2C_TXFIFO_EMPTY_INT_RAW_V 0x1 357 #define I2C_TXFIFO_EMPTY_INT_RAW_S 1 358 /* I2C_RXFIFO_FULL_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ 359 /*description: The raw interrupt status bit for rxfifo full when use apb fifo access.*/ 360 #define I2C_RXFIFO_FULL_INT_RAW (BIT(0)) 361 #define I2C_RXFIFO_FULL_INT_RAW_M (BIT(0)) 362 #define I2C_RXFIFO_FULL_INT_RAW_V 0x1 363 #define I2C_RXFIFO_FULL_INT_RAW_S 0 364 365 #define I2C_INT_CLR_REG(i) (REG_I2C_BASE(i) + 0x0024) 366 /* I2C_TX_SEND_EMPTY_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */ 367 /*description: Set this bit to clear the tx_send_empty_int interrupt.*/ 368 #define I2C_TX_SEND_EMPTY_INT_CLR (BIT(12)) 369 #define I2C_TX_SEND_EMPTY_INT_CLR_M (BIT(12)) 370 #define I2C_TX_SEND_EMPTY_INT_CLR_V 0x1 371 #define I2C_TX_SEND_EMPTY_INT_CLR_S 12 372 /* I2C_RX_REC_FULL_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */ 373 /*description: Set this bit to clear the rx_rec_full_int interrupt.*/ 374 #define I2C_RX_REC_FULL_INT_CLR (BIT(11)) 375 #define I2C_RX_REC_FULL_INT_CLR_M (BIT(11)) 376 #define I2C_RX_REC_FULL_INT_CLR_V 0x1 377 #define I2C_RX_REC_FULL_INT_CLR_S 11 378 /* I2C_ACK_ERR_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */ 379 /*description: Set this bit to clear the ack_err_int interrupt.*/ 380 #define I2C_ACK_ERR_INT_CLR (BIT(10)) 381 #define I2C_ACK_ERR_INT_CLR_M (BIT(10)) 382 #define I2C_ACK_ERR_INT_CLR_V 0x1 383 #define I2C_ACK_ERR_INT_CLR_S 10 384 /* I2C_TRANS_START_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */ 385 /*description: Set this bit to clear the trans_start_int interrupt.*/ 386 #define I2C_TRANS_START_INT_CLR (BIT(9)) 387 #define I2C_TRANS_START_INT_CLR_M (BIT(9)) 388 #define I2C_TRANS_START_INT_CLR_V 0x1 389 #define I2C_TRANS_START_INT_CLR_S 9 390 /* I2C_TIME_OUT_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */ 391 /*description: Set this bit to clear the time_out_int interrupt.*/ 392 #define I2C_TIME_OUT_INT_CLR (BIT(8)) 393 #define I2C_TIME_OUT_INT_CLR_M (BIT(8)) 394 #define I2C_TIME_OUT_INT_CLR_V 0x1 395 #define I2C_TIME_OUT_INT_CLR_S 8 396 /* I2C_TRANS_COMPLETE_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */ 397 /*description: Set this bit to clear the trans_complete_int interrupt.*/ 398 #define I2C_TRANS_COMPLETE_INT_CLR (BIT(7)) 399 #define I2C_TRANS_COMPLETE_INT_CLR_M (BIT(7)) 400 #define I2C_TRANS_COMPLETE_INT_CLR_V 0x1 401 #define I2C_TRANS_COMPLETE_INT_CLR_S 7 402 /* I2C_MASTER_TRAN_COMP_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */ 403 /*description: Set this bit to clear the master_tran_comp interrupt.*/ 404 #define I2C_MASTER_TRAN_COMP_INT_CLR (BIT(6)) 405 #define I2C_MASTER_TRAN_COMP_INT_CLR_M (BIT(6)) 406 #define I2C_MASTER_TRAN_COMP_INT_CLR_V 0x1 407 #define I2C_MASTER_TRAN_COMP_INT_CLR_S 6 408 /* I2C_ARBITRATION_LOST_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */ 409 /*description: Set this bit to clear the arbitration_lost_int interrupt.*/ 410 #define I2C_ARBITRATION_LOST_INT_CLR (BIT(5)) 411 #define I2C_ARBITRATION_LOST_INT_CLR_M (BIT(5)) 412 #define I2C_ARBITRATION_LOST_INT_CLR_V 0x1 413 #define I2C_ARBITRATION_LOST_INT_CLR_S 5 414 /* I2C_SLAVE_TRAN_COMP_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ 415 /*description: Set this bit to clear the slave_tran_comp_int interrupt.*/ 416 #define I2C_SLAVE_TRAN_COMP_INT_CLR (BIT(4)) 417 #define I2C_SLAVE_TRAN_COMP_INT_CLR_M (BIT(4)) 418 #define I2C_SLAVE_TRAN_COMP_INT_CLR_V 0x1 419 #define I2C_SLAVE_TRAN_COMP_INT_CLR_S 4 420 /* I2C_END_DETECT_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ 421 /*description: Set this bit to clear the end_detect_int interrupt.*/ 422 #define I2C_END_DETECT_INT_CLR (BIT(3)) 423 #define I2C_END_DETECT_INT_CLR_M (BIT(3)) 424 #define I2C_END_DETECT_INT_CLR_V 0x1 425 #define I2C_END_DETECT_INT_CLR_S 3 426 /* I2C_RXFIFO_OVF_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */ 427 /*description: Set this bit to clear the rxfifo_ovf_int interrupt.*/ 428 #define I2C_RXFIFO_OVF_INT_CLR (BIT(2)) 429 #define I2C_RXFIFO_OVF_INT_CLR_M (BIT(2)) 430 #define I2C_RXFIFO_OVF_INT_CLR_V 0x1 431 #define I2C_RXFIFO_OVF_INT_CLR_S 2 432 /* I2C_TXFIFO_EMPTY_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ 433 /*description: Set this bit to clear the txfifo_empty_int interrupt.*/ 434 #define I2C_TXFIFO_EMPTY_INT_CLR (BIT(1)) 435 #define I2C_TXFIFO_EMPTY_INT_CLR_M (BIT(1)) 436 #define I2C_TXFIFO_EMPTY_INT_CLR_V 0x1 437 #define I2C_TXFIFO_EMPTY_INT_CLR_S 1 438 /* I2C_RXFIFO_FULL_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ 439 /*description: Set this bit to clear the rxfifo_full_int interrupt.*/ 440 #define I2C_RXFIFO_FULL_INT_CLR (BIT(0)) 441 #define I2C_RXFIFO_FULL_INT_CLR_M (BIT(0)) 442 #define I2C_RXFIFO_FULL_INT_CLR_V 0x1 443 #define I2C_RXFIFO_FULL_INT_CLR_S 0 444 445 #define I2C_INT_ENA_REG(i) (REG_I2C_BASE(i) + 0x0028) 446 /* I2C_TX_SEND_EMPTY_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */ 447 /*description: The enable bit for tx_send_empty_int interrupt.*/ 448 #define I2C_TX_SEND_EMPTY_INT_ENA (BIT(12)) 449 #define I2C_TX_SEND_EMPTY_INT_ENA_M (BIT(12)) 450 #define I2C_TX_SEND_EMPTY_INT_ENA_V 0x1 451 #define I2C_TX_SEND_EMPTY_INT_ENA_S 12 452 /* I2C_RX_REC_FULL_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ 453 /*description: The enable bit for rx_rec_full_int interrupt.*/ 454 #define I2C_RX_REC_FULL_INT_ENA (BIT(11)) 455 #define I2C_RX_REC_FULL_INT_ENA_M (BIT(11)) 456 #define I2C_RX_REC_FULL_INT_ENA_V 0x1 457 #define I2C_RX_REC_FULL_INT_ENA_S 11 458 /* I2C_ACK_ERR_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ 459 /*description: The enable bit for ack_err_int interrupt.*/ 460 #define I2C_ACK_ERR_INT_ENA (BIT(10)) 461 #define I2C_ACK_ERR_INT_ENA_M (BIT(10)) 462 #define I2C_ACK_ERR_INT_ENA_V 0x1 463 #define I2C_ACK_ERR_INT_ENA_S 10 464 /* I2C_TRANS_START_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ 465 /*description: The enable bit for trans_start_int interrupt.*/ 466 #define I2C_TRANS_START_INT_ENA (BIT(9)) 467 #define I2C_TRANS_START_INT_ENA_M (BIT(9)) 468 #define I2C_TRANS_START_INT_ENA_V 0x1 469 #define I2C_TRANS_START_INT_ENA_S 9 470 /* I2C_TIME_OUT_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ 471 /*description: The enable bit for time_out_int interrupt.*/ 472 #define I2C_TIME_OUT_INT_ENA (BIT(8)) 473 #define I2C_TIME_OUT_INT_ENA_M (BIT(8)) 474 #define I2C_TIME_OUT_INT_ENA_V 0x1 475 #define I2C_TIME_OUT_INT_ENA_S 8 476 /* I2C_TRANS_COMPLETE_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ 477 /*description: The enable bit for trans_complete_int interrupt.*/ 478 #define I2C_TRANS_COMPLETE_INT_ENA (BIT(7)) 479 #define I2C_TRANS_COMPLETE_INT_ENA_M (BIT(7)) 480 #define I2C_TRANS_COMPLETE_INT_ENA_V 0x1 481 #define I2C_TRANS_COMPLETE_INT_ENA_S 7 482 /* I2C_MASTER_TRAN_COMP_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ 483 /*description: The enable bit for master_tran_comp_int interrupt.*/ 484 #define I2C_MASTER_TRAN_COMP_INT_ENA (BIT(6)) 485 #define I2C_MASTER_TRAN_COMP_INT_ENA_M (BIT(6)) 486 #define I2C_MASTER_TRAN_COMP_INT_ENA_V 0x1 487 #define I2C_MASTER_TRAN_COMP_INT_ENA_S 6 488 /* I2C_ARBITRATION_LOST_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ 489 /*description: The enable bit for arbitration_lost_int interrupt.*/ 490 #define I2C_ARBITRATION_LOST_INT_ENA (BIT(5)) 491 #define I2C_ARBITRATION_LOST_INT_ENA_M (BIT(5)) 492 #define I2C_ARBITRATION_LOST_INT_ENA_V 0x1 493 #define I2C_ARBITRATION_LOST_INT_ENA_S 5 494 /* I2C_SLAVE_TRAN_COMP_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ 495 /*description: The enable bit for slave_tran_comp_int interrupt.*/ 496 #define I2C_SLAVE_TRAN_COMP_INT_ENA (BIT(4)) 497 #define I2C_SLAVE_TRAN_COMP_INT_ENA_M (BIT(4)) 498 #define I2C_SLAVE_TRAN_COMP_INT_ENA_V 0x1 499 #define I2C_SLAVE_TRAN_COMP_INT_ENA_S 4 500 /* I2C_END_DETECT_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ 501 /*description: The enable bit for end_detect_int interrupt.*/ 502 #define I2C_END_DETECT_INT_ENA (BIT(3)) 503 #define I2C_END_DETECT_INT_ENA_M (BIT(3)) 504 #define I2C_END_DETECT_INT_ENA_V 0x1 505 #define I2C_END_DETECT_INT_ENA_S 3 506 /* I2C_RXFIFO_OVF_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ 507 /*description: The enable bit for rxfifo_ovf_int interrupt.*/ 508 #define I2C_RXFIFO_OVF_INT_ENA (BIT(2)) 509 #define I2C_RXFIFO_OVF_INT_ENA_M (BIT(2)) 510 #define I2C_RXFIFO_OVF_INT_ENA_V 0x1 511 #define I2C_RXFIFO_OVF_INT_ENA_S 2 512 /* I2C_TXFIFO_EMPTY_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ 513 /*description: The enable bit for txfifo_empty_int interrupt.*/ 514 #define I2C_TXFIFO_EMPTY_INT_ENA (BIT(1)) 515 #define I2C_TXFIFO_EMPTY_INT_ENA_M (BIT(1)) 516 #define I2C_TXFIFO_EMPTY_INT_ENA_V 0x1 517 #define I2C_TXFIFO_EMPTY_INT_ENA_S 1 518 /* I2C_RXFIFO_FULL_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ 519 /*description: The enable bit for rxfifo_full_int interrupt.*/ 520 #define I2C_RXFIFO_FULL_INT_ENA (BIT(0)) 521 #define I2C_RXFIFO_FULL_INT_ENA_M (BIT(0)) 522 #define I2C_RXFIFO_FULL_INT_ENA_V 0x1 523 #define I2C_RXFIFO_FULL_INT_ENA_S 0 524 525 #define I2C_INT_STATUS_REG(i) (REG_I2C_BASE(i) + 0x002c) 526 /* I2C_TX_SEND_EMPTY_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */ 527 /*description: The masked interrupt status for tx_send_empty_int interrupt.*/ 528 #define I2C_TX_SEND_EMPTY_INT_ST (BIT(12)) 529 #define I2C_TX_SEND_EMPTY_INT_ST_M (BIT(12)) 530 #define I2C_TX_SEND_EMPTY_INT_ST_V 0x1 531 #define I2C_TX_SEND_EMPTY_INT_ST_S 12 532 /* I2C_RX_REC_FULL_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ 533 /*description: The masked interrupt status for rx_rec_full_int interrupt.*/ 534 #define I2C_RX_REC_FULL_INT_ST (BIT(11)) 535 #define I2C_RX_REC_FULL_INT_ST_M (BIT(11)) 536 #define I2C_RX_REC_FULL_INT_ST_V 0x1 537 #define I2C_RX_REC_FULL_INT_ST_S 11 538 /* I2C_ACK_ERR_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ 539 /*description: The masked interrupt status for ack_err_int interrupt.*/ 540 #define I2C_ACK_ERR_INT_ST (BIT(10)) 541 #define I2C_ACK_ERR_INT_ST_M (BIT(10)) 542 #define I2C_ACK_ERR_INT_ST_V 0x1 543 #define I2C_ACK_ERR_INT_ST_S 10 544 /* I2C_TRANS_START_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ 545 /*description: The masked interrupt status for trans_start_int interrupt.*/ 546 #define I2C_TRANS_START_INT_ST (BIT(9)) 547 #define I2C_TRANS_START_INT_ST_M (BIT(9)) 548 #define I2C_TRANS_START_INT_ST_V 0x1 549 #define I2C_TRANS_START_INT_ST_S 9 550 /* I2C_TIME_OUT_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ 551 /*description: The masked interrupt status for time_out_int interrupt.*/ 552 #define I2C_TIME_OUT_INT_ST (BIT(8)) 553 #define I2C_TIME_OUT_INT_ST_M (BIT(8)) 554 #define I2C_TIME_OUT_INT_ST_V 0x1 555 #define I2C_TIME_OUT_INT_ST_S 8 556 /* I2C_TRANS_COMPLETE_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ 557 /*description: The masked interrupt status for trans_complete_int interrupt.*/ 558 #define I2C_TRANS_COMPLETE_INT_ST (BIT(7)) 559 #define I2C_TRANS_COMPLETE_INT_ST_M (BIT(7)) 560 #define I2C_TRANS_COMPLETE_INT_ST_V 0x1 561 #define I2C_TRANS_COMPLETE_INT_ST_S 7 562 /* I2C_MASTER_TRAN_COMP_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ 563 /*description: The masked interrupt status for master_tran_comp_int interrupt.*/ 564 #define I2C_MASTER_TRAN_COMP_INT_ST (BIT(6)) 565 #define I2C_MASTER_TRAN_COMP_INT_ST_M (BIT(6)) 566 #define I2C_MASTER_TRAN_COMP_INT_ST_V 0x1 567 #define I2C_MASTER_TRAN_COMP_INT_ST_S 6 568 /* I2C_ARBITRATION_LOST_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ 569 /*description: The masked interrupt status for arbitration_lost_int interrupt.*/ 570 #define I2C_ARBITRATION_LOST_INT_ST (BIT(5)) 571 #define I2C_ARBITRATION_LOST_INT_ST_M (BIT(5)) 572 #define I2C_ARBITRATION_LOST_INT_ST_V 0x1 573 #define I2C_ARBITRATION_LOST_INT_ST_S 5 574 /* I2C_SLAVE_TRAN_COMP_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ 575 /*description: The masked interrupt status for slave_tran_comp_int interrupt.*/ 576 #define I2C_SLAVE_TRAN_COMP_INT_ST (BIT(4)) 577 #define I2C_SLAVE_TRAN_COMP_INT_ST_M (BIT(4)) 578 #define I2C_SLAVE_TRAN_COMP_INT_ST_V 0x1 579 #define I2C_SLAVE_TRAN_COMP_INT_ST_S 4 580 /* I2C_END_DETECT_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ 581 /*description: The masked interrupt status for end_detect_int interrupt.*/ 582 #define I2C_END_DETECT_INT_ST (BIT(3)) 583 #define I2C_END_DETECT_INT_ST_M (BIT(3)) 584 #define I2C_END_DETECT_INT_ST_V 0x1 585 #define I2C_END_DETECT_INT_ST_S 3 586 /* I2C_RXFIFO_OVF_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ 587 /*description: The masked interrupt status for rxfifo_ovf_int interrupt.*/ 588 #define I2C_RXFIFO_OVF_INT_ST (BIT(2)) 589 #define I2C_RXFIFO_OVF_INT_ST_M (BIT(2)) 590 #define I2C_RXFIFO_OVF_INT_ST_V 0x1 591 #define I2C_RXFIFO_OVF_INT_ST_S 2 592 /* I2C_TXFIFO_EMPTY_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ 593 /*description: The masked interrupt status for txfifo_empty_int interrupt.*/ 594 #define I2C_TXFIFO_EMPTY_INT_ST (BIT(1)) 595 #define I2C_TXFIFO_EMPTY_INT_ST_M (BIT(1)) 596 #define I2C_TXFIFO_EMPTY_INT_ST_V 0x1 597 #define I2C_TXFIFO_EMPTY_INT_ST_S 1 598 /* I2C_RXFIFO_FULL_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ 599 /*description: The masked interrupt status for rxfifo_full_int interrupt.*/ 600 #define I2C_RXFIFO_FULL_INT_ST (BIT(0)) 601 #define I2C_RXFIFO_FULL_INT_ST_M (BIT(0)) 602 #define I2C_RXFIFO_FULL_INT_ST_V 0x1 603 #define I2C_RXFIFO_FULL_INT_ST_S 0 604 605 #define I2C_SDA_HOLD_REG(i) (REG_I2C_BASE(i) + 0x0030) 606 /* I2C_SDA_HOLD_TIME : R/W ;bitpos:[9:0] ;default: 10'b0 ; */ 607 /*description: This register is used to configure the clock num I2C used to 608 hold the data after the negedge of SCL.*/ 609 #define I2C_SDA_HOLD_TIME 0x000003FF 610 #define I2C_SDA_HOLD_TIME_M ((I2C_SDA_HOLD_TIME_V)<<(I2C_SDA_HOLD_TIME_S)) 611 #define I2C_SDA_HOLD_TIME_V 0x3FF 612 #define I2C_SDA_HOLD_TIME_S 0 613 614 #define I2C_SDA_SAMPLE_REG(i) (REG_I2C_BASE(i) + 0x0034) 615 /* I2C_SDA_SAMPLE_TIME : R/W ;bitpos:[9:0] ;default: 10'b0 ; */ 616 /*description: This register is used to configure the clock num I2C used to 617 sample data on SDA after the posedge of SCL*/ 618 #define I2C_SDA_SAMPLE_TIME 0x000003FF 619 #define I2C_SDA_SAMPLE_TIME_M ((I2C_SDA_SAMPLE_TIME_V)<<(I2C_SDA_SAMPLE_TIME_S)) 620 #define I2C_SDA_SAMPLE_TIME_V 0x3FF 621 #define I2C_SDA_SAMPLE_TIME_S 0 622 623 #define I2C_SCL_HIGH_PERIOD_REG(i) (REG_I2C_BASE(i) + 0x0038) 624 /* I2C_SCL_HIGH_PERIOD : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ 625 /*description: This register is used to configure the clock num during SCL is low level.*/ 626 #define I2C_SCL_HIGH_PERIOD 0x00003FFF 627 #define I2C_SCL_HIGH_PERIOD_M ((I2C_SCL_HIGH_PERIOD_V)<<(I2C_SCL_HIGH_PERIOD_S)) 628 #define I2C_SCL_HIGH_PERIOD_V 0x3FFF 629 #define I2C_SCL_HIGH_PERIOD_S 0 630 631 #define I2C_SCL_START_HOLD_REG(i) (REG_I2C_BASE(i) + 0x0040) 632 /* I2C_SCL_START_HOLD_TIME : R/W ;bitpos:[9:0] ;default: 10'b1000 ; */ 633 /*description: This register is used to configure the clock num between the 634 negedge of SDA and negedge of SCL for start mark.*/ 635 #define I2C_SCL_START_HOLD_TIME 0x000003FF 636 #define I2C_SCL_START_HOLD_TIME_M ((I2C_SCL_START_HOLD_TIME_V)<<(I2C_SCL_START_HOLD_TIME_S)) 637 #define I2C_SCL_START_HOLD_TIME_V 0x3FF 638 #define I2C_SCL_START_HOLD_TIME_S 0 639 640 #define I2C_SCL_RSTART_SETUP_REG(i) (REG_I2C_BASE(i) + 0x0044) 641 /* I2C_SCL_RSTART_SETUP_TIME : R/W ;bitpos:[9:0] ;default: 10'b1000 ; */ 642 /*description: This register is used to configure the clock num between the 643 posedge of SCL and the negedge of SDA for restart mark.*/ 644 #define I2C_SCL_RSTART_SETUP_TIME 0x000003FF 645 #define I2C_SCL_RSTART_SETUP_TIME_M ((I2C_SCL_RSTART_SETUP_TIME_V)<<(I2C_SCL_RSTART_SETUP_TIME_S)) 646 #define I2C_SCL_RSTART_SETUP_TIME_V 0x3FF 647 #define I2C_SCL_RSTART_SETUP_TIME_S 0 648 649 #define I2C_SCL_STOP_HOLD_REG(i) (REG_I2C_BASE(i) + 0x0048) 650 /* I2C_SCL_STOP_HOLD_TIME : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ 651 /*description: This register is used to configure the clock num after the STOP bit's posedge.*/ 652 #define I2C_SCL_STOP_HOLD_TIME 0x00003FFF 653 #define I2C_SCL_STOP_HOLD_TIME_M ((I2C_SCL_STOP_HOLD_TIME_V)<<(I2C_SCL_STOP_HOLD_TIME_S)) 654 #define I2C_SCL_STOP_HOLD_TIME_V 0x3FFF 655 #define I2C_SCL_STOP_HOLD_TIME_S 0 656 657 #define I2C_SCL_STOP_SETUP_REG(i) (REG_I2C_BASE(i) + 0x004C) 658 /* I2C_SCL_STOP_SETUP_TIME : R/W ;bitpos:[9:0] ;default: 10'b0 ; */ 659 /*description: This register is used to configure the clock num between the 660 posedge of SCL and the posedge of SDA.*/ 661 #define I2C_SCL_STOP_SETUP_TIME 0x000003FF 662 #define I2C_SCL_STOP_SETUP_TIME_M ((I2C_SCL_STOP_SETUP_TIME_V)<<(I2C_SCL_STOP_SETUP_TIME_S)) 663 #define I2C_SCL_STOP_SETUP_TIME_V 0x3FF 664 #define I2C_SCL_STOP_SETUP_TIME_S 0 665 666 #define I2C_SCL_FILTER_CFG_REG(i) (REG_I2C_BASE(i) + 0x0050) 667 /* I2C_SCL_FILTER_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */ 668 /*description: This is the filter enable bit for SCL.*/ 669 #define I2C_SCL_FILTER_EN (BIT(3)) 670 #define I2C_SCL_FILTER_EN_M (BIT(3)) 671 #define I2C_SCL_FILTER_EN_V 0x1 672 #define I2C_SCL_FILTER_EN_S 3 673 /* I2C_SCL_FILTER_THRES : R/W ;bitpos:[2:0] ;default: 3'b0 ; */ 674 /*description: When input SCL's pulse width is smaller than this register value 675 I2C ignores this pulse.*/ 676 #define I2C_SCL_FILTER_THRES 0x00000007 677 #define I2C_SCL_FILTER_THRES_M ((I2C_SCL_FILTER_THRES_V)<<(I2C_SCL_FILTER_THRES_S)) 678 #define I2C_SCL_FILTER_THRES_V 0x7 679 #define I2C_SCL_FILTER_THRES_S 0 680 681 #define I2C_SDA_FILTER_CFG_REG(i) (REG_I2C_BASE(i) + 0x0054) 682 /* I2C_SDA_FILTER_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */ 683 /*description: This is the filter enable bit for SDA.*/ 684 #define I2C_SDA_FILTER_EN (BIT(3)) 685 #define I2C_SDA_FILTER_EN_M (BIT(3)) 686 #define I2C_SDA_FILTER_EN_V 0x1 687 #define I2C_SDA_FILTER_EN_S 3 688 /* I2C_SDA_FILTER_THRES : R/W ;bitpos:[2:0] ;default: 3'b0 ; */ 689 /*description: When input SCL's pulse width is smaller than this register value 690 I2C ignores this pulse.*/ 691 #define I2C_SDA_FILTER_THRES 0x00000007 692 #define I2C_SDA_FILTER_THRES_M ((I2C_SDA_FILTER_THRES_V)<<(I2C_SDA_FILTER_THRES_S)) 693 #define I2C_SDA_FILTER_THRES_V 0x7 694 #define I2C_SDA_FILTER_THRES_S 0 695 696 #define I2C_COMD0_REG(i) (REG_I2C_BASE(i) + 0x0058) 697 /* I2C_COMMAND0_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ 698 /*description: When command0 is done in I2C Master mode this bit changes to high level.*/ 699 #define I2C_COMMAND0_DONE (BIT(31)) 700 #define I2C_COMMAND0_DONE_M (BIT(31)) 701 #define I2C_COMMAND0_DONE_V 0x1 702 #define I2C_COMMAND0_DONE_S 31 703 /* I2C_COMMAND0 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ 704 /*description: This is the content of command0. It consists of three part. op_code 705 is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ 706 #define I2C_COMMAND0 0x00003FFF 707 #define I2C_COMMAND0_M ((I2C_COMMAND0_V)<<(I2C_COMMAND0_S)) 708 #define I2C_COMMAND0_V 0x3FFF 709 #define I2C_COMMAND0_S 0 710 711 #define I2C_COMD1_REG(i) (REG_I2C_BASE(i) + 0x005C) 712 /* I2C_COMMAND1_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ 713 /*description: When command1 is done in I2C Master mode this bit changes to high level.*/ 714 #define I2C_COMMAND1_DONE (BIT(31)) 715 #define I2C_COMMAND1_DONE_M (BIT(31)) 716 #define I2C_COMMAND1_DONE_V 0x1 717 #define I2C_COMMAND1_DONE_S 31 718 /* I2C_COMMAND1 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ 719 /*description: This is the content of command1. It consists of three part. op_code 720 is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ 721 #define I2C_COMMAND1 0x00003FFF 722 #define I2C_COMMAND1_M ((I2C_COMMAND1_V)<<(I2C_COMMAND1_S)) 723 #define I2C_COMMAND1_V 0x3FFF 724 #define I2C_COMMAND1_S 0 725 726 #define I2C_COMD2_REG(i) (REG_I2C_BASE(i) + 0x0060) 727 /* I2C_COMMAND2_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ 728 /*description: When command2 is done in I2C Master mode this bit changes to high level.*/ 729 #define I2C_COMMAND2_DONE (BIT(31)) 730 #define I2C_COMMAND2_DONE_M (BIT(31)) 731 #define I2C_COMMAND2_DONE_V 0x1 732 #define I2C_COMMAND2_DONE_S 31 733 /* I2C_COMMAND2 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ 734 /*description: This is the content of command2. It consists of three part. op_code 735 is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ 736 #define I2C_COMMAND2 0x00003FFF 737 #define I2C_COMMAND2_M ((I2C_COMMAND2_V)<<(I2C_COMMAND2_S)) 738 #define I2C_COMMAND2_V 0x3FFF 739 #define I2C_COMMAND2_S 0 740 741 #define I2C_COMD3_REG(i) (REG_I2C_BASE(i) + 0x0064) 742 /* I2C_COMMAND3_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ 743 /*description: When command3 is done in I2C Master mode this bit changes to high level.*/ 744 #define I2C_COMMAND3_DONE (BIT(31)) 745 #define I2C_COMMAND3_DONE_M (BIT(31)) 746 #define I2C_COMMAND3_DONE_V 0x1 747 #define I2C_COMMAND3_DONE_S 31 748 /* I2C_COMMAND3 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ 749 /*description: This is the content of command3. It consists of three part. op_code 750 is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ 751 #define I2C_COMMAND3 0x00003FFF 752 #define I2C_COMMAND3_M ((I2C_COMMAND3_V)<<(I2C_COMMAND3_S)) 753 #define I2C_COMMAND3_V 0x3FFF 754 #define I2C_COMMAND3_S 0 755 756 #define I2C_COMD4_REG(i) (REG_I2C_BASE(i) + 0x0068) 757 /* I2C_COMMAND4_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ 758 /*description: When command4 is done in I2C Master mode this bit changes to high level.*/ 759 #define I2C_COMMAND4_DONE (BIT(31)) 760 #define I2C_COMMAND4_DONE_M (BIT(31)) 761 #define I2C_COMMAND4_DONE_V 0x1 762 #define I2C_COMMAND4_DONE_S 31 763 /* I2C_COMMAND4 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ 764 /*description: This is the content of command4. It consists of three part. op_code 765 is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ 766 #define I2C_COMMAND4 0x00003FFF 767 #define I2C_COMMAND4_M ((I2C_COMMAND4_V)<<(I2C_COMMAND4_S)) 768 #define I2C_COMMAND4_V 0x3FFF 769 #define I2C_COMMAND4_S 0 770 771 #define I2C_COMD5_REG(i) (REG_I2C_BASE(i) + 0x006C) 772 /* I2C_COMMAND5_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ 773 /*description: When command5 is done in I2C Master mode this bit changes to high level.*/ 774 #define I2C_COMMAND5_DONE (BIT(31)) 775 #define I2C_COMMAND5_DONE_M (BIT(31)) 776 #define I2C_COMMAND5_DONE_V 0x1 777 #define I2C_COMMAND5_DONE_S 31 778 /* I2C_COMMAND5 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ 779 /*description: This is the content of command5. It consists of three part. op_code 780 is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ 781 #define I2C_COMMAND5 0x00003FFF 782 #define I2C_COMMAND5_M ((I2C_COMMAND5_V)<<(I2C_COMMAND5_S)) 783 #define I2C_COMMAND5_V 0x3FFF 784 #define I2C_COMMAND5_S 0 785 786 #define I2C_COMD6_REG(i) (REG_I2C_BASE(i) + 0x0070) 787 /* I2C_COMMAND6_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ 788 /*description: When command6 is done in I2C Master mode this bit changes to high level.*/ 789 #define I2C_COMMAND6_DONE (BIT(31)) 790 #define I2C_COMMAND6_DONE_M (BIT(31)) 791 #define I2C_COMMAND6_DONE_V 0x1 792 #define I2C_COMMAND6_DONE_S 31 793 /* I2C_COMMAND6 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ 794 /*description: This is the content of command6. It consists of three part. op_code 795 is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ 796 #define I2C_COMMAND6 0x00003FFF 797 #define I2C_COMMAND6_M ((I2C_COMMAND6_V)<<(I2C_COMMAND6_S)) 798 #define I2C_COMMAND6_V 0x3FFF 799 #define I2C_COMMAND6_S 0 800 801 #define I2C_COMD7_REG(i) (REG_I2C_BASE(i) + 0x0074) 802 /* I2C_COMMAND7_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ 803 /*description: When command7 is done in I2C Master mode this bit changes to high level.*/ 804 #define I2C_COMMAND7_DONE (BIT(31)) 805 #define I2C_COMMAND7_DONE_M (BIT(31)) 806 #define I2C_COMMAND7_DONE_V 0x1 807 #define I2C_COMMAND7_DONE_S 31 808 /* I2C_COMMAND7 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ 809 /*description: This is the content of command7. It consists of three part. op_code 810 is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ 811 #define I2C_COMMAND7 0x00003FFF 812 #define I2C_COMMAND7_M ((I2C_COMMAND7_V)<<(I2C_COMMAND7_S)) 813 #define I2C_COMMAND7_V 0x3FFF 814 #define I2C_COMMAND7_S 0 815 816 #define I2C_COMD8_REG(i) (REG_I2C_BASE(i) + 0x0078) 817 /* I2C_COMMAND8_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ 818 /*description: When command8 is done in I2C Master mode this bit changes to high level.*/ 819 #define I2C_COMMAND8_DONE (BIT(31)) 820 #define I2C_COMMAND8_DONE_M (BIT(31)) 821 #define I2C_COMMAND8_DONE_V 0x1 822 #define I2C_COMMAND8_DONE_S 31 823 /* I2C_COMMAND8 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ 824 /*description: This is the content of command8. It consists of three part. op_code 825 is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ 826 #define I2C_COMMAND8 0x00003FFF 827 #define I2C_COMMAND8_M ((I2C_COMMAND8_V)<<(I2C_COMMAND8_S)) 828 #define I2C_COMMAND8_V 0x3FFF 829 #define I2C_COMMAND8_S 0 830 831 #define I2C_COMD9_REG(i) (REG_I2C_BASE(i) + 0x007C) 832 /* I2C_COMMAND9_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ 833 /*description: When command9 is done in I2C Master mode this bit changes to high level.*/ 834 #define I2C_COMMAND9_DONE (BIT(31)) 835 #define I2C_COMMAND9_DONE_M (BIT(31)) 836 #define I2C_COMMAND9_DONE_V 0x1 837 #define I2C_COMMAND9_DONE_S 31 838 /* I2C_COMMAND9 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ 839 /*description: This is the content of command9. It consists of three part. op_code 840 is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ 841 #define I2C_COMMAND9 0x00003FFF 842 #define I2C_COMMAND9_M ((I2C_COMMAND9_V)<<(I2C_COMMAND9_S)) 843 #define I2C_COMMAND9_V 0x3FFF 844 #define I2C_COMMAND9_S 0 845 846 #define I2C_COMD10_REG(i) (REG_I2C_BASE(i) + 0x0080) 847 /* I2C_COMMAND10_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ 848 /*description: When command10 is done in I2C Master mode this bit changes to high level.*/ 849 #define I2C_COMMAND10_DONE (BIT(31)) 850 #define I2C_COMMAND10_DONE_M (BIT(31)) 851 #define I2C_COMMAND10_DONE_V 0x1 852 #define I2C_COMMAND10_DONE_S 31 853 /* I2C_COMMAND10 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ 854 /*description: This is the content of command10. It consists of three part. 855 op_code is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ 856 #define I2C_COMMAND10 0x00003FFF 857 #define I2C_COMMAND10_M ((I2C_COMMAND10_V)<<(I2C_COMMAND10_S)) 858 #define I2C_COMMAND10_V 0x3FFF 859 #define I2C_COMMAND10_S 0 860 861 #define I2C_COMD11_REG(i) (REG_I2C_BASE(i) + 0x0084) 862 /* I2C_COMMAND11_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ 863 /*description: When command11 is done in I2C Master mode this bit changes to high level.*/ 864 #define I2C_COMMAND11_DONE (BIT(31)) 865 #define I2C_COMMAND11_DONE_M (BIT(31)) 866 #define I2C_COMMAND11_DONE_V 0x1 867 #define I2C_COMMAND11_DONE_S 31 868 /* I2C_COMMAND11 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ 869 /*description: This is the content of command11. It consists of three part. 870 op_code is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ 871 #define I2C_COMMAND11 0x00003FFF 872 #define I2C_COMMAND11_M ((I2C_COMMAND11_V)<<(I2C_COMMAND11_S)) 873 #define I2C_COMMAND11_V 0x3FFF 874 #define I2C_COMMAND11_S 0 875 876 #define I2C_COMD12_REG(i) (REG_I2C_BASE(i) + 0x0088) 877 /* I2C_COMMAND12_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ 878 /*description: When command12 is done in I2C Master mode this bit changes to high level.*/ 879 #define I2C_COMMAND12_DONE (BIT(31)) 880 #define I2C_COMMAND12_DONE_M (BIT(31)) 881 #define I2C_COMMAND12_DONE_V 0x1 882 #define I2C_COMMAND12_DONE_S 31 883 /* I2C_COMMAND12 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ 884 /*description: This is the content of command12. It consists of three part. 885 op_code is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ 886 #define I2C_COMMAND12 0x00003FFF 887 #define I2C_COMMAND12_M ((I2C_COMMAND12_V)<<(I2C_COMMAND12_S)) 888 #define I2C_COMMAND12_V 0x3FFF 889 #define I2C_COMMAND12_S 0 890 891 #define I2C_COMD13_REG(i) (REG_I2C_BASE(i) + 0x008C) 892 /* I2C_COMMAND13_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ 893 /*description: When command13 is done in I2C Master mode this bit changes to high level.*/ 894 #define I2C_COMMAND13_DONE (BIT(31)) 895 #define I2C_COMMAND13_DONE_M (BIT(31)) 896 #define I2C_COMMAND13_DONE_V 0x1 897 #define I2C_COMMAND13_DONE_S 31 898 /* I2C_COMMAND13 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ 899 /*description: This is the content of command13. It consists of three part. 900 op_code is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ 901 #define I2C_COMMAND13 0x00003FFF 902 #define I2C_COMMAND13_M ((I2C_COMMAND13_V)<<(I2C_COMMAND13_S)) 903 #define I2C_COMMAND13_V 0x3FFF 904 #define I2C_COMMAND13_S 0 905 906 #define I2C_COMD14_REG(i) (REG_I2C_BASE(i) + 0x0090) 907 /* I2C_COMMAND14_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ 908 /*description: When command14 is done in I2C Master mode this bit changes to high level.*/ 909 #define I2C_COMMAND14_DONE (BIT(31)) 910 #define I2C_COMMAND14_DONE_M (BIT(31)) 911 #define I2C_COMMAND14_DONE_V 0x1 912 #define I2C_COMMAND14_DONE_S 31 913 /* I2C_COMMAND14 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ 914 /*description: This is the content of command14. It consists of three part. 915 op_code is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ 916 #define I2C_COMMAND14 0x00003FFF 917 #define I2C_COMMAND14_M ((I2C_COMMAND14_V)<<(I2C_COMMAND14_S)) 918 #define I2C_COMMAND14_V 0x3FFF 919 #define I2C_COMMAND14_S 0 920 921 #define I2C_COMD15_REG(i) (REG_I2C_BASE(i) + 0x0094) 922 /* I2C_COMMAND15_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ 923 /*description: When command15 is done in I2C Master mode this bit changes to high level.*/ 924 #define I2C_COMMAND15_DONE (BIT(31)) 925 #define I2C_COMMAND15_DONE_M (BIT(31)) 926 #define I2C_COMMAND15_DONE_V 0x1 927 #define I2C_COMMAND15_DONE_S 31 928 /* I2C_COMMAND15 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ 929 /*description: This is the content of command15. It consists of three part. 930 op_code is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit.*/ 931 #define I2C_COMMAND15 0x00003FFF 932 #define I2C_COMMAND15_M ((I2C_COMMAND15_V)<<(I2C_COMMAND15_S)) 933 #define I2C_COMMAND15_V 0x3FFF 934 #define I2C_COMMAND15_S 0 935 936 #define I2C_DATE_REG(i) (REG_I2C_BASE(i) + 0x00F8) 937 /* I2C_DATE : R/W ;bitpos:[31:0] ;default: 32'h16042000 ; */ 938 /*description: */ 939 #define I2C_DATE 0xFFFFFFFF 940 #define I2C_DATE_M ((I2C_DATE_V)<<(I2C_DATE_S)) 941 #define I2C_DATE_V 0xFFFFFFFF 942 #define I2C_DATE_S 0 943 944 #define I2C_FIFO_START_ADDR_REG(i) (REG_I2C_BASE(i) + 0x0100) 945 946 947 948 949 #endif /*_SOC_I2C_REG_H_ */ 950
