| /hal_espressif-3.6.0/components/driver/esp32s3/ |
| D | rtc_tempsensor.c | 74 HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_tctrl, tsens_clk_div, tsens.clk_div); in temp_sensor_set_config()
108 HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_peri_clk_gate_conf, tsens_clk_en, 1); in temp_sensor_start()
109 HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_tctrl, tsens_power_up_force, 1); in temp_sensor_start()
110 HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_tctrl2, tsens_xpd_force, 1); in temp_sensor_start()
111 HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_tctrl, tsens_power_up, 1); in temp_sensor_start()
112 HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_tctrl, tsens_dump_out, 0); in temp_sensor_start()
120 HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_tctrl, tsens_power_up_force, 0); in temp_sensor_stop()
121 HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_tctrl2, tsens_xpd_force, 0); in temp_sensor_stop()
122 HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_tctrl, tsens_power_up, 0); in temp_sensor_stop()
142 HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_tctrl, tsens_dump_out, 1); in temp_sensor_read_raw()
[all …]
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| /hal_espressif-3.6.0/components/hal/esp32/include/hal/ |
| D | adc_ll.h | 93 HAL_FORCE_MODIFY_U32_REG_FIELD(SYSCON.saradc_fsm, rstb_wait, rst_wait); in adc_ll_digi_set_fsm_time()
95 HAL_FORCE_MODIFY_U32_REG_FIELD(SYSCON.saradc_fsm, start_wait, start_wait); in adc_ll_digi_set_fsm_time()
97 HAL_FORCE_MODIFY_U32_REG_FIELD(SYSCON.saradc_fsm, standby_wait, standby_wait); in adc_ll_digi_set_fsm_time()
108 HAL_FORCE_MODIFY_U32_REG_FIELD(SYSCON.saradc_fsm, sample_cycle, sample_cycle); in adc_ll_set_sample_cycle()
119 HAL_FORCE_MODIFY_U32_REG_FIELD(SYSCON.saradc_ctrl, sar_clk_div, div); in adc_ll_digi_set_clk_div()
130 HAL_FORCE_MODIFY_U32_REG_FIELD(SYSCON.saradc_ctrl2, max_meas_num, meas_num); in adc_ll_digi_set_convert_limit_num()
334 HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_read_ctrl, sar1_clk_div, div); in adc_ll_set_sar_clk_div()
336 HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_read_ctrl2, sar2_clk_div, div); in adc_ll_set_sar_clk_div()
609 HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_meas_wait1, sar_amp_wait1, 1); in adc_ll_amp_disable()
610 HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_meas_wait1, sar_amp_wait2, 1); in adc_ll_amp_disable()
[all …]
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| D | dac_ll.h | 68 HAL_FORCE_MODIFY_U32_REG_FIELD(RTCIO.pad_dac[channel], dac, value); in dac_ll_update_output_value()
71 HAL_FORCE_MODIFY_U32_REG_FIELD(RTCIO.pad_dac[channel], dac, value); in dac_ll_update_output_value()
130 …HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_dac_ctrl1, sw_fstep, (sw_freq > 0xFFFF) ? 0xFFFF : sw_freq… in dac_ll_cw_set_freq()
177 … HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_dac_ctrl2, dac_dc1, offset ? offset : (-128 - offset)); in dac_ll_cw_set_dc_offset()
182 … HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_dac_ctrl2, dac_dc2, offset ? offset : (-128 - offset)); in dac_ll_cw_set_dc_offset()
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| D | touch_sensor_ll.h | 67 HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_touch_ctrl1, touch_meas_delay, meas_time); in touch_ll_set_meas_time()
69 …HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_touch_ctrl1, touch_xpd_wait, SOC_TOUCH_PAD_MEASURE_WAIT_MA… in touch_ll_set_meas_time()
93 HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_touch_ctrl2, touch_sleep_cycles, sleep_time); in touch_ll_set_sleep_time()
298 HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.touch_thresh[tp_wrap / 2], l_thresh, threshold); in touch_ll_set_threshold()
300 HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.touch_thresh[tp_wrap / 2], h_thresh, threshold); in touch_ll_set_threshold()
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| D | gpio_ll.h | 264 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->status1_w1tc, intr_st, mask); in gpio_ll_clear_intr_status_high()
327 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->enable1_w1tc, data, (0x1 << (gpio_num - 32))); in gpio_ll_output_disable()
346 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->enable1_w1ts, data, (0x1 << (gpio_num - 32))); in gpio_ll_output_enable()
429 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->out1_w1ts, data, (1 << (gpio_num - 32))); in gpio_ll_set_level()
435 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->out1_w1tc, data, (1 << (gpio_num - 32))); in gpio_ll_set_level()
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| D | twai_ll.h | 495 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->error_warning_limit_reg, ewl, ewl); in twai_ll_set_err_warn_lim()
535 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->rx_error_counter_reg, rxerr, rec); in twai_ll_set_rec()
563 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->tx_error_counter_reg, txerr, tec); in twai_ll_set_tec()
582 …HAL_FORCE_MODIFY_U32_REG_FIELD(hw->acceptance_filter.acr[i], byte, ((code_swapped >> (i * 8)) & 0x… in twai_ll_set_acc_filter()
583 …HAL_FORCE_MODIFY_U32_REG_FIELD(hw->acceptance_filter.amr[i], byte, ((mask_swapped >> (i * 8)) & 0x… in twai_ll_set_acc_filter()
825 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->acceptance_filter.acr[i], byte, reg_save->acr_reg[i]); in twai_ll_restore_reg()
826 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->acceptance_filter.amr[i], byte, reg_save->amr_reg[i]); in twai_ll_restore_reg()
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| D | sigmadelta_ll.h | 58 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->channel[channel], duty, (uint32_t)duty); in sigmadelta_ll_set_duty()
70 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->channel[channel], prescale, prescale); in sigmadelta_ll_set_prescale()
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| /hal_espressif-3.6.0/components/hal/esp32h2/include/hal/ |
| D | twai_ll.h | 403 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->error_warning_limit_reg, ewl, ewl); in twai_ll_set_err_warn_lim()
443 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->rx_error_counter_reg, rxerr, rec); in twai_ll_set_rec()
471 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->tx_error_counter_reg, txerr, tec); in twai_ll_set_tec()
490 …HAL_FORCE_MODIFY_U32_REG_FIELD(hw->acceptance_filter.acr[i], byte, ((code_swapped >> (i * 8)) & 0x… in twai_ll_set_acc_filter()
491 …HAL_FORCE_MODIFY_U32_REG_FIELD(hw->acceptance_filter.amr[i], byte, ((mask_swapped >> (i * 8)) & 0x… in twai_ll_set_acc_filter()
656 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clock_divider_reg, cd, (divider / 2) - 1); in twai_ll_set_clkout()
660 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clock_divider_reg, cd, 255); in twai_ll_set_clkout()
663 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clock_divider_reg, cd, 0); in twai_ll_set_clkout()
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| D | uart_ll.h | 169 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clk_conf, sclk_div_num, sclk_div - 1); in uart_ll_set_baudrate()
457 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->txbrk_conf, tx_brk_num, break_num); in uart_ll_tx_break()
524 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf1, xon_char, flow_ctrl->xon_char); in uart_ll_set_sw_flow_ctrl()
525 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf0, xoff_char, flow_ctrl->xoff_char); in uart_ll_set_sw_flow_ctrl()
547 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_char, data, cmd_char->cmd_char); in uart_ll_set_at_cmd_char()
548 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_char, char_num, cmd_char->char_num); in uart_ll_set_at_cmd_char()
549 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_postcnt, post_idle_num, cmd_char->post_idle); in uart_ll_set_at_cmd_char()
550 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_precnt, pre_idle_num, cmd_char->pre_idle); in uart_ll_set_at_cmd_char()
551 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_gaptout, rx_gap_tout, cmd_char->gap_tout); in uart_ll_set_at_cmd_char()
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| D | adc_ll.h | 102 HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.fsm_wait, rstb_wait, rst_wait); in adc_ll_digi_set_fsm_time()
104 HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.fsm_wait, xpd_wait, start_wait); in adc_ll_digi_set_fsm_time()
106 HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.fsm_wait, standby_wait, standby_wait); in adc_ll_digi_set_fsm_time()
132 HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.ctrl, sar_clk_div, div); in adc_ll_digi_set_clk_div()
143 HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.ctrl2, max_meas_num, meas_num); in adc_ll_digi_set_convert_limit_num()
289 HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.apb_adc_clkm_conf, clkm_div_num, div_num); in adc_ll_digi_controller_clk_div()
426 HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.dma_conf, apb_adc_eof_num, num); in adc_ll_digi_dma_set_eof_num()
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| D | spimem_flash_ll.h | 161 HAL_FORCE_MODIFY_U32_REG_FIELD(dev->flash_sus_cmd, flash_pes_command, sus_cmd); in spimem_flash_ll_suspend_cmd_setup()
173 HAL_FORCE_MODIFY_U32_REG_FIELD(dev->flash_sus_cmd, flash_per_command, res_cmd); in spimem_flash_ll_resume_cmd_setup()
185 HAL_FORCE_MODIFY_U32_REG_FIELD(dev->flash_sus_cmd, wait_pesr_command, pesr_cmd); in spimem_flash_ll_rd_sus_cmd_setup()
222 HAL_FORCE_MODIFY_U32_REG_FIELD(dev->flash_sus_ctrl, pesr_end_msk, sus_conf); in spimem_flash_ll_set_read_sus_status()
233 HAL_FORCE_MODIFY_U32_REG_FIELD(dev->flash_waiti_ctrl, waiti_cmd, 0x05); in spimem_flash_ll_auto_wait_idle_init()
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| D | sigmadelta_ll.h | 58 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->channel[channel], duty, (uint32_t)duty); in sigmadelta_ll_set_duty()
70 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->channel[channel], prescale, prescale); in sigmadelta_ll_set_prescale()
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| /hal_espressif-3.6.0/components/hal/esp32s2/include/hal/ |
| D | twai_ll.h | 403 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->error_warning_limit_reg, ewl, ewl); in twai_ll_set_err_warn_lim()
443 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->rx_error_counter_reg, rxerr, rec); in twai_ll_set_rec()
471 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->tx_error_counter_reg, txerr, tec); in twai_ll_set_tec()
490 …HAL_FORCE_MODIFY_U32_REG_FIELD(hw->acceptance_filter.acr[i], byte, ((code_swapped >> (i * 8)) & 0x… in twai_ll_set_acc_filter()
491 …HAL_FORCE_MODIFY_U32_REG_FIELD(hw->acceptance_filter.amr[i], byte, ((mask_swapped >> (i * 8)) & 0x… in twai_ll_set_acc_filter()
656 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clock_divider_reg, cd, (divider / 2) - 1); in twai_ll_set_clkout()
660 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clock_divider_reg, cd, 255); in twai_ll_set_clkout()
663 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clock_divider_reg, cd, 0); in twai_ll_set_clkout()
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| D | dac_ll.h | 80 HAL_FORCE_MODIFY_U32_REG_FIELD(RTCIO.pad_dac[channel], dac, value); in dac_ll_update_output_value()
83 HAL_FORCE_MODIFY_U32_REG_FIELD(RTCIO.pad_dac[channel], dac, value); in dac_ll_update_output_value()
151 …HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_dac_ctrl1, sw_fstep, (sw_freq > 0xFFFF) ? 0xFFFF : sw_freq… in dac_ll_cw_set_freq()
198 … HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_dac_ctrl2, dac_dc1, offset ? offset : (-128 - offset)); in dac_ll_cw_set_dc_offset()
203 … HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_dac_ctrl2, dac_dc2, offset ? offset : (-128 - offset)); in dac_ll_cw_set_dc_offset()
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| D | uart_ll.h | 409 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->idle_conf, tx_brk_num, break_num); in uart_ll_tx_break()
476 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf1, xon_char, flow_ctrl->xon_char); in uart_ll_set_sw_flow_ctrl()
477 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf0, xoff_char, flow_ctrl->xoff_char); in uart_ll_set_sw_flow_ctrl()
499 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_char, data, cmd_char->cmd_char); in uart_ll_set_at_cmd_char()
500 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_char, char_num, cmd_char->char_num); in uart_ll_set_at_cmd_char()
501 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_postcnt, post_idle_num, cmd_char->post_idle); in uart_ll_set_at_cmd_char()
502 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_precnt, pre_idle_num, cmd_char->pre_idle); in uart_ll_set_at_cmd_char()
503 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_gaptout, rx_gap_tout, cmd_char->gap_tout); in uart_ll_set_at_cmd_char()
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| D | adc_ll.h | 115 HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.fsm_wait, rstb_wait, rst_wait); in adc_ll_digi_set_fsm_time()
117 HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.fsm_wait, xpd_wait, start_wait); in adc_ll_digi_set_fsm_time()
119 HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.fsm_wait, standby_wait, standby_wait); in adc_ll_digi_set_fsm_time()
147 HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.ctrl, sar_clk_div, div); in adc_ll_digi_set_clk_div()
158 HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.ctrl2, max_meas_num, meas_num); in adc_ll_digi_set_convert_limit_num()
335 HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.apb_adc_clkm_conf, clkm_div_num, div_num); in adc_ll_digi_controller_clk_div()
517 HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.dma_conf, apb_adc_eof_num, num); in adc_ll_digi_dma_set_eof_num()
583 HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_reader1_ctrl, sar1_clk_div, div); in adc_ll_set_sar_clk_div()
585 HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_reader2_ctrl, sar2_clk_div, div); in adc_ll_set_sar_clk_div()
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| D | sigmadelta_ll.h | 58 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->channel[channel], duty, (uint32_t)duty); in sigmadelta_ll_set_duty()
70 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->channel[channel], prescale, prescale); in sigmadelta_ll_set_prescale()
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| /hal_espressif-3.6.0/components/hal/esp32s3/include/hal/ |
| D | twai_ll.h | 403 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->error_warning_limit_reg, ewl, ewl); in twai_ll_set_err_warn_lim()
443 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->rx_error_counter_reg, rxerr, rec); in twai_ll_set_rec()
471 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->tx_error_counter_reg, txerr, tec); in twai_ll_set_tec()
490 …HAL_FORCE_MODIFY_U32_REG_FIELD(hw->acceptance_filter.acr[i], byte, ((code_swapped >> (i * 8)) & 0x… in twai_ll_set_acc_filter()
491 …HAL_FORCE_MODIFY_U32_REG_FIELD(hw->acceptance_filter.amr[i], byte, ((mask_swapped >> (i * 8)) & 0x… in twai_ll_set_acc_filter()
656 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clock_divider_reg, cd, (divider / 2) - 1); in twai_ll_set_clkout()
660 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clock_divider_reg, cd, 255); in twai_ll_set_clkout()
663 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clock_divider_reg, cd, 0); in twai_ll_set_clkout()
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| D | adc_ll.h | 125 HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.fsm_wait, rstb_wait, rst_wait); in adc_ll_digi_set_fsm_time()
127 HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.fsm_wait, xpd_wait, start_wait); in adc_ll_digi_set_fsm_time()
129 HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.fsm_wait, standby_wait, standby_wait); in adc_ll_digi_set_fsm_time()
158 HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.ctrl, sar_clk_div, div); in adc_ll_digi_set_clk_div()
169 HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.ctrl2, max_meas_num, meas_num); in adc_ll_digi_set_convert_limit_num()
341 HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.apb_adc_clkm_conf, clkm_div_num, div_num); in adc_ll_digi_controller_clk_div()
471 HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.dma_conf, apb_adc_eof_num, num); in adc_ll_digi_dma_set_eof_num()
798 HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_reader1_ctrl, sar1_clk_div, div); in adc_ll_set_sar_clk_div()
800 HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_reader2_ctrl, sar2_clk_div, div); in adc_ll_set_sar_clk_div()
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| D | uart_ll.h | 167 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clk_conf, sclk_div_num, sclk_div - 1); in uart_ll_set_baudrate()
456 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->txbrk_conf, tx_brk_num, break_num); in uart_ll_tx_break()
522 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf1, xon_char, flow_ctrl->xon_char); in uart_ll_set_sw_flow_ctrl()
523 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf0, xoff_char, flow_ctrl->xoff_char); in uart_ll_set_sw_flow_ctrl()
545 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_char, at_cmd_char, cmd_char->cmd_char); in uart_ll_set_at_cmd_char()
546 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_char, char_num, cmd_char->char_num); in uart_ll_set_at_cmd_char()
547 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_postcnt, post_idle_num, cmd_char->post_idle); in uart_ll_set_at_cmd_char()
548 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_precnt, pre_idle_num, cmd_char->pre_idle); in uart_ll_set_at_cmd_char()
549 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_gaptout, rx_gap_tout, cmd_char->gap_tout); in uart_ll_set_at_cmd_char()
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| D | sigmadelta_ll.h | 58 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->channel[channel], duty, (uint8_t)duty); in sigmadelta_ll_set_duty()
70 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->channel[channel], prescale, prescale); in sigmadelta_ll_set_prescale()
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| /hal_espressif-3.6.0/components/hal/esp32c3/include/hal/ |
| D | twai_ll.h | 403 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->error_warning_limit_reg, ewl, ewl); in twai_ll_set_err_warn_lim()
443 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->rx_error_counter_reg, rxerr, rec); in twai_ll_set_rec()
471 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->tx_error_counter_reg, txerr, tec); in twai_ll_set_tec()
490 …HAL_FORCE_MODIFY_U32_REG_FIELD(hw->acceptance_filter.acr[i], byte, ((code_swapped >> (i * 8)) & 0x… in twai_ll_set_acc_filter()
491 …HAL_FORCE_MODIFY_U32_REG_FIELD(hw->acceptance_filter.amr[i], byte, ((mask_swapped >> (i * 8)) & 0x… in twai_ll_set_acc_filter()
656 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clock_divider_reg, cd, (divider / 2) - 1); in twai_ll_set_clkout()
660 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clock_divider_reg, cd, 255); in twai_ll_set_clkout()
663 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clock_divider_reg, cd, 0); in twai_ll_set_clkout()
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| D | uart_ll.h | 169 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clk_conf, sclk_div_num, sclk_div - 1); in uart_ll_set_baudrate()
457 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->txbrk_conf, tx_brk_num, break_num); in uart_ll_tx_break()
524 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf1, xon_char, flow_ctrl->xon_char); in uart_ll_set_sw_flow_ctrl()
525 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf0, xoff_char, flow_ctrl->xoff_char); in uart_ll_set_sw_flow_ctrl()
547 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_char, data, cmd_char->cmd_char); in uart_ll_set_at_cmd_char()
548 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_char, char_num, cmd_char->char_num); in uart_ll_set_at_cmd_char()
549 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_postcnt, post_idle_num, cmd_char->post_idle); in uart_ll_set_at_cmd_char()
550 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_precnt, pre_idle_num, cmd_char->pre_idle); in uart_ll_set_at_cmd_char()
551 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_gaptout, rx_gap_tout, cmd_char->gap_tout); in uart_ll_set_at_cmd_char()
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| D | adc_ll.h | 102 HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.fsm_wait, rstb_wait, rst_wait); in adc_ll_digi_set_fsm_time()
104 HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.fsm_wait, xpd_wait, start_wait); in adc_ll_digi_set_fsm_time()
106 HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.fsm_wait, standby_wait, standby_wait); in adc_ll_digi_set_fsm_time()
132 HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.ctrl, sar_clk_div, div); in adc_ll_digi_set_clk_div()
143 HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.ctrl2, max_meas_num, meas_num); in adc_ll_digi_set_convert_limit_num()
289 HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.apb_adc_clkm_conf, clkm_div_num, div_num); in adc_ll_digi_controller_clk_div()
426 HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.dma_conf, apb_adc_eof_num, num); in adc_ll_digi_dma_set_eof_num()
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| D | spimem_flash_ll.h | 161 HAL_FORCE_MODIFY_U32_REG_FIELD(dev->flash_sus_cmd, flash_pes_command, sus_cmd); in spimem_flash_ll_suspend_cmd_setup()
173 HAL_FORCE_MODIFY_U32_REG_FIELD(dev->flash_sus_cmd, flash_per_command, res_cmd); in spimem_flash_ll_resume_cmd_setup()
185 HAL_FORCE_MODIFY_U32_REG_FIELD(dev->flash_sus_cmd, wait_pesr_command, pesr_cmd); in spimem_flash_ll_rd_sus_cmd_setup()
222 HAL_FORCE_MODIFY_U32_REG_FIELD(dev->flash_sus_ctrl, pesr_end_msk, sus_conf); in spimem_flash_ll_set_read_sus_status()
233 HAL_FORCE_MODIFY_U32_REG_FIELD(dev->flash_waiti_ctrl, waiti_cmd, 0x05); in spimem_flash_ll_auto_wait_idle_init()
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