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Searched refs:EXTMEM_ICACHE_CTRL1_REG (Results 1 – 9 of 9) sorted by relevance

/hal_espressif-3.6.0/zephyr/esp32c3/src/boot/
Dbootloader_init.c92 REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, EXTMEM_ICACHE_SHUT_IBUS); in bootloader_reset_mmu()
93 REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, EXTMEM_ICACHE_SHUT_DBUS); in bootloader_reset_mmu()
/hal_espressif-3.6.0/components/bootloader_support/src/esp32h2/
Dbootloader_esp32h2.c81 REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, EXTMEM_ICACHE_SHUT_IBUS); in bootloader_reset_mmu()
82 REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, EXTMEM_ICACHE_SHUT_DBUS); in bootloader_reset_mmu()
/hal_espressif-3.6.0/components/bootloader_support/src/esp32c3/
Dbootloader_esp32c3.c82 REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, EXTMEM_ICACHE_SHUT_IBUS); in bootloader_reset_mmu()
83 REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, EXTMEM_ICACHE_SHUT_DBUS); in bootloader_reset_mmu()
/hal_espressif-3.6.0/zephyr/esp32s3/src/boot/
Dbootloader_init.c60 REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, EXTMEM_ICACHE_SHUT_CORE0_BUS); in bootloader_reset_mmu()
61 REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, EXTMEM_ICACHE_SHUT_CORE1_BUS); in bootloader_reset_mmu()
/hal_espressif-3.6.0/components/bootloader_support/src/esp32s3/
Dbootloader_esp32s3.c81 REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, EXTMEM_ICACHE_SHUT_CORE0_BUS); in bootloader_reset_mmu()
83 REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, EXTMEM_ICACHE_SHUT_CORE1_BUS); in bootloader_reset_mmu()
/hal_espressif-3.6.0/components/bootloader_support/src/
Dbootloader_utility.c811 REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, EXTMEM_ICACHE_SHUT_IBUS);
812 REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, EXTMEM_ICACHE_SHUT_DBUS);
814 REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, EXTMEM_ICACHE_SHUT_IBUS);
815 REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, EXTMEM_ICACHE_SHUT_DBUS);
/hal_espressif-3.6.0/components/soc/esp32h2/include/soc/
Dextmem_reg.h30 #define EXTMEM_ICACHE_CTRL1_REG (DR_REG_EXTMEM_BASE + 0x004) macro
/hal_espressif-3.6.0/components/soc/esp32c3/include/soc/
Dextmem_reg.h30 #define EXTMEM_ICACHE_CTRL1_REG (DR_REG_EXTMEM_BASE + 0x004) macro
/hal_espressif-3.6.0/components/soc/esp32s3/include/soc/
Dextmem_reg.h405 #define EXTMEM_ICACHE_CTRL1_REG (DR_REG_EXTMEM_BASE + 0x64) macro