1 // Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 // 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 #ifndef _SOC_EXTMEM_REG_H_ 15 #define _SOC_EXTMEM_REG_H_ 16 17 18 #include "soc.h" 19 #ifdef __cplusplus 20 extern "C" { 21 #endif 22 23 #define EXTMEM_DCACHE_CTRL_REG (DR_REG_EXTMEM_BASE + 0x0) 24 /* EXTMEM_DCACHE_BLOCKSIZE_MODE : R/W ;bitpos:[4:3] ;default: 2'b0 ; */ 25 /*description: The bit is used to configure cache block size.0: 16 bytes, 1: 32 bytes,2: 64 byt 26 es.*/ 27 #define EXTMEM_DCACHE_BLOCKSIZE_MODE 0x00000003 28 #define EXTMEM_DCACHE_BLOCKSIZE_MODE_M ((EXTMEM_DCACHE_BLOCKSIZE_MODE_V)<<(EXTMEM_DCACHE_BLOCKSIZE_MODE_S)) 29 #define EXTMEM_DCACHE_BLOCKSIZE_MODE_V 0x3 30 #define EXTMEM_DCACHE_BLOCKSIZE_MODE_S 3 31 /* EXTMEM_DCACHE_SIZE_MODE : R/W ;bitpos:[2] ;default: 1'b0 ; */ 32 /*description: The bit is used to configure cache memory size.0: 32KB, 1: 64KB.*/ 33 #define EXTMEM_DCACHE_SIZE_MODE (BIT(2)) 34 #define EXTMEM_DCACHE_SIZE_MODE_M (BIT(2)) 35 #define EXTMEM_DCACHE_SIZE_MODE_V 0x1 36 #define EXTMEM_DCACHE_SIZE_MODE_S 2 37 /* EXTMEM_DCACHE_ENABLE : R/W ;bitpos:[0] ;default: 1'b0 ; */ 38 /*description: The bit is used to activate the data cache. 0: disable, 1: enable.*/ 39 #define EXTMEM_DCACHE_ENABLE (BIT(0)) 40 #define EXTMEM_DCACHE_ENABLE_M (BIT(0)) 41 #define EXTMEM_DCACHE_ENABLE_V 0x1 42 #define EXTMEM_DCACHE_ENABLE_S 0 43 44 #define EXTMEM_DCACHE_CTRL1_REG (DR_REG_EXTMEM_BASE + 0x4) 45 /* EXTMEM_DCACHE_SHUT_CORE1_BUS : R/W ;bitpos:[1] ;default: 1'b1 ; */ 46 /*description: The bit is used to disable core1 dbus, 0: enable, 1: disable.*/ 47 #define EXTMEM_DCACHE_SHUT_CORE1_BUS (BIT(1)) 48 #define EXTMEM_DCACHE_SHUT_CORE1_BUS_M (BIT(1)) 49 #define EXTMEM_DCACHE_SHUT_CORE1_BUS_V 0x1 50 #define EXTMEM_DCACHE_SHUT_CORE1_BUS_S 1 51 /* EXTMEM_DCACHE_SHUT_CORE0_BUS : R/W ;bitpos:[0] ;default: 1'b1 ; */ 52 /*description: The bit is used to disable core0 dbus, 0: enable, 1: disable.*/ 53 #define EXTMEM_DCACHE_SHUT_CORE0_BUS (BIT(0)) 54 #define EXTMEM_DCACHE_SHUT_CORE0_BUS_M (BIT(0)) 55 #define EXTMEM_DCACHE_SHUT_CORE0_BUS_V 0x1 56 #define EXTMEM_DCACHE_SHUT_CORE0_BUS_S 0 57 58 #define EXTMEM_DCACHE_TAG_POWER_CTRL_REG (DR_REG_EXTMEM_BASE + 0x8) 59 /* EXTMEM_DCACHE_TAG_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */ 60 /*description: The bit is used to power dcache tag memory up, 0: follow rtc_lslp_pd, 1: power 61 up.*/ 62 #define EXTMEM_DCACHE_TAG_MEM_FORCE_PU (BIT(2)) 63 #define EXTMEM_DCACHE_TAG_MEM_FORCE_PU_M (BIT(2)) 64 #define EXTMEM_DCACHE_TAG_MEM_FORCE_PU_V 0x1 65 #define EXTMEM_DCACHE_TAG_MEM_FORCE_PU_S 2 66 /* EXTMEM_DCACHE_TAG_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */ 67 /*description: The bit is used to power dcache tag memory down, 0: follow rtc_lslp_pd, 1: powe 68 r down.*/ 69 #define EXTMEM_DCACHE_TAG_MEM_FORCE_PD (BIT(1)) 70 #define EXTMEM_DCACHE_TAG_MEM_FORCE_PD_M (BIT(1)) 71 #define EXTMEM_DCACHE_TAG_MEM_FORCE_PD_V 0x1 72 #define EXTMEM_DCACHE_TAG_MEM_FORCE_PD_S 1 73 /* EXTMEM_DCACHE_TAG_MEM_FORCE_ON : R/W ;bitpos:[0] ;default: 1'b1 ; */ 74 /*description: The bit is used to close clock gating of dcache tag memory. 1: close gating, 0: 75 open clock gating..*/ 76 #define EXTMEM_DCACHE_TAG_MEM_FORCE_ON (BIT(0)) 77 #define EXTMEM_DCACHE_TAG_MEM_FORCE_ON_M (BIT(0)) 78 #define EXTMEM_DCACHE_TAG_MEM_FORCE_ON_V 0x1 79 #define EXTMEM_DCACHE_TAG_MEM_FORCE_ON_S 0 80 81 #define EXTMEM_DCACHE_PRELOCK_CTRL_REG (DR_REG_EXTMEM_BASE + 0xC) 82 /* EXTMEM_DCACHE_PRELOCK_SCT1_EN : R/W ;bitpos:[1] ;default: 1'h0 ; */ 83 /*description: The bit is used to enable the second section of prelock function..*/ 84 #define EXTMEM_DCACHE_PRELOCK_SCT1_EN (BIT(1)) 85 #define EXTMEM_DCACHE_PRELOCK_SCT1_EN_M (BIT(1)) 86 #define EXTMEM_DCACHE_PRELOCK_SCT1_EN_V 0x1 87 #define EXTMEM_DCACHE_PRELOCK_SCT1_EN_S 1 88 /* EXTMEM_DCACHE_PRELOCK_SCT0_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */ 89 /*description: The bit is used to enable the first section of prelock function..*/ 90 #define EXTMEM_DCACHE_PRELOCK_SCT0_EN (BIT(0)) 91 #define EXTMEM_DCACHE_PRELOCK_SCT0_EN_M (BIT(0)) 92 #define EXTMEM_DCACHE_PRELOCK_SCT0_EN_V 0x1 93 #define EXTMEM_DCACHE_PRELOCK_SCT0_EN_S 0 94 95 #define EXTMEM_DCACHE_PRELOCK_SCT0_ADDR_REG (DR_REG_EXTMEM_BASE + 0x10) 96 /* EXTMEM_DCACHE_PRELOCK_SCT0_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 97 /*description: The bits are used to configure the first start virtual address of data prelock, 98 which is combined with DCACHE_PRELOCK_SCT0_SIZE_REG.*/ 99 #define EXTMEM_DCACHE_PRELOCK_SCT0_ADDR 0xFFFFFFFF 100 #define EXTMEM_DCACHE_PRELOCK_SCT0_ADDR_M ((EXTMEM_DCACHE_PRELOCK_SCT0_ADDR_V)<<(EXTMEM_DCACHE_PRELOCK_SCT0_ADDR_S)) 101 #define EXTMEM_DCACHE_PRELOCK_SCT0_ADDR_V 0xFFFFFFFF 102 #define EXTMEM_DCACHE_PRELOCK_SCT0_ADDR_S 0 103 104 #define EXTMEM_DCACHE_PRELOCK_SCT1_ADDR_REG (DR_REG_EXTMEM_BASE + 0x14) 105 /* EXTMEM_DCACHE_PRELOCK_SCT1_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 106 /*description: The bits are used to configure the second start virtual address of data prelock, 107 which is combined with DCACHE_PRELOCK_SCT1_SIZE_REG.*/ 108 #define EXTMEM_DCACHE_PRELOCK_SCT1_ADDR 0xFFFFFFFF 109 #define EXTMEM_DCACHE_PRELOCK_SCT1_ADDR_M ((EXTMEM_DCACHE_PRELOCK_SCT1_ADDR_V)<<(EXTMEM_DCACHE_PRELOCK_SCT1_ADDR_S)) 110 #define EXTMEM_DCACHE_PRELOCK_SCT1_ADDR_V 0xFFFFFFFF 111 #define EXTMEM_DCACHE_PRELOCK_SCT1_ADDR_S 0 112 113 #define EXTMEM_DCACHE_PRELOCK_SCT_SIZE_REG (DR_REG_EXTMEM_BASE + 0x18) 114 /* EXTMEM_DCACHE_PRELOCK_SCT0_SIZE : R/W ;bitpos:[31:16] ;default: 16'h0 ; */ 115 /*description: The bits are used to configure the first length of data locking, which is combin 116 ed with DCACHE_PRELOCK_SCT0_ADDR_REG.*/ 117 #define EXTMEM_DCACHE_PRELOCK_SCT0_SIZE 0x0000FFFF 118 #define EXTMEM_DCACHE_PRELOCK_SCT0_SIZE_M ((EXTMEM_DCACHE_PRELOCK_SCT0_SIZE_V)<<(EXTMEM_DCACHE_PRELOCK_SCT0_SIZE_S)) 119 #define EXTMEM_DCACHE_PRELOCK_SCT0_SIZE_V 0xFFFF 120 #define EXTMEM_DCACHE_PRELOCK_SCT0_SIZE_S 16 121 /* EXTMEM_DCACHE_PRELOCK_SCT1_SIZE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ 122 /*description: The bits are used to configure the second length of data locking, which is combi 123 ned with DCACHE_PRELOCK_SCT1_ADDR_REG.*/ 124 #define EXTMEM_DCACHE_PRELOCK_SCT1_SIZE 0x0000FFFF 125 #define EXTMEM_DCACHE_PRELOCK_SCT1_SIZE_M ((EXTMEM_DCACHE_PRELOCK_SCT1_SIZE_V)<<(EXTMEM_DCACHE_PRELOCK_SCT1_SIZE_S)) 126 #define EXTMEM_DCACHE_PRELOCK_SCT1_SIZE_V 0xFFFF 127 #define EXTMEM_DCACHE_PRELOCK_SCT1_SIZE_S 0 128 129 #define EXTMEM_DCACHE_LOCK_CTRL_REG (DR_REG_EXTMEM_BASE + 0x1C) 130 /* EXTMEM_DCACHE_LOCK_DONE : RO ;bitpos:[2] ;default: 1'b1 ; */ 131 /*description: The bit is used to indicate unlock/lock operation is finished..*/ 132 #define EXTMEM_DCACHE_LOCK_DONE (BIT(2)) 133 #define EXTMEM_DCACHE_LOCK_DONE_M (BIT(2)) 134 #define EXTMEM_DCACHE_LOCK_DONE_V 0x1 135 #define EXTMEM_DCACHE_LOCK_DONE_S 2 136 /* EXTMEM_DCACHE_UNLOCK_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ 137 /*description: The bit is used to enable unlock operation. It will be cleared by hardware after 138 unlock operation done..*/ 139 #define EXTMEM_DCACHE_UNLOCK_ENA (BIT(1)) 140 #define EXTMEM_DCACHE_UNLOCK_ENA_M (BIT(1)) 141 #define EXTMEM_DCACHE_UNLOCK_ENA_V 0x1 142 #define EXTMEM_DCACHE_UNLOCK_ENA_S 1 143 /* EXTMEM_DCACHE_LOCK_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ 144 /*description: The bit is used to enable lock operation. It will be cleared by hardware after l 145 ock operation done..*/ 146 #define EXTMEM_DCACHE_LOCK_ENA (BIT(0)) 147 #define EXTMEM_DCACHE_LOCK_ENA_M (BIT(0)) 148 #define EXTMEM_DCACHE_LOCK_ENA_V 0x1 149 #define EXTMEM_DCACHE_LOCK_ENA_S 0 150 151 #define EXTMEM_DCACHE_LOCK_ADDR_REG (DR_REG_EXTMEM_BASE + 0x20) 152 /* EXTMEM_DCACHE_LOCK_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ 153 /*description: The bits are used to configure the start virtual address for lock operations. It 154 should be combined with DCACHE_LOCK_SIZE_REG..*/ 155 #define EXTMEM_DCACHE_LOCK_ADDR 0xFFFFFFFF 156 #define EXTMEM_DCACHE_LOCK_ADDR_M ((EXTMEM_DCACHE_LOCK_ADDR_V)<<(EXTMEM_DCACHE_LOCK_ADDR_S)) 157 #define EXTMEM_DCACHE_LOCK_ADDR_V 0xFFFFFFFF 158 #define EXTMEM_DCACHE_LOCK_ADDR_S 0 159 160 #define EXTMEM_DCACHE_LOCK_SIZE_REG (DR_REG_EXTMEM_BASE + 0x24) 161 /* EXTMEM_DCACHE_LOCK_SIZE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ 162 /*description: The bits are used to configure the length for lock operations. The bits are the 163 counts of cache block. It should be combined with DCACHE_LOCK_ADDR_REG..*/ 164 #define EXTMEM_DCACHE_LOCK_SIZE 0x0000FFFF 165 #define EXTMEM_DCACHE_LOCK_SIZE_M ((EXTMEM_DCACHE_LOCK_SIZE_V)<<(EXTMEM_DCACHE_LOCK_SIZE_S)) 166 #define EXTMEM_DCACHE_LOCK_SIZE_V 0xFFFF 167 #define EXTMEM_DCACHE_LOCK_SIZE_S 0 168 169 #define EXTMEM_DCACHE_SYNC_CTRL_REG (DR_REG_EXTMEM_BASE + 0x28) 170 /* EXTMEM_DCACHE_SYNC_DONE : RO ;bitpos:[3] ;default: 1'b0 ; */ 171 /*description: The bit is used to indicate clean/writeback/invalidate operation is finished..*/ 172 #define EXTMEM_DCACHE_SYNC_DONE (BIT(3)) 173 #define EXTMEM_DCACHE_SYNC_DONE_M (BIT(3)) 174 #define EXTMEM_DCACHE_SYNC_DONE_V 0x1 175 #define EXTMEM_DCACHE_SYNC_DONE_S 3 176 /* EXTMEM_DCACHE_CLEAN_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ 177 /*description: The bit is used to enable clean operation. It will be cleared by hardware after 178 clean operation done..*/ 179 #define EXTMEM_DCACHE_CLEAN_ENA (BIT(2)) 180 #define EXTMEM_DCACHE_CLEAN_ENA_M (BIT(2)) 181 #define EXTMEM_DCACHE_CLEAN_ENA_V 0x1 182 #define EXTMEM_DCACHE_CLEAN_ENA_S 2 183 /* EXTMEM_DCACHE_WRITEBACK_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ 184 /*description: The bit is used to enable writeback operation. It will be cleared by hardware af 185 ter writeback operation done..*/ 186 #define EXTMEM_DCACHE_WRITEBACK_ENA (BIT(1)) 187 #define EXTMEM_DCACHE_WRITEBACK_ENA_M (BIT(1)) 188 #define EXTMEM_DCACHE_WRITEBACK_ENA_V 0x1 189 #define EXTMEM_DCACHE_WRITEBACK_ENA_S 1 190 /* EXTMEM_DCACHE_INVALIDATE_ENA : R/W ;bitpos:[0] ;default: 1'b1 ; */ 191 /*description: The bit is used to enable invalidate operation. It will be cleared by hardware a 192 fter invalidate operation done..*/ 193 #define EXTMEM_DCACHE_INVALIDATE_ENA (BIT(0)) 194 #define EXTMEM_DCACHE_INVALIDATE_ENA_M (BIT(0)) 195 #define EXTMEM_DCACHE_INVALIDATE_ENA_V 0x1 196 #define EXTMEM_DCACHE_INVALIDATE_ENA_S 0 197 198 #define EXTMEM_DCACHE_SYNC_ADDR_REG (DR_REG_EXTMEM_BASE + 0x2C) 199 /* EXTMEM_DCACHE_SYNC_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ 200 /*description: The bits are used to configure the start virtual address for clean operations. I 201 t should be combined with DCACHE_SYNC_SIZE_REG..*/ 202 #define EXTMEM_DCACHE_SYNC_ADDR 0xFFFFFFFF 203 #define EXTMEM_DCACHE_SYNC_ADDR_M ((EXTMEM_DCACHE_SYNC_ADDR_V)<<(EXTMEM_DCACHE_SYNC_ADDR_S)) 204 #define EXTMEM_DCACHE_SYNC_ADDR_V 0xFFFFFFFF 205 #define EXTMEM_DCACHE_SYNC_ADDR_S 0 206 207 #define EXTMEM_DCACHE_SYNC_SIZE_REG (DR_REG_EXTMEM_BASE + 0x30) 208 /* EXTMEM_DCACHE_SYNC_SIZE : R/W ;bitpos:[22:0] ;default: 23'h0 ; */ 209 /*description: The bits are used to configure the length for sync operations. The bits are the 210 counts of cache block. It should be combined with DCACHE_SYNC_ADDR_REG..*/ 211 #define EXTMEM_DCACHE_SYNC_SIZE 0x007FFFFF 212 #define EXTMEM_DCACHE_SYNC_SIZE_M ((EXTMEM_DCACHE_SYNC_SIZE_V)<<(EXTMEM_DCACHE_SYNC_SIZE_S)) 213 #define EXTMEM_DCACHE_SYNC_SIZE_V 0x7FFFFF 214 #define EXTMEM_DCACHE_SYNC_SIZE_S 0 215 216 #define EXTMEM_DCACHE_OCCUPY_CTRL_REG (DR_REG_EXTMEM_BASE + 0x34) 217 /* EXTMEM_DCACHE_OCCUPY_DONE : RO ;bitpos:[1] ;default: 1'b1 ; */ 218 /*description: The bit is used to indicate occupy operation is finished..*/ 219 #define EXTMEM_DCACHE_OCCUPY_DONE (BIT(1)) 220 #define EXTMEM_DCACHE_OCCUPY_DONE_M (BIT(1)) 221 #define EXTMEM_DCACHE_OCCUPY_DONE_V 0x1 222 #define EXTMEM_DCACHE_OCCUPY_DONE_S 1 223 /* EXTMEM_DCACHE_OCCUPY_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ 224 /*description: The bit is used to enable occupy operation. It will be cleared by hardware after 225 issuing Auot-Invalidate Operation..*/ 226 #define EXTMEM_DCACHE_OCCUPY_ENA (BIT(0)) 227 #define EXTMEM_DCACHE_OCCUPY_ENA_M (BIT(0)) 228 #define EXTMEM_DCACHE_OCCUPY_ENA_V 0x1 229 #define EXTMEM_DCACHE_OCCUPY_ENA_S 0 230 231 #define EXTMEM_DCACHE_OCCUPY_ADDR_REG (DR_REG_EXTMEM_BASE + 0x38) 232 /* EXTMEM_DCACHE_OCCUPY_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ 233 /*description: The bits are used to configure the start virtual address for occupy operation. I 234 t should be combined with DCACHE_OCCUPY_SIZE_REG..*/ 235 #define EXTMEM_DCACHE_OCCUPY_ADDR 0xFFFFFFFF 236 #define EXTMEM_DCACHE_OCCUPY_ADDR_M ((EXTMEM_DCACHE_OCCUPY_ADDR_V)<<(EXTMEM_DCACHE_OCCUPY_ADDR_S)) 237 #define EXTMEM_DCACHE_OCCUPY_ADDR_V 0xFFFFFFFF 238 #define EXTMEM_DCACHE_OCCUPY_ADDR_S 0 239 240 #define EXTMEM_DCACHE_OCCUPY_SIZE_REG (DR_REG_EXTMEM_BASE + 0x3C) 241 /* EXTMEM_DCACHE_OCCUPY_SIZE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ 242 /*description: The bits are used to configure the length for occupy operation. The bits are the 243 counts of cache block. It should be combined with DCACHE_OCCUPY_ADDR_REG..*/ 244 #define EXTMEM_DCACHE_OCCUPY_SIZE 0x0000FFFF 245 #define EXTMEM_DCACHE_OCCUPY_SIZE_M ((EXTMEM_DCACHE_OCCUPY_SIZE_V)<<(EXTMEM_DCACHE_OCCUPY_SIZE_S)) 246 #define EXTMEM_DCACHE_OCCUPY_SIZE_V 0xFFFF 247 #define EXTMEM_DCACHE_OCCUPY_SIZE_S 0 248 249 #define EXTMEM_DCACHE_PRELOAD_CTRL_REG (DR_REG_EXTMEM_BASE + 0x40) 250 /* EXTMEM_DCACHE_PRELOAD_ORDER : R/W ;bitpos:[2] ;default: 1'b0 ; */ 251 /*description: The bit is used to configure the direction of preload operation. 1: descending, 252 0: ascending..*/ 253 #define EXTMEM_DCACHE_PRELOAD_ORDER (BIT(2)) 254 #define EXTMEM_DCACHE_PRELOAD_ORDER_M (BIT(2)) 255 #define EXTMEM_DCACHE_PRELOAD_ORDER_V 0x1 256 #define EXTMEM_DCACHE_PRELOAD_ORDER_S 2 257 /* EXTMEM_DCACHE_PRELOAD_DONE : RO ;bitpos:[1] ;default: 1'b1 ; */ 258 /*description: The bit is used to indicate preload operation is finished..*/ 259 #define EXTMEM_DCACHE_PRELOAD_DONE (BIT(1)) 260 #define EXTMEM_DCACHE_PRELOAD_DONE_M (BIT(1)) 261 #define EXTMEM_DCACHE_PRELOAD_DONE_V 0x1 262 #define EXTMEM_DCACHE_PRELOAD_DONE_S 1 263 /* EXTMEM_DCACHE_PRELOAD_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ 264 /*description: The bit is used to enable preload operation. It will be cleared by hardware afte 265 r preload operation done..*/ 266 #define EXTMEM_DCACHE_PRELOAD_ENA (BIT(0)) 267 #define EXTMEM_DCACHE_PRELOAD_ENA_M (BIT(0)) 268 #define EXTMEM_DCACHE_PRELOAD_ENA_V 0x1 269 #define EXTMEM_DCACHE_PRELOAD_ENA_S 0 270 271 #define EXTMEM_DCACHE_PRELOAD_ADDR_REG (DR_REG_EXTMEM_BASE + 0x44) 272 /* EXTMEM_DCACHE_PRELOAD_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ 273 /*description: The bits are used to configure the start virtual address for preload operation. 274 It should be combined with DCACHE_PRELOAD_SIZE_REG..*/ 275 #define EXTMEM_DCACHE_PRELOAD_ADDR 0xFFFFFFFF 276 #define EXTMEM_DCACHE_PRELOAD_ADDR_M ((EXTMEM_DCACHE_PRELOAD_ADDR_V)<<(EXTMEM_DCACHE_PRELOAD_ADDR_S)) 277 #define EXTMEM_DCACHE_PRELOAD_ADDR_V 0xFFFFFFFF 278 #define EXTMEM_DCACHE_PRELOAD_ADDR_S 0 279 280 #define EXTMEM_DCACHE_PRELOAD_SIZE_REG (DR_REG_EXTMEM_BASE + 0x48) 281 /* EXTMEM_DCACHE_PRELOAD_SIZE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ 282 /*description: The bits are used to configure the length for preload operation. The bits are th 283 e counts of cache block. It should be combined with DCACHE_PRELOAD_ADDR_REG...*/ 284 #define EXTMEM_DCACHE_PRELOAD_SIZE 0x0000FFFF 285 #define EXTMEM_DCACHE_PRELOAD_SIZE_M ((EXTMEM_DCACHE_PRELOAD_SIZE_V)<<(EXTMEM_DCACHE_PRELOAD_SIZE_S)) 286 #define EXTMEM_DCACHE_PRELOAD_SIZE_V 0xFFFF 287 #define EXTMEM_DCACHE_PRELOAD_SIZE_S 0 288 289 #define EXTMEM_DCACHE_AUTOLOAD_CTRL_REG (DR_REG_EXTMEM_BASE + 0x4C) 290 /* EXTMEM_DCACHE_AUTOLOAD_BUFFER_CLEAR : R/W ;bitpos:[9] ;default: 1'b0 ; */ 291 /*description: The bit is used to clear autoload buffer in dcache..*/ 292 #define EXTMEM_DCACHE_AUTOLOAD_BUFFER_CLEAR (BIT(9)) 293 #define EXTMEM_DCACHE_AUTOLOAD_BUFFER_CLEAR_M (BIT(9)) 294 #define EXTMEM_DCACHE_AUTOLOAD_BUFFER_CLEAR_V 0x1 295 #define EXTMEM_DCACHE_AUTOLOAD_BUFFER_CLEAR_S 9 296 /* EXTMEM_DCACHE_AUTOLOAD_SIZE : R/W ;bitpos:[8:7] ;default: 2'h0 ; */ 297 /*description: The bits are used to configure the numbers of the cache block for the issuing au 298 toload operation..*/ 299 #define EXTMEM_DCACHE_AUTOLOAD_SIZE 0x00000003 300 #define EXTMEM_DCACHE_AUTOLOAD_SIZE_M ((EXTMEM_DCACHE_AUTOLOAD_SIZE_V)<<(EXTMEM_DCACHE_AUTOLOAD_SIZE_S)) 301 #define EXTMEM_DCACHE_AUTOLOAD_SIZE_V 0x3 302 #define EXTMEM_DCACHE_AUTOLOAD_SIZE_S 7 303 /* EXTMEM_DCACHE_AUTOLOAD_RQST : R/W ;bitpos:[6:5] ;default: 2'b0 ; */ 304 /*description: The bits are used to configure trigger conditions for autoload. 0/3: cache miss, 305 1: cache hit, 2: both cache miss and hit..*/ 306 #define EXTMEM_DCACHE_AUTOLOAD_RQST 0x00000003 307 #define EXTMEM_DCACHE_AUTOLOAD_RQST_M ((EXTMEM_DCACHE_AUTOLOAD_RQST_V)<<(EXTMEM_DCACHE_AUTOLOAD_RQST_S)) 308 #define EXTMEM_DCACHE_AUTOLOAD_RQST_V 0x3 309 #define EXTMEM_DCACHE_AUTOLOAD_RQST_S 5 310 /* EXTMEM_DCACHE_AUTOLOAD_ORDER : R/W ;bitpos:[4] ;default: 1'b0 ; */ 311 /*description: The bits are used to configure the direction of autoload. 1: descending, 0: asce 312 nding..*/ 313 #define EXTMEM_DCACHE_AUTOLOAD_ORDER (BIT(4)) 314 #define EXTMEM_DCACHE_AUTOLOAD_ORDER_M (BIT(4)) 315 #define EXTMEM_DCACHE_AUTOLOAD_ORDER_V 0x1 316 #define EXTMEM_DCACHE_AUTOLOAD_ORDER_S 4 317 /* EXTMEM_DCACHE_AUTOLOAD_DONE : RO ;bitpos:[3] ;default: 1'b1 ; */ 318 /*description: The bit is used to indicate autoload operation is finished..*/ 319 #define EXTMEM_DCACHE_AUTOLOAD_DONE (BIT(3)) 320 #define EXTMEM_DCACHE_AUTOLOAD_DONE_M (BIT(3)) 321 #define EXTMEM_DCACHE_AUTOLOAD_DONE_V 0x1 322 #define EXTMEM_DCACHE_AUTOLOAD_DONE_S 3 323 /* EXTMEM_DCACHE_AUTOLOAD_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ 324 /*description: The bit is used to enable and disable autoload operation. It is combined with dc 325 ache_autoload_done. 1: enable, 0: disable. .*/ 326 #define EXTMEM_DCACHE_AUTOLOAD_ENA (BIT(2)) 327 #define EXTMEM_DCACHE_AUTOLOAD_ENA_M (BIT(2)) 328 #define EXTMEM_DCACHE_AUTOLOAD_ENA_V 0x1 329 #define EXTMEM_DCACHE_AUTOLOAD_ENA_S 2 330 /* EXTMEM_DCACHE_AUTOLOAD_SCT1_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ 331 /*description: The bits are used to enable the second section for autoload operation..*/ 332 #define EXTMEM_DCACHE_AUTOLOAD_SCT1_ENA (BIT(1)) 333 #define EXTMEM_DCACHE_AUTOLOAD_SCT1_ENA_M (BIT(1)) 334 #define EXTMEM_DCACHE_AUTOLOAD_SCT1_ENA_V 0x1 335 #define EXTMEM_DCACHE_AUTOLOAD_SCT1_ENA_S 1 336 /* EXTMEM_DCACHE_AUTOLOAD_SCT0_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ 337 /*description: The bits are used to enable the first section for autoload operation..*/ 338 #define EXTMEM_DCACHE_AUTOLOAD_SCT0_ENA (BIT(0)) 339 #define EXTMEM_DCACHE_AUTOLOAD_SCT0_ENA_M (BIT(0)) 340 #define EXTMEM_DCACHE_AUTOLOAD_SCT0_ENA_V 0x1 341 #define EXTMEM_DCACHE_AUTOLOAD_SCT0_ENA_S 0 342 343 #define EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR_REG (DR_REG_EXTMEM_BASE + 0x50) 344 /* EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ 345 /*description: The bits are used to configure the start virtual address of the first section fo 346 r autoload operation. It should be combined with dcache_autoload_sct0_ena..*/ 347 #define EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR 0xFFFFFFFF 348 #define EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR_M ((EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR_V)<<(EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR_S)) 349 #define EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR_V 0xFFFFFFFF 350 #define EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR_S 0 351 352 #define EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE_REG (DR_REG_EXTMEM_BASE + 0x54) 353 /* EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE : R/W ;bitpos:[26:0] ;default: 27'h0 ; */ 354 /*description: The bits are used to configure the length of the first section for autoload oper 355 ation. It should be combined with dcache_autoload_sct0_ena..*/ 356 #define EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE 0x07FFFFFF 357 #define EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE_M ((EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE_V)<<(EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE_S)) 358 #define EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE_V 0x7FFFFFF 359 #define EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE_S 0 360 361 #define EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR_REG (DR_REG_EXTMEM_BASE + 0x58) 362 /* EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ 363 /*description: The bits are used to configure the start virtual address of the second section f 364 or autoload operation. It should be combined with dcache_autoload_sct1_ena..*/ 365 #define EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR 0xFFFFFFFF 366 #define EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR_M ((EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR_V)<<(EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR_S)) 367 #define EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR_V 0xFFFFFFFF 368 #define EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR_S 0 369 370 #define EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE_REG (DR_REG_EXTMEM_BASE + 0x5C) 371 /* EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE : R/W ;bitpos:[26:0] ;default: 27'h0 ; */ 372 /*description: The bits are used to configure the length of the second section for autoload ope 373 ration. It should be combined with dcache_autoload_sct1_ena..*/ 374 #define EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE 0x07FFFFFF 375 #define EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE_M ((EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE_V)<<(EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE_S)) 376 #define EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE_V 0x7FFFFFF 377 #define EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE_S 0 378 379 #define EXTMEM_ICACHE_CTRL_REG (DR_REG_EXTMEM_BASE + 0x60) 380 /* EXTMEM_ICACHE_BLOCKSIZE_MODE : R/W ;bitpos:[3] ;default: 1'b0 ; */ 381 /*description: The bit is used to configure cache block size.0: 16 bytes, 1: 32 bytes.*/ 382 #define EXTMEM_ICACHE_BLOCKSIZE_MODE (BIT(3)) 383 #define EXTMEM_ICACHE_BLOCKSIZE_MODE_M (BIT(3)) 384 #define EXTMEM_ICACHE_BLOCKSIZE_MODE_V 0x1 385 #define EXTMEM_ICACHE_BLOCKSIZE_MODE_S 3 386 /* EXTMEM_ICACHE_SIZE_MODE : R/W ;bitpos:[2] ;default: 1'b0 ; */ 387 /*description: The bit is used to configure cache memory size.0: 16KB, 1: 32KB.*/ 388 #define EXTMEM_ICACHE_SIZE_MODE (BIT(2)) 389 #define EXTMEM_ICACHE_SIZE_MODE_M (BIT(2)) 390 #define EXTMEM_ICACHE_SIZE_MODE_V 0x1 391 #define EXTMEM_ICACHE_SIZE_MODE_S 2 392 /* EXTMEM_ICACHE_WAY_MODE : R/W ;bitpos:[1] ;default: 1'b0 ; */ 393 /*description: The bit is used to configure cache way mode.0: 4-way, 1: 8-way.*/ 394 #define EXTMEM_ICACHE_WAY_MODE (BIT(1)) 395 #define EXTMEM_ICACHE_WAY_MODE_M (BIT(1)) 396 #define EXTMEM_ICACHE_WAY_MODE_V 0x1 397 #define EXTMEM_ICACHE_WAY_MODE_S 1 398 /* EXTMEM_ICACHE_ENABLE : R/W ;bitpos:[0] ;default: 1'b0 ; */ 399 /*description: The bit is used to activate the data cache. 0: disable, 1: enable.*/ 400 #define EXTMEM_ICACHE_ENABLE (BIT(0)) 401 #define EXTMEM_ICACHE_ENABLE_M (BIT(0)) 402 #define EXTMEM_ICACHE_ENABLE_V 0x1 403 #define EXTMEM_ICACHE_ENABLE_S 0 404 405 #define EXTMEM_ICACHE_CTRL1_REG (DR_REG_EXTMEM_BASE + 0x64) 406 /* EXTMEM_ICACHE_SHUT_CORE1_BUS : R/W ;bitpos:[1] ;default: 1'b1 ; */ 407 /*description: The bit is used to disable core1 ibus, 0: enable, 1: disable.*/ 408 #define EXTMEM_ICACHE_SHUT_CORE1_BUS (BIT(1)) 409 #define EXTMEM_ICACHE_SHUT_CORE1_BUS_M (BIT(1)) 410 #define EXTMEM_ICACHE_SHUT_CORE1_BUS_V 0x1 411 #define EXTMEM_ICACHE_SHUT_CORE1_BUS_S 1 412 /* EXTMEM_ICACHE_SHUT_CORE0_BUS : R/W ;bitpos:[0] ;default: 1'b1 ; */ 413 /*description: The bit is used to disable core0 ibus, 0: enable, 1: disable.*/ 414 #define EXTMEM_ICACHE_SHUT_CORE0_BUS (BIT(0)) 415 #define EXTMEM_ICACHE_SHUT_CORE0_BUS_M (BIT(0)) 416 #define EXTMEM_ICACHE_SHUT_CORE0_BUS_V 0x1 417 #define EXTMEM_ICACHE_SHUT_CORE0_BUS_S 0 418 419 #define EXTMEM_ICACHE_TAG_POWER_CTRL_REG (DR_REG_EXTMEM_BASE + 0x68) 420 /* EXTMEM_ICACHE_TAG_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */ 421 /*description: The bit is used to power icache tag memory up, 0: follow rtc_lslp, 1: power up.*/ 422 #define EXTMEM_ICACHE_TAG_MEM_FORCE_PU (BIT(2)) 423 #define EXTMEM_ICACHE_TAG_MEM_FORCE_PU_M (BIT(2)) 424 #define EXTMEM_ICACHE_TAG_MEM_FORCE_PU_V 0x1 425 #define EXTMEM_ICACHE_TAG_MEM_FORCE_PU_S 2 426 /* EXTMEM_ICACHE_TAG_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */ 427 /*description: The bit is used to power icache tag memory down, 0: follow rtc_lslp, 1: power d 428 own.*/ 429 #define EXTMEM_ICACHE_TAG_MEM_FORCE_PD (BIT(1)) 430 #define EXTMEM_ICACHE_TAG_MEM_FORCE_PD_M (BIT(1)) 431 #define EXTMEM_ICACHE_TAG_MEM_FORCE_PD_V 0x1 432 #define EXTMEM_ICACHE_TAG_MEM_FORCE_PD_S 1 433 /* EXTMEM_ICACHE_TAG_MEM_FORCE_ON : R/W ;bitpos:[0] ;default: 1'b1 ; */ 434 /*description: The bit is used to close clock gating of icache tag memory. 1: close gating, 0: 435 open clock gating..*/ 436 #define EXTMEM_ICACHE_TAG_MEM_FORCE_ON (BIT(0)) 437 #define EXTMEM_ICACHE_TAG_MEM_FORCE_ON_M (BIT(0)) 438 #define EXTMEM_ICACHE_TAG_MEM_FORCE_ON_V 0x1 439 #define EXTMEM_ICACHE_TAG_MEM_FORCE_ON_S 0 440 441 #define EXTMEM_ICACHE_PRELOCK_CTRL_REG (DR_REG_EXTMEM_BASE + 0x6C) 442 /* EXTMEM_ICACHE_PRELOCK_SCT1_EN : R/W ;bitpos:[1] ;default: 1'h0 ; */ 443 /*description: The bit is used to enable the second section of prelock function..*/ 444 #define EXTMEM_ICACHE_PRELOCK_SCT1_EN (BIT(1)) 445 #define EXTMEM_ICACHE_PRELOCK_SCT1_EN_M (BIT(1)) 446 #define EXTMEM_ICACHE_PRELOCK_SCT1_EN_V 0x1 447 #define EXTMEM_ICACHE_PRELOCK_SCT1_EN_S 1 448 /* EXTMEM_ICACHE_PRELOCK_SCT0_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */ 449 /*description: The bit is used to enable the first section of prelock function..*/ 450 #define EXTMEM_ICACHE_PRELOCK_SCT0_EN (BIT(0)) 451 #define EXTMEM_ICACHE_PRELOCK_SCT0_EN_M (BIT(0)) 452 #define EXTMEM_ICACHE_PRELOCK_SCT0_EN_V 0x1 453 #define EXTMEM_ICACHE_PRELOCK_SCT0_EN_S 0 454 455 #define EXTMEM_ICACHE_PRELOCK_SCT0_ADDR_REG (DR_REG_EXTMEM_BASE + 0x70) 456 /* EXTMEM_ICACHE_PRELOCK_SCT0_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 457 /*description: The bits are used to configure the first start virtual address of data prelock, 458 which is combined with ICACHE_PRELOCK_SCT0_SIZE_REG.*/ 459 #define EXTMEM_ICACHE_PRELOCK_SCT0_ADDR 0xFFFFFFFF 460 #define EXTMEM_ICACHE_PRELOCK_SCT0_ADDR_M ((EXTMEM_ICACHE_PRELOCK_SCT0_ADDR_V)<<(EXTMEM_ICACHE_PRELOCK_SCT0_ADDR_S)) 461 #define EXTMEM_ICACHE_PRELOCK_SCT0_ADDR_V 0xFFFFFFFF 462 #define EXTMEM_ICACHE_PRELOCK_SCT0_ADDR_S 0 463 464 #define EXTMEM_ICACHE_PRELOCK_SCT1_ADDR_REG (DR_REG_EXTMEM_BASE + 0x74) 465 /* EXTMEM_ICACHE_PRELOCK_SCT1_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 466 /*description: The bits are used to configure the second start virtual address of data prelock, 467 which is combined with ICACHE_PRELOCK_SCT1_SIZE_REG.*/ 468 #define EXTMEM_ICACHE_PRELOCK_SCT1_ADDR 0xFFFFFFFF 469 #define EXTMEM_ICACHE_PRELOCK_SCT1_ADDR_M ((EXTMEM_ICACHE_PRELOCK_SCT1_ADDR_V)<<(EXTMEM_ICACHE_PRELOCK_SCT1_ADDR_S)) 470 #define EXTMEM_ICACHE_PRELOCK_SCT1_ADDR_V 0xFFFFFFFF 471 #define EXTMEM_ICACHE_PRELOCK_SCT1_ADDR_S 0 472 473 #define EXTMEM_ICACHE_PRELOCK_SCT_SIZE_REG (DR_REG_EXTMEM_BASE + 0x78) 474 /* EXTMEM_ICACHE_PRELOCK_SCT0_SIZE : R/W ;bitpos:[31:16] ;default: 16'h0 ; */ 475 /*description: The bits are used to configure the first length of data locking, which is combin 476 ed with ICACHE_PRELOCK_SCT0_ADDR_REG.*/ 477 #define EXTMEM_ICACHE_PRELOCK_SCT0_SIZE 0x0000FFFF 478 #define EXTMEM_ICACHE_PRELOCK_SCT0_SIZE_M ((EXTMEM_ICACHE_PRELOCK_SCT0_SIZE_V)<<(EXTMEM_ICACHE_PRELOCK_SCT0_SIZE_S)) 479 #define EXTMEM_ICACHE_PRELOCK_SCT0_SIZE_V 0xFFFF 480 #define EXTMEM_ICACHE_PRELOCK_SCT0_SIZE_S 16 481 /* EXTMEM_ICACHE_PRELOCK_SCT1_SIZE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ 482 /*description: The bits are used to configure the second length of data locking, which is combi 483 ned with ICACHE_PRELOCK_SCT1_ADDR_REG.*/ 484 #define EXTMEM_ICACHE_PRELOCK_SCT1_SIZE 0x0000FFFF 485 #define EXTMEM_ICACHE_PRELOCK_SCT1_SIZE_M ((EXTMEM_ICACHE_PRELOCK_SCT1_SIZE_V)<<(EXTMEM_ICACHE_PRELOCK_SCT1_SIZE_S)) 486 #define EXTMEM_ICACHE_PRELOCK_SCT1_SIZE_V 0xFFFF 487 #define EXTMEM_ICACHE_PRELOCK_SCT1_SIZE_S 0 488 489 #define EXTMEM_ICACHE_LOCK_CTRL_REG (DR_REG_EXTMEM_BASE + 0x7C) 490 /* EXTMEM_ICACHE_LOCK_DONE : RO ;bitpos:[2] ;default: 1'b1 ; */ 491 /*description: The bit is used to indicate unlock/lock operation is finished..*/ 492 #define EXTMEM_ICACHE_LOCK_DONE (BIT(2)) 493 #define EXTMEM_ICACHE_LOCK_DONE_M (BIT(2)) 494 #define EXTMEM_ICACHE_LOCK_DONE_V 0x1 495 #define EXTMEM_ICACHE_LOCK_DONE_S 2 496 /* EXTMEM_ICACHE_UNLOCK_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ 497 /*description: The bit is used to enable unlock operation. It will be cleared by hardware after 498 unlock operation done..*/ 499 #define EXTMEM_ICACHE_UNLOCK_ENA (BIT(1)) 500 #define EXTMEM_ICACHE_UNLOCK_ENA_M (BIT(1)) 501 #define EXTMEM_ICACHE_UNLOCK_ENA_V 0x1 502 #define EXTMEM_ICACHE_UNLOCK_ENA_S 1 503 /* EXTMEM_ICACHE_LOCK_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ 504 /*description: The bit is used to enable lock operation. It will be cleared by hardware after l 505 ock operation done..*/ 506 #define EXTMEM_ICACHE_LOCK_ENA (BIT(0)) 507 #define EXTMEM_ICACHE_LOCK_ENA_M (BIT(0)) 508 #define EXTMEM_ICACHE_LOCK_ENA_V 0x1 509 #define EXTMEM_ICACHE_LOCK_ENA_S 0 510 511 #define EXTMEM_ICACHE_LOCK_ADDR_REG (DR_REG_EXTMEM_BASE + 0x80) 512 /* EXTMEM_ICACHE_LOCK_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ 513 /*description: The bits are used to configure the start virtual address for lock operations. It 514 should be combined with ICACHE_LOCK_SIZE_REG..*/ 515 #define EXTMEM_ICACHE_LOCK_ADDR 0xFFFFFFFF 516 #define EXTMEM_ICACHE_LOCK_ADDR_M ((EXTMEM_ICACHE_LOCK_ADDR_V)<<(EXTMEM_ICACHE_LOCK_ADDR_S)) 517 #define EXTMEM_ICACHE_LOCK_ADDR_V 0xFFFFFFFF 518 #define EXTMEM_ICACHE_LOCK_ADDR_S 0 519 520 #define EXTMEM_ICACHE_LOCK_SIZE_REG (DR_REG_EXTMEM_BASE + 0x84) 521 /* EXTMEM_ICACHE_LOCK_SIZE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ 522 /*description: The bits are used to configure the length for lock operations. The bits are the 523 counts of cache block. It should be combined with ICACHE_LOCK_ADDR_REG..*/ 524 #define EXTMEM_ICACHE_LOCK_SIZE 0x0000FFFF 525 #define EXTMEM_ICACHE_LOCK_SIZE_M ((EXTMEM_ICACHE_LOCK_SIZE_V)<<(EXTMEM_ICACHE_LOCK_SIZE_S)) 526 #define EXTMEM_ICACHE_LOCK_SIZE_V 0xFFFF 527 #define EXTMEM_ICACHE_LOCK_SIZE_S 0 528 529 #define EXTMEM_ICACHE_SYNC_CTRL_REG (DR_REG_EXTMEM_BASE + 0x88) 530 /* EXTMEM_ICACHE_SYNC_DONE : RO ;bitpos:[1] ;default: 1'b0 ; */ 531 /*description: The bit is used to indicate invalidate operation is finished..*/ 532 #define EXTMEM_ICACHE_SYNC_DONE (BIT(1)) 533 #define EXTMEM_ICACHE_SYNC_DONE_M (BIT(1)) 534 #define EXTMEM_ICACHE_SYNC_DONE_V 0x1 535 #define EXTMEM_ICACHE_SYNC_DONE_S 1 536 /* EXTMEM_ICACHE_INVALIDATE_ENA : R/W ;bitpos:[0] ;default: 1'b1 ; */ 537 /*description: The bit is used to enable invalidate operation. It will be cleared by hardware a 538 fter invalidate operation done..*/ 539 #define EXTMEM_ICACHE_INVALIDATE_ENA (BIT(0)) 540 #define EXTMEM_ICACHE_INVALIDATE_ENA_M (BIT(0)) 541 #define EXTMEM_ICACHE_INVALIDATE_ENA_V 0x1 542 #define EXTMEM_ICACHE_INVALIDATE_ENA_S 0 543 544 #define EXTMEM_ICACHE_SYNC_ADDR_REG (DR_REG_EXTMEM_BASE + 0x8C) 545 /* EXTMEM_ICACHE_SYNC_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ 546 /*description: The bits are used to configure the start virtual address for clean operations. I 547 t should be combined with ICACHE_SYNC_SIZE_REG..*/ 548 #define EXTMEM_ICACHE_SYNC_ADDR 0xFFFFFFFF 549 #define EXTMEM_ICACHE_SYNC_ADDR_M ((EXTMEM_ICACHE_SYNC_ADDR_V)<<(EXTMEM_ICACHE_SYNC_ADDR_S)) 550 #define EXTMEM_ICACHE_SYNC_ADDR_V 0xFFFFFFFF 551 #define EXTMEM_ICACHE_SYNC_ADDR_S 0 552 553 #define EXTMEM_ICACHE_SYNC_SIZE_REG (DR_REG_EXTMEM_BASE + 0x90) 554 /* EXTMEM_ICACHE_SYNC_SIZE : R/W ;bitpos:[22:0] ;default: 23'h0 ; */ 555 /*description: The bits are used to configure the length for sync operations. The bits are the 556 counts of cache block. It should be combined with ICACHE_SYNC_ADDR_REG..*/ 557 #define EXTMEM_ICACHE_SYNC_SIZE 0x007FFFFF 558 #define EXTMEM_ICACHE_SYNC_SIZE_M ((EXTMEM_ICACHE_SYNC_SIZE_V)<<(EXTMEM_ICACHE_SYNC_SIZE_S)) 559 #define EXTMEM_ICACHE_SYNC_SIZE_V 0x7FFFFF 560 #define EXTMEM_ICACHE_SYNC_SIZE_S 0 561 562 #define EXTMEM_ICACHE_PRELOAD_CTRL_REG (DR_REG_EXTMEM_BASE + 0x94) 563 /* EXTMEM_ICACHE_PRELOAD_ORDER : R/W ;bitpos:[2] ;default: 1'b0 ; */ 564 /*description: The bit is used to configure the direction of preload operation. 1: descending, 565 0: ascending..*/ 566 #define EXTMEM_ICACHE_PRELOAD_ORDER (BIT(2)) 567 #define EXTMEM_ICACHE_PRELOAD_ORDER_M (BIT(2)) 568 #define EXTMEM_ICACHE_PRELOAD_ORDER_V 0x1 569 #define EXTMEM_ICACHE_PRELOAD_ORDER_S 2 570 /* EXTMEM_ICACHE_PRELOAD_DONE : RO ;bitpos:[1] ;default: 1'b1 ; */ 571 /*description: The bit is used to indicate preload operation is finished..*/ 572 #define EXTMEM_ICACHE_PRELOAD_DONE (BIT(1)) 573 #define EXTMEM_ICACHE_PRELOAD_DONE_M (BIT(1)) 574 #define EXTMEM_ICACHE_PRELOAD_DONE_V 0x1 575 #define EXTMEM_ICACHE_PRELOAD_DONE_S 1 576 /* EXTMEM_ICACHE_PRELOAD_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ 577 /*description: The bit is used to enable preload operation. It will be cleared by hardware afte 578 r preload operation done..*/ 579 #define EXTMEM_ICACHE_PRELOAD_ENA (BIT(0)) 580 #define EXTMEM_ICACHE_PRELOAD_ENA_M (BIT(0)) 581 #define EXTMEM_ICACHE_PRELOAD_ENA_V 0x1 582 #define EXTMEM_ICACHE_PRELOAD_ENA_S 0 583 584 #define EXTMEM_ICACHE_PRELOAD_ADDR_REG (DR_REG_EXTMEM_BASE + 0x98) 585 /* EXTMEM_ICACHE_PRELOAD_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ 586 /*description: The bits are used to configure the start virtual address for preload operation. 587 It should be combined with ICACHE_PRELOAD_SIZE_REG..*/ 588 #define EXTMEM_ICACHE_PRELOAD_ADDR 0xFFFFFFFF 589 #define EXTMEM_ICACHE_PRELOAD_ADDR_M ((EXTMEM_ICACHE_PRELOAD_ADDR_V)<<(EXTMEM_ICACHE_PRELOAD_ADDR_S)) 590 #define EXTMEM_ICACHE_PRELOAD_ADDR_V 0xFFFFFFFF 591 #define EXTMEM_ICACHE_PRELOAD_ADDR_S 0 592 593 #define EXTMEM_ICACHE_PRELOAD_SIZE_REG (DR_REG_EXTMEM_BASE + 0x9C) 594 /* EXTMEM_ICACHE_PRELOAD_SIZE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ 595 /*description: The bits are used to configure the length for preload operation. The bits are th 596 e counts of cache block. It should be combined with ICACHE_PRELOAD_ADDR_REG...*/ 597 #define EXTMEM_ICACHE_PRELOAD_SIZE 0x0000FFFF 598 #define EXTMEM_ICACHE_PRELOAD_SIZE_M ((EXTMEM_ICACHE_PRELOAD_SIZE_V)<<(EXTMEM_ICACHE_PRELOAD_SIZE_S)) 599 #define EXTMEM_ICACHE_PRELOAD_SIZE_V 0xFFFF 600 #define EXTMEM_ICACHE_PRELOAD_SIZE_S 0 601 602 #define EXTMEM_ICACHE_AUTOLOAD_CTRL_REG (DR_REG_EXTMEM_BASE + 0xA0) 603 /* EXTMEM_ICACHE_AUTOLOAD_BUFFER_CLEAR : R/W ;bitpos:[9] ;default: 1'b0 ; */ 604 /*description: The bit is used to clear autoload buffer in icache..*/ 605 #define EXTMEM_ICACHE_AUTOLOAD_BUFFER_CLEAR (BIT(9)) 606 #define EXTMEM_ICACHE_AUTOLOAD_BUFFER_CLEAR_M (BIT(9)) 607 #define EXTMEM_ICACHE_AUTOLOAD_BUFFER_CLEAR_V 0x1 608 #define EXTMEM_ICACHE_AUTOLOAD_BUFFER_CLEAR_S 9 609 /* EXTMEM_ICACHE_AUTOLOAD_SIZE : R/W ;bitpos:[8:7] ;default: 2'h0 ; */ 610 /*description: The bits are used to configure the numbers of the cache block for the issuing au 611 toload operation..*/ 612 #define EXTMEM_ICACHE_AUTOLOAD_SIZE 0x00000003 613 #define EXTMEM_ICACHE_AUTOLOAD_SIZE_M ((EXTMEM_ICACHE_AUTOLOAD_SIZE_V)<<(EXTMEM_ICACHE_AUTOLOAD_SIZE_S)) 614 #define EXTMEM_ICACHE_AUTOLOAD_SIZE_V 0x3 615 #define EXTMEM_ICACHE_AUTOLOAD_SIZE_S 7 616 /* EXTMEM_ICACHE_AUTOLOAD_RQST : R/W ;bitpos:[6:5] ;default: 2'b0 ; */ 617 /*description: The bits are used to configure trigger conditions for autoload. 0/3: cache miss, 618 1: cache hit, 2: both cache miss and hit..*/ 619 #define EXTMEM_ICACHE_AUTOLOAD_RQST 0x00000003 620 #define EXTMEM_ICACHE_AUTOLOAD_RQST_M ((EXTMEM_ICACHE_AUTOLOAD_RQST_V)<<(EXTMEM_ICACHE_AUTOLOAD_RQST_S)) 621 #define EXTMEM_ICACHE_AUTOLOAD_RQST_V 0x3 622 #define EXTMEM_ICACHE_AUTOLOAD_RQST_S 5 623 /* EXTMEM_ICACHE_AUTOLOAD_ORDER : R/W ;bitpos:[4] ;default: 1'b0 ; */ 624 /*description: The bits are used to configure the direction of autoload. 1: descending, 0: asce 625 nding..*/ 626 #define EXTMEM_ICACHE_AUTOLOAD_ORDER (BIT(4)) 627 #define EXTMEM_ICACHE_AUTOLOAD_ORDER_M (BIT(4)) 628 #define EXTMEM_ICACHE_AUTOLOAD_ORDER_V 0x1 629 #define EXTMEM_ICACHE_AUTOLOAD_ORDER_S 4 630 /* EXTMEM_ICACHE_AUTOLOAD_DONE : RO ;bitpos:[3] ;default: 1'b1 ; */ 631 /*description: The bit is used to indicate autoload operation is finished..*/ 632 #define EXTMEM_ICACHE_AUTOLOAD_DONE (BIT(3)) 633 #define EXTMEM_ICACHE_AUTOLOAD_DONE_M (BIT(3)) 634 #define EXTMEM_ICACHE_AUTOLOAD_DONE_V 0x1 635 #define EXTMEM_ICACHE_AUTOLOAD_DONE_S 3 636 /* EXTMEM_ICACHE_AUTOLOAD_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ 637 /*description: The bit is used to enable and disable autoload operation. It is combined with ic 638 ache_autoload_done. 1: enable, 0: disable. .*/ 639 #define EXTMEM_ICACHE_AUTOLOAD_ENA (BIT(2)) 640 #define EXTMEM_ICACHE_AUTOLOAD_ENA_M (BIT(2)) 641 #define EXTMEM_ICACHE_AUTOLOAD_ENA_V 0x1 642 #define EXTMEM_ICACHE_AUTOLOAD_ENA_S 2 643 /* EXTMEM_ICACHE_AUTOLOAD_SCT1_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ 644 /*description: The bits are used to enable the second section for autoload operation..*/ 645 #define EXTMEM_ICACHE_AUTOLOAD_SCT1_ENA (BIT(1)) 646 #define EXTMEM_ICACHE_AUTOLOAD_SCT1_ENA_M (BIT(1)) 647 #define EXTMEM_ICACHE_AUTOLOAD_SCT1_ENA_V 0x1 648 #define EXTMEM_ICACHE_AUTOLOAD_SCT1_ENA_S 1 649 /* EXTMEM_ICACHE_AUTOLOAD_SCT0_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ 650 /*description: The bits are used to enable the first section for autoload operation..*/ 651 #define EXTMEM_ICACHE_AUTOLOAD_SCT0_ENA (BIT(0)) 652 #define EXTMEM_ICACHE_AUTOLOAD_SCT0_ENA_M (BIT(0)) 653 #define EXTMEM_ICACHE_AUTOLOAD_SCT0_ENA_V 0x1 654 #define EXTMEM_ICACHE_AUTOLOAD_SCT0_ENA_S 0 655 656 #define EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR_REG (DR_REG_EXTMEM_BASE + 0xA4) 657 /* EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ 658 /*description: The bits are used to configure the start virtual address of the first section fo 659 r autoload operation. It should be combined with icache_autoload_sct0_ena..*/ 660 #define EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR 0xFFFFFFFF 661 #define EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR_M ((EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR_V)<<(EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR_S)) 662 #define EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR_V 0xFFFFFFFF 663 #define EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR_S 0 664 665 #define EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE_REG (DR_REG_EXTMEM_BASE + 0xA8) 666 /* EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE : R/W ;bitpos:[26:0] ;default: 27'h0 ; */ 667 /*description: The bits are used to configure the length of the first section for autoload oper 668 ation. It should be combined with icache_autoload_sct0_ena..*/ 669 #define EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE 0x07FFFFFF 670 #define EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE_M ((EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE_V)<<(EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE_S)) 671 #define EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE_V 0x7FFFFFF 672 #define EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE_S 0 673 674 #define EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR_REG (DR_REG_EXTMEM_BASE + 0xAC) 675 /* EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ 676 /*description: The bits are used to configure the start virtual address of the second section f 677 or autoload operation. It should be combined with icache_autoload_sct1_ena..*/ 678 #define EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR 0xFFFFFFFF 679 #define EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR_M ((EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR_V)<<(EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR_S)) 680 #define EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR_V 0xFFFFFFFF 681 #define EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR_S 0 682 683 #define EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE_REG (DR_REG_EXTMEM_BASE + 0xB0) 684 /* EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE : R/W ;bitpos:[26:0] ;default: 27'h0 ; */ 685 /*description: The bits are used to configure the length of the second section for autoload ope 686 ration. It should be combined with icache_autoload_sct1_ena..*/ 687 #define EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE 0x07FFFFFF 688 #define EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE_M ((EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE_V)<<(EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE_S)) 689 #define EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE_V 0x7FFFFFF 690 #define EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE_S 0 691 692 #define EXTMEM_IBUS_TO_FLASH_START_VADDR_REG (DR_REG_EXTMEM_BASE + 0xB4) 693 /* EXTMEM_IBUS_TO_FLASH_START_VADDR : R/W ;bitpos:[31:0] ;default: 32'h44000000 ; */ 694 /*description: The bits are used to configure the start virtual address of ibus to access flash 695 . The register is used to give constraints to ibus access counter..*/ 696 #define EXTMEM_IBUS_TO_FLASH_START_VADDR 0xFFFFFFFF 697 #define EXTMEM_IBUS_TO_FLASH_START_VADDR_M ((EXTMEM_IBUS_TO_FLASH_START_VADDR_V)<<(EXTMEM_IBUS_TO_FLASH_START_VADDR_S)) 698 #define EXTMEM_IBUS_TO_FLASH_START_VADDR_V 0xFFFFFFFF 699 #define EXTMEM_IBUS_TO_FLASH_START_VADDR_S 0 700 701 #define EXTMEM_IBUS_TO_FLASH_END_VADDR_REG (DR_REG_EXTMEM_BASE + 0xB8) 702 /* EXTMEM_IBUS_TO_FLASH_END_VADDR : R/W ;bitpos:[31:0] ;default: 32'h47ffffff ; */ 703 /*description: The bits are used to configure the end virtual address of ibus to access flash. 704 The register is used to give constraints to ibus access counter..*/ 705 #define EXTMEM_IBUS_TO_FLASH_END_VADDR 0xFFFFFFFF 706 #define EXTMEM_IBUS_TO_FLASH_END_VADDR_M ((EXTMEM_IBUS_TO_FLASH_END_VADDR_V)<<(EXTMEM_IBUS_TO_FLASH_END_VADDR_S)) 707 #define EXTMEM_IBUS_TO_FLASH_END_VADDR_V 0xFFFFFFFF 708 #define EXTMEM_IBUS_TO_FLASH_END_VADDR_S 0 709 710 #define EXTMEM_DBUS_TO_FLASH_START_VADDR_REG (DR_REG_EXTMEM_BASE + 0xBC) 711 /* EXTMEM_DBUS_TO_FLASH_START_VADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ 712 /*description: The bits are used to configure the start virtual address of dbus to access flash 713 . The register is used to give constraints to dbus access counter..*/ 714 #define EXTMEM_DBUS_TO_FLASH_START_VADDR 0xFFFFFFFF 715 #define EXTMEM_DBUS_TO_FLASH_START_VADDR_M ((EXTMEM_DBUS_TO_FLASH_START_VADDR_V)<<(EXTMEM_DBUS_TO_FLASH_START_VADDR_S)) 716 #define EXTMEM_DBUS_TO_FLASH_START_VADDR_V 0xFFFFFFFF 717 #define EXTMEM_DBUS_TO_FLASH_START_VADDR_S 0 718 719 #define EXTMEM_DBUS_TO_FLASH_END_VADDR_REG (DR_REG_EXTMEM_BASE + 0xC0) 720 /* EXTMEM_DBUS_TO_FLASH_END_VADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ 721 /*description: The bits are used to configure the end virtual address of dbus to access flash. 722 The register is used to give constraints to dbus access counter..*/ 723 #define EXTMEM_DBUS_TO_FLASH_END_VADDR 0xFFFFFFFF 724 #define EXTMEM_DBUS_TO_FLASH_END_VADDR_M ((EXTMEM_DBUS_TO_FLASH_END_VADDR_V)<<(EXTMEM_DBUS_TO_FLASH_END_VADDR_S)) 725 #define EXTMEM_DBUS_TO_FLASH_END_VADDR_V 0xFFFFFFFF 726 #define EXTMEM_DBUS_TO_FLASH_END_VADDR_S 0 727 728 #define EXTMEM_CACHE_ACS_CNT_CLR_REG (DR_REG_EXTMEM_BASE + 0xC4) 729 /* EXTMEM_ICACHE_ACS_CNT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */ 730 /*description: The bit is used to clear icache counter..*/ 731 #define EXTMEM_ICACHE_ACS_CNT_CLR (BIT(1)) 732 #define EXTMEM_ICACHE_ACS_CNT_CLR_M (BIT(1)) 733 #define EXTMEM_ICACHE_ACS_CNT_CLR_V 0x1 734 #define EXTMEM_ICACHE_ACS_CNT_CLR_S 1 735 /* EXTMEM_DCACHE_ACS_CNT_CLR : WOD ;bitpos:[0] ;default: 1'b0 ; */ 736 /*description: The bit is used to clear dcache counter..*/ 737 #define EXTMEM_DCACHE_ACS_CNT_CLR (BIT(0)) 738 #define EXTMEM_DCACHE_ACS_CNT_CLR_M (BIT(0)) 739 #define EXTMEM_DCACHE_ACS_CNT_CLR_V 0x1 740 #define EXTMEM_DCACHE_ACS_CNT_CLR_S 0 741 742 #define EXTMEM_IBUS_ACS_MISS_CNT_REG (DR_REG_EXTMEM_BASE + 0xC8) 743 /* EXTMEM_IBUS_ACS_MISS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 744 /*description: The bits are used to count the number of the cache miss caused by ibus access fl 745 ash/spiram..*/ 746 #define EXTMEM_IBUS_ACS_MISS_CNT 0xFFFFFFFF 747 #define EXTMEM_IBUS_ACS_MISS_CNT_M ((EXTMEM_IBUS_ACS_MISS_CNT_V)<<(EXTMEM_IBUS_ACS_MISS_CNT_S)) 748 #define EXTMEM_IBUS_ACS_MISS_CNT_V 0xFFFFFFFF 749 #define EXTMEM_IBUS_ACS_MISS_CNT_S 0 750 751 #define EXTMEM_IBUS_ACS_CNT_REG (DR_REG_EXTMEM_BASE + 0xCC) 752 /* EXTMEM_IBUS_ACS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 753 /*description: The bits are used to count the number of ibus access flash/spiram through icache 754 ..*/ 755 #define EXTMEM_IBUS_ACS_CNT 0xFFFFFFFF 756 #define EXTMEM_IBUS_ACS_CNT_M ((EXTMEM_IBUS_ACS_CNT_V)<<(EXTMEM_IBUS_ACS_CNT_S)) 757 #define EXTMEM_IBUS_ACS_CNT_V 0xFFFFFFFF 758 #define EXTMEM_IBUS_ACS_CNT_S 0 759 760 #define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_REG (DR_REG_EXTMEM_BASE + 0xD0) 761 /* EXTMEM_DBUS_ACS_FLASH_MISS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 762 /*description: The bits are used to count the number of the cache miss caused by dbus access fl 763 ash..*/ 764 #define EXTMEM_DBUS_ACS_FLASH_MISS_CNT 0xFFFFFFFF 765 #define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_M ((EXTMEM_DBUS_ACS_FLASH_MISS_CNT_V)<<(EXTMEM_DBUS_ACS_FLASH_MISS_CNT_S)) 766 #define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_V 0xFFFFFFFF 767 #define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_S 0 768 769 #define EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT_REG (DR_REG_EXTMEM_BASE + 0xD4) 770 /* EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 771 /*description: The bits are used to count the number of the cache miss caused by dbus access sp 772 iram..*/ 773 #define EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT 0xFFFFFFFF 774 #define EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT_M ((EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT_V)<<(EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT_S)) 775 #define EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT_V 0xFFFFFFFF 776 #define EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT_S 0 777 778 #define EXTMEM_DBUS_ACS_CNT_REG (DR_REG_EXTMEM_BASE + 0xD8) 779 /* EXTMEM_DBUS_ACS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 780 /*description: The bits are used to count the number of dbus access flash/spiram through dcache 781 ..*/ 782 #define EXTMEM_DBUS_ACS_CNT 0xFFFFFFFF 783 #define EXTMEM_DBUS_ACS_CNT_M ((EXTMEM_DBUS_ACS_CNT_V)<<(EXTMEM_DBUS_ACS_CNT_S)) 784 #define EXTMEM_DBUS_ACS_CNT_V 0xFFFFFFFF 785 #define EXTMEM_DBUS_ACS_CNT_S 0 786 787 #define EXTMEM_CACHE_ILG_INT_ENA_REG (DR_REG_EXTMEM_BASE + 0xDC) 788 /* EXTMEM_DBUS_CNT_OVF_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ 789 /*description: The bit is used to enable interrupt by dbus counter overflow..*/ 790 #define EXTMEM_DBUS_CNT_OVF_INT_ENA (BIT(8)) 791 #define EXTMEM_DBUS_CNT_OVF_INT_ENA_M (BIT(8)) 792 #define EXTMEM_DBUS_CNT_OVF_INT_ENA_V 0x1 793 #define EXTMEM_DBUS_CNT_OVF_INT_ENA_S 8 794 /* EXTMEM_IBUS_CNT_OVF_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ 795 /*description: The bit is used to enable interrupt by ibus counter overflow..*/ 796 #define EXTMEM_IBUS_CNT_OVF_INT_ENA (BIT(7)) 797 #define EXTMEM_IBUS_CNT_OVF_INT_ENA_M (BIT(7)) 798 #define EXTMEM_IBUS_CNT_OVF_INT_ENA_V 0x1 799 #define EXTMEM_IBUS_CNT_OVF_INT_ENA_S 7 800 /* EXTMEM_DCACHE_OCCUPY_EXC_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ 801 /*description: The bit is used to enable interrupt by dcache trying to replace a line whose blo 802 cks all have been occupied by occupy-mode..*/ 803 #define EXTMEM_DCACHE_OCCUPY_EXC_INT_ENA (BIT(6)) 804 #define EXTMEM_DCACHE_OCCUPY_EXC_INT_ENA_M (BIT(6)) 805 #define EXTMEM_DCACHE_OCCUPY_EXC_INT_ENA_V 0x1 806 #define EXTMEM_DCACHE_OCCUPY_EXC_INT_ENA_S 6 807 /* EXTMEM_MMU_ENTRY_FAULT_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ 808 /*description: The bit is used to enable interrupt by mmu entry fault..*/ 809 #define EXTMEM_MMU_ENTRY_FAULT_INT_ENA (BIT(5)) 810 #define EXTMEM_MMU_ENTRY_FAULT_INT_ENA_M (BIT(5)) 811 #define EXTMEM_MMU_ENTRY_FAULT_INT_ENA_V 0x1 812 #define EXTMEM_MMU_ENTRY_FAULT_INT_ENA_S 5 813 /* EXTMEM_DCACHE_WRITE_FLASH_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ 814 /*description: The bit is used to enable interrupt by dcache trying to write flash..*/ 815 #define EXTMEM_DCACHE_WRITE_FLASH_INT_ENA (BIT(4)) 816 #define EXTMEM_DCACHE_WRITE_FLASH_INT_ENA_M (BIT(4)) 817 #define EXTMEM_DCACHE_WRITE_FLASH_INT_ENA_V 0x1 818 #define EXTMEM_DCACHE_WRITE_FLASH_INT_ENA_S 4 819 /* EXTMEM_DCACHE_PRELOAD_OP_FAULT_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ 820 /*description: The bit is used to enable interrupt by preload configurations fault..*/ 821 #define EXTMEM_DCACHE_PRELOAD_OP_FAULT_INT_ENA (BIT(3)) 822 #define EXTMEM_DCACHE_PRELOAD_OP_FAULT_INT_ENA_M (BIT(3)) 823 #define EXTMEM_DCACHE_PRELOAD_OP_FAULT_INT_ENA_V 0x1 824 #define EXTMEM_DCACHE_PRELOAD_OP_FAULT_INT_ENA_S 3 825 /* EXTMEM_DCACHE_SYNC_OP_FAULT_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ 826 /*description: The bit is used to enable interrupt by sync configurations fault..*/ 827 #define EXTMEM_DCACHE_SYNC_OP_FAULT_INT_ENA (BIT(2)) 828 #define EXTMEM_DCACHE_SYNC_OP_FAULT_INT_ENA_M (BIT(2)) 829 #define EXTMEM_DCACHE_SYNC_OP_FAULT_INT_ENA_V 0x1 830 #define EXTMEM_DCACHE_SYNC_OP_FAULT_INT_ENA_S 2 831 /* EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ 832 /*description: The bit is used to enable interrupt by preload configurations fault..*/ 833 #define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA (BIT(1)) 834 #define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA_M (BIT(1)) 835 #define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA_V 0x1 836 #define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA_S 1 837 /* EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ 838 /*description: The bit is used to enable interrupt by sync configurations fault..*/ 839 #define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA (BIT(0)) 840 #define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA_M (BIT(0)) 841 #define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA_V 0x1 842 #define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA_S 0 843 844 #define EXTMEM_CACHE_ILG_INT_CLR_REG (DR_REG_EXTMEM_BASE + 0xE0) 845 /* EXTMEM_DBUS_CNT_OVF_INT_CLR : WOD ;bitpos:[8] ;default: 1'b0 ; */ 846 /*description: The bit is used to clear interrupt by dbus counter overflow..*/ 847 #define EXTMEM_DBUS_CNT_OVF_INT_CLR (BIT(8)) 848 #define EXTMEM_DBUS_CNT_OVF_INT_CLR_M (BIT(8)) 849 #define EXTMEM_DBUS_CNT_OVF_INT_CLR_V 0x1 850 #define EXTMEM_DBUS_CNT_OVF_INT_CLR_S 8 851 /* EXTMEM_IBUS_CNT_OVF_INT_CLR : WOD ;bitpos:[7] ;default: 1'b0 ; */ 852 /*description: The bit is used to clear interrupt by ibus counter overflow..*/ 853 #define EXTMEM_IBUS_CNT_OVF_INT_CLR (BIT(7)) 854 #define EXTMEM_IBUS_CNT_OVF_INT_CLR_M (BIT(7)) 855 #define EXTMEM_IBUS_CNT_OVF_INT_CLR_V 0x1 856 #define EXTMEM_IBUS_CNT_OVF_INT_CLR_S 7 857 /* EXTMEM_DCACHE_OCCUPY_EXC_INT_CLR : WOD ;bitpos:[6] ;default: 1'b0 ; */ 858 /*description: The bit is used to clear interrupt by dcache trying to replace a line whose bloc 859 ks all have been occupied by occupy-mode..*/ 860 #define EXTMEM_DCACHE_OCCUPY_EXC_INT_CLR (BIT(6)) 861 #define EXTMEM_DCACHE_OCCUPY_EXC_INT_CLR_M (BIT(6)) 862 #define EXTMEM_DCACHE_OCCUPY_EXC_INT_CLR_V 0x1 863 #define EXTMEM_DCACHE_OCCUPY_EXC_INT_CLR_S 6 864 /* EXTMEM_MMU_ENTRY_FAULT_INT_CLR : WOD ;bitpos:[5] ;default: 1'b0 ; */ 865 /*description: The bit is used to clear interrupt by mmu entry fault..*/ 866 #define EXTMEM_MMU_ENTRY_FAULT_INT_CLR (BIT(5)) 867 #define EXTMEM_MMU_ENTRY_FAULT_INT_CLR_M (BIT(5)) 868 #define EXTMEM_MMU_ENTRY_FAULT_INT_CLR_V 0x1 869 #define EXTMEM_MMU_ENTRY_FAULT_INT_CLR_S 5 870 /* EXTMEM_DCACHE_WRITE_FLASH_INT_CLR : WOD ;bitpos:[4] ;default: 1'b0 ; */ 871 /*description: The bit is used to clear interrupt by dcache trying to write flash..*/ 872 #define EXTMEM_DCACHE_WRITE_FLASH_INT_CLR (BIT(4)) 873 #define EXTMEM_DCACHE_WRITE_FLASH_INT_CLR_M (BIT(4)) 874 #define EXTMEM_DCACHE_WRITE_FLASH_INT_CLR_V 0x1 875 #define EXTMEM_DCACHE_WRITE_FLASH_INT_CLR_S 4 876 /* EXTMEM_DCACHE_PRELOAD_OP_FAULT_INT_CLR : WOD ;bitpos:[3] ;default: 1'b0 ; */ 877 /*description: The bit is used to clear interrupt by preload configurations fault..*/ 878 #define EXTMEM_DCACHE_PRELOAD_OP_FAULT_INT_CLR (BIT(3)) 879 #define EXTMEM_DCACHE_PRELOAD_OP_FAULT_INT_CLR_M (BIT(3)) 880 #define EXTMEM_DCACHE_PRELOAD_OP_FAULT_INT_CLR_V 0x1 881 #define EXTMEM_DCACHE_PRELOAD_OP_FAULT_INT_CLR_S 3 882 /* EXTMEM_DCACHE_SYNC_OP_FAULT_INT_CLR : WOD ;bitpos:[2] ;default: 1'b0 ; */ 883 /*description: The bit is used to clear interrupt by sync configurations fault..*/ 884 #define EXTMEM_DCACHE_SYNC_OP_FAULT_INT_CLR (BIT(2)) 885 #define EXTMEM_DCACHE_SYNC_OP_FAULT_INT_CLR_M (BIT(2)) 886 #define EXTMEM_DCACHE_SYNC_OP_FAULT_INT_CLR_V 0x1 887 #define EXTMEM_DCACHE_SYNC_OP_FAULT_INT_CLR_S 2 888 /* EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */ 889 /*description: The bit is used to clear interrupt by preload configurations fault..*/ 890 #define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR (BIT(1)) 891 #define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR_M (BIT(1)) 892 #define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR_V 0x1 893 #define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR_S 1 894 /* EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR : WOD ;bitpos:[0] ;default: 1'b0 ; */ 895 /*description: The bit is used to clear interrupt by sync configurations fault..*/ 896 #define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR (BIT(0)) 897 #define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR_M (BIT(0)) 898 #define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR_V 0x1 899 #define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR_S 0 900 901 #define EXTMEM_CACHE_ILG_INT_ST_REG (DR_REG_EXTMEM_BASE + 0xE4) 902 /* EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT_OVF_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ 903 /*description: The bit is used to indicate interrupt by dbus access spiram miss counter overflo 904 w..*/ 905 #define EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT_OVF_ST (BIT(11)) 906 #define EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT_OVF_ST_M (BIT(11)) 907 #define EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT_OVF_ST_V 0x1 908 #define EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT_OVF_ST_S 11 909 /* EXTMEM_DBUS_ACS_FLASH_MISS_CNT_OVF_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ 910 /*description: The bit is used to indicate interrupt by dbus access flash miss counter overflow 911 ..*/ 912 #define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_OVF_ST (BIT(10)) 913 #define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_OVF_ST_M (BIT(10)) 914 #define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_OVF_ST_V 0x1 915 #define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_OVF_ST_S 10 916 /* EXTMEM_DBUS_ACS_CNT_OVF_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ 917 /*description: The bit is used to indicate interrupt by dbus access flash/spiram counter overfl 918 ow..*/ 919 #define EXTMEM_DBUS_ACS_CNT_OVF_ST (BIT(9)) 920 #define EXTMEM_DBUS_ACS_CNT_OVF_ST_M (BIT(9)) 921 #define EXTMEM_DBUS_ACS_CNT_OVF_ST_V 0x1 922 #define EXTMEM_DBUS_ACS_CNT_OVF_ST_S 9 923 /* EXTMEM_IBUS_ACS_MISS_CNT_OVF_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ 924 /*description: The bit is used to indicate interrupt by ibus access flash/spiram miss counter o 925 verflow..*/ 926 #define EXTMEM_IBUS_ACS_MISS_CNT_OVF_ST (BIT(8)) 927 #define EXTMEM_IBUS_ACS_MISS_CNT_OVF_ST_M (BIT(8)) 928 #define EXTMEM_IBUS_ACS_MISS_CNT_OVF_ST_V 0x1 929 #define EXTMEM_IBUS_ACS_MISS_CNT_OVF_ST_S 8 930 /* EXTMEM_IBUS_ACS_CNT_OVF_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ 931 /*description: The bit is used to indicate interrupt by ibus access flash/spiram counter overfl 932 ow..*/ 933 #define EXTMEM_IBUS_ACS_CNT_OVF_ST (BIT(7)) 934 #define EXTMEM_IBUS_ACS_CNT_OVF_ST_M (BIT(7)) 935 #define EXTMEM_IBUS_ACS_CNT_OVF_ST_V 0x1 936 #define EXTMEM_IBUS_ACS_CNT_OVF_ST_S 7 937 /* EXTMEM_DCACHE_OCCUPY_EXC_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ 938 /*description: The bit is used to indicate interrupt by dcache trying to replace a line whose b 939 locks all have been occupied by occupy-mode..*/ 940 #define EXTMEM_DCACHE_OCCUPY_EXC_ST (BIT(6)) 941 #define EXTMEM_DCACHE_OCCUPY_EXC_ST_M (BIT(6)) 942 #define EXTMEM_DCACHE_OCCUPY_EXC_ST_V 0x1 943 #define EXTMEM_DCACHE_OCCUPY_EXC_ST_S 6 944 /* EXTMEM_MMU_ENTRY_FAULT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ 945 /*description: The bit is used to indicate interrupt by mmu entry fault..*/ 946 #define EXTMEM_MMU_ENTRY_FAULT_ST (BIT(5)) 947 #define EXTMEM_MMU_ENTRY_FAULT_ST_M (BIT(5)) 948 #define EXTMEM_MMU_ENTRY_FAULT_ST_V 0x1 949 #define EXTMEM_MMU_ENTRY_FAULT_ST_S 5 950 /* EXTMEM_DCACHE_WRITE_FLASH_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ 951 /*description: The bit is used to indicate interrupt by dcache trying to write flash..*/ 952 #define EXTMEM_DCACHE_WRITE_FLASH_ST (BIT(4)) 953 #define EXTMEM_DCACHE_WRITE_FLASH_ST_M (BIT(4)) 954 #define EXTMEM_DCACHE_WRITE_FLASH_ST_V 0x1 955 #define EXTMEM_DCACHE_WRITE_FLASH_ST_S 4 956 /* EXTMEM_DCACHE_PRELOAD_OP_FAULT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ 957 /*description: The bit is used to indicate interrupt by preload configurations fault..*/ 958 #define EXTMEM_DCACHE_PRELOAD_OP_FAULT_ST (BIT(3)) 959 #define EXTMEM_DCACHE_PRELOAD_OP_FAULT_ST_M (BIT(3)) 960 #define EXTMEM_DCACHE_PRELOAD_OP_FAULT_ST_V 0x1 961 #define EXTMEM_DCACHE_PRELOAD_OP_FAULT_ST_S 3 962 /* EXTMEM_DCACHE_SYNC_OP_FAULT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ 963 /*description: The bit is used to indicate interrupt by sync configurations fault..*/ 964 #define EXTMEM_DCACHE_SYNC_OP_FAULT_ST (BIT(2)) 965 #define EXTMEM_DCACHE_SYNC_OP_FAULT_ST_M (BIT(2)) 966 #define EXTMEM_DCACHE_SYNC_OP_FAULT_ST_V 0x1 967 #define EXTMEM_DCACHE_SYNC_OP_FAULT_ST_S 2 968 /* EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ 969 /*description: The bit is used to indicate interrupt by preload configurations fault..*/ 970 #define EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST (BIT(1)) 971 #define EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST_M (BIT(1)) 972 #define EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST_V 0x1 973 #define EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST_S 1 974 /* EXTMEM_ICACHE_SYNC_OP_FAULT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ 975 /*description: The bit is used to indicate interrupt by sync configurations fault..*/ 976 #define EXTMEM_ICACHE_SYNC_OP_FAULT_ST (BIT(0)) 977 #define EXTMEM_ICACHE_SYNC_OP_FAULT_ST_M (BIT(0)) 978 #define EXTMEM_ICACHE_SYNC_OP_FAULT_ST_V 0x1 979 #define EXTMEM_ICACHE_SYNC_OP_FAULT_ST_S 0 980 981 #define EXTMEM_CORE0_ACS_CACHE_INT_ENA_REG (DR_REG_EXTMEM_BASE + 0xE8) 982 /* EXTMEM_CORE0_DBUS_REJECT_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ 983 /*description: The bit is used to enable interrupt by authentication fail..*/ 984 #define EXTMEM_CORE0_DBUS_REJECT_INT_ENA (BIT(4)) 985 #define EXTMEM_CORE0_DBUS_REJECT_INT_ENA_M (BIT(4)) 986 #define EXTMEM_CORE0_DBUS_REJECT_INT_ENA_V 0x1 987 #define EXTMEM_CORE0_DBUS_REJECT_INT_ENA_S 4 988 /* EXTMEM_CORE0_DBUS_ACS_MSK_DC_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ 989 /*description: The bit is used to enable interrupt by cpu access dcache while the corresponding 990 dbus is disabled which include speculative access..*/ 991 #define EXTMEM_CORE0_DBUS_ACS_MSK_DC_INT_ENA (BIT(3)) 992 #define EXTMEM_CORE0_DBUS_ACS_MSK_DC_INT_ENA_M (BIT(3)) 993 #define EXTMEM_CORE0_DBUS_ACS_MSK_DC_INT_ENA_V 0x1 994 #define EXTMEM_CORE0_DBUS_ACS_MSK_DC_INT_ENA_S 3 995 /* EXTMEM_CORE0_IBUS_REJECT_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ 996 /*description: The bit is used to enable interrupt by authentication fail..*/ 997 #define EXTMEM_CORE0_IBUS_REJECT_INT_ENA (BIT(2)) 998 #define EXTMEM_CORE0_IBUS_REJECT_INT_ENA_M (BIT(2)) 999 #define EXTMEM_CORE0_IBUS_REJECT_INT_ENA_V 0x1 1000 #define EXTMEM_CORE0_IBUS_REJECT_INT_ENA_S 2 1001 /* EXTMEM_CORE0_IBUS_WR_IC_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ 1002 /*description: The bit is used to enable interrupt by ibus trying to write icache.*/ 1003 #define EXTMEM_CORE0_IBUS_WR_IC_INT_ENA (BIT(1)) 1004 #define EXTMEM_CORE0_IBUS_WR_IC_INT_ENA_M (BIT(1)) 1005 #define EXTMEM_CORE0_IBUS_WR_IC_INT_ENA_V 0x1 1006 #define EXTMEM_CORE0_IBUS_WR_IC_INT_ENA_S 1 1007 /* EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ 1008 /*description: The bit is used to enable interrupt by cpu access icache while the corresponding 1009 ibus is disabled which include speculative access..*/ 1010 #define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA (BIT(0)) 1011 #define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA_M (BIT(0)) 1012 #define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA_V 0x1 1013 #define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA_S 0 1014 1015 #define EXTMEM_CORE0_ACS_CACHE_INT_CLR_REG (DR_REG_EXTMEM_BASE + 0xEC) 1016 /* EXTMEM_CORE0_DBUS_REJECT_INT_CLR : WOD ;bitpos:[4] ;default: 1'b0 ; */ 1017 /*description: The bit is used to clear interrupt by authentication fail..*/ 1018 #define EXTMEM_CORE0_DBUS_REJECT_INT_CLR (BIT(4)) 1019 #define EXTMEM_CORE0_DBUS_REJECT_INT_CLR_M (BIT(4)) 1020 #define EXTMEM_CORE0_DBUS_REJECT_INT_CLR_V 0x1 1021 #define EXTMEM_CORE0_DBUS_REJECT_INT_CLR_S 4 1022 /* EXTMEM_CORE0_DBUS_ACS_MSK_DC_INT_CLR : WOD ;bitpos:[3] ;default: 1'b0 ; */ 1023 /*description: The bit is used to clear interrupt by cpu access dcache while the corresponding 1024 dbus is disabled or dcache is disabled which include speculative access..*/ 1025 #define EXTMEM_CORE0_DBUS_ACS_MSK_DC_INT_CLR (BIT(3)) 1026 #define EXTMEM_CORE0_DBUS_ACS_MSK_DC_INT_CLR_M (BIT(3)) 1027 #define EXTMEM_CORE0_DBUS_ACS_MSK_DC_INT_CLR_V 0x1 1028 #define EXTMEM_CORE0_DBUS_ACS_MSK_DC_INT_CLR_S 3 1029 /* EXTMEM_CORE0_IBUS_REJECT_INT_CLR : WOD ;bitpos:[2] ;default: 1'b0 ; */ 1030 /*description: The bit is used to clear interrupt by authentication fail..*/ 1031 #define EXTMEM_CORE0_IBUS_REJECT_INT_CLR (BIT(2)) 1032 #define EXTMEM_CORE0_IBUS_REJECT_INT_CLR_M (BIT(2)) 1033 #define EXTMEM_CORE0_IBUS_REJECT_INT_CLR_V 0x1 1034 #define EXTMEM_CORE0_IBUS_REJECT_INT_CLR_S 2 1035 /* EXTMEM_CORE0_IBUS_WR_IC_INT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */ 1036 /*description: The bit is used to clear interrupt by ibus trying to write icache.*/ 1037 #define EXTMEM_CORE0_IBUS_WR_IC_INT_CLR (BIT(1)) 1038 #define EXTMEM_CORE0_IBUS_WR_IC_INT_CLR_M (BIT(1)) 1039 #define EXTMEM_CORE0_IBUS_WR_IC_INT_CLR_V 0x1 1040 #define EXTMEM_CORE0_IBUS_WR_IC_INT_CLR_S 1 1041 /* EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR : WOD ;bitpos:[0] ;default: 1'b0 ; */ 1042 /*description: The bit is used to clear interrupt by cpu access icache while the corresponding 1043 ibus is disabled or icache is disabled which include speculative access..*/ 1044 #define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR (BIT(0)) 1045 #define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR_M (BIT(0)) 1046 #define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR_V 0x1 1047 #define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR_S 0 1048 1049 #define EXTMEM_CORE0_ACS_CACHE_INT_ST_REG (DR_REG_EXTMEM_BASE + 0xF0) 1050 /* EXTMEM_CORE0_DBUS_REJECT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ 1051 /*description: The bit is used to indicate interrupt by authentication fail..*/ 1052 #define EXTMEM_CORE0_DBUS_REJECT_ST (BIT(4)) 1053 #define EXTMEM_CORE0_DBUS_REJECT_ST_M (BIT(4)) 1054 #define EXTMEM_CORE0_DBUS_REJECT_ST_V 0x1 1055 #define EXTMEM_CORE0_DBUS_REJECT_ST_S 4 1056 /* EXTMEM_CORE0_DBUS_ACS_MSK_DCACHE_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ 1057 /*description: The bit is used to indicate interrupt by cpu access dcache while the core0_dbus 1058 is disabled or dcache is disabled which include speculative access..*/ 1059 #define EXTMEM_CORE0_DBUS_ACS_MSK_DCACHE_ST (BIT(3)) 1060 #define EXTMEM_CORE0_DBUS_ACS_MSK_DCACHE_ST_M (BIT(3)) 1061 #define EXTMEM_CORE0_DBUS_ACS_MSK_DCACHE_ST_V 0x1 1062 #define EXTMEM_CORE0_DBUS_ACS_MSK_DCACHE_ST_S 3 1063 /* EXTMEM_CORE0_IBUS_REJECT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ 1064 /*description: The bit is used to indicate interrupt by authentication fail..*/ 1065 #define EXTMEM_CORE0_IBUS_REJECT_ST (BIT(2)) 1066 #define EXTMEM_CORE0_IBUS_REJECT_ST_M (BIT(2)) 1067 #define EXTMEM_CORE0_IBUS_REJECT_ST_V 0x1 1068 #define EXTMEM_CORE0_IBUS_REJECT_ST_S 2 1069 /* EXTMEM_CORE0_IBUS_WR_ICACHE_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ 1070 /*description: The bit is used to indicate interrupt by ibus trying to write icache.*/ 1071 #define EXTMEM_CORE0_IBUS_WR_ICACHE_ST (BIT(1)) 1072 #define EXTMEM_CORE0_IBUS_WR_ICACHE_ST_M (BIT(1)) 1073 #define EXTMEM_CORE0_IBUS_WR_ICACHE_ST_V 0x1 1074 #define EXTMEM_CORE0_IBUS_WR_ICACHE_ST_S 1 1075 /* EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ 1076 /*description: The bit is used to indicate interrupt by cpu access icache while the core0_ibus 1077 is disabled or icache is disabled which include speculative access..*/ 1078 #define EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST (BIT(0)) 1079 #define EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST_M (BIT(0)) 1080 #define EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST_V 0x1 1081 #define EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST_S 0 1082 1083 #define EXTMEM_CORE1_ACS_CACHE_INT_ENA_REG (DR_REG_EXTMEM_BASE + 0xF4) 1084 /* EXTMEM_CORE1_DBUS_REJECT_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ 1085 /*description: The bit is used to enable interrupt by authentication fail..*/ 1086 #define EXTMEM_CORE1_DBUS_REJECT_INT_ENA (BIT(4)) 1087 #define EXTMEM_CORE1_DBUS_REJECT_INT_ENA_M (BIT(4)) 1088 #define EXTMEM_CORE1_DBUS_REJECT_INT_ENA_V 0x1 1089 #define EXTMEM_CORE1_DBUS_REJECT_INT_ENA_S 4 1090 /* EXTMEM_CORE1_DBUS_ACS_MSK_DC_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ 1091 /*description: The bit is used to enable interrupt by cpu access dcache while the corresponding 1092 dbus is disabled which include speculative access..*/ 1093 #define EXTMEM_CORE1_DBUS_ACS_MSK_DC_INT_ENA (BIT(3)) 1094 #define EXTMEM_CORE1_DBUS_ACS_MSK_DC_INT_ENA_M (BIT(3)) 1095 #define EXTMEM_CORE1_DBUS_ACS_MSK_DC_INT_ENA_V 0x1 1096 #define EXTMEM_CORE1_DBUS_ACS_MSK_DC_INT_ENA_S 3 1097 /* EXTMEM_CORE1_IBUS_REJECT_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ 1098 /*description: The bit is used to enable interrupt by authentication fail..*/ 1099 #define EXTMEM_CORE1_IBUS_REJECT_INT_ENA (BIT(2)) 1100 #define EXTMEM_CORE1_IBUS_REJECT_INT_ENA_M (BIT(2)) 1101 #define EXTMEM_CORE1_IBUS_REJECT_INT_ENA_V 0x1 1102 #define EXTMEM_CORE1_IBUS_REJECT_INT_ENA_S 2 1103 /* EXTMEM_CORE1_IBUS_WR_IC_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ 1104 /*description: The bit is used to enable interrupt by ibus trying to write icache.*/ 1105 #define EXTMEM_CORE1_IBUS_WR_IC_INT_ENA (BIT(1)) 1106 #define EXTMEM_CORE1_IBUS_WR_IC_INT_ENA_M (BIT(1)) 1107 #define EXTMEM_CORE1_IBUS_WR_IC_INT_ENA_V 0x1 1108 #define EXTMEM_CORE1_IBUS_WR_IC_INT_ENA_S 1 1109 /* EXTMEM_CORE1_IBUS_ACS_MSK_IC_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ 1110 /*description: The bit is used to enable interrupt by cpu access icache while the corresponding 1111 ibus is disabled which include speculative access..*/ 1112 #define EXTMEM_CORE1_IBUS_ACS_MSK_IC_INT_ENA (BIT(0)) 1113 #define EXTMEM_CORE1_IBUS_ACS_MSK_IC_INT_ENA_M (BIT(0)) 1114 #define EXTMEM_CORE1_IBUS_ACS_MSK_IC_INT_ENA_V 0x1 1115 #define EXTMEM_CORE1_IBUS_ACS_MSK_IC_INT_ENA_S 0 1116 1117 #define EXTMEM_CORE1_ACS_CACHE_INT_CLR_REG (DR_REG_EXTMEM_BASE + 0xF8) 1118 /* EXTMEM_CORE1_DBUS_REJECT_INT_CLR : WOD ;bitpos:[4] ;default: 1'b0 ; */ 1119 /*description: The bit is used to clear interrupt by authentication fail..*/ 1120 #define EXTMEM_CORE1_DBUS_REJECT_INT_CLR (BIT(4)) 1121 #define EXTMEM_CORE1_DBUS_REJECT_INT_CLR_M (BIT(4)) 1122 #define EXTMEM_CORE1_DBUS_REJECT_INT_CLR_V 0x1 1123 #define EXTMEM_CORE1_DBUS_REJECT_INT_CLR_S 4 1124 /* EXTMEM_CORE1_DBUS_ACS_MSK_DC_INT_CLR : WOD ;bitpos:[3] ;default: 1'b0 ; */ 1125 /*description: The bit is used to clear interrupt by cpu access dcache while the corresponding 1126 dbus is disabled or dcache is disabled which include speculative access..*/ 1127 #define EXTMEM_CORE1_DBUS_ACS_MSK_DC_INT_CLR (BIT(3)) 1128 #define EXTMEM_CORE1_DBUS_ACS_MSK_DC_INT_CLR_M (BIT(3)) 1129 #define EXTMEM_CORE1_DBUS_ACS_MSK_DC_INT_CLR_V 0x1 1130 #define EXTMEM_CORE1_DBUS_ACS_MSK_DC_INT_CLR_S 3 1131 /* EXTMEM_CORE1_IBUS_REJECT_INT_CLR : WOD ;bitpos:[2] ;default: 1'b0 ; */ 1132 /*description: The bit is used to clear interrupt by authentication fail..*/ 1133 #define EXTMEM_CORE1_IBUS_REJECT_INT_CLR (BIT(2)) 1134 #define EXTMEM_CORE1_IBUS_REJECT_INT_CLR_M (BIT(2)) 1135 #define EXTMEM_CORE1_IBUS_REJECT_INT_CLR_V 0x1 1136 #define EXTMEM_CORE1_IBUS_REJECT_INT_CLR_S 2 1137 /* EXTMEM_CORE1_IBUS_WR_IC_INT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */ 1138 /*description: The bit is used to clear interrupt by ibus trying to write icache.*/ 1139 #define EXTMEM_CORE1_IBUS_WR_IC_INT_CLR (BIT(1)) 1140 #define EXTMEM_CORE1_IBUS_WR_IC_INT_CLR_M (BIT(1)) 1141 #define EXTMEM_CORE1_IBUS_WR_IC_INT_CLR_V 0x1 1142 #define EXTMEM_CORE1_IBUS_WR_IC_INT_CLR_S 1 1143 /* EXTMEM_CORE1_IBUS_ACS_MSK_IC_INT_CLR : WOD ;bitpos:[0] ;default: 1'b0 ; */ 1144 /*description: The bit is used to clear interrupt by cpu access icache while the corresponding 1145 ibus is disabled or icache is disabled which include speculative access..*/ 1146 #define EXTMEM_CORE1_IBUS_ACS_MSK_IC_INT_CLR (BIT(0)) 1147 #define EXTMEM_CORE1_IBUS_ACS_MSK_IC_INT_CLR_M (BIT(0)) 1148 #define EXTMEM_CORE1_IBUS_ACS_MSK_IC_INT_CLR_V 0x1 1149 #define EXTMEM_CORE1_IBUS_ACS_MSK_IC_INT_CLR_S 0 1150 1151 #define EXTMEM_CORE1_ACS_CACHE_INT_ST_REG (DR_REG_EXTMEM_BASE + 0xFC) 1152 /* EXTMEM_CORE1_DBUS_REJECT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ 1153 /*description: The bit is used to indicate interrupt by authentication fail..*/ 1154 #define EXTMEM_CORE1_DBUS_REJECT_ST (BIT(4)) 1155 #define EXTMEM_CORE1_DBUS_REJECT_ST_M (BIT(4)) 1156 #define EXTMEM_CORE1_DBUS_REJECT_ST_V 0x1 1157 #define EXTMEM_CORE1_DBUS_REJECT_ST_S 4 1158 /* EXTMEM_CORE1_DBUS_ACS_MSK_DCACHE_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ 1159 /*description: The bit is used to indicate interrupt by cpu access dcache while the core1_dbus 1160 is disabled or dcache is disabled which include speculative access..*/ 1161 #define EXTMEM_CORE1_DBUS_ACS_MSK_DCACHE_ST (BIT(3)) 1162 #define EXTMEM_CORE1_DBUS_ACS_MSK_DCACHE_ST_M (BIT(3)) 1163 #define EXTMEM_CORE1_DBUS_ACS_MSK_DCACHE_ST_V 0x1 1164 #define EXTMEM_CORE1_DBUS_ACS_MSK_DCACHE_ST_S 3 1165 /* EXTMEM_CORE1_IBUS_REJECT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ 1166 /*description: The bit is used to indicate interrupt by authentication fail..*/ 1167 #define EXTMEM_CORE1_IBUS_REJECT_ST (BIT(2)) 1168 #define EXTMEM_CORE1_IBUS_REJECT_ST_M (BIT(2)) 1169 #define EXTMEM_CORE1_IBUS_REJECT_ST_V 0x1 1170 #define EXTMEM_CORE1_IBUS_REJECT_ST_S 2 1171 /* EXTMEM_CORE1_IBUS_WR_ICACHE_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ 1172 /*description: The bit is used to indicate interrupt by ibus trying to write icache.*/ 1173 #define EXTMEM_CORE1_IBUS_WR_ICACHE_ST (BIT(1)) 1174 #define EXTMEM_CORE1_IBUS_WR_ICACHE_ST_M (BIT(1)) 1175 #define EXTMEM_CORE1_IBUS_WR_ICACHE_ST_V 0x1 1176 #define EXTMEM_CORE1_IBUS_WR_ICACHE_ST_S 1 1177 /* EXTMEM_CORE1_IBUS_ACS_MSK_ICACHE_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ 1178 /*description: The bit is used to indicate interrupt by cpu access icache while the core1_ibus 1179 is disabled or icache is disabled which include speculative access..*/ 1180 #define EXTMEM_CORE1_IBUS_ACS_MSK_ICACHE_ST (BIT(0)) 1181 #define EXTMEM_CORE1_IBUS_ACS_MSK_ICACHE_ST_M (BIT(0)) 1182 #define EXTMEM_CORE1_IBUS_ACS_MSK_ICACHE_ST_V 0x1 1183 #define EXTMEM_CORE1_IBUS_ACS_MSK_ICACHE_ST_S 0 1184 1185 #define EXTMEM_CORE0_DBUS_REJECT_ST_REG (DR_REG_EXTMEM_BASE + 0x100) 1186 /* EXTMEM_CORE0_DBUS_WORLD : RO ;bitpos:[6] ;default: 1'b0 ; */ 1187 /*description: The bit is used to indicate the world of CPU access dbus when authentication fai 1188 l. 0: WORLD0, 1: WORLD1.*/ 1189 #define EXTMEM_CORE0_DBUS_WORLD (BIT(6)) 1190 #define EXTMEM_CORE0_DBUS_WORLD_M (BIT(6)) 1191 #define EXTMEM_CORE0_DBUS_WORLD_V 0x1 1192 #define EXTMEM_CORE0_DBUS_WORLD_S 6 1193 /* EXTMEM_CORE0_DBUS_ATTR : RO ;bitpos:[5:3] ;default: 3'b0 ; */ 1194 /*description: The bits are used to indicate the attribute of CPU access dbus when authenticati 1195 on fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able..*/ 1196 #define EXTMEM_CORE0_DBUS_ATTR 0x00000007 1197 #define EXTMEM_CORE0_DBUS_ATTR_M ((EXTMEM_CORE0_DBUS_ATTR_V)<<(EXTMEM_CORE0_DBUS_ATTR_S)) 1198 #define EXTMEM_CORE0_DBUS_ATTR_V 0x7 1199 #define EXTMEM_CORE0_DBUS_ATTR_S 3 1200 /* EXTMEM_CORE0_DBUS_TAG_ATTR : RO ;bitpos:[2:0] ;default: 3'b0 ; */ 1201 /*description: The bits are used to indicate the attribute of data from external memory when au 1202 thentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able..*/ 1203 #define EXTMEM_CORE0_DBUS_TAG_ATTR 0x00000007 1204 #define EXTMEM_CORE0_DBUS_TAG_ATTR_M ((EXTMEM_CORE0_DBUS_TAG_ATTR_V)<<(EXTMEM_CORE0_DBUS_TAG_ATTR_S)) 1205 #define EXTMEM_CORE0_DBUS_TAG_ATTR_V 0x7 1206 #define EXTMEM_CORE0_DBUS_TAG_ATTR_S 0 1207 1208 #define EXTMEM_CORE0_DBUS_REJECT_VADDR_REG (DR_REG_EXTMEM_BASE + 0x104) 1209 /* EXTMEM_CORE0_DBUS_VADDR : RO ;bitpos:[31:0] ;default: 32'hffffffff ; */ 1210 /*description: The bits are used to indicate the virtual address of CPU access dbus when authen 1211 tication fail..*/ 1212 #define EXTMEM_CORE0_DBUS_VADDR 0xFFFFFFFF 1213 #define EXTMEM_CORE0_DBUS_VADDR_M ((EXTMEM_CORE0_DBUS_VADDR_V)<<(EXTMEM_CORE0_DBUS_VADDR_S)) 1214 #define EXTMEM_CORE0_DBUS_VADDR_V 0xFFFFFFFF 1215 #define EXTMEM_CORE0_DBUS_VADDR_S 0 1216 1217 #define EXTMEM_CORE0_IBUS_REJECT_ST_REG (DR_REG_EXTMEM_BASE + 0x108) 1218 /* EXTMEM_CORE0_IBUS_WORLD : RO ;bitpos:[6] ;default: 1'b0 ; */ 1219 /*description: The bit is used to indicate the world of CPU access ibus when authentication fai 1220 l. 0: WORLD0, 1: WORLD1.*/ 1221 #define EXTMEM_CORE0_IBUS_WORLD (BIT(6)) 1222 #define EXTMEM_CORE0_IBUS_WORLD_M (BIT(6)) 1223 #define EXTMEM_CORE0_IBUS_WORLD_V 0x1 1224 #define EXTMEM_CORE0_IBUS_WORLD_S 6 1225 /* EXTMEM_CORE0_IBUS_ATTR : RO ;bitpos:[5:3] ;default: 3'b0 ; */ 1226 /*description: The bits are used to indicate the attribute of CPU access ibus when authenticati 1227 on fail. 0: invalidate, 1: execute-able, 2: read-able.*/ 1228 #define EXTMEM_CORE0_IBUS_ATTR 0x00000007 1229 #define EXTMEM_CORE0_IBUS_ATTR_M ((EXTMEM_CORE0_IBUS_ATTR_V)<<(EXTMEM_CORE0_IBUS_ATTR_S)) 1230 #define EXTMEM_CORE0_IBUS_ATTR_V 0x7 1231 #define EXTMEM_CORE0_IBUS_ATTR_S 3 1232 /* EXTMEM_CORE0_IBUS_TAG_ATTR : RO ;bitpos:[2:0] ;default: 3'b0 ; */ 1233 /*description: The bits are used to indicate the attribute of data from external memory when au 1234 thentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able..*/ 1235 #define EXTMEM_CORE0_IBUS_TAG_ATTR 0x00000007 1236 #define EXTMEM_CORE0_IBUS_TAG_ATTR_M ((EXTMEM_CORE0_IBUS_TAG_ATTR_V)<<(EXTMEM_CORE0_IBUS_TAG_ATTR_S)) 1237 #define EXTMEM_CORE0_IBUS_TAG_ATTR_V 0x7 1238 #define EXTMEM_CORE0_IBUS_TAG_ATTR_S 0 1239 1240 #define EXTMEM_CORE0_IBUS_REJECT_VADDR_REG (DR_REG_EXTMEM_BASE + 0x10C) 1241 /* EXTMEM_CORE0_IBUS_VADDR : RO ;bitpos:[31:0] ;default: 32'hffffffff ; */ 1242 /*description: The bits are used to indicate the virtual address of CPU access ibus when authe 1243 ntication fail..*/ 1244 #define EXTMEM_CORE0_IBUS_VADDR 0xFFFFFFFF 1245 #define EXTMEM_CORE0_IBUS_VADDR_M ((EXTMEM_CORE0_IBUS_VADDR_V)<<(EXTMEM_CORE0_IBUS_VADDR_S)) 1246 #define EXTMEM_CORE0_IBUS_VADDR_V 0xFFFFFFFF 1247 #define EXTMEM_CORE0_IBUS_VADDR_S 0 1248 1249 #define EXTMEM_CORE1_DBUS_REJECT_ST_REG (DR_REG_EXTMEM_BASE + 0x110) 1250 /* EXTMEM_CORE1_DBUS_WORLD : RO ;bitpos:[6] ;default: 1'b0 ; */ 1251 /*description: The bit is used to indicate the world of CPU access dbus when authentication fai 1252 l. 0: WORLD0, 1: WORLD1.*/ 1253 #define EXTMEM_CORE1_DBUS_WORLD (BIT(6)) 1254 #define EXTMEM_CORE1_DBUS_WORLD_M (BIT(6)) 1255 #define EXTMEM_CORE1_DBUS_WORLD_V 0x1 1256 #define EXTMEM_CORE1_DBUS_WORLD_S 6 1257 /* EXTMEM_CORE1_DBUS_ATTR : RO ;bitpos:[5:3] ;default: 3'b0 ; */ 1258 /*description: The bits are used to indicate the attribute of CPU access dbus when authenticati 1259 on fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able..*/ 1260 #define EXTMEM_CORE1_DBUS_ATTR 0x00000007 1261 #define EXTMEM_CORE1_DBUS_ATTR_M ((EXTMEM_CORE1_DBUS_ATTR_V)<<(EXTMEM_CORE1_DBUS_ATTR_S)) 1262 #define EXTMEM_CORE1_DBUS_ATTR_V 0x7 1263 #define EXTMEM_CORE1_DBUS_ATTR_S 3 1264 /* EXTMEM_CORE1_DBUS_TAG_ATTR : RO ;bitpos:[2:0] ;default: 3'b0 ; */ 1265 /*description: The bits are used to indicate the attribute of data from external memory when au 1266 thentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able..*/ 1267 #define EXTMEM_CORE1_DBUS_TAG_ATTR 0x00000007 1268 #define EXTMEM_CORE1_DBUS_TAG_ATTR_M ((EXTMEM_CORE1_DBUS_TAG_ATTR_V)<<(EXTMEM_CORE1_DBUS_TAG_ATTR_S)) 1269 #define EXTMEM_CORE1_DBUS_TAG_ATTR_V 0x7 1270 #define EXTMEM_CORE1_DBUS_TAG_ATTR_S 0 1271 1272 #define EXTMEM_CORE1_DBUS_REJECT_VADDR_REG (DR_REG_EXTMEM_BASE + 0x114) 1273 /* EXTMEM_CORE1_DBUS_VADDR : RO ;bitpos:[31:0] ;default: 32'hffffffff ; */ 1274 /*description: The bits are used to indicate the virtual address of CPU access dbus when authen 1275 tication fail..*/ 1276 #define EXTMEM_CORE1_DBUS_VADDR 0xFFFFFFFF 1277 #define EXTMEM_CORE1_DBUS_VADDR_M ((EXTMEM_CORE1_DBUS_VADDR_V)<<(EXTMEM_CORE1_DBUS_VADDR_S)) 1278 #define EXTMEM_CORE1_DBUS_VADDR_V 0xFFFFFFFF 1279 #define EXTMEM_CORE1_DBUS_VADDR_S 0 1280 1281 #define EXTMEM_CORE1_IBUS_REJECT_ST_REG (DR_REG_EXTMEM_BASE + 0x118) 1282 /* EXTMEM_CORE1_IBUS_WORLD : RO ;bitpos:[6] ;default: 1'b0 ; */ 1283 /*description: The bit is used to indicate the world of CPU access ibus when authentication fai 1284 l. 0: WORLD0, 1: WORLD1.*/ 1285 #define EXTMEM_CORE1_IBUS_WORLD (BIT(6)) 1286 #define EXTMEM_CORE1_IBUS_WORLD_M (BIT(6)) 1287 #define EXTMEM_CORE1_IBUS_WORLD_V 0x1 1288 #define EXTMEM_CORE1_IBUS_WORLD_S 6 1289 /* EXTMEM_CORE1_IBUS_ATTR : RO ;bitpos:[5:3] ;default: 3'b0 ; */ 1290 /*description: The bits are used to indicate the attribute of CPU access ibus when authenticati 1291 on fail. 0: invalidate, 1: execute-able, 2: read-able.*/ 1292 #define EXTMEM_CORE1_IBUS_ATTR 0x00000007 1293 #define EXTMEM_CORE1_IBUS_ATTR_M ((EXTMEM_CORE1_IBUS_ATTR_V)<<(EXTMEM_CORE1_IBUS_ATTR_S)) 1294 #define EXTMEM_CORE1_IBUS_ATTR_V 0x7 1295 #define EXTMEM_CORE1_IBUS_ATTR_S 3 1296 /* EXTMEM_CORE1_IBUS_TAG_ATTR : RO ;bitpos:[2:0] ;default: 3'b0 ; */ 1297 /*description: The bits are used to indicate the attribute of data from external memory when au 1298 thentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able..*/ 1299 #define EXTMEM_CORE1_IBUS_TAG_ATTR 0x00000007 1300 #define EXTMEM_CORE1_IBUS_TAG_ATTR_M ((EXTMEM_CORE1_IBUS_TAG_ATTR_V)<<(EXTMEM_CORE1_IBUS_TAG_ATTR_S)) 1301 #define EXTMEM_CORE1_IBUS_TAG_ATTR_V 0x7 1302 #define EXTMEM_CORE1_IBUS_TAG_ATTR_S 0 1303 1304 #define EXTMEM_CORE1_IBUS_REJECT_VADDR_REG (DR_REG_EXTMEM_BASE + 0x11C) 1305 /* EXTMEM_CORE1_IBUS_VADDR : RO ;bitpos:[31:0] ;default: 32'hffffffff ; */ 1306 /*description: The bits are used to indicate the virtual address of CPU access ibus when authe 1307 ntication fail..*/ 1308 #define EXTMEM_CORE1_IBUS_VADDR 0xFFFFFFFF 1309 #define EXTMEM_CORE1_IBUS_VADDR_M ((EXTMEM_CORE1_IBUS_VADDR_V)<<(EXTMEM_CORE1_IBUS_VADDR_S)) 1310 #define EXTMEM_CORE1_IBUS_VADDR_V 0xFFFFFFFF 1311 #define EXTMEM_CORE1_IBUS_VADDR_S 0 1312 1313 #define EXTMEM_CACHE_MMU_FAULT_CONTENT_REG (DR_REG_EXTMEM_BASE + 0x120) 1314 /* EXTMEM_CACHE_MMU_FAULT_CODE : RO ;bitpos:[19:16] ;default: 4'h0 ; */ 1315 /*description: The right-most 3 bits are used to indicate the operations which cause mmu fault 1316 occurrence. 0: default, 1: cpu miss, 2: preload miss, 3: writeback, 4: cpu miss 1317 evict recovery address, 5: load miss evict recovery address, 6: external dma tx, 1318 7: external dma rx. The most significant bit is used to indicate this operation 1319 occurs in which one icache. .*/ 1320 #define EXTMEM_CACHE_MMU_FAULT_CODE 0x0000000F 1321 #define EXTMEM_CACHE_MMU_FAULT_CODE_M ((EXTMEM_CACHE_MMU_FAULT_CODE_V)<<(EXTMEM_CACHE_MMU_FAULT_CODE_S)) 1322 #define EXTMEM_CACHE_MMU_FAULT_CODE_V 0xF 1323 #define EXTMEM_CACHE_MMU_FAULT_CODE_S 16 1324 /* EXTMEM_CACHE_MMU_FAULT_CONTENT : RO ;bitpos:[15:0] ;default: 17'h0 ; */ 1325 /*description: The bits are used to indicate the content of mmu entry which cause mmu fault...*/ 1326 #define EXTMEM_CACHE_MMU_FAULT_CONTENT 0x0000FFFF 1327 #define EXTMEM_CACHE_MMU_FAULT_CONTENT_M ((EXTMEM_CACHE_MMU_FAULT_CONTENT_V)<<(EXTMEM_CACHE_MMU_FAULT_CONTENT_S)) 1328 #define EXTMEM_CACHE_MMU_FAULT_CONTENT_V 0xFFFF 1329 #define EXTMEM_CACHE_MMU_FAULT_CONTENT_S 0 1330 1331 #define EXTMEM_CACHE_MMU_FAULT_VADDR_REG (DR_REG_EXTMEM_BASE + 0x124) 1332 /* EXTMEM_CACHE_MMU_FAULT_VADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 1333 /*description: The bits are used to indicate the virtual address which cause mmu fault...*/ 1334 #define EXTMEM_CACHE_MMU_FAULT_VADDR 0xFFFFFFFF 1335 #define EXTMEM_CACHE_MMU_FAULT_VADDR_M ((EXTMEM_CACHE_MMU_FAULT_VADDR_V)<<(EXTMEM_CACHE_MMU_FAULT_VADDR_S)) 1336 #define EXTMEM_CACHE_MMU_FAULT_VADDR_V 0xFFFFFFFF 1337 #define EXTMEM_CACHE_MMU_FAULT_VADDR_S 0 1338 1339 #define EXTMEM_CACHE_WRAP_AROUND_CTRL_REG (DR_REG_EXTMEM_BASE + 0x128) 1340 /* EXTMEM_CACHE_SRAM_RD_WRAP_AROUND : R/W ;bitpos:[1] ;default: 1'b0 ; */ 1341 /*description: The bit is used to enable wrap around mode when read data from spiram..*/ 1342 #define EXTMEM_CACHE_SRAM_RD_WRAP_AROUND (BIT(1)) 1343 #define EXTMEM_CACHE_SRAM_RD_WRAP_AROUND_M (BIT(1)) 1344 #define EXTMEM_CACHE_SRAM_RD_WRAP_AROUND_V 0x1 1345 #define EXTMEM_CACHE_SRAM_RD_WRAP_AROUND_S 1 1346 /* EXTMEM_CACHE_FLASH_WRAP_AROUND : R/W ;bitpos:[0] ;default: 1'b0 ; */ 1347 /*description: The bit is used to enable wrap around mode when read data from flash..*/ 1348 #define EXTMEM_CACHE_FLASH_WRAP_AROUND (BIT(0)) 1349 #define EXTMEM_CACHE_FLASH_WRAP_AROUND_M (BIT(0)) 1350 #define EXTMEM_CACHE_FLASH_WRAP_AROUND_V 0x1 1351 #define EXTMEM_CACHE_FLASH_WRAP_AROUND_S 0 1352 1353 #define EXTMEM_CACHE_MMU_POWER_CTRL_REG (DR_REG_EXTMEM_BASE + 0x12C) 1354 /* EXTMEM_CACHE_MMU_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */ 1355 /*description: The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power up.*/ 1356 #define EXTMEM_CACHE_MMU_MEM_FORCE_PU (BIT(2)) 1357 #define EXTMEM_CACHE_MMU_MEM_FORCE_PU_M (BIT(2)) 1358 #define EXTMEM_CACHE_MMU_MEM_FORCE_PU_V 0x1 1359 #define EXTMEM_CACHE_MMU_MEM_FORCE_PU_S 2 1360 /* EXTMEM_CACHE_MMU_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */ 1361 /*description: The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power down.*/ 1362 #define EXTMEM_CACHE_MMU_MEM_FORCE_PD (BIT(1)) 1363 #define EXTMEM_CACHE_MMU_MEM_FORCE_PD_M (BIT(1)) 1364 #define EXTMEM_CACHE_MMU_MEM_FORCE_PD_V 0x1 1365 #define EXTMEM_CACHE_MMU_MEM_FORCE_PD_S 1 1366 /* EXTMEM_CACHE_MMU_MEM_FORCE_ON : R/W ;bitpos:[0] ;default: 1'b1 ; */ 1367 /*description: The bit is used to enable clock gating to save power when access mmu memory, 0: 1368 enable, 1: disable.*/ 1369 #define EXTMEM_CACHE_MMU_MEM_FORCE_ON (BIT(0)) 1370 #define EXTMEM_CACHE_MMU_MEM_FORCE_ON_M (BIT(0)) 1371 #define EXTMEM_CACHE_MMU_MEM_FORCE_ON_V 0x1 1372 #define EXTMEM_CACHE_MMU_MEM_FORCE_ON_S 0 1373 1374 #define EXTMEM_CACHE_STATE_REG (DR_REG_EXTMEM_BASE + 0x130) 1375 /* EXTMEM_DCACHE_STATE : RO ;bitpos:[23:12] ;default: 12'h001 ; */ 1376 /*description: The bit is used to indicate whether dcache main fsm is in idle state or not. 1: 1377 in idle state, 0: not in idle state.*/ 1378 #define EXTMEM_DCACHE_STATE 0x00000FFF 1379 #define EXTMEM_DCACHE_STATE_M ((EXTMEM_DCACHE_STATE_V)<<(EXTMEM_DCACHE_STATE_S)) 1380 #define EXTMEM_DCACHE_STATE_V 0xFFF 1381 #define EXTMEM_DCACHE_STATE_S 12 1382 /* EXTMEM_ICACHE_STATE : RO ;bitpos:[11:0] ;default: 12'h001 ; */ 1383 /*description: The bit is used to indicate whether icache main fsm is in idle state or not. 1: 1384 in idle state, 0: not in idle state.*/ 1385 #define EXTMEM_ICACHE_STATE 0x00000FFF 1386 #define EXTMEM_ICACHE_STATE_M ((EXTMEM_ICACHE_STATE_V)<<(EXTMEM_ICACHE_STATE_S)) 1387 #define EXTMEM_ICACHE_STATE_V 0xFFF 1388 #define EXTMEM_ICACHE_STATE_S 0 1389 1390 #define EXTMEM_CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE_REG (DR_REG_EXTMEM_BASE + 0x134) 1391 /* EXTMEM_RECORD_DISABLE_G0CB_DECRYPT : R/W ;bitpos:[1] ;default: 1'b0 ; */ 1392 /*description: Reserved..*/ 1393 #define EXTMEM_RECORD_DISABLE_G0CB_DECRYPT (BIT(1)) 1394 #define EXTMEM_RECORD_DISABLE_G0CB_DECRYPT_M (BIT(1)) 1395 #define EXTMEM_RECORD_DISABLE_G0CB_DECRYPT_V 0x1 1396 #define EXTMEM_RECORD_DISABLE_G0CB_DECRYPT_S 1 1397 /* EXTMEM_RECORD_DISABLE_DB_ENCRYPT : R/W ;bitpos:[0] ;default: 1'b0 ; */ 1398 /*description: Reserved..*/ 1399 #define EXTMEM_RECORD_DISABLE_DB_ENCRYPT (BIT(0)) 1400 #define EXTMEM_RECORD_DISABLE_DB_ENCRYPT_M (BIT(0)) 1401 #define EXTMEM_RECORD_DISABLE_DB_ENCRYPT_V 0x1 1402 #define EXTMEM_RECORD_DISABLE_DB_ENCRYPT_S 0 1403 1404 #define EXTMEM_CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON_REG (DR_REG_EXTMEM_BASE + 0x138) 1405 /* EXTMEM_CLK_FORCE_ON_CRYPT : R/W ;bitpos:[2] ;default: 1'b1 ; */ 1406 /*description: The bit is used to close clock gating of external memory encrypt and decrypt clo 1407 ck. 1: close gating, 0: open clock gating..*/ 1408 #define EXTMEM_CLK_FORCE_ON_CRYPT (BIT(2)) 1409 #define EXTMEM_CLK_FORCE_ON_CRYPT_M (BIT(2)) 1410 #define EXTMEM_CLK_FORCE_ON_CRYPT_V 0x1 1411 #define EXTMEM_CLK_FORCE_ON_CRYPT_S 2 1412 /* EXTMEM_CLK_FORCE_ON_AUTO_CRYPT : R/W ;bitpos:[1] ;default: 1'b1 ; */ 1413 /*description: The bit is used to close clock gating of automatic crypt clock. 1: close gating, 1414 0: open clock gating..*/ 1415 #define EXTMEM_CLK_FORCE_ON_AUTO_CRYPT (BIT(1)) 1416 #define EXTMEM_CLK_FORCE_ON_AUTO_CRYPT_M (BIT(1)) 1417 #define EXTMEM_CLK_FORCE_ON_AUTO_CRYPT_V 0x1 1418 #define EXTMEM_CLK_FORCE_ON_AUTO_CRYPT_S 1 1419 /* EXTMEM_CLK_FORCE_ON_MANUAL_CRYPT : R/W ;bitpos:[0] ;default: 1'b1 ; */ 1420 /*description: The bit is used to close clock gating of manual crypt clock. 1: close gating, 0: 1421 open clock gating..*/ 1422 #define EXTMEM_CLK_FORCE_ON_MANUAL_CRYPT (BIT(0)) 1423 #define EXTMEM_CLK_FORCE_ON_MANUAL_CRYPT_M (BIT(0)) 1424 #define EXTMEM_CLK_FORCE_ON_MANUAL_CRYPT_V 0x1 1425 #define EXTMEM_CLK_FORCE_ON_MANUAL_CRYPT_S 0 1426 1427 #define EXTMEM_CACHE_BRIDGE_ARBITER_CTRL_REG (DR_REG_EXTMEM_BASE + 0x13C) 1428 /* EXTMEM_ALLOC_WB_HOLD_ARBITER : R/W ;bitpos:[0] ;default: 1'b0 ; */ 1429 /*description: Reserved..*/ 1430 #define EXTMEM_ALLOC_WB_HOLD_ARBITER (BIT(0)) 1431 #define EXTMEM_ALLOC_WB_HOLD_ARBITER_M (BIT(0)) 1432 #define EXTMEM_ALLOC_WB_HOLD_ARBITER_V 0x1 1433 #define EXTMEM_ALLOC_WB_HOLD_ARBITER_S 0 1434 1435 #define EXTMEM_CACHE_PRELOAD_INT_CTRL_REG (DR_REG_EXTMEM_BASE + 0x140) 1436 /* EXTMEM_DCACHE_PRELOAD_INT_CLR : WOD ;bitpos:[5] ;default: 1'b0 ; */ 1437 /*description: The bit is used to clear the interrupt by dcache pre-load done..*/ 1438 #define EXTMEM_DCACHE_PRELOAD_INT_CLR (BIT(5)) 1439 #define EXTMEM_DCACHE_PRELOAD_INT_CLR_M (BIT(5)) 1440 #define EXTMEM_DCACHE_PRELOAD_INT_CLR_V 0x1 1441 #define EXTMEM_DCACHE_PRELOAD_INT_CLR_S 5 1442 /* EXTMEM_DCACHE_PRELOAD_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ 1443 /*description: The bit is used to enable the interrupt by dcache pre-load done..*/ 1444 #define EXTMEM_DCACHE_PRELOAD_INT_ENA (BIT(4)) 1445 #define EXTMEM_DCACHE_PRELOAD_INT_ENA_M (BIT(4)) 1446 #define EXTMEM_DCACHE_PRELOAD_INT_ENA_V 0x1 1447 #define EXTMEM_DCACHE_PRELOAD_INT_ENA_S 4 1448 /* EXTMEM_DCACHE_PRELOAD_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ 1449 /*description: The bit is used to indicate the interrupt by dcache pre-load done..*/ 1450 #define EXTMEM_DCACHE_PRELOAD_INT_ST (BIT(3)) 1451 #define EXTMEM_DCACHE_PRELOAD_INT_ST_M (BIT(3)) 1452 #define EXTMEM_DCACHE_PRELOAD_INT_ST_V 0x1 1453 #define EXTMEM_DCACHE_PRELOAD_INT_ST_S 3 1454 /* EXTMEM_ICACHE_PRELOAD_INT_CLR : WOD ;bitpos:[2] ;default: 1'b0 ; */ 1455 /*description: The bit is used to clear the interrupt by icache pre-load done..*/ 1456 #define EXTMEM_ICACHE_PRELOAD_INT_CLR (BIT(2)) 1457 #define EXTMEM_ICACHE_PRELOAD_INT_CLR_M (BIT(2)) 1458 #define EXTMEM_ICACHE_PRELOAD_INT_CLR_V 0x1 1459 #define EXTMEM_ICACHE_PRELOAD_INT_CLR_S 2 1460 /* EXTMEM_ICACHE_PRELOAD_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ 1461 /*description: The bit is used to enable the interrupt by icache pre-load done..*/ 1462 #define EXTMEM_ICACHE_PRELOAD_INT_ENA (BIT(1)) 1463 #define EXTMEM_ICACHE_PRELOAD_INT_ENA_M (BIT(1)) 1464 #define EXTMEM_ICACHE_PRELOAD_INT_ENA_V 0x1 1465 #define EXTMEM_ICACHE_PRELOAD_INT_ENA_S 1 1466 /* EXTMEM_ICACHE_PRELOAD_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ 1467 /*description: The bit is used to indicate the interrupt by icache pre-load done..*/ 1468 #define EXTMEM_ICACHE_PRELOAD_INT_ST (BIT(0)) 1469 #define EXTMEM_ICACHE_PRELOAD_INT_ST_M (BIT(0)) 1470 #define EXTMEM_ICACHE_PRELOAD_INT_ST_V 0x1 1471 #define EXTMEM_ICACHE_PRELOAD_INT_ST_S 0 1472 1473 #define EXTMEM_CACHE_SYNC_INT_CTRL_REG (DR_REG_EXTMEM_BASE + 0x144) 1474 /* EXTMEM_DCACHE_SYNC_INT_CLR : WOD ;bitpos:[5] ;default: 1'b0 ; */ 1475 /*description: The bit is used to clear the interrupt by dcache sync done..*/ 1476 #define EXTMEM_DCACHE_SYNC_INT_CLR (BIT(5)) 1477 #define EXTMEM_DCACHE_SYNC_INT_CLR_M (BIT(5)) 1478 #define EXTMEM_DCACHE_SYNC_INT_CLR_V 0x1 1479 #define EXTMEM_DCACHE_SYNC_INT_CLR_S 5 1480 /* EXTMEM_DCACHE_SYNC_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ 1481 /*description: The bit is used to enable the interrupt by dcache sync done..*/ 1482 #define EXTMEM_DCACHE_SYNC_INT_ENA (BIT(4)) 1483 #define EXTMEM_DCACHE_SYNC_INT_ENA_M (BIT(4)) 1484 #define EXTMEM_DCACHE_SYNC_INT_ENA_V 0x1 1485 #define EXTMEM_DCACHE_SYNC_INT_ENA_S 4 1486 /* EXTMEM_DCACHE_SYNC_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ 1487 /*description: The bit is used to indicate the interrupt by dcache sync done..*/ 1488 #define EXTMEM_DCACHE_SYNC_INT_ST (BIT(3)) 1489 #define EXTMEM_DCACHE_SYNC_INT_ST_M (BIT(3)) 1490 #define EXTMEM_DCACHE_SYNC_INT_ST_V 0x1 1491 #define EXTMEM_DCACHE_SYNC_INT_ST_S 3 1492 /* EXTMEM_ICACHE_SYNC_INT_CLR : WOD ;bitpos:[2] ;default: 1'b0 ; */ 1493 /*description: The bit is used to clear the interrupt by icache sync done..*/ 1494 #define EXTMEM_ICACHE_SYNC_INT_CLR (BIT(2)) 1495 #define EXTMEM_ICACHE_SYNC_INT_CLR_M (BIT(2)) 1496 #define EXTMEM_ICACHE_SYNC_INT_CLR_V 0x1 1497 #define EXTMEM_ICACHE_SYNC_INT_CLR_S 2 1498 /* EXTMEM_ICACHE_SYNC_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ 1499 /*description: The bit is used to enable the interrupt by icache sync done..*/ 1500 #define EXTMEM_ICACHE_SYNC_INT_ENA (BIT(1)) 1501 #define EXTMEM_ICACHE_SYNC_INT_ENA_M (BIT(1)) 1502 #define EXTMEM_ICACHE_SYNC_INT_ENA_V 0x1 1503 #define EXTMEM_ICACHE_SYNC_INT_ENA_S 1 1504 /* EXTMEM_ICACHE_SYNC_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ 1505 /*description: The bit is used to indicate the interrupt by icache sync done..*/ 1506 #define EXTMEM_ICACHE_SYNC_INT_ST (BIT(0)) 1507 #define EXTMEM_ICACHE_SYNC_INT_ST_M (BIT(0)) 1508 #define EXTMEM_ICACHE_SYNC_INT_ST_V 0x1 1509 #define EXTMEM_ICACHE_SYNC_INT_ST_S 0 1510 1511 #define EXTMEM_CACHE_MMU_OWNER_REG (DR_REG_EXTMEM_BASE + 0x148) 1512 /* EXTMEM_CACHE_MMU_OWNER : R/W ;bitpos:[23:0] ;default: 24'h0 ; */ 1513 /*description: The bits are used to specify the owner of MMU.bit0: icache, bit1: dcache, bit2: 1514 dma, bit3: reserved..*/ 1515 #define EXTMEM_CACHE_MMU_OWNER 0x00FFFFFF 1516 #define EXTMEM_CACHE_MMU_OWNER_M ((EXTMEM_CACHE_MMU_OWNER_V)<<(EXTMEM_CACHE_MMU_OWNER_S)) 1517 #define EXTMEM_CACHE_MMU_OWNER_V 0xFFFFFF 1518 #define EXTMEM_CACHE_MMU_OWNER_S 0 1519 1520 #define EXTMEM_CACHE_CONF_MISC_REG (DR_REG_EXTMEM_BASE + 0x14C) 1521 /* EXTMEM_CACHE_TRACE_ENA : R/W ;bitpos:[2] ;default: 1'b1 ; */ 1522 /*description: The bit is used to enable cache trace function..*/ 1523 #define EXTMEM_CACHE_TRACE_ENA (BIT(2)) 1524 #define EXTMEM_CACHE_TRACE_ENA_M (BIT(2)) 1525 #define EXTMEM_CACHE_TRACE_ENA_V 0x1 1526 #define EXTMEM_CACHE_TRACE_ENA_S 2 1527 /* EXTMEM_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT : R/W ;bitpos:[1] ;default: 1'b1 ; */ 1528 /*description: The bit is used to disable checking mmu entry fault by sync operation..*/ 1529 #define EXTMEM_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT (BIT(1)) 1530 #define EXTMEM_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT_M (BIT(1)) 1531 #define EXTMEM_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT_V 0x1 1532 #define EXTMEM_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT_S 1 1533 /* EXTMEM_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT : R/W ;bitpos:[0] ;default: 1'b1 ; */ 1534 /*description: The bit is used to disable checking mmu entry fault by preload operation..*/ 1535 #define EXTMEM_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT (BIT(0)) 1536 #define EXTMEM_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT_M (BIT(0)) 1537 #define EXTMEM_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT_V 0x1 1538 #define EXTMEM_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT_S 0 1539 1540 #define EXTMEM_DCACHE_FREEZE_REG (DR_REG_EXTMEM_BASE + 0x150) 1541 /* EXTMEM_DCACHE_FREEZE_DONE : RO ;bitpos:[2] ;default: 1'b1 ; */ 1542 /*description: The bit is used to indicate dcache freeze success.*/ 1543 #define EXTMEM_DCACHE_FREEZE_DONE (BIT(2)) 1544 #define EXTMEM_DCACHE_FREEZE_DONE_M (BIT(2)) 1545 #define EXTMEM_DCACHE_FREEZE_DONE_V 0x1 1546 #define EXTMEM_DCACHE_FREEZE_DONE_S 2 1547 /* EXTMEM_DCACHE_FREEZE_MODE : R/W ;bitpos:[1] ;default: 1'b0 ; */ 1548 /*description: The bit is used to configure freeze mode, 0: assert busy if CPU miss 1: assert 1549 hit if CPU miss.*/ 1550 #define EXTMEM_DCACHE_FREEZE_MODE (BIT(1)) 1551 #define EXTMEM_DCACHE_FREEZE_MODE_M (BIT(1)) 1552 #define EXTMEM_DCACHE_FREEZE_MODE_V 0x1 1553 #define EXTMEM_DCACHE_FREEZE_MODE_S 1 1554 /* EXTMEM_DCACHE_FREEZE_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ 1555 /*description: The bit is used to enable dcache freeze mode.*/ 1556 #define EXTMEM_DCACHE_FREEZE_ENA (BIT(0)) 1557 #define EXTMEM_DCACHE_FREEZE_ENA_M (BIT(0)) 1558 #define EXTMEM_DCACHE_FREEZE_ENA_V 0x1 1559 #define EXTMEM_DCACHE_FREEZE_ENA_S 0 1560 1561 #define EXTMEM_ICACHE_FREEZE_REG (DR_REG_EXTMEM_BASE + 0x154) 1562 /* EXTMEM_ICACHE_FREEZE_DONE : RO ;bitpos:[2] ;default: 1'b1 ; */ 1563 /*description: The bit is used to indicate icache freeze success.*/ 1564 #define EXTMEM_ICACHE_FREEZE_DONE (BIT(2)) 1565 #define EXTMEM_ICACHE_FREEZE_DONE_M (BIT(2)) 1566 #define EXTMEM_ICACHE_FREEZE_DONE_V 0x1 1567 #define EXTMEM_ICACHE_FREEZE_DONE_S 2 1568 /* EXTMEM_ICACHE_FREEZE_MODE : R/W ;bitpos:[1] ;default: 1'b0 ; */ 1569 /*description: The bit is used to configure freeze mode, 0: assert busy if CPU miss 1: assert 1570 hit if CPU miss.*/ 1571 #define EXTMEM_ICACHE_FREEZE_MODE (BIT(1)) 1572 #define EXTMEM_ICACHE_FREEZE_MODE_M (BIT(1)) 1573 #define EXTMEM_ICACHE_FREEZE_MODE_V 0x1 1574 #define EXTMEM_ICACHE_FREEZE_MODE_S 1 1575 /* EXTMEM_ICACHE_FREEZE_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ 1576 /*description: The bit is used to enable icache freeze mode.*/ 1577 #define EXTMEM_ICACHE_FREEZE_ENA (BIT(0)) 1578 #define EXTMEM_ICACHE_FREEZE_ENA_M (BIT(0)) 1579 #define EXTMEM_ICACHE_FREEZE_ENA_V 0x1 1580 #define EXTMEM_ICACHE_FREEZE_ENA_S 0 1581 1582 #define EXTMEM_ICACHE_ATOMIC_OPERATE_ENA_REG (DR_REG_EXTMEM_BASE + 0x158) 1583 /* EXTMEM_ICACHE_ATOMIC_OPERATE_ENA : R/W ;bitpos:[0] ;default: 1'b1 ; */ 1584 /*description: The bit is used to activate icache atomic operation protection. In this case, sy 1585 nc/lock operation can not interrupt miss-work. This feature does not work during 1586 invalidateAll operation..*/ 1587 #define EXTMEM_ICACHE_ATOMIC_OPERATE_ENA (BIT(0)) 1588 #define EXTMEM_ICACHE_ATOMIC_OPERATE_ENA_M (BIT(0)) 1589 #define EXTMEM_ICACHE_ATOMIC_OPERATE_ENA_V 0x1 1590 #define EXTMEM_ICACHE_ATOMIC_OPERATE_ENA_S 0 1591 1592 #define EXTMEM_DCACHE_ATOMIC_OPERATE_ENA_REG (DR_REG_EXTMEM_BASE + 0x15C) 1593 /* EXTMEM_DCACHE_ATOMIC_OPERATE_ENA : R/W ;bitpos:[0] ;default: 1'b1 ; */ 1594 /*description: The bit is used to activate dcache atomic operation protection. In this case, sy 1595 nc/lock/occupy operation can not interrupt miss-work. This feature does not work 1596 during invalidateAll operation..*/ 1597 #define EXTMEM_DCACHE_ATOMIC_OPERATE_ENA (BIT(0)) 1598 #define EXTMEM_DCACHE_ATOMIC_OPERATE_ENA_M (BIT(0)) 1599 #define EXTMEM_DCACHE_ATOMIC_OPERATE_ENA_V 0x1 1600 #define EXTMEM_DCACHE_ATOMIC_OPERATE_ENA_S 0 1601 1602 #define EXTMEM_CACHE_REQUEST_REG (DR_REG_EXTMEM_BASE + 0x160) 1603 /* EXTMEM_CACHE_REQUEST_BYPASS : R/W ;bitpos:[0] ;default: 1'b0 ; */ 1604 /*description: The bit is used to disable request recording which could cause performance issue.*/ 1605 #define EXTMEM_CACHE_REQUEST_BYPASS (BIT(0)) 1606 #define EXTMEM_CACHE_REQUEST_BYPASS_M (BIT(0)) 1607 #define EXTMEM_CACHE_REQUEST_BYPASS_V 0x1 1608 #define EXTMEM_CACHE_REQUEST_BYPASS_S 0 1609 1610 #define EXTMEM_CLOCK_GATE_REG (DR_REG_EXTMEM_BASE + 0x164) 1611 /* EXTMEM_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ 1612 /*description: Reserved..*/ 1613 #define EXTMEM_CLK_EN (BIT(0)) 1614 #define EXTMEM_CLK_EN_M (BIT(0)) 1615 #define EXTMEM_CLK_EN_V 0x1 1616 #define EXTMEM_CLK_EN_S 0 1617 1618 #define EXTMEM_CACHE_TAG_OBJECT_CTRL_REG (DR_REG_EXTMEM_BASE + 0x180) 1619 /* EXTMEM_DCACHE_TAG_OBJECT : R/W ;bitpos:[1] ;default: 1'b0 ; */ 1620 /*description: Set this bit to set dcache tag memory as object. This bit should be onehot with 1621 the others fields inside this register..*/ 1622 #define EXTMEM_DCACHE_TAG_OBJECT (BIT(1)) 1623 #define EXTMEM_DCACHE_TAG_OBJECT_M (BIT(1)) 1624 #define EXTMEM_DCACHE_TAG_OBJECT_V 0x1 1625 #define EXTMEM_DCACHE_TAG_OBJECT_S 1 1626 /* EXTMEM_ICACHE_TAG_OBJECT : R/W ;bitpos:[0] ;default: 1'b0 ; */ 1627 /*description: Set this bit to set icache tag memory as object. This bit should be onehot with 1628 the others fields inside this register..*/ 1629 #define EXTMEM_ICACHE_TAG_OBJECT (BIT(0)) 1630 #define EXTMEM_ICACHE_TAG_OBJECT_M (BIT(0)) 1631 #define EXTMEM_ICACHE_TAG_OBJECT_V 0x1 1632 #define EXTMEM_ICACHE_TAG_OBJECT_S 0 1633 1634 #define EXTMEM_CACHE_TAG_WAY_OBJECT_REG (DR_REG_EXTMEM_BASE + 0x184) 1635 /* EXTMEM_CACHE_TAG_WAY_OBJECT : R/W ;bitpos:[2:0] ;default: 3'h0 ; */ 1636 /*description: Set this bits to select which way of the tag-object will be accessed. 0: way0, 1 1637 : way1, 2: way2, 3: way3, .., 7: way7..*/ 1638 #define EXTMEM_CACHE_TAG_WAY_OBJECT 0x00000007 1639 #define EXTMEM_CACHE_TAG_WAY_OBJECT_M ((EXTMEM_CACHE_TAG_WAY_OBJECT_V)<<(EXTMEM_CACHE_TAG_WAY_OBJECT_S)) 1640 #define EXTMEM_CACHE_TAG_WAY_OBJECT_V 0x7 1641 #define EXTMEM_CACHE_TAG_WAY_OBJECT_S 0 1642 1643 #define EXTMEM_CACHE_VADDR_REG (DR_REG_EXTMEM_BASE + 0x188) 1644 /* EXTMEM_CACHE_VADDR : R/W ;bitpos:[31:0] ;default: 32'h00000000 ; */ 1645 /*description: Those bits stores the virtual address which will decide where inside the specifi 1646 ed tag memory object will be accessed..*/ 1647 #define EXTMEM_CACHE_VADDR 0xFFFFFFFF 1648 #define EXTMEM_CACHE_VADDR_M ((EXTMEM_CACHE_VADDR_V)<<(EXTMEM_CACHE_VADDR_S)) 1649 #define EXTMEM_CACHE_VADDR_V 0xFFFFFFFF 1650 #define EXTMEM_CACHE_VADDR_S 0 1651 1652 #define EXTMEM_CACHE_TAG_CONTENT_REG (DR_REG_EXTMEM_BASE + 0x18C) 1653 /* EXTMEM_CACHE_TAG_CONTENT : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 1654 /*description: This is a constant place where we can write data to or read data from the tag me 1655 mory on the specified cache..*/ 1656 #define EXTMEM_CACHE_TAG_CONTENT 0xFFFFFFFF 1657 #define EXTMEM_CACHE_TAG_CONTENT_M ((EXTMEM_CACHE_TAG_CONTENT_V)<<(EXTMEM_CACHE_TAG_CONTENT_S)) 1658 #define EXTMEM_CACHE_TAG_CONTENT_V 0xFFFFFFFF 1659 #define EXTMEM_CACHE_TAG_CONTENT_S 0 1660 1661 #define EXTMEM_DATE_REG (DR_REG_EXTMEM_BASE + 0x3FC) 1662 /* EXTMEM_DATE : R/W ;bitpos:[27:0] ;default: 28'h2012310 ; */ 1663 /*description: version information..*/ 1664 #define EXTMEM_DATE 0x0FFFFFFF 1665 #define EXTMEM_DATE_M ((EXTMEM_DATE_V)<<(EXTMEM_DATE_S)) 1666 #define EXTMEM_DATE_V 0xFFFFFFF 1667 #define EXTMEM_DATE_S 0 1668 1669 1670 #ifdef __cplusplus 1671 } 1672 #endif 1673 1674 1675 1676 #endif /*_SOC_EXTMEM_REG_H_ */ 1677
