1 /* 2 * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #ifndef _SOC_EFUSE_REG_H_ 7 #define _SOC_EFUSE_REG_H_ 8 9 10 #include "soc.h" 11 #define EFUSE_BLK0_RDATA0_REG (DR_REG_EFUSE_BASE + 0x000) 12 /* EFUSE_RD_FLASH_CRYPT_CNT : RO ;bitpos:[26:20] ;default: 7'b0 ; */ 13 /*description: read for flash_crypt_cnt*/ 14 #define EFUSE_RD_FLASH_CRYPT_CNT 0x0000007F 15 #define EFUSE_RD_FLASH_CRYPT_CNT_M ((EFUSE_RD_FLASH_CRYPT_CNT_V)<<(EFUSE_RD_FLASH_CRYPT_CNT_S)) 16 #define EFUSE_RD_FLASH_CRYPT_CNT_V 0x7F 17 #define EFUSE_RD_FLASH_CRYPT_CNT_S 20 18 /* EFUSE_RD_EFUSE_RD_DIS : RO ;bitpos:[19:16] ;default: 4'b0 ; */ 19 /*description: read for efuse_rd_disable*/ 20 #define EFUSE_RD_EFUSE_RD_DIS 0x0000000F 21 #define EFUSE_RD_EFUSE_RD_DIS_M ((EFUSE_RD_EFUSE_RD_DIS_V)<<(EFUSE_RD_EFUSE_RD_DIS_S)) 22 #define EFUSE_RD_EFUSE_RD_DIS_V 0xF 23 #define EFUSE_RD_EFUSE_RD_DIS_S 16 24 25 /* Read disable bits for efuse blocks 1-3 */ 26 #define EFUSE_RD_DIS_BLK1 (1<<16) 27 #define EFUSE_RD_DIS_BLK2 (1<<17) 28 #define EFUSE_RD_DIS_BLK3 (1<<18) 29 /* Read disable FLASH_CRYPT_CONFIG, CODING_SCHEME & KEY_STATUS 30 in efuse block 0 31 */ 32 #define EFUSE_RD_DIS_BLK0_PARTIAL (1<<19) 33 34 /* EFUSE_RD_EFUSE_WR_DIS : RO ;bitpos:[15:0] ;default: 16'b0 ; */ 35 /*description: read for efuse_wr_disable*/ 36 #define EFUSE_RD_EFUSE_WR_DIS 0x0000FFFF 37 #define EFUSE_RD_EFUSE_WR_DIS_M ((EFUSE_RD_EFUSE_WR_DIS_V)<<(EFUSE_RD_EFUSE_WR_DIS_S)) 38 #define EFUSE_RD_EFUSE_WR_DIS_V 0xFFFF 39 #define EFUSE_RD_EFUSE_WR_DIS_S 0 40 41 /* Write disable bits */ 42 #define EFUSE_WR_DIS_RD_DIS (1<<0) /*< disable writing read disable reg */ 43 #define EFUSE_WR_DIS_WR_DIS (1<<1) /*< disable writing write disable reg */ 44 #define EFUSE_WR_DIS_FLASH_CRYPT_CNT (1<<2) 45 #define EFUSE_WR_DIS_MAC_SPI_CONFIG_HD (1<<3) /*< disable writing MAC & SPI config hd efuses */ 46 #define EFUSE_WR_DIS_XPD_SDIO (1<<5) /*< disable writing SDIO config efuses */ 47 #define EFUSE_WR_DIS_SPI_PAD_CONFIG (1<<6) /*< disable writing SPI_PAD_CONFIG efuses */ 48 #define EFUSE_WR_DIS_BLK1 (1<<7) /*< disable writing BLK1 efuses */ 49 #define EFUSE_WR_DIS_BLK2 (1<<8) /*< disable writing BLK2 efuses */ 50 #define EFUSE_WR_DIS_BLK3 (1<<9) /*< disable writing BLK3 efuses */ 51 #define EFUSE_WR_DIS_FLASH_CRYPT_CODING_SCHEME (1<<10) /*< disable writing FLASH_CRYPT_CONFIG and CODING_SCHEME efuses */ 52 #define EFUSE_WR_DIS_ABS_DONE_0 (1<<12) /*< disable writing ABS_DONE_0 efuse */ 53 #define EFUSE_WR_DIS_ABS_DONE_1 (1<<13) /*< disable writing ABS_DONE_1 efuse */ 54 #define EFUSE_WR_DIS_JTAG_DISABLE (1<<14) /*< disable writing JTAG_DISABLE efuse */ 55 #define EFUSE_WR_DIS_CONSOLE_DL_DISABLE (1<<15) /*< disable writing CONSOLE_DEBUG_DISABLE, DISABLE_DL_ENCRYPT, DISABLE_DL_DECRYPT and DISABLE_DL_CACHE efuses */ 56 57 #define EFUSE_BLK0_RDATA1_REG (DR_REG_EFUSE_BASE + 0x004) 58 /* EFUSE_RD_WIFI_MAC_CRC_LOW : RO ;bitpos:[31:0] ;default: 32'b0 ; */ 59 /*description: read for low 32bit WIFI_MAC_Address*/ 60 #define EFUSE_RD_WIFI_MAC_CRC_LOW 0xFFFFFFFF 61 #define EFUSE_RD_WIFI_MAC_CRC_LOW_M ((EFUSE_RD_WIFI_MAC_CRC_LOW_V)<<(EFUSE_RD_WIFI_MAC_CRC_LOW_S)) 62 #define EFUSE_RD_WIFI_MAC_CRC_LOW_V 0xFFFFFFFF 63 #define EFUSE_RD_WIFI_MAC_CRC_LOW_S 0 64 65 #define EFUSE_BLK0_RDATA2_REG (DR_REG_EFUSE_BASE + 0x008) 66 /* EFUSE_RD_WIFI_MAC_CRC_HIGH : RO ;bitpos:[23:0] ;default: 24'b0 ; */ 67 /*description: read for high 24bit WIFI_MAC_Address*/ 68 #define EFUSE_RD_WIFI_MAC_CRC_HIGH 0x00FFFFFF 69 #define EFUSE_RD_WIFI_MAC_CRC_HIGH_M ((EFUSE_RD_WIFI_MAC_CRC_HIGH_V)<<(EFUSE_RD_WIFI_MAC_CRC_HIGH_S)) 70 #define EFUSE_RD_WIFI_MAC_CRC_HIGH_V 0xFFFFFF 71 #define EFUSE_RD_WIFI_MAC_CRC_HIGH_S 0 72 73 #define EFUSE_BLK0_RDATA3_REG (DR_REG_EFUSE_BASE + 0x00c) 74 /* EFUSE_RD_CHIP_VER_REV1 : R/W ;bitpos:[15] ;default: 1'b0 ; */ 75 /*description: bit is set to 1 for rev1 silicon*/ 76 #define EFUSE_RD_CHIP_VER_REV1 (BIT(15)) 77 #define EFUSE_RD_CHIP_VER_REV1_M ((EFUSE_RD_CHIP_VER_REV1_V)<<(EFUSE_RD_CHIP_VER_REV1_S)) 78 #define EFUSE_RD_CHIP_VER_REV1_V 0x1 79 #define EFUSE_RD_CHIP_VER_REV1_S 15 80 /* EFUSE_RD_BLK3_PART_RESERVE : R/W ; bitpos:[14] ; default: 1'b0; */ 81 /*description: If set, this bit indicates that BLOCK3[143:96] is reserved for internal use*/ 82 #define EFUSE_RD_BLK3_PART_RESERVE (BIT(14)) 83 #define EFUSE_RD_BLK3_PART_RESERVE_M ((EFUSE_RD_BLK3_PART_RESERVE_V)<<(EFUSE_RD_BLK3_PART_RESERVE_S)) 84 #define EFUSE_RD_BLK3_PART_RESERVE_V 0x1 85 #define EFUSE_RD_BLK3_PART_RESERVE_S 14 86 /* EFUSE_RD_CHIP_CPU_FREQ_RATED : R/W ;bitpos:[13] ;default: 1'b0 ; */ 87 /*description: If set, the ESP32's maximum CPU frequency has been rated*/ 88 #define EFUSE_RD_CHIP_CPU_FREQ_RATED (BIT(13)) 89 #define EFUSE_RD_CHIP_CPU_FREQ_RATED_M ((EFUSE_RD_CHIP_CPU_FREQ_RATED_V)<<(EFUSE_RD_CHIP_CPU_FREQ_RATED_S)) 90 #define EFUSE_RD_CHIP_CPU_FREQ_RATED_V 0x1 91 #define EFUSE_RD_CHIP_CPU_FREQ_RATED_S 13 92 /* EFUSE_RD_CHIP_CPU_FREQ_LOW : R/W ;bitpos:[12] ;default: 1'b0 ; */ 93 /*description: If set alongside EFUSE_RD_CHIP_CPU_FREQ_RATED, the ESP32's max CPU frequency is rated for 160MHz. 240MHz otherwise*/ 94 #define EFUSE_RD_CHIP_CPU_FREQ_LOW (BIT(12)) 95 #define EFUSE_RD_CHIP_CPU_FREQ_LOW_M ((EFUSE_RD_CHIP_CPU_FREQ_LOW_V)<<(EFUSE_RD_CHIP_CPU_FREQ_LOW_S)) 96 #define EFUSE_RD_CHIP_CPU_FREQ_LOW_V 0x1 97 #define EFUSE_RD_CHIP_CPU_FREQ_LOW_S 12 98 /* EFUSE_RD_CHIP_VER_PKG : R/W ;bitpos:[11:9] ;default: 3'b0 ; */ 99 /*description: least significant bits of chip package */ 100 #define EFUSE_RD_CHIP_VER_PKG 0x00000007 101 #define EFUSE_RD_CHIP_VER_PKG_M ((EFUSE_RD_CHIP_VER_PKG_V)<<(EFUSE_RD_CHIP_VER_PKG_S)) 102 #define EFUSE_RD_CHIP_VER_PKG_V 0x7 103 #define EFUSE_RD_CHIP_VER_PKG_S 9 104 #define EFUSE_RD_CHIP_VER_PKG_ESP32D0WDQ6 0 105 #define EFUSE_RD_CHIP_VER_PKG_ESP32D0WDQ5 1 106 #define EFUSE_RD_CHIP_VER_PKG_ESP32D2WDQ5 2 107 #define EFUSE_RD_CHIP_VER_PKG_ESP32PICOD2 4 /* Deprecated: this chip was never mass produced */ 108 #define EFUSE_RD_CHIP_VER_PKG_ESP32U4WDH 4 109 #define EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4 5 110 #define EFUSE_RD_CHIP_VER_PKG_ESP32PICOV302 6 111 #define EFUSE_RD_CHIP_VER_PKG_ESP32D0WDR2V3 7 112 /* EFUSE_RD_SPI_PAD_CONFIG_HD : RO ;bitpos:[8:4] ;default: 5'b0 ; */ 113 /*description: read for SPI_pad_config_hd*/ 114 #define EFUSE_RD_SPI_PAD_CONFIG_HD 0x0000001F 115 #define EFUSE_RD_SPI_PAD_CONFIG_HD_M ((EFUSE_RD_SPI_PAD_CONFIG_HD_V)<<(EFUSE_RD_SPI_PAD_CONFIG_HD_S)) 116 #define EFUSE_RD_SPI_PAD_CONFIG_HD_V 0x1F 117 #define EFUSE_RD_SPI_PAD_CONFIG_HD_S 4 118 /* EFUSE_RD_CHIP_VER_DIS_CACHE : RO ;bitpos:[3] ;default: 1'b0 ; */ 119 /*description: */ 120 #define EFUSE_RD_CHIP_VER_DIS_CACHE (BIT(3)) 121 #define EFUSE_RD_CHIP_VER_DIS_CACHE_M (BIT(3)) 122 #define EFUSE_RD_CHIP_VER_DIS_CACHE_V 0x1 123 #define EFUSE_RD_CHIP_VER_DIS_CACHE_S 3 124 /* EFUSE_RD_CHIP_VER_PKG_4BIT : RO ;bitpos:[2] ;default: 1'b0 ; */ 125 /*description: most significant bit of chip package */ 126 #define EFUSE_RD_CHIP_VER_PKG_4BIT (BIT(2)) 127 #define EFUSE_RD_CHIP_VER_PKG_4BIT_M (BIT(2)) 128 #define EFUSE_RD_CHIP_VER_PKG_4BIT_V 0x1 129 #define EFUSE_RD_CHIP_VER_PKG_4BIT_S 2 130 /* EFUSE_RD_CHIP_VER_DIS_BT : RO ;bitpos:[1] ;default: 1'b0 ; */ 131 /*description: */ 132 #define EFUSE_RD_CHIP_VER_DIS_BT (BIT(1)) 133 #define EFUSE_RD_CHIP_VER_DIS_BT_M (BIT(1)) 134 #define EFUSE_RD_CHIP_VER_DIS_BT_V 0x1 135 #define EFUSE_RD_CHIP_VER_DIS_BT_S 1 136 /* EFUSE_RD_CHIP_VER_DIS_APP_CPU : RO ;bitpos:[0] ;default: 1'b0 ; */ 137 /*description: */ 138 #define EFUSE_RD_CHIP_VER_DIS_APP_CPU (BIT(0)) 139 #define EFUSE_RD_CHIP_VER_DIS_APP_CPU_M (BIT(0)) 140 #define EFUSE_RD_CHIP_VER_DIS_APP_CPU_V 0x1 141 #define EFUSE_RD_CHIP_VER_DIS_APP_CPU_S 0 142 143 #define EFUSE_BLK0_RDATA4_REG (DR_REG_EFUSE_BASE + 0x010) 144 /* EFUSE_RD_SDIO_FORCE : RO ;bitpos:[16] ;default: 1'b0 ; */ 145 /*description: read for sdio_force*/ 146 #define EFUSE_RD_SDIO_FORCE (BIT(16)) 147 #define EFUSE_RD_SDIO_FORCE_M (BIT(16)) 148 #define EFUSE_RD_SDIO_FORCE_V 0x1 149 #define EFUSE_RD_SDIO_FORCE_S 16 150 /* EFUSE_RD_SDIO_TIEH : RO ;bitpos:[15] ;default: 1'b0 ; */ 151 /*description: read for SDIO_TIEH*/ 152 #define EFUSE_RD_SDIO_TIEH (BIT(15)) 153 #define EFUSE_RD_SDIO_TIEH_M (BIT(15)) 154 #define EFUSE_RD_SDIO_TIEH_V 0x1 155 #define EFUSE_RD_SDIO_TIEH_S 15 156 /* EFUSE_RD_XPD_SDIO_REG : RO ;bitpos:[14] ;default: 1'b0 ; */ 157 /*description: read for XPD_SDIO_REG*/ 158 #define EFUSE_RD_XPD_SDIO_REG (BIT(14)) 159 #define EFUSE_RD_XPD_SDIO_REG_M (BIT(14)) 160 #define EFUSE_RD_XPD_SDIO_REG_V 0x1 161 #define EFUSE_RD_XPD_SDIO_REG_S 14 162 /* EFUSE_RD_ADC_VREF : R/W ;bitpos:[12:8] ;default: 5'b0 ; */ 163 /*description: True ADC reference voltage */ 164 #define EFUSE_RD_ADC_VREF 0x0000001F 165 #define EFUSE_RD_ADC_VREF_M ((EFUSE_RD_ADC_VREF_V)<<(EFUSE_RD_ADC_VREF_S)) 166 #define EFUSE_RD_ADC_VREF_V 0x1F 167 #define EFUSE_RD_ADC_VREF_S 8 168 /* Note: EFUSE_ADC_VREF and SDIO_DREFH/M/L share the same address space. Newer 169 * versions of ESP32 come with EFUSE_ADC_VREF already burned, therefore 170 * SDIO_DREFH/M/L is only available in older versions of ESP32 */ 171 /* EFUSE_RD_SDIO_DREFL : RO ;bitpos:[13:12] ;default: 2'b0 ; */ 172 /*description: */ 173 #define EFUSE_RD_SDIO_DREFL 0x00000003 174 #define EFUSE_RD_SDIO_DREFL_M ((EFUSE_RD_SDIO_DREFL_V)<<(EFUSE_RD_SDIO_DREFL_S)) 175 #define EFUSE_RD_SDIO_DREFL_V 0x3 176 #define EFUSE_RD_SDIO_DREFL_S 12 177 /* EFUSE_RD_SDIO_DREFM : RO ;bitpos:[11:10] ;default: 2'b0 ; */ 178 /*description: */ 179 #define EFUSE_RD_SDIO_DREFM 0x00000003 180 #define EFUSE_RD_SDIO_DREFM_M ((EFUSE_RD_SDIO_DREFM_V)<<(EFUSE_RD_SDIO_DREFM_S)) 181 #define EFUSE_RD_SDIO_DREFM_V 0x3 182 #define EFUSE_RD_SDIO_DREFM_S 10 183 /* EFUSE_RD_SDIO_DREFH : RO ;bitpos:[9:8] ;default: 2'b0 ; */ 184 /*description: */ 185 #define EFUSE_RD_SDIO_DREFH 0x00000003 186 #define EFUSE_RD_SDIO_DREFH_M ((EFUSE_RD_SDIO_DREFH_V)<<(EFUSE_RD_SDIO_DREFH_S)) 187 #define EFUSE_RD_SDIO_DREFH_V 0x3 188 #define EFUSE_RD_SDIO_DREFH_S 8 189 /* EFUSE_RD_CK8M_FREQ : RO ;bitpos:[7:0] ;default: 8'b0 ; */ 190 /*description: */ 191 #define EFUSE_RD_CK8M_FREQ 0x000000FF 192 #define EFUSE_RD_CK8M_FREQ_M ((EFUSE_RD_CK8M_FREQ_V)<<(EFUSE_RD_CK8M_FREQ_S)) 193 #define EFUSE_RD_CK8M_FREQ_V 0xFF 194 #define EFUSE_RD_CK8M_FREQ_S 0 195 196 #define EFUSE_BLK0_RDATA5_REG (DR_REG_EFUSE_BASE + 0x014) 197 /* EFUSE_RD_FLASH_CRYPT_CONFIG : RO ;bitpos:[31:28] ;default: 4'b0 ; */ 198 /*description: read for flash_crypt_config*/ 199 #define EFUSE_RD_FLASH_CRYPT_CONFIG 0x0000000F 200 #define EFUSE_RD_FLASH_CRYPT_CONFIG_M ((EFUSE_RD_FLASH_CRYPT_CONFIG_V)<<(EFUSE_RD_FLASH_CRYPT_CONFIG_S)) 201 #define EFUSE_RD_FLASH_CRYPT_CONFIG_V 0xF 202 #define EFUSE_RD_FLASH_CRYPT_CONFIG_S 28 203 /* EFUSE_RD_DIG_VOL_L6: RO; bitpos:[27:24]; */ 204 /*descritpion: This field stores the difference between the digital regulator voltage at level6 and 1.2 V. (RO) 205 BIT[27] is the sign bit, 0: + , 1: - 206 BIT[26:24] is the difference value, unit: 0.017V 207 volt_lv6 = BIT[27] ? 1.2 - BIT[26:24] * 0.017 : 1.2 + BIT[26:24] * 0.017 */ 208 #define EFUSE_RD_DIG_VOL_L6 0x0F 209 #define EFUSE_RD_DIG_VOL_L6_M ((EFUSE_RD_DIG_VOL_L6_V)<<(EFUSE_RD_DIG_VOL_L6_S)) 210 #define EFUSE_RD_DIG_VOL_L6_V 0x0F 211 #define EFUSE_RD_DIG_VOL_L6_S 24 212 /* EFUSE_RD_VOL_LEVEL_HP_INV: RO; bitpos:[23:22] */ 213 /*description: This field stores the voltage level for CPU to run at 240 MHz, or for flash/PSRAM to run at 80 MHz. 214 0x0: level 7; 0x1: level 6; 0x2: level 5; 0x3: level 4. (RO)*/ 215 #define EFUSE_RD_VOL_LEVEL_HP_INV 0x03 216 #define EFUSE_RD_VOL_LEVEL_HP_INV_M ((EFUSE_RD_VOL_LEVEL_HP_INV_V)<<(EFUSE_RD_VOL_LEVEL_HP_INV_S)) 217 #define EFUSE_RD_VOL_LEVEL_HP_INV_V 0x03 218 #define EFUSE_RD_VOL_LEVEL_HP_INV_S 22 219 /* EFUSE_RD_INST_CONFIG : RO ;bitpos:[27:20] ;default: 8'b0 ; */ 220 /* Deprecated */ 221 #define EFUSE_RD_INST_CONFIG 0x000000FF /** Deprecated **/ 222 #define EFUSE_RD_INST_CONFIG_M ((EFUSE_RD_INST_CONFIG_V)<<(EFUSE_RD_INST_CONFIG_S)) /** Deprecated **/ 223 #define EFUSE_RD_INST_CONFIG_V 0xFF /** Deprecated **/ 224 #define EFUSE_RD_INST_CONFIG_S 20 /** Deprecated **/ 225 /* EFUSE_RD_SPI_PAD_CONFIG_CS0 : RO ;bitpos:[19:15] ;default: 5'b0 ; */ 226 /*description: read for SPI_pad_config_cs0*/ 227 #define EFUSE_RD_SPI_PAD_CONFIG_CS0 0x0000001F 228 #define EFUSE_RD_SPI_PAD_CONFIG_CS0_M ((EFUSE_RD_SPI_PAD_CONFIG_CS0_V)<<(EFUSE_RD_SPI_PAD_CONFIG_CS0_S)) 229 #define EFUSE_RD_SPI_PAD_CONFIG_CS0_V 0x1F 230 #define EFUSE_RD_SPI_PAD_CONFIG_CS0_S 15 231 /* EFUSE_RD_SPI_PAD_CONFIG_D : RO ;bitpos:[14:10] ;default: 5'b0 ; */ 232 /*description: read for SPI_pad_config_d*/ 233 #define EFUSE_RD_SPI_PAD_CONFIG_D 0x0000001F 234 #define EFUSE_RD_SPI_PAD_CONFIG_D_M ((EFUSE_RD_SPI_PAD_CONFIG_D_V)<<(EFUSE_RD_SPI_PAD_CONFIG_D_S)) 235 #define EFUSE_RD_SPI_PAD_CONFIG_D_V 0x1F 236 #define EFUSE_RD_SPI_PAD_CONFIG_D_S 10 237 /* EFUSE_RD_SPI_PAD_CONFIG_Q : RO ;bitpos:[9:5] ;default: 5'b0 ; */ 238 /*description: read for SPI_pad_config_q*/ 239 #define EFUSE_RD_SPI_PAD_CONFIG_Q 0x0000001F 240 #define EFUSE_RD_SPI_PAD_CONFIG_Q_M ((EFUSE_RD_SPI_PAD_CONFIG_Q_V)<<(EFUSE_RD_SPI_PAD_CONFIG_Q_S)) 241 #define EFUSE_RD_SPI_PAD_CONFIG_Q_V 0x1F 242 #define EFUSE_RD_SPI_PAD_CONFIG_Q_S 5 243 /* EFUSE_RD_SPI_PAD_CONFIG_CLK : RO ;bitpos:[4:0] ;default: 5'b0 ; */ 244 /*description: read for SPI_pad_config_clk*/ 245 #define EFUSE_RD_SPI_PAD_CONFIG_CLK 0x0000001F 246 #define EFUSE_RD_SPI_PAD_CONFIG_CLK_M ((EFUSE_RD_SPI_PAD_CONFIG_CLK_V)<<(EFUSE_RD_SPI_PAD_CONFIG_CLK_S)) 247 #define EFUSE_RD_SPI_PAD_CONFIG_CLK_V 0x1F 248 #define EFUSE_RD_SPI_PAD_CONFIG_CLK_S 0 249 250 #define EFUSE_BLK0_RDATA6_REG (DR_REG_EFUSE_BASE + 0x018) 251 /* EFUSE_RD_KEY_STATUS : RO ;bitpos:[10] ;default: 1'b0 ; */ 252 /*description: read for key_status*/ 253 #define EFUSE_RD_KEY_STATUS (BIT(10)) 254 #define EFUSE_RD_KEY_STATUS_M (BIT(10)) 255 #define EFUSE_RD_KEY_STATUS_V 0x1 256 #define EFUSE_RD_KEY_STATUS_S 10 257 /* EFUSE_RD_DISABLE_DL_CACHE : RO ;bitpos:[9] ;default: 1'b0 ; */ 258 /*description: read for download_dis_cache*/ 259 #define EFUSE_RD_DISABLE_DL_CACHE (BIT(9)) 260 #define EFUSE_RD_DISABLE_DL_CACHE_M (BIT(9)) 261 #define EFUSE_RD_DISABLE_DL_CACHE_V 0x1 262 #define EFUSE_RD_DISABLE_DL_CACHE_S 9 263 /* EFUSE_RD_DISABLE_DL_DECRYPT : RO ;bitpos:[8] ;default: 1'b0 ; */ 264 /*description: read for download_dis_decrypt*/ 265 #define EFUSE_RD_DISABLE_DL_DECRYPT (BIT(8)) 266 #define EFUSE_RD_DISABLE_DL_DECRYPT_M (BIT(8)) 267 #define EFUSE_RD_DISABLE_DL_DECRYPT_V 0x1 268 #define EFUSE_RD_DISABLE_DL_DECRYPT_S 8 269 /* EFUSE_RD_DISABLE_DL_ENCRYPT : RO ;bitpos:[7] ;default: 1'b0 ; */ 270 /*description: read for download_dis_encrypt*/ 271 #define EFUSE_RD_DISABLE_DL_ENCRYPT (BIT(7)) 272 #define EFUSE_RD_DISABLE_DL_ENCRYPT_M (BIT(7)) 273 #define EFUSE_RD_DISABLE_DL_ENCRYPT_V 0x1 274 #define EFUSE_RD_DISABLE_DL_ENCRYPT_S 7 275 /* EFUSE_RD_DISABLE_JTAG : RO ;bitpos:[6] ;default: 1'b0 ; */ 276 /*description: read for JTAG_disable*/ 277 #define EFUSE_RD_DISABLE_JTAG (BIT(6)) 278 #define EFUSE_RD_DISABLE_JTAG_M (BIT(6)) 279 #define EFUSE_RD_DISABLE_JTAG_V 0x1 280 #define EFUSE_RD_DISABLE_JTAG_S 6 281 /* EFUSE_RD_ABS_DONE_1 : RO ;bitpos:[5] ;default: 1'b0 ; */ 282 /*description: read for abstract_done_1*/ 283 #define EFUSE_RD_ABS_DONE_1 (BIT(5)) 284 #define EFUSE_RD_ABS_DONE_1_M (BIT(5)) 285 #define EFUSE_RD_ABS_DONE_1_V 0x1 286 #define EFUSE_RD_ABS_DONE_1_S 5 287 /* EFUSE_RD_ABS_DONE_0 : RO ;bitpos:[4] ;default: 1'b0 ; */ 288 /*description: read for abstract_done_0*/ 289 #define EFUSE_RD_ABS_DONE_0 (BIT(4)) 290 #define EFUSE_RD_ABS_DONE_0_M (BIT(4)) 291 #define EFUSE_RD_ABS_DONE_0_V 0x1 292 #define EFUSE_RD_ABS_DONE_0_S 4 293 /* EFUSE_RD_DISABLE_SDIO_HOST : RO ;bitpos:[3] ;default: 1'b0 ; */ 294 /*description: */ 295 #define EFUSE_RD_DISABLE_SDIO_HOST (BIT(3)) 296 #define EFUSE_RD_DISABLE_SDIO_HOST_M (BIT(3)) 297 #define EFUSE_RD_DISABLE_SDIO_HOST_V 0x1 298 #define EFUSE_RD_DISABLE_SDIO_HOST_S 3 299 /* EFUSE_RD_CONSOLE_DEBUG_DISABLE : RO ;bitpos:[2] ;default: 1'b0 ; */ 300 /*description: read for console_debug_disable*/ 301 #define EFUSE_RD_CONSOLE_DEBUG_DISABLE (BIT(2)) 302 #define EFUSE_RD_CONSOLE_DEBUG_DISABLE_M (BIT(2)) 303 #define EFUSE_RD_CONSOLE_DEBUG_DISABLE_V 0x1 304 #define EFUSE_RD_CONSOLE_DEBUG_DISABLE_S 2 305 /* EFUSE_RD_CODING_SCHEME : RO ;bitpos:[1:0] ;default: 2'b0 ; */ 306 /*description: read for coding_scheme*/ 307 #define EFUSE_RD_CODING_SCHEME 0x00000003 308 #define EFUSE_RD_CODING_SCHEME_M ((EFUSE_RD_CODING_SCHEME_V)<<(EFUSE_RD_CODING_SCHEME_S)) 309 #define EFUSE_RD_CODING_SCHEME_V 0x3 310 #define EFUSE_RD_CODING_SCHEME_S 0 311 312 #define EFUSE_CODING_SCHEME_VAL_NONE 0x0 313 #define EFUSE_CODING_SCHEME_VAL_34 0x1 314 #define EFUSE_CODING_SCHEME_VAL_REPEAT 0x2 315 316 #define EFUSE_BLK0_WDATA0_REG (DR_REG_EFUSE_BASE + 0x01c) 317 /* EFUSE_FLASH_CRYPT_CNT : R/W ;bitpos:[26:20] ;default: 7'b0 ; */ 318 /*description: program for flash_crypt_cnt*/ 319 #define EFUSE_FLASH_CRYPT_CNT 0x0000007F 320 #define EFUSE_FLASH_CRYPT_CNT_M ((EFUSE_FLASH_CRYPT_CNT_V)<<(EFUSE_FLASH_CRYPT_CNT_S)) 321 #define EFUSE_FLASH_CRYPT_CNT_V 0x7F 322 #define EFUSE_FLASH_CRYPT_CNT_S 20 323 /* EFUSE_RD_DIS : R/W ;bitpos:[19:16] ;default: 4'b0 ; */ 324 /*description: program for efuse_rd_disable*/ 325 #define EFUSE_RD_DIS 0x0000000F 326 #define EFUSE_RD_DIS_M ((EFUSE_RD_DIS_V)<<(EFUSE_RD_DIS_S)) 327 #define EFUSE_RD_DIS_V 0xF 328 #define EFUSE_RD_DIS_S 16 329 /* EFUSE_WR_DIS : R/W ;bitpos:[15:0] ;default: 16'b0 ; */ 330 /*description: program for efuse_wr_disable*/ 331 #define EFUSE_WR_DIS 0x0000FFFF 332 #define EFUSE_WR_DIS_M ((EFUSE_WR_DIS_V)<<(EFUSE_WR_DIS_S)) 333 #define EFUSE_WR_DIS_V 0xFFFF 334 #define EFUSE_WR_DIS_S 0 335 336 #define EFUSE_BLK0_WDATA1_REG (DR_REG_EFUSE_BASE + 0x020) 337 /* EFUSE_WIFI_MAC_CRC_LOW : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ 338 /*description: program for low 32bit WIFI_MAC_Address*/ 339 #define EFUSE_WIFI_MAC_CRC_LOW 0xFFFFFFFF 340 #define EFUSE_WIFI_MAC_CRC_LOW_M ((EFUSE_WIFI_MAC_CRC_LOW_V)<<(EFUSE_WIFI_MAC_CRC_LOW_S)) 341 #define EFUSE_WIFI_MAC_CRC_LOW_V 0xFFFFFFFF 342 #define EFUSE_WIFI_MAC_CRC_LOW_S 0 343 344 #define EFUSE_BLK0_WDATA2_REG (DR_REG_EFUSE_BASE + 0x024) 345 /* EFUSE_WIFI_MAC_CRC_HIGH : R/W ;bitpos:[23:0] ;default: 24'b0 ; */ 346 /*description: program for high 24bit WIFI_MAC_Address*/ 347 #define EFUSE_WIFI_MAC_CRC_HIGH 0x00FFFFFF 348 #define EFUSE_WIFI_MAC_CRC_HIGH_M ((EFUSE_WIFI_MAC_CRC_HIGH_V)<<(EFUSE_WIFI_MAC_CRC_HIGH_S)) 349 #define EFUSE_WIFI_MAC_CRC_HIGH_V 0xFFFFFF 350 #define EFUSE_WIFI_MAC_CRC_HIGH_S 0 351 352 #define EFUSE_BLK0_WDATA3_REG (DR_REG_EFUSE_BASE + 0x028) 353 /* EFUSE_CHIP_VER_REV1 : R/W ;bitpos:[15] ;default: 1'b0 ; */ 354 /*description: */ 355 #define EFUSE_CHIP_VER_REV1 (BIT(15)) 356 #define EFUSE_CHIP_VER_REV1_M ((EFUSE_CHIP_VER_REV1_V)<<(EFUSE_CHIP_VER_REV1_S)) 357 #define EFUSE_CHIP_VER_REV1_V 0x1 358 #define EFUSE_CHIP_VER_REV1_S 15 359 /* EFUSE_BLK3_PART_RESERVE : R/W ; bitpos:[14] ; default: 1'b0; */ 360 /*description: If set, this bit indicates that BLOCK3[143:96] is reserved for internal use*/ 361 #define EFUSE_BLK3_PART_RESERVE (BIT(14)) 362 #define EFUSE_BLK3_PART_RESERVE_M ((EFUSE_BLK3_PART_RESERVE_V)<<(EFUSE_BLK3_PART_RESERVE_S)) 363 #define EFUSE_BLK3_PART_RESERVE_V 0x1 364 #define EFUSE_BLK3_PART_RESERVE_S 14 365 /* EFUSE_CHIP_CPU_FREQ_RATED : R/W ;bitpos:[13] ;default: 1'b0 ; */ 366 /*description: If set, the ESP32's maximum CPU frequency has been rated*/ 367 #define EFUSE_CHIP_CPU_FREQ_RATED (BIT(13)) 368 #define EFUSE_CHIP_CPU_FREQ_RATED_M ((EFUSE_CHIP_CPU_FREQ_RATED_V)<<(EFUSE_CHIP_CPU_FREQ_RATED_S)) 369 #define EFUSE_CHIP_CPU_FREQ_RATED_V 0x1 370 #define EFUSE_CHIP_CPU_FREQ_RATED_S 13 371 /* EFUSE_CHIP_CPU_FREQ_LOW : R/W ;bitpos:[12] ;default: 1'b0 ; */ 372 /*description: If set alongside EFUSE_CHIP_CPU_FREQ_RATED, the ESP32's max CPU frequency is rated for 160MHz. 240MHz otherwise*/ 373 #define EFUSE_CHIP_CPU_FREQ_LOW (BIT(12)) 374 #define EFUSE_CHIP_CPU_FREQ_LOW_M ((EFUSE_CHIP_CPU_FREQ_LOW_V)<<(EFUSE_CHIP_CPU_FREQ_LOW_S)) 375 #define EFUSE_CHIP_CPU_FREQ_LOW_V 0x1 376 #define EFUSE_CHIP_CPU_FREQ_LOW_S 12 377 /* EFUSE_CHIP_VER_PKG : R/W ;bitpos:[11:9] ;default: 3'b0 ; */ 378 /*description: least significant bits of chip package */ 379 #define EFUSE_CHIP_VER_PKG 0x00000007 380 #define EFUSE_CHIP_VER_PKG_M ((EFUSE_CHIP_VER_PKG_V)<<(EFUSE_CHIP_VER_PKG_S)) 381 #define EFUSE_CHIP_VER_PKG_V 0x7 382 #define EFUSE_CHIP_VER_PKG_S 9 383 #define EFUSE_CHIP_VER_PKG_ESP32D0WDQ6 0 384 #define EFUSE_CHIP_VER_PKG_ESP32D0WDQ5 1 385 #define EFUSE_CHIP_VER_PKG_ESP32D2WDQ5 2 386 #define EFUSE_CHIP_VER_PKG_ESP32PICOD2 4 387 #define EFUSE_CHIP_VER_PKG_ESP32PICOD4 5 388 #define EFUSE_CHIP_VER_PKG_ESP32PICOV302 6 389 /* EFUSE_SPI_PAD_CONFIG_HD : R/W ;bitpos:[8:4] ;default: 5'b0 ; */ 390 /*description: program for SPI_pad_config_hd*/ 391 #define EFUSE_SPI_PAD_CONFIG_HD 0x0000001F 392 #define EFUSE_SPI_PAD_CONFIG_HD_M ((EFUSE_SPI_PAD_CONFIG_HD_V)<<(EFUSE_SPI_PAD_CONFIG_HD_S)) 393 #define EFUSE_SPI_PAD_CONFIG_HD_V 0x1F 394 #define EFUSE_SPI_PAD_CONFIG_HD_S 4 395 /* EFUSE_CHIP_VER_DIS_CACHE : R/W ;bitpos:[3] ;default: 1'b0 ; */ 396 /*description: */ 397 #define EFUSE_CHIP_VER_DIS_CACHE (BIT(3)) 398 #define EFUSE_CHIP_VER_DIS_CACHE_M (BIT(3)) 399 #define EFUSE_CHIP_VER_DIS_CACHE_V 0x1 400 #define EFUSE_CHIP_VER_DIS_CACHE_S 3 401 /* EFUSE_CHIP_VER_PKG_4BIT : RO ;bitpos:[2] ;default: 1'b0 ; */ 402 /*description: most significant bit of chip package */ 403 #define EFUSE_CHIP_VER_PKG_4BIT (BIT(2)) 404 #define EFUSE_CHIP_VER_PKG_4BIT_M (BIT(2)) 405 #define EFUSE_CHIP_VER_PKG_4BIT_V 0x1 406 #define EFUSE_CHIP_VER_PKG_4BIT_S 2 407 /* EFUSE_CHIP_VER_DIS_BT : R/W ;bitpos:[1] ;default: 1'b0 ; */ 408 /*description: */ 409 #define EFUSE_CHIP_VER_DIS_BT (BIT(1)) 410 #define EFUSE_CHIP_VER_DIS_BT_M (BIT(1)) 411 #define EFUSE_CHIP_VER_DIS_BT_V 0x1 412 #define EFUSE_CHIP_VER_DIS_BT_S 1 413 /* EFUSE_CHIP_VER_DIS_APP_CPU : R/W ;bitpos:[0] ;default: 1'b0 ; */ 414 /*description: */ 415 #define EFUSE_CHIP_VER_DIS_APP_CPU (BIT(0)) 416 #define EFUSE_CHIP_VER_DIS_APP_CPU_M (BIT(0)) 417 #define EFUSE_CHIP_VER_DIS_APP_CPU_V 0x1 418 #define EFUSE_CHIP_VER_DIS_APP_CPU_S 0 419 420 #define EFUSE_BLK0_WDATA4_REG (DR_REG_EFUSE_BASE + 0x02c) 421 /* EFUSE_SDIO_FORCE : R/W ;bitpos:[16] ;default: 1'b0 ; */ 422 /*description: program for sdio_force*/ 423 #define EFUSE_SDIO_FORCE (BIT(16)) 424 #define EFUSE_SDIO_FORCE_M (BIT(16)) 425 #define EFUSE_SDIO_FORCE_V 0x1 426 #define EFUSE_SDIO_FORCE_S 16 427 /* EFUSE_SDIO_TIEH : R/W ;bitpos:[15] ;default: 1'b0 ; */ 428 /*description: program for SDIO_TIEH*/ 429 #define EFUSE_SDIO_TIEH (BIT(15)) 430 #define EFUSE_SDIO_TIEH_M (BIT(15)) 431 #define EFUSE_SDIO_TIEH_V 0x1 432 #define EFUSE_SDIO_TIEH_S 15 433 /* EFUSE_XPD_SDIO_REG : R/W ;bitpos:[14] ;default: 1'b0 ; */ 434 /*description: program for XPD_SDIO_REG*/ 435 #define EFUSE_XPD_SDIO_REG (BIT(14)) 436 #define EFUSE_XPD_SDIO_REG_M (BIT(14)) 437 #define EFUSE_XPD_SDIO_REG_V 0x1 438 #define EFUSE_XPD_SDIO_REG_S 14 439 /* EFUSE_ADC_VREF : R/W ;bitpos:[12:8] ;default: 5'b0 ; */ 440 /*description: True ADC reference voltage */ 441 #define EFUSE_ADC_VREF 0x0000001F 442 #define EFUSE_ADC_VREF_M ((EFUSE_ADC_VREF_V)<<(EFUSE_ADC_VREF_S)) 443 #define EFUSE_ADC_VREF_V 0x1F 444 #define EFUSE_ADC_VREF_S 8 445 /* Note: EFUSE_ADC_VREF and SDIO_DREFH/M/L share the same address space. Newer 446 * versions of ESP32 come with EFUSE_ADC_VREF already burned, therefore 447 * SDIO_DREFH/M/L is only available in older versions of ESP32 */ 448 /* EFUSE_SDIO_DREFL : R/W ;bitpos:[13:12] ;default: 2'b0 ; */ 449 /*description: */ 450 #define EFUSE_SDIO_DREFL 0x00000003 451 #define EFUSE_SDIO_DREFL_M ((EFUSE_SDIO_DREFL_V)<<(EFUSE_SDIO_DREFL_S)) 452 #define EFUSE_SDIO_DREFL_V 0x3 453 #define EFUSE_SDIO_DREFL_S 12 454 /* EFUSE_SDIO_DREFM : R/W ;bitpos:[11:10] ;default: 2'b0 ; */ 455 /*description: */ 456 #define EFUSE_SDIO_DREFM 0x00000003 457 #define EFUSE_SDIO_DREFM_M ((EFUSE_SDIO_DREFM_V)<<(EFUSE_SDIO_DREFM_S)) 458 #define EFUSE_SDIO_DREFM_V 0x3 459 #define EFUSE_SDIO_DREFM_S 10 460 /* EFUSE_SDIO_DREFH : R/W ;bitpos:[9:8] ;default: 2'b0 ; */ 461 /*description: */ 462 #define EFUSE_SDIO_DREFH 0x00000003 463 #define EFUSE_SDIO_DREFH_M ((EFUSE_SDIO_DREFH_V)<<(EFUSE_SDIO_DREFH_S)) 464 #define EFUSE_SDIO_DREFH_V 0x3 465 #define EFUSE_SDIO_DREFH_S 8 466 /* EFUSE_CK8M_FREQ : R/W ;bitpos:[7:0] ;default: 8'b0 ; */ 467 /*description: */ 468 #define EFUSE_CK8M_FREQ 0x000000FF 469 #define EFUSE_CK8M_FREQ_M ((EFUSE_CK8M_FREQ_V)<<(EFUSE_CK8M_FREQ_S)) 470 #define EFUSE_CK8M_FREQ_V 0xFF 471 #define EFUSE_CK8M_FREQ_S 0 472 473 #define EFUSE_BLK0_WDATA5_REG (DR_REG_EFUSE_BASE + 0x030) 474 /* EFUSE_FLASH_CRYPT_CONFIG : R/W ;bitpos:[31:28] ;default: 4'b0 ; */ 475 /*description: program for flash_crypt_config*/ 476 #define EFUSE_FLASH_CRYPT_CONFIG 0x0000000F 477 #define EFUSE_FLASH_CRYPT_CONFIG_M ((EFUSE_FLASH_CRYPT_CONFIG_V)<<(EFUSE_FLASH_CRYPT_CONFIG_S)) 478 #define EFUSE_FLASH_CRYPT_CONFIG_V 0xF 479 #define EFUSE_FLASH_CRYPT_CONFIG_S 28 480 /* EFUSE_DIG_VOL_L6: R/W; bitpos:[27:24]; */ 481 /*descritpion: This field stores the difference between the digital regulator voltage at level6 and 1.2 V. (R/W) 482 BIT[27] is the sign bit, 0: + , 1: - 483 BIT[26:24] is the difference value, unit: 0.017V 484 volt_lv6 = BIT[27] ? 1.2 - BIT[26:24] * 0.017 : 1.2 + BIT[26:24] * 0.017 */ 485 #define EFUSE_DIG_VOL_L6 0x0F 486 #define EFUSE_DIG_VOL_L6_M ((EFUSE_RD_DIG_VOL_L6_V)<<(EFUSE_RD_DIG_VOL_L6_S)) 487 #define EFUSE_DIG_VOL_L6_V 0x0F 488 #define EFUSE_DIG_VOL_L6_S 24 489 /* EFUSE_VOL_LEVEL_HP_INV: R/W; bitpos:[23:22] */ 490 /*description: This field stores the voltage level for CPU to run at 240 MHz, or for flash/PSRAM to run at 80 MHz. 491 0x0: level 7; 0x1: level 6; 0x2: level 5; 0x3: level 4. (R/W)*/ 492 #define EFUSE_VOL_LEVEL_HP_INV 0x03 493 #define EFUSE_VOL_LEVEL_HP_INV_M ((EFUSE_RD_VOL_LEVEL_HP_INV_V)<<(EFUSE_RD_VOL_LEVEL_HP_INV_S)) 494 #define EFUSE_VOL_LEVEL_HP_INV_V 0x03 495 #define EFUSE_VOL_LEVEL_HP_INV_S 22 496 /* EFUSE_INST_CONFIG : R/W ;bitpos:[27:20] ;default: 8'b0 ; */ 497 /* Deprecated */ 498 #define EFUSE_INST_CONFIG 0x000000FF /** Deprecated **/ 499 #define EFUSE_INST_CONFIG_M ((EFUSE_INST_CONFIG_V)<<(EFUSE_INST_CONFIG_S)) /** Deprecated **/ 500 #define EFUSE_INST_CONFIG_V 0xFF /** Deprecated **/ 501 #define EFUSE_INST_CONFIG_S 20 /** Deprecated **/ 502 /* EFUSE_SPI_PAD_CONFIG_CS0 : R/W ;bitpos:[19:15] ;default: 5'b0 ; */ 503 /*description: program for SPI_pad_config_cs0*/ 504 #define EFUSE_SPI_PAD_CONFIG_CS0 0x0000001F 505 #define EFUSE_SPI_PAD_CONFIG_CS0_M ((EFUSE_SPI_PAD_CONFIG_CS0_V)<<(EFUSE_SPI_PAD_CONFIG_CS0_S)) 506 #define EFUSE_SPI_PAD_CONFIG_CS0_V 0x1F 507 #define EFUSE_SPI_PAD_CONFIG_CS0_S 15 508 /* EFUSE_SPI_PAD_CONFIG_D : R/W ;bitpos:[14:10] ;default: 5'b0 ; */ 509 /*description: program for SPI_pad_config_d*/ 510 #define EFUSE_SPI_PAD_CONFIG_D 0x0000001F 511 #define EFUSE_SPI_PAD_CONFIG_D_M ((EFUSE_SPI_PAD_CONFIG_D_V)<<(EFUSE_SPI_PAD_CONFIG_D_S)) 512 #define EFUSE_SPI_PAD_CONFIG_D_V 0x1F 513 #define EFUSE_SPI_PAD_CONFIG_D_S 10 514 /* EFUSE_SPI_PAD_CONFIG_Q : R/W ;bitpos:[9:5] ;default: 5'b0 ; */ 515 /*description: program for SPI_pad_config_q*/ 516 #define EFUSE_SPI_PAD_CONFIG_Q 0x0000001F 517 #define EFUSE_SPI_PAD_CONFIG_Q_M ((EFUSE_SPI_PAD_CONFIG_Q_V)<<(EFUSE_SPI_PAD_CONFIG_Q_S)) 518 #define EFUSE_SPI_PAD_CONFIG_Q_V 0x1F 519 #define EFUSE_SPI_PAD_CONFIG_Q_S 5 520 /* EFUSE_SPI_PAD_CONFIG_CLK : R/W ;bitpos:[4:0] ;default: 5'b0 ; */ 521 /*description: program for SPI_pad_config_clk*/ 522 #define EFUSE_SPI_PAD_CONFIG_CLK 0x0000001F 523 #define EFUSE_SPI_PAD_CONFIG_CLK_M ((EFUSE_SPI_PAD_CONFIG_CLK_V)<<(EFUSE_SPI_PAD_CONFIG_CLK_S)) 524 #define EFUSE_SPI_PAD_CONFIG_CLK_V 0x1F 525 #define EFUSE_SPI_PAD_CONFIG_CLK_S 0 526 527 #define EFUSE_BLK0_WDATA6_REG (DR_REG_EFUSE_BASE + 0x034) 528 /* EFUSE_KEY_STATUS : R/W ;bitpos:[10] ;default: 1'b0 ; */ 529 /*description: program for key_status*/ 530 #define EFUSE_KEY_STATUS (BIT(10)) 531 #define EFUSE_KEY_STATUS_M (BIT(10)) 532 #define EFUSE_KEY_STATUS_V 0x1 533 #define EFUSE_KEY_STATUS_S 10 534 /* EFUSE_DISABLE_DL_CACHE : R/W ;bitpos:[9] ;default: 1'b0 ; */ 535 /*description: program for download_dis_cache*/ 536 #define EFUSE_DISABLE_DL_CACHE (BIT(9)) 537 #define EFUSE_DISABLE_DL_CACHE_M (BIT(9)) 538 #define EFUSE_DISABLE_DL_CACHE_V 0x1 539 #define EFUSE_DISABLE_DL_CACHE_S 9 540 /* EFUSE_DISABLE_DL_DECRYPT : R/W ;bitpos:[8] ;default: 1'b0 ; */ 541 /*description: program for download_dis_decrypt*/ 542 #define EFUSE_DISABLE_DL_DECRYPT (BIT(8)) 543 #define EFUSE_DISABLE_DL_DECRYPT_M (BIT(8)) 544 #define EFUSE_DISABLE_DL_DECRYPT_V 0x1 545 #define EFUSE_DISABLE_DL_DECRYPT_S 8 546 /* EFUSE_DISABLE_DL_ENCRYPT : R/W ;bitpos:[7] ;default: 1'b0 ; */ 547 /*description: program for download_dis_encrypt*/ 548 #define EFUSE_DISABLE_DL_ENCRYPT (BIT(7)) 549 #define EFUSE_DISABLE_DL_ENCRYPT_M (BIT(7)) 550 #define EFUSE_DISABLE_DL_ENCRYPT_V 0x1 551 #define EFUSE_DISABLE_DL_ENCRYPT_S 7 552 /* EFUSE_DISABLE_JTAG : R/W ;bitpos:[6] ;default: 1'b0 ; */ 553 /*description: program for JTAG_disable*/ 554 #define EFUSE_DISABLE_JTAG (BIT(6)) 555 #define EFUSE_DISABLE_JTAG_M (BIT(6)) 556 #define EFUSE_DISABLE_JTAG_V 0x1 557 #define EFUSE_DISABLE_JTAG_S 6 558 /* EFUSE_ABS_DONE_1 : R/W ;bitpos:[5] ;default: 1'b0 ; */ 559 /*description: program for abstract_done_1*/ 560 #define EFUSE_ABS_DONE_1 (BIT(5)) 561 #define EFUSE_ABS_DONE_1_M (BIT(5)) 562 #define EFUSE_ABS_DONE_1_V 0x1 563 #define EFUSE_ABS_DONE_1_S 5 564 /* EFUSE_ABS_DONE_0 : R/W ;bitpos:[4] ;default: 1'b0 ; */ 565 /*description: program for abstract_done_0*/ 566 #define EFUSE_ABS_DONE_0 (BIT(4)) 567 #define EFUSE_ABS_DONE_0_M (BIT(4)) 568 #define EFUSE_ABS_DONE_0_V 0x1 569 #define EFUSE_ABS_DONE_0_S 4 570 /* EFUSE_DISABLE_SDIO_HOST : R/W ;bitpos:[3] ;default: 1'b0 ; */ 571 /*description: */ 572 #define EFUSE_DISABLE_SDIO_HOST (BIT(3)) 573 #define EFUSE_DISABLE_SDIO_HOST_M (BIT(3)) 574 #define EFUSE_DISABLE_SDIO_HOST_V 0x1 575 #define EFUSE_DISABLE_SDIO_HOST_S 3 576 /* EFUSE_CONSOLE_DEBUG_DISABLE : R/W ;bitpos:[2] ;default: 1'b0 ; */ 577 /*description: program for console_debug_disable*/ 578 #define EFUSE_CONSOLE_DEBUG_DISABLE (BIT(2)) 579 #define EFUSE_CONSOLE_DEBUG_DISABLE_M (BIT(2)) 580 #define EFUSE_CONSOLE_DEBUG_DISABLE_V 0x1 581 #define EFUSE_CONSOLE_DEBUG_DISABLE_S 2 582 /* EFUSE_CODING_SCHEME : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ 583 /*description: program for coding_scheme*/ 584 #define EFUSE_CODING_SCHEME 0x00000003 585 #define EFUSE_CODING_SCHEME_M ((EFUSE_CODING_SCHEME_V)<<(EFUSE_CODING_SCHEME_S)) 586 #define EFUSE_CODING_SCHEME_V 0x3 587 #define EFUSE_CODING_SCHEME_S 0 588 589 #define EFUSE_BLK1_RDATA0_REG (DR_REG_EFUSE_BASE + 0x038) 590 /* EFUSE_BLK1_DOUT0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 591 /*description: read for BLOCK1*/ 592 #define EFUSE_BLK1_DOUT0 0xFFFFFFFF 593 #define EFUSE_BLK1_DOUT0_M ((EFUSE_BLK1_DOUT0_V)<<(EFUSE_BLK1_DOUT0_S)) 594 #define EFUSE_BLK1_DOUT0_V 0xFFFFFFFF 595 #define EFUSE_BLK1_DOUT0_S 0 596 597 #define EFUSE_BLK1_RDATA1_REG (DR_REG_EFUSE_BASE + 0x03c) 598 /* EFUSE_BLK1_DOUT1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 599 /*description: read for BLOCK1*/ 600 #define EFUSE_BLK1_DOUT1 0xFFFFFFFF 601 #define EFUSE_BLK1_DOUT1_M ((EFUSE_BLK1_DOUT1_V)<<(EFUSE_BLK1_DOUT1_S)) 602 #define EFUSE_BLK1_DOUT1_V 0xFFFFFFFF 603 #define EFUSE_BLK1_DOUT1_S 0 604 605 #define EFUSE_BLK1_RDATA2_REG (DR_REG_EFUSE_BASE + 0x040) 606 /* EFUSE_BLK1_DOUT2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 607 /*description: read for BLOCK1*/ 608 #define EFUSE_BLK1_DOUT2 0xFFFFFFFF 609 #define EFUSE_BLK1_DOUT2_M ((EFUSE_BLK1_DOUT2_V)<<(EFUSE_BLK1_DOUT2_S)) 610 #define EFUSE_BLK1_DOUT2_V 0xFFFFFFFF 611 #define EFUSE_BLK1_DOUT2_S 0 612 613 #define EFUSE_BLK1_RDATA3_REG (DR_REG_EFUSE_BASE + 0x044) 614 /* EFUSE_BLK1_DOUT3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 615 /*description: read for BLOCK1*/ 616 #define EFUSE_BLK1_DOUT3 0xFFFFFFFF 617 #define EFUSE_BLK1_DOUT3_M ((EFUSE_BLK1_DOUT3_V)<<(EFUSE_BLK1_DOUT3_S)) 618 #define EFUSE_BLK1_DOUT3_V 0xFFFFFFFF 619 #define EFUSE_BLK1_DOUT3_S 0 620 621 #define EFUSE_BLK1_RDATA4_REG (DR_REG_EFUSE_BASE + 0x048) 622 /* EFUSE_BLK1_DOUT4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 623 /*description: read for BLOCK1*/ 624 #define EFUSE_BLK1_DOUT4 0xFFFFFFFF 625 #define EFUSE_BLK1_DOUT4_M ((EFUSE_BLK1_DOUT4_V)<<(EFUSE_BLK1_DOUT4_S)) 626 #define EFUSE_BLK1_DOUT4_V 0xFFFFFFFF 627 #define EFUSE_BLK1_DOUT4_S 0 628 629 #define EFUSE_BLK1_RDATA5_REG (DR_REG_EFUSE_BASE + 0x04c) 630 /* EFUSE_BLK1_DOUT5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 631 /*description: read for BLOCK1*/ 632 #define EFUSE_BLK1_DOUT5 0xFFFFFFFF 633 #define EFUSE_BLK1_DOUT5_M ((EFUSE_BLK1_DOUT5_V)<<(EFUSE_BLK1_DOUT5_S)) 634 #define EFUSE_BLK1_DOUT5_V 0xFFFFFFFF 635 #define EFUSE_BLK1_DOUT5_S 0 636 637 #define EFUSE_BLK1_RDATA6_REG (DR_REG_EFUSE_BASE + 0x050) 638 /* EFUSE_BLK1_DOUT6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 639 /*description: read for BLOCK1*/ 640 #define EFUSE_BLK1_DOUT6 0xFFFFFFFF 641 #define EFUSE_BLK1_DOUT6_M ((EFUSE_BLK1_DOUT6_V)<<(EFUSE_BLK1_DOUT6_S)) 642 #define EFUSE_BLK1_DOUT6_V 0xFFFFFFFF 643 #define EFUSE_BLK1_DOUT6_S 0 644 645 #define EFUSE_BLK1_RDATA7_REG (DR_REG_EFUSE_BASE + 0x054) 646 /* EFUSE_BLK1_DOUT7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 647 /*description: read for BLOCK1*/ 648 #define EFUSE_BLK1_DOUT7 0xFFFFFFFF 649 #define EFUSE_BLK1_DOUT7_M ((EFUSE_BLK1_DOUT7_V)<<(EFUSE_BLK1_DOUT7_S)) 650 #define EFUSE_BLK1_DOUT7_V 0xFFFFFFFF 651 #define EFUSE_BLK1_DOUT7_S 0 652 653 #define EFUSE_BLK2_RDATA0_REG (DR_REG_EFUSE_BASE + 0x058) 654 /* EFUSE_BLK2_DOUT0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 655 /*description: read for BLOCK2*/ 656 #define EFUSE_BLK2_DOUT0 0xFFFFFFFF 657 #define EFUSE_BLK2_DOUT0_M ((EFUSE_BLK2_DOUT0_V)<<(EFUSE_BLK2_DOUT0_S)) 658 #define EFUSE_BLK2_DOUT0_V 0xFFFFFFFF 659 #define EFUSE_BLK2_DOUT0_S 0 660 661 #define EFUSE_BLK2_RDATA1_REG (DR_REG_EFUSE_BASE + 0x05c) 662 /* EFUSE_BLK2_DOUT1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 663 /*description: read for BLOCK2*/ 664 #define EFUSE_BLK2_DOUT1 0xFFFFFFFF 665 #define EFUSE_BLK2_DOUT1_M ((EFUSE_BLK2_DOUT1_V)<<(EFUSE_BLK2_DOUT1_S)) 666 #define EFUSE_BLK2_DOUT1_V 0xFFFFFFFF 667 #define EFUSE_BLK2_DOUT1_S 0 668 669 #define EFUSE_BLK2_RDATA2_REG (DR_REG_EFUSE_BASE + 0x060) 670 /* EFUSE_BLK2_DOUT2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 671 /*description: read for BLOCK2*/ 672 #define EFUSE_BLK2_DOUT2 0xFFFFFFFF 673 #define EFUSE_BLK2_DOUT2_M ((EFUSE_BLK2_DOUT2_V)<<(EFUSE_BLK2_DOUT2_S)) 674 #define EFUSE_BLK2_DOUT2_V 0xFFFFFFFF 675 #define EFUSE_BLK2_DOUT2_S 0 676 677 #define EFUSE_BLK2_RDATA3_REG (DR_REG_EFUSE_BASE + 0x064) 678 /* EFUSE_BLK2_DOUT3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 679 /*description: read for BLOCK2*/ 680 #define EFUSE_BLK2_DOUT3 0xFFFFFFFF 681 #define EFUSE_BLK2_DOUT3_M ((EFUSE_BLK2_DOUT3_V)<<(EFUSE_BLK2_DOUT3_S)) 682 #define EFUSE_BLK2_DOUT3_V 0xFFFFFFFF 683 #define EFUSE_BLK2_DOUT3_S 0 684 685 #define EFUSE_BLK2_RDATA4_REG (DR_REG_EFUSE_BASE + 0x068) 686 /* EFUSE_BLK2_DOUT4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 687 /*description: read for BLOCK2*/ 688 #define EFUSE_BLK2_DOUT4 0xFFFFFFFF 689 #define EFUSE_BLK2_DOUT4_M ((EFUSE_BLK2_DOUT4_V)<<(EFUSE_BLK2_DOUT4_S)) 690 #define EFUSE_BLK2_DOUT4_V 0xFFFFFFFF 691 #define EFUSE_BLK2_DOUT4_S 0 692 693 #define EFUSE_BLK2_RDATA5_REG (DR_REG_EFUSE_BASE + 0x06c) 694 /* EFUSE_BLK2_DOUT5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 695 /*description: read for BLOCK2*/ 696 #define EFUSE_BLK2_DOUT5 0xFFFFFFFF 697 #define EFUSE_BLK2_DOUT5_M ((EFUSE_BLK2_DOUT5_V)<<(EFUSE_BLK2_DOUT5_S)) 698 #define EFUSE_BLK2_DOUT5_V 0xFFFFFFFF 699 #define EFUSE_BLK2_DOUT5_S 0 700 701 #define EFUSE_BLK2_RDATA6_REG (DR_REG_EFUSE_BASE + 0x070) 702 /* EFUSE_BLK2_DOUT6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 703 /*description: read for BLOCK2*/ 704 #define EFUSE_BLK2_DOUT6 0xFFFFFFFF 705 #define EFUSE_BLK2_DOUT6_M ((EFUSE_BLK2_DOUT6_V)<<(EFUSE_BLK2_DOUT6_S)) 706 #define EFUSE_BLK2_DOUT6_V 0xFFFFFFFF 707 #define EFUSE_BLK2_DOUT6_S 0 708 709 #define EFUSE_BLK2_RDATA7_REG (DR_REG_EFUSE_BASE + 0x074) 710 /* EFUSE_BLK2_DOUT7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 711 /*description: read for BLOCK2*/ 712 #define EFUSE_BLK2_DOUT7 0xFFFFFFFF 713 #define EFUSE_BLK2_DOUT7_M ((EFUSE_BLK2_DOUT7_V)<<(EFUSE_BLK2_DOUT7_S)) 714 #define EFUSE_BLK2_DOUT7_V 0xFFFFFFFF 715 #define EFUSE_BLK2_DOUT7_S 0 716 717 #define EFUSE_BLK3_RDATA0_REG (DR_REG_EFUSE_BASE + 0x078) 718 /* EFUSE_BLK3_DOUT0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 719 /*description: read for BLOCK3*/ 720 #define EFUSE_BLK3_DOUT0 0xFFFFFFFF 721 #define EFUSE_BLK3_DOUT0_M ((EFUSE_BLK3_DOUT0_V)<<(EFUSE_BLK3_DOUT0_S)) 722 #define EFUSE_BLK3_DOUT0_V 0xFFFFFFFF 723 #define EFUSE_BLK3_DOUT0_S 0 724 725 #define EFUSE_BLK3_RDATA1_REG (DR_REG_EFUSE_BASE + 0x07c) 726 /* EFUSE_BLK3_DOUT1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 727 /*description: read for BLOCK3*/ 728 #define EFUSE_BLK3_DOUT1 0xFFFFFFFF 729 #define EFUSE_BLK3_DOUT1_M ((EFUSE_BLK3_DOUT1_V)<<(EFUSE_BLK3_DOUT1_S)) 730 #define EFUSE_BLK3_DOUT1_V 0xFFFFFFFF 731 #define EFUSE_BLK3_DOUT1_S 0 732 733 #define EFUSE_BLK3_RDATA2_REG (DR_REG_EFUSE_BASE + 0x080) 734 /* EFUSE_BLK3_DOUT2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 735 /*description: read for BLOCK3*/ 736 #define EFUSE_BLK3_DOUT2 0xFFFFFFFF 737 #define EFUSE_BLK3_DOUT2_M ((EFUSE_BLK3_DOUT2_V)<<(EFUSE_BLK3_DOUT2_S)) 738 #define EFUSE_BLK3_DOUT2_V 0xFFFFFFFF 739 #define EFUSE_BLK3_DOUT2_S 0 740 741 /* Note: Newer ESP32s utilize BLK3_DATA3 and parts of BLK3_DATA4 for calibration 742 * purposes. This usage is indicated by the EFUSE_RD_BLK3_PART_RESERVE bit.*/ 743 #define EFUSE_BLK3_RDATA3_REG (DR_REG_EFUSE_BASE + 0x084) 744 /* EFUSE_BLK3_DOUT3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 745 /*description: read for BLOCK3*/ 746 #define EFUSE_BLK3_DOUT3 0xFFFFFFFF 747 #define EFUSE_BLK3_DOUT3_M ((EFUSE_BLK3_DOUT3_V)<<(EFUSE_BLK3_DOUT3_S)) 748 #define EFUSE_BLK3_DOUT3_V 0xFFFFFFFF 749 #define EFUSE_BLK3_DOUT3_S 0 750 /* EFUSE_RD_ADC2_TP_HIGH : R/W ;bitpos:[31:23] ;default: 9'b0 ; */ 751 /*description: ADC2 Two Point calibration high point. Only valid if EFUSE_RD_BLK3_PART_RESERVE */ 752 #define EFUSE_RD_ADC2_TP_HIGH 0x1FF 753 #define EFUSE_RD_ADC2_TP_HIGH_M ((EFUSE_RD_ADC2_TP_HIGH_V)<<(EFUSE_RD_ADC2_TP_HIGH_S)) 754 #define EFUSE_RD_ADC2_TP_HIGH_V 0x1FF 755 #define EFUSE_RD_ADC2_TP_HIGH_S 23 756 /* EFUSE_RD_ADC2_TP_LOW : R/W ;bitpos:[22:16] ;default: 7'b0 ; */ 757 /*description: ADC2 Two Point calibration low point. Only valid if EFUSE_RD_BLK3_PART_RESERVE */ 758 #define EFUSE_RD_ADC2_TP_LOW 0x7F 759 #define EFUSE_RD_ADC2_TP_LOW_M ((EFUSE_RD_ADC2_TP_LOW_V)<<(EFUSE_RD_ADC2_TP_LOW_S)) 760 #define EFUSE_RD_ADC2_TP_LOW_V 0x7F 761 #define EFUSE_RD_ADC2_TP_LOW_S 16 762 /* EFUSE_RD_ADC1_TP_HIGH : R/W ;bitpos:[15:7] ;default: 9'b0 ; */ 763 /*description: ADC1 Two Point calibration high point. Only valid if EFUSE_RD_BLK3_PART_RESERVE */ 764 #define EFUSE_RD_ADC1_TP_HIGH 0x1FF 765 #define EFUSE_RD_ADC1_TP_HIGH_M ((EFUSE_RD_ADC1_TP_HIGH_V)<<(EFUSE_RD_ADC1_TP_HIGH_S)) 766 #define EFUSE_RD_ADC1_TP_HIGH_V 0x1FF 767 #define EFUSE_RD_ADC1_TP_HIGH_S 7 768 /* EFUSE_RD_ADC1_TP_LOW : R/W ;bitpos:[6:0] ;default: 7'b0 ; */ 769 /*description: ADC1 Two Point calibration low point. Only valid if EFUSE_RD_BLK3_PART_RESERVE */ 770 #define EFUSE_RD_ADC1_TP_LOW 0x7F 771 #define EFUSE_RD_ADC1_TP_LOW_M ((EFUSE_RD_ADC1_TP_LOW_V)<<(EFUSE_RD_ADC1_TP_LOW_S)) 772 #define EFUSE_RD_ADC1_TP_LOW_V 0x7F 773 #define EFUSE_RD_ADC1_TP_LOW_S 0 774 775 #define EFUSE_BLK3_RDATA4_REG (DR_REG_EFUSE_BASE + 0x088) 776 /* EFUSE_BLK3_DOUT4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 777 /*description: read for BLOCK3*/ 778 #define EFUSE_BLK3_DOUT4 0xFFFFFFFF 779 #define EFUSE_BLK3_DOUT4_M ((EFUSE_BLK3_DOUT4_V)<<(EFUSE_BLK3_DOUT4_S)) 780 #define EFUSE_BLK3_DOUT4_V 0xFFFFFFFF 781 #define EFUSE_BLK3_DOUT4_S 0 782 /* EFUSE_RD_CAL_RESERVED: R/W ; bitpos:[0:15] ; default : 16'h0 ; */ 783 /*description: Reserved for future calibration use. Indicated by EFUSE_RD_BLK3_PART_RESERVE */ 784 #define EFUSE_RD_CAL_RESERVED 0x0000FFFF 785 #define EFUSE_RD_CAL_RESERVED_M ((EFUSE_RD_CAL_RESERVED_V)<<(EFUSE_RD_CAL_RESERVED_S)) 786 #define EFUSE_RD_CAL_RESERVED_V 0xFFFF 787 #define EFUSE_RD_CAL_RESERVED_S 0 788 789 #define EFUSE_BLK3_RDATA5_REG (DR_REG_EFUSE_BASE + 0x08c) 790 /* EFUSE_BLK3_DOUT5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 791 /*description: read for BLOCK3*/ 792 #define EFUSE_BLK3_DOUT5 0xFFFFFFFF 793 #define EFUSE_BLK3_DOUT5_M ((EFUSE_BLK3_DOUT5_V)<<(EFUSE_BLK3_DOUT5_S)) 794 #define EFUSE_BLK3_DOUT5_V 0xFFFFFFFF 795 #define EFUSE_BLK3_DOUT5_S 0 796 797 #define EFUSE_BLK3_RDATA6_REG (DR_REG_EFUSE_BASE + 0x090) 798 /* EFUSE_BLK3_DOUT6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 799 /*description: read for BLOCK3*/ 800 #define EFUSE_BLK3_DOUT6 0xFFFFFFFF 801 #define EFUSE_BLK3_DOUT6_M ((EFUSE_BLK3_DOUT6_V)<<(EFUSE_BLK3_DOUT6_S)) 802 #define EFUSE_BLK3_DOUT6_V 0xFFFFFFFF 803 #define EFUSE_BLK3_DOUT6_S 0 804 805 #define EFUSE_BLK3_RDATA7_REG (DR_REG_EFUSE_BASE + 0x094) 806 /* EFUSE_BLK3_DOUT7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 807 /*description: read for BLOCK3*/ 808 #define EFUSE_BLK3_DOUT7 0xFFFFFFFF 809 #define EFUSE_BLK3_DOUT7_M ((EFUSE_BLK3_DOUT7_V)<<(EFUSE_BLK3_DOUT7_S)) 810 #define EFUSE_BLK3_DOUT7_V 0xFFFFFFFF 811 #define EFUSE_BLK3_DOUT7_S 0 812 813 #define EFUSE_BLK1_WDATA0_REG (DR_REG_EFUSE_BASE + 0x098) 814 /* EFUSE_BLK1_DIN0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 815 /*description: program for BLOCK1*/ 816 #define EFUSE_BLK1_DIN0 0xFFFFFFFF 817 #define EFUSE_BLK1_DIN0_M ((EFUSE_BLK1_DIN0_V)<<(EFUSE_BLK1_DIN0_S)) 818 #define EFUSE_BLK1_DIN0_V 0xFFFFFFFF 819 #define EFUSE_BLK1_DIN0_S 0 820 821 #define EFUSE_BLK1_WDATA1_REG (DR_REG_EFUSE_BASE + 0x09c) 822 /* EFUSE_BLK1_DIN1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 823 /*description: program for BLOCK1*/ 824 #define EFUSE_BLK1_DIN1 0xFFFFFFFF 825 #define EFUSE_BLK1_DIN1_M ((EFUSE_BLK1_DIN1_V)<<(EFUSE_BLK1_DIN1_S)) 826 #define EFUSE_BLK1_DIN1_V 0xFFFFFFFF 827 #define EFUSE_BLK1_DIN1_S 0 828 829 #define EFUSE_BLK1_WDATA2_REG (DR_REG_EFUSE_BASE + 0x0a0) 830 /* EFUSE_BLK1_DIN2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 831 /*description: program for BLOCK1*/ 832 #define EFUSE_BLK1_DIN2 0xFFFFFFFF 833 #define EFUSE_BLK1_DIN2_M ((EFUSE_BLK1_DIN2_V)<<(EFUSE_BLK1_DIN2_S)) 834 #define EFUSE_BLK1_DIN2_V 0xFFFFFFFF 835 #define EFUSE_BLK1_DIN2_S 0 836 837 #define EFUSE_BLK1_WDATA3_REG (DR_REG_EFUSE_BASE + 0x0a4) 838 /* EFUSE_BLK1_DIN3 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 839 /*description: program for BLOCK1*/ 840 #define EFUSE_BLK1_DIN3 0xFFFFFFFF 841 #define EFUSE_BLK1_DIN3_M ((EFUSE_BLK1_DIN3_V)<<(EFUSE_BLK1_DIN3_S)) 842 #define EFUSE_BLK1_DIN3_V 0xFFFFFFFF 843 #define EFUSE_BLK1_DIN3_S 0 844 845 #define EFUSE_BLK1_WDATA4_REG (DR_REG_EFUSE_BASE + 0x0a8) 846 /* EFUSE_BLK1_DIN4 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 847 /*description: program for BLOCK1*/ 848 #define EFUSE_BLK1_DIN4 0xFFFFFFFF 849 #define EFUSE_BLK1_DIN4_M ((EFUSE_BLK1_DIN4_V)<<(EFUSE_BLK1_DIN4_S)) 850 #define EFUSE_BLK1_DIN4_V 0xFFFFFFFF 851 #define EFUSE_BLK1_DIN4_S 0 852 853 #define EFUSE_BLK1_WDATA5_REG (DR_REG_EFUSE_BASE + 0x0ac) 854 /* EFUSE_BLK1_DIN5 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 855 /*description: program for BLOCK1*/ 856 #define EFUSE_BLK1_DIN5 0xFFFFFFFF 857 #define EFUSE_BLK1_DIN5_M ((EFUSE_BLK1_DIN5_V)<<(EFUSE_BLK1_DIN5_S)) 858 #define EFUSE_BLK1_DIN5_V 0xFFFFFFFF 859 #define EFUSE_BLK1_DIN5_S 0 860 861 #define EFUSE_BLK1_WDATA6_REG (DR_REG_EFUSE_BASE + 0x0b0) 862 /* EFUSE_BLK1_DIN6 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 863 /*description: program for BLOCK1*/ 864 #define EFUSE_BLK1_DIN6 0xFFFFFFFF 865 #define EFUSE_BLK1_DIN6_M ((EFUSE_BLK1_DIN6_V)<<(EFUSE_BLK1_DIN6_S)) 866 #define EFUSE_BLK1_DIN6_V 0xFFFFFFFF 867 #define EFUSE_BLK1_DIN6_S 0 868 869 #define EFUSE_BLK1_WDATA7_REG (DR_REG_EFUSE_BASE + 0x0b4) 870 /* EFUSE_BLK1_DIN7 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 871 /*description: program for BLOCK1*/ 872 #define EFUSE_BLK1_DIN7 0xFFFFFFFF 873 #define EFUSE_BLK1_DIN7_M ((EFUSE_BLK1_DIN7_V)<<(EFUSE_BLK1_DIN7_S)) 874 #define EFUSE_BLK1_DIN7_V 0xFFFFFFFF 875 #define EFUSE_BLK1_DIN7_S 0 876 877 #define EFUSE_BLK2_WDATA0_REG (DR_REG_EFUSE_BASE + 0x0b8) 878 /* EFUSE_BLK2_DIN0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 879 /*description: program for BLOCK2*/ 880 #define EFUSE_BLK2_DIN0 0xFFFFFFFF 881 #define EFUSE_BLK2_DIN0_M ((EFUSE_BLK2_DIN0_V)<<(EFUSE_BLK2_DIN0_S)) 882 #define EFUSE_BLK2_DIN0_V 0xFFFFFFFF 883 #define EFUSE_BLK2_DIN0_S 0 884 885 #define EFUSE_BLK2_WDATA1_REG (DR_REG_EFUSE_BASE + 0x0bc) 886 /* EFUSE_BLK2_DIN1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 887 /*description: program for BLOCK2*/ 888 #define EFUSE_BLK2_DIN1 0xFFFFFFFF 889 #define EFUSE_BLK2_DIN1_M ((EFUSE_BLK2_DIN1_V)<<(EFUSE_BLK2_DIN1_S)) 890 #define EFUSE_BLK2_DIN1_V 0xFFFFFFFF 891 #define EFUSE_BLK2_DIN1_S 0 892 893 #define EFUSE_BLK2_WDATA2_REG (DR_REG_EFUSE_BASE + 0x0c0) 894 /* EFUSE_BLK2_DIN2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 895 /*description: program for BLOCK2*/ 896 #define EFUSE_BLK2_DIN2 0xFFFFFFFF 897 #define EFUSE_BLK2_DIN2_M ((EFUSE_BLK2_DIN2_V)<<(EFUSE_BLK2_DIN2_S)) 898 #define EFUSE_BLK2_DIN2_V 0xFFFFFFFF 899 #define EFUSE_BLK2_DIN2_S 0 900 901 #define EFUSE_BLK2_WDATA3_REG (DR_REG_EFUSE_BASE + 0x0c4) 902 /* EFUSE_BLK2_DIN3 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 903 /*description: program for BLOCK2*/ 904 #define EFUSE_BLK2_DIN3 0xFFFFFFFF 905 #define EFUSE_BLK2_DIN3_M ((EFUSE_BLK2_DIN3_V)<<(EFUSE_BLK2_DIN3_S)) 906 #define EFUSE_BLK2_DIN3_V 0xFFFFFFFF 907 #define EFUSE_BLK2_DIN3_S 0 908 909 #define EFUSE_BLK2_WDATA4_REG (DR_REG_EFUSE_BASE + 0x0c8) 910 /* EFUSE_BLK2_DIN4 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 911 /*description: program for BLOCK2*/ 912 #define EFUSE_BLK2_DIN4 0xFFFFFFFF 913 #define EFUSE_BLK2_DIN4_M ((EFUSE_BLK2_DIN4_V)<<(EFUSE_BLK2_DIN4_S)) 914 #define EFUSE_BLK2_DIN4_V 0xFFFFFFFF 915 #define EFUSE_BLK2_DIN4_S 0 916 917 #define EFUSE_BLK2_WDATA5_REG (DR_REG_EFUSE_BASE + 0x0cc) 918 /* EFUSE_BLK2_DIN5 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 919 /*description: program for BLOCK2*/ 920 #define EFUSE_BLK2_DIN5 0xFFFFFFFF 921 #define EFUSE_BLK2_DIN5_M ((EFUSE_BLK2_DIN5_V)<<(EFUSE_BLK2_DIN5_S)) 922 #define EFUSE_BLK2_DIN5_V 0xFFFFFFFF 923 #define EFUSE_BLK2_DIN5_S 0 924 925 #define EFUSE_BLK2_WDATA6_REG (DR_REG_EFUSE_BASE + 0x0d0) 926 /* EFUSE_BLK2_DIN6 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 927 /*description: program for BLOCK2*/ 928 #define EFUSE_BLK2_DIN6 0xFFFFFFFF 929 #define EFUSE_BLK2_DIN6_M ((EFUSE_BLK2_DIN6_V)<<(EFUSE_BLK2_DIN6_S)) 930 #define EFUSE_BLK2_DIN6_V 0xFFFFFFFF 931 #define EFUSE_BLK2_DIN6_S 0 932 933 #define EFUSE_BLK2_WDATA7_REG (DR_REG_EFUSE_BASE + 0x0d4) 934 /* EFUSE_BLK2_DIN7 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 935 /*description: program for BLOCK2*/ 936 #define EFUSE_BLK2_DIN7 0xFFFFFFFF 937 #define EFUSE_BLK2_DIN7_M ((EFUSE_BLK2_DIN7_V)<<(EFUSE_BLK2_DIN7_S)) 938 #define EFUSE_BLK2_DIN7_V 0xFFFFFFFF 939 #define EFUSE_BLK2_DIN7_S 0 940 941 #define EFUSE_BLK3_WDATA0_REG (DR_REG_EFUSE_BASE + 0x0d8) 942 /* EFUSE_BLK3_DIN0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 943 /*description: program for BLOCK3*/ 944 #define EFUSE_BLK3_DIN0 0xFFFFFFFF 945 #define EFUSE_BLK3_DIN0_M ((EFUSE_BLK3_DIN0_V)<<(EFUSE_BLK3_DIN0_S)) 946 #define EFUSE_BLK3_DIN0_V 0xFFFFFFFF 947 #define EFUSE_BLK3_DIN0_S 0 948 949 #define EFUSE_BLK3_WDATA1_REG (DR_REG_EFUSE_BASE + 0x0dc) 950 /* EFUSE_BLK3_DIN1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 951 /*description: program for BLOCK3*/ 952 #define EFUSE_BLK3_DIN1 0xFFFFFFFF 953 #define EFUSE_BLK3_DIN1_M ((EFUSE_BLK3_DIN1_V)<<(EFUSE_BLK3_DIN1_S)) 954 #define EFUSE_BLK3_DIN1_V 0xFFFFFFFF 955 #define EFUSE_BLK3_DIN1_S 0 956 957 #define EFUSE_BLK3_WDATA2_REG (DR_REG_EFUSE_BASE + 0x0e0) 958 /* EFUSE_BLK3_DIN2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 959 /*description: program for BLOCK3*/ 960 #define EFUSE_BLK3_DIN2 0xFFFFFFFF 961 #define EFUSE_BLK3_DIN2_M ((EFUSE_BLK3_DIN2_V)<<(EFUSE_BLK3_DIN2_S)) 962 #define EFUSE_BLK3_DIN2_V 0xFFFFFFFF 963 #define EFUSE_BLK3_DIN2_S 0 964 965 /* Note: Newer ESP32s utilize BLK3_DATA3 and parts of BLK3_DATA4 for calibration 966 * purposes. This usage is indicated by the EFUSE_RD_BLK3_PART_RESERVE bit.*/ 967 #define EFUSE_BLK3_WDATA3_REG (DR_REG_EFUSE_BASE + 0x0e4) 968 /* EFUSE_BLK3_DIN3 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 969 /*description: program for BLOCK3*/ 970 #define EFUSE_BLK3_DIN3 0xFFFFFFFF 971 #define EFUSE_BLK3_DIN3_M ((EFUSE_BLK3_DIN3_V)<<(EFUSE_BLK3_DIN3_S)) 972 #define EFUSE_BLK3_DIN3_V 0xFFFFFFFF 973 #define EFUSE_BLK3_DIN3_S 0 974 /* EFUSE_ADC2_TP_HIGH : R/W ;bitpos:[31:23] ;default: 9'b0 ; */ 975 /*description: ADC2 Two Point calibration high point. Only valid if EFUSE_RD_BLK3_PART_RESERVE */ 976 #define EFUSE_ADC2_TP_HIGH 0x1FF 977 #define EFUSE_ADC2_TP_HIGH_M ((EFUSE_ADC2_TP_HIGH_V)<<(EFUSE_ADC2_TP_HIGH_S)) 978 #define EFUSE_ADC2_TP_HIGH_V 0x1FF 979 #define EFUSE_ADC2_TP_HIGH_S 23 980 /* EFUSE_ADC2_TP_LOW : R/W ;bitpos:[22:16] ;default: 7'b0 ; */ 981 /*description: ADC2 Two Point calibration low point. Only valid if EFUSE_RD_BLK3_PART_RESERVE */ 982 #define EFUSE_ADC2_TP_LOW 0x7F 983 #define EFUSE_ADC2_TP_LOW_M ((EFUSE_ADC2_TP_LOW_V)<<(EFUSE_ADC2_TP_LOW_S)) 984 #define EFUSE_ADC2_TP_LOW_V 0x7F 985 #define EFUSE_ADC2_TP_LOW_S 16 986 /* EFUSE_ADC1_TP_HIGH : R/W ;bitpos:[15:7] ;default: 9'b0 ; */ 987 /*description: ADC1 Two Point calibration high point. Only valid if EFUSE_RD_BLK3_PART_RESERVE */ 988 #define EFUSE_ADC1_TP_HIGH 0x1FF 989 #define EFUSE_ADC1_TP_HIGH_M ((EFUSE_ADC1_TP_HIGH_V)<<(EFUSE_ADC1_TP_HIGH_S)) 990 #define EFUSE_ADC1_TP_HIGH_V 0x1FF 991 #define EFUSE_ADC1_TP_HIGH_S 7 992 /* EFUSE_ADC1_TP_LOW : R/W ;bitpos:[6:0] ;default: 7'b0 ; */ 993 /*description: ADC1 Two Point calibration low point. Only valid if EFUSE_RD_BLK3_PART_RESERVE */ 994 #define EFUSE_ADC1_TP_LOW 0x7F 995 #define EFUSE_ADC1_TP_LOW_M ((EFUSE_ADC1_TP_LOW_V)<<(EFUSE_ADC1_TP_LOW_S)) 996 #define EFUSE_ADC1_TP_LOW_V 0x7F 997 #define EFUSE_ADC1_TP_LOW_S 0 998 999 #define EFUSE_BLK3_WDATA4_REG (DR_REG_EFUSE_BASE + 0x0e8) 1000 /* EFUSE_BLK3_DIN4 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 1001 /*description: program for BLOCK3*/ 1002 #define EFUSE_BLK3_DIN4 0xFFFFFFFF 1003 #define EFUSE_BLK3_DIN4_M ((EFUSE_BLK3_DIN4_V)<<(EFUSE_BLK3_DIN4_S)) 1004 #define EFUSE_BLK3_DIN4_V 0xFFFFFFFF 1005 #define EFUSE_BLK3_DIN4_S 0 1006 /* EFUSE_CAL_RESERVED: R/W ; bitpos:[0:15] ; default : 16'h0 ; */ 1007 /*description: Reserved for future calibration use. Indicated by EFUSE_BLK3_PART_RESERVE */ 1008 #define EFUSE_CAL_RESERVED 0x0000FFFF 1009 #define EFUSE_CAL_RESERVED_M ((EFUSE_CAL_RESERVED_V)<<(EFUSE_CAL_RESERVED_S)) 1010 #define EFUSE_CAL_RESERVED_V 0xFFFF 1011 #define EFUSE_CAL_RESERVED_S 0 1012 1013 #define EFUSE_BLK3_WDATA5_REG (DR_REG_EFUSE_BASE + 0x0ec) 1014 /* EFUSE_BLK3_DIN5 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 1015 /*description: program for BLOCK3*/ 1016 #define EFUSE_BLK3_DIN5 0xFFFFFFFF 1017 #define EFUSE_BLK3_DIN5_M ((EFUSE_BLK3_DIN5_V)<<(EFUSE_BLK3_DIN5_S)) 1018 #define EFUSE_BLK3_DIN5_V 0xFFFFFFFF 1019 #define EFUSE_BLK3_DIN5_S 0 1020 1021 #define EFUSE_BLK3_WDATA6_REG (DR_REG_EFUSE_BASE + 0x0f0) 1022 /* EFUSE_BLK3_DIN6 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 1023 /*description: program for BLOCK3*/ 1024 #define EFUSE_BLK3_DIN6 0xFFFFFFFF 1025 #define EFUSE_BLK3_DIN6_M ((EFUSE_BLK3_DIN6_V)<<(EFUSE_BLK3_DIN6_S)) 1026 #define EFUSE_BLK3_DIN6_V 0xFFFFFFFF 1027 #define EFUSE_BLK3_DIN6_S 0 1028 1029 #define EFUSE_BLK3_WDATA7_REG (DR_REG_EFUSE_BASE + 0x0f4) 1030 /* EFUSE_BLK3_DIN7 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 1031 /*description: program for BLOCK3*/ 1032 #define EFUSE_BLK3_DIN7 0xFFFFFFFF 1033 #define EFUSE_BLK3_DIN7_M ((EFUSE_BLK3_DIN7_V)<<(EFUSE_BLK3_DIN7_S)) 1034 #define EFUSE_BLK3_DIN7_V 0xFFFFFFFF 1035 #define EFUSE_BLK3_DIN7_S 0 1036 1037 #define EFUSE_CLK_REG (DR_REG_EFUSE_BASE + 0x0f8) 1038 /* EFUSE_CLK_EN : R/W ;bitpos:[16] ;default: 1'b0 ; */ 1039 /*description: */ 1040 #define EFUSE_CLK_EN (BIT(16)) 1041 #define EFUSE_CLK_EN_M (BIT(16)) 1042 #define EFUSE_CLK_EN_V 0x1 1043 #define EFUSE_CLK_EN_S 16 1044 /* EFUSE_CLK_SEL1 : R/W ;bitpos:[15:8] ;default: 8'h40 ; */ 1045 /*description: efuse timing configure*/ 1046 #define EFUSE_CLK_SEL1 0x000000FF 1047 #define EFUSE_CLK_SEL1_M ((EFUSE_CLK_SEL1_V)<<(EFUSE_CLK_SEL1_S)) 1048 #define EFUSE_CLK_SEL1_V 0xFF 1049 #define EFUSE_CLK_SEL1_S 8 1050 /* EFUSE_CLK_SEL0 : R/W ;bitpos:[7:0] ;default: 8'h52 ; */ 1051 /*description: efuse timing configure*/ 1052 #define EFUSE_CLK_SEL0 0x000000FF 1053 #define EFUSE_CLK_SEL0_M ((EFUSE_CLK_SEL0_V)<<(EFUSE_CLK_SEL0_S)) 1054 #define EFUSE_CLK_SEL0_V 0xFF 1055 #define EFUSE_CLK_SEL0_S 0 1056 1057 #define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x0fc) 1058 /* EFUSE_FORCE_NO_WR_RD_DIS : R/W ;bitpos:[16] ;default: 1'h1 ; */ 1059 /*description: */ 1060 #define EFUSE_FORCE_NO_WR_RD_DIS (BIT(16)) 1061 #define EFUSE_FORCE_NO_WR_RD_DIS_M (BIT(16)) 1062 #define EFUSE_FORCE_NO_WR_RD_DIS_V 0x1 1063 #define EFUSE_FORCE_NO_WR_RD_DIS_S 16 1064 /* EFUSE_OP_CODE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ 1065 /*description: efuse operation code*/ 1066 #define EFUSE_OP_CODE 0x0000FFFF 1067 #define EFUSE_OP_CODE_M ((EFUSE_OP_CODE_V)<<(EFUSE_OP_CODE_S)) 1068 #define EFUSE_OP_CODE_V 0xFFFF 1069 #define EFUSE_OP_CODE_S 0 1070 1071 #define EFUSE_STATUS_REG (DR_REG_EFUSE_BASE + 0x100) 1072 /* EFUSE_DEBUG : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 1073 /*description: */ 1074 #define EFUSE_DEBUG 0xFFFFFFFF 1075 #define EFUSE_DEBUG_M ((EFUSE_DEBUG_V)<<(EFUSE_DEBUG_S)) 1076 #define EFUSE_DEBUG_V 0xFFFFFFFF 1077 #define EFUSE_DEBUG_S 0 1078 1079 #define EFUSE_CMD_REG (DR_REG_EFUSE_BASE + 0x104) 1080 /* EFUSE_PGM_CMD : R/W ;bitpos:[1] ;default: 1'b0 ; */ 1081 /*description: command for program*/ 1082 #define EFUSE_PGM_CMD (BIT(1)) 1083 #define EFUSE_PGM_CMD_M (BIT(1)) 1084 #define EFUSE_PGM_CMD_V 0x1 1085 #define EFUSE_PGM_CMD_S 1 1086 /* EFUSE_READ_CMD : R/W ;bitpos:[0] ;default: 1'b0 ; */ 1087 /*description: command for read*/ 1088 #define EFUSE_READ_CMD (BIT(0)) 1089 #define EFUSE_READ_CMD_M (BIT(0)) 1090 #define EFUSE_READ_CMD_V 0x1 1091 #define EFUSE_READ_CMD_S 0 1092 1093 #define EFUSE_INT_RAW_REG (DR_REG_EFUSE_BASE + 0x108) 1094 /* EFUSE_PGM_DONE_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ 1095 /*description: program done interrupt raw status*/ 1096 #define EFUSE_PGM_DONE_INT_RAW (BIT(1)) 1097 #define EFUSE_PGM_DONE_INT_RAW_M (BIT(1)) 1098 #define EFUSE_PGM_DONE_INT_RAW_V 0x1 1099 #define EFUSE_PGM_DONE_INT_RAW_S 1 1100 /* EFUSE_READ_DONE_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ 1101 /*description: read done interrupt raw status*/ 1102 #define EFUSE_READ_DONE_INT_RAW (BIT(0)) 1103 #define EFUSE_READ_DONE_INT_RAW_M (BIT(0)) 1104 #define EFUSE_READ_DONE_INT_RAW_V 0x1 1105 #define EFUSE_READ_DONE_INT_RAW_S 0 1106 1107 #define EFUSE_INT_ST_REG (DR_REG_EFUSE_BASE + 0x10c) 1108 /* EFUSE_PGM_DONE_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ 1109 /*description: program done interrupt status*/ 1110 #define EFUSE_PGM_DONE_INT_ST (BIT(1)) 1111 #define EFUSE_PGM_DONE_INT_ST_M (BIT(1)) 1112 #define EFUSE_PGM_DONE_INT_ST_V 0x1 1113 #define EFUSE_PGM_DONE_INT_ST_S 1 1114 /* EFUSE_READ_DONE_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ 1115 /*description: read done interrupt status*/ 1116 #define EFUSE_READ_DONE_INT_ST (BIT(0)) 1117 #define EFUSE_READ_DONE_INT_ST_M (BIT(0)) 1118 #define EFUSE_READ_DONE_INT_ST_V 0x1 1119 #define EFUSE_READ_DONE_INT_ST_S 0 1120 1121 #define EFUSE_INT_ENA_REG (DR_REG_EFUSE_BASE + 0x110) 1122 /* EFUSE_PGM_DONE_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ 1123 /*description: program done interrupt enable*/ 1124 #define EFUSE_PGM_DONE_INT_ENA (BIT(1)) 1125 #define EFUSE_PGM_DONE_INT_ENA_M (BIT(1)) 1126 #define EFUSE_PGM_DONE_INT_ENA_V 0x1 1127 #define EFUSE_PGM_DONE_INT_ENA_S 1 1128 /* EFUSE_READ_DONE_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ 1129 /*description: read done interrupt enable*/ 1130 #define EFUSE_READ_DONE_INT_ENA (BIT(0)) 1131 #define EFUSE_READ_DONE_INT_ENA_M (BIT(0)) 1132 #define EFUSE_READ_DONE_INT_ENA_V 0x1 1133 #define EFUSE_READ_DONE_INT_ENA_S 0 1134 1135 #define EFUSE_INT_CLR_REG (DR_REG_EFUSE_BASE + 0x114) 1136 /* EFUSE_PGM_DONE_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ 1137 /*description: program done interrupt clear*/ 1138 #define EFUSE_PGM_DONE_INT_CLR (BIT(1)) 1139 #define EFUSE_PGM_DONE_INT_CLR_M (BIT(1)) 1140 #define EFUSE_PGM_DONE_INT_CLR_V 0x1 1141 #define EFUSE_PGM_DONE_INT_CLR_S 1 1142 /* EFUSE_READ_DONE_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ 1143 /*description: read done interrupt clear*/ 1144 #define EFUSE_READ_DONE_INT_CLR (BIT(0)) 1145 #define EFUSE_READ_DONE_INT_CLR_M (BIT(0)) 1146 #define EFUSE_READ_DONE_INT_CLR_V 0x1 1147 #define EFUSE_READ_DONE_INT_CLR_S 0 1148 1149 #define EFUSE_DAC_CONF_REG (DR_REG_EFUSE_BASE + 0x118) 1150 /* EFUSE_DAC_CLK_PAD_SEL : R/W ;bitpos:[8] ;default: 1'b0 ; */ 1151 /*description: */ 1152 #define EFUSE_DAC_CLK_PAD_SEL (BIT(8)) 1153 #define EFUSE_DAC_CLK_PAD_SEL_M (BIT(8)) 1154 #define EFUSE_DAC_CLK_PAD_SEL_V 0x1 1155 #define EFUSE_DAC_CLK_PAD_SEL_S 8 1156 /* EFUSE_DAC_CLK_DIV : R/W ;bitpos:[7:0] ;default: 8'd40 ; */ 1157 /*description: efuse timing configure*/ 1158 #define EFUSE_DAC_CLK_DIV 0x000000FF 1159 #define EFUSE_DAC_CLK_DIV_M ((EFUSE_DAC_CLK_DIV_V)<<(EFUSE_DAC_CLK_DIV_S)) 1160 #define EFUSE_DAC_CLK_DIV_V 0xFF 1161 #define EFUSE_DAC_CLK_DIV_S 0 1162 1163 #define EFUSE_DEC_STATUS_REG (DR_REG_EFUSE_BASE + 0x11c) 1164 /* EFUSE_DEC_WARNINGS : RO ;bitpos:[11:0] ;default: 12'b0 ; */ 1165 /*description: the decode result of 3/4 coding scheme has warning*/ 1166 #define EFUSE_DEC_WARNINGS 0x00000FFF 1167 #define EFUSE_DEC_WARNINGS_M ((EFUSE_DEC_WARNINGS_V)<<(EFUSE_DEC_WARNINGS_S)) 1168 #define EFUSE_DEC_WARNINGS_V 0xFFF 1169 #define EFUSE_DEC_WARNINGS_S 0 1170 1171 #define EFUSE_DATE_REG (DR_REG_EFUSE_BASE + 0x1FC) 1172 /* EFUSE_DATE : R/W ;bitpos:[31:0] ;default: 32'h16042600 ; */ 1173 /*description: */ 1174 #define EFUSE_DATE 0xFFFFFFFF 1175 #define EFUSE_DATE_M ((EFUSE_DATE_V)<<(EFUSE_DATE_S)) 1176 #define EFUSE_DATE_V 0xFFFFFFFF 1177 #define EFUSE_DATE_S 0 1178 1179 1180 1181 1182 #endif /*_SOC_EFUSE_REG_H_ */ 1183
