Searched refs:DR_REG_SYSTEM_BASE (Results 1 – 8 of 8) sorted by relevance
22 #define DPORT_ROM_CTRL_0_REG (DR_REG_SYSTEM_BASE + 0x000)30 #define DPORT_ROM_CTRL_1_REG (DR_REG_SYSTEM_BASE + 0x004)44 #define DPORT_SRAM_CTRL_0_REG (DR_REG_SYSTEM_BASE + 0x008)52 #define DPORT_SRAM_CTRL_1_REG (DR_REG_SYSTEM_BASE + 0x00C)61 #define DPORT_CPU_PERI_CLK_EN_REG (DR_REG_SYSTEM_BASE + 0x010)79 #define DPORT_CPU_PERI_RST_EN_REG (DR_REG_SYSTEM_BASE + 0x014)93 #define DPORT_CPU_PER_CONF_REG (DR_REG_SYSTEM_BASE + 0x018)119 #define DPORT_JTAG_CTRL_0_REG (DR_REG_SYSTEM_BASE + 0x01C)127 #define DPORT_JTAG_CTRL_1_REG (DR_REG_SYSTEM_BASE + 0x020)135 #define DPORT_JTAG_CTRL_2_REG (DR_REG_SYSTEM_BASE + 0x024)[all …]
27 #define DR_REG_SYSTEM_BASE 0x3f4c0000 macro
23 #define SYSTEM_CPU_PERI_CLK_EN_REG (DR_REG_SYSTEM_BASE + 0x000)37 #define SYSTEM_CPU_PERI_RST_EN_REG (DR_REG_SYSTEM_BASE + 0x004)51 #define SYSTEM_CPU_PER_CONF_REG (DR_REG_SYSTEM_BASE + 0x008)65 #define SYSTEM_MEM_PD_MASK_REG (DR_REG_SYSTEM_BASE + 0x00C)73 #define SYSTEM_CPU_INTR_FROM_CPU_0_REG (DR_REG_SYSTEM_BASE + 0x010)81 #define SYSTEM_CPU_INTR_FROM_CPU_1_REG (DR_REG_SYSTEM_BASE + 0x014)89 #define SYSTEM_CPU_INTR_FROM_CPU_2_REG (DR_REG_SYSTEM_BASE + 0x018)97 #define SYSTEM_CPU_INTR_FROM_CPU_3_REG (DR_REG_SYSTEM_BASE + 0x01C)105 #define SYSTEM_RSA_PD_CTRL_REG (DR_REG_SYSTEM_BASE + 0x020)125 #define SYSTEM_EDMA_CTRL_REG (DR_REG_SYSTEM_BASE + 0x024)[all …]
27 #define DR_REG_SYSTEM_BASE 0x600c0000 macro
23 #define SYSTEM_CORE_1_CONTROL_0_REG (DR_REG_SYSTEM_BASE + 0x0)43 #define SYSTEM_CORE_1_CONTROL_1_REG (DR_REG_SYSTEM_BASE + 0x4)51 #define SYSTEM_CPU_PERI_CLK_EN_REG (DR_REG_SYSTEM_BASE + 0x8)65 #define SYSTEM_CPU_PERI_RST_EN_REG (DR_REG_SYSTEM_BASE + 0xC)79 #define SYSTEM_CPU_PER_CONF_REG (DR_REG_SYSTEM_BASE + 0x10)105 #define SYSTEM_MEM_PD_MASK_REG (DR_REG_SYSTEM_BASE + 0x14)113 #define SYSTEM_PERIP_CLK_EN0_REG (DR_REG_SYSTEM_BASE + 0x18)307 #define SYSTEM_PERIP_CLK_EN1_REG (DR_REG_SYSTEM_BASE + 0x1C)375 #define SYSTEM_PERIP_RST_EN0_REG (DR_REG_SYSTEM_BASE + 0x20)569 #define SYSTEM_PERIP_RST_EN1_REG (DR_REG_SYSTEM_BASE + 0x24)[all …]
98 #define DR_REG_SYSTEM_BASE 0x600C0000 macro
22 #define SYSTEM_CPU_PERI_CLK_EN_REG (DR_REG_SYSTEM_BASE + 0x000)36 #define SYSTEM_CPU_PERI_RST_EN_REG (DR_REG_SYSTEM_BASE + 0x004)50 #define SYSTEM_CPU_PER_CONF_REG (DR_REG_SYSTEM_BASE + 0x008)76 #define SYSTEM_MEM_PD_MASK_REG (DR_REG_SYSTEM_BASE + 0x00C)84 #define SYSTEM_PERIP_CLK_EN0_REG (DR_REG_SYSTEM_BASE + 0x010)278 #define SYSTEM_PERIP_CLK_EN1_REG (DR_REG_SYSTEM_BASE + 0x014)340 #define SYSTEM_PERIP_RST_EN0_REG (DR_REG_SYSTEM_BASE + 0x018)534 #define SYSTEM_PERIP_RST_EN1_REG (DR_REG_SYSTEM_BASE + 0x01C)596 #define SYSTEM_BT_LPCK_DIV_INT_REG (DR_REG_SYSTEM_BASE + 0x020)604 #define SYSTEM_BT_LPCK_DIV_FRAC_REG (DR_REG_SYSTEM_BASE + 0x024)[all …]
