DR_REG_RTCIO_BASE (reference) in projects: hal_espressif-3.6.0

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Searched refs:DR_REG_RTCIO_BASE (Results 1 – 10 of 10) sorted by relevance

/hal_espressif-3.6.0/components/soc/esp32s3/include/soc/
D	rtc_io_reg.h	23 #define RTC_GPIO_OUT_REG (DR_REG_RTCIO_BASE + 0x0) 31 #define RTC_GPIO_OUT_W1TS_REG (DR_REG_RTCIO_BASE + 0x4) 39 #define RTC_GPIO_OUT_W1TC_REG (DR_REG_RTCIO_BASE + 0x8) 47 #define RTC_GPIO_ENABLE_REG (DR_REG_RTCIO_BASE + 0xC) 55 #define RTC_GPIO_ENABLE_W1TS_REG (DR_REG_RTCIO_BASE + 0x10) 63 #define RTC_GPIO_ENABLE_W1TC_REG (DR_REG_RTCIO_BASE + 0x14) 71 #define RTC_GPIO_STATUS_REG (DR_REG_RTCIO_BASE + 0x18) 79 #define RTC_GPIO_STATUS_W1TS_REG (DR_REG_RTCIO_BASE + 0x1C) 87 #define RTC_GPIO_STATUS_W1TC_REG (DR_REG_RTCIO_BASE + 0x20) 95 #define RTC_GPIO_IN_REG (DR_REG_RTCIO_BASE + 0x24) [all …]
D	soc.h	`40 #define DR_REG_RTCIO_BASE 0x60008400 macro`
/hal_espressif-3.6.0/components/soc/esp32s2/include/soc/
D	rtc_io_reg.h	22 #define RTC_GPIO_OUT_REG (DR_REG_RTCIO_BASE + 0x0) 30 #define RTC_GPIO_OUT_W1TS_REG (DR_REG_RTCIO_BASE + 0x4) 38 #define RTC_GPIO_OUT_W1TC_REG (DR_REG_RTCIO_BASE + 0x8) 46 #define RTC_GPIO_ENABLE_REG (DR_REG_RTCIO_BASE + 0xC) 54 #define RTC_GPIO_ENABLE_W1TS_REG (DR_REG_RTCIO_BASE + 0x10) 62 #define RTC_GPIO_ENABLE_W1TC_REG (DR_REG_RTCIO_BASE + 0x14) 70 #define RTC_GPIO_STATUS_REG (DR_REG_RTCIO_BASE + 0x18) 78 #define RTC_GPIO_STATUS_W1TS_REG (DR_REG_RTCIO_BASE + 0x1C) 86 #define RTC_GPIO_STATUS_W1TC_REG (DR_REG_RTCIO_BASE + 0x20) 94 #define RTC_GPIO_IN_REG (DR_REG_RTCIO_BASE + 0x24) [all …]
D	soc.h	`54 #define DR_REG_RTCIO_BASE 0x3f408400 macro`
/hal_espressif-3.6.0/components/soc/esp32/include/soc/
D	rtc_io_reg.h	19 #define RTC_GPIO_OUT_REG (DR_REG_RTCIO_BASE + 0x0) 27 #define RTC_GPIO_OUT_W1TS_REG (DR_REG_RTCIO_BASE + 0x4) 35 #define RTC_GPIO_OUT_W1TC_REG (DR_REG_RTCIO_BASE + 0x8) 43 #define RTC_GPIO_ENABLE_REG (DR_REG_RTCIO_BASE + 0xc) 51 #define RTC_GPIO_ENABLE_W1TS_REG (DR_REG_RTCIO_BASE + 0x10) 59 #define RTC_GPIO_ENABLE_W1TC_REG (DR_REG_RTCIO_BASE + 0x14) 67 #define RTC_GPIO_STATUS_REG (DR_REG_RTCIO_BASE + 0x18) 75 #define RTC_GPIO_STATUS_W1TS_REG (DR_REG_RTCIO_BASE + 0x1c) 83 #define RTC_GPIO_STATUS_W1TC_REG (DR_REG_RTCIO_BASE + 0x20) 91 #define RTC_GPIO_IN_REG (DR_REG_RTCIO_BASE + 0x24) [all …]
D	soc.h	`47 #define DR_REG_RTCIO_BASE 0x3ff48400 macro`
/hal_espressif-3.6.0/components/soc/esp32h2/include/soc/
D	soc.h	`56 #define DR_REG_RTCIO_BASE 0x60008400 macro`
/hal_espressif-3.6.0/components/ulp/include/esp32s3/
D	ulp.h	`294 } else if (reg < DR_REG_RTCIO_BASE) { in SOC_REG_TO_ULP_PERIPH_SEL()`
/hal_espressif-3.6.0/components/ulp/include/esp32s2/
D	ulp.h	`293 } else if (reg < DR_REG_RTCIO_BASE) { in SOC_REG_TO_ULP_PERIPH_SEL()`
/hal_espressif-3.6.0/components/ulp/include/esp32/
D	ulp.h	`327 } else if (reg < DR_REG_RTCIO_BASE) { in SOC_REG_TO_ULP_PERIPH_SEL()`

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