DR_REG_RTCCNTL_BASE (reference) in projects: hal_espressif-3.6.0

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Searched refs:DR_REG_RTCCNTL_BASE (Results 1 – 18 of 18) sorted by relevance

/hal_espressif-3.6.0/components/soc/esp32h2/include/soc/
D	rtc_cntl_reg.h	40 #define RTC_CNTL_OPTIONS0_REG (DR_REG_RTCCNTL_BASE + 0x0000) 194 #define RTC_CNTL_SLP_TIMER0_REG (DR_REG_RTCCNTL_BASE + 0x0004) 202 #define RTC_CNTL_SLP_TIMER1_REG (DR_REG_RTCCNTL_BASE + 0x0008) 216 #define RTC_CNTL_TIME_UPDATE_REG (DR_REG_RTCCNTL_BASE + 0x000C) 242 #define RTC_CNTL_TIME_LOW0_REG (DR_REG_RTCCNTL_BASE + 0x0010) 250 #define RTC_CNTL_TIME_HIGH0_REG (DR_REG_RTCCNTL_BASE + 0x0014) 258 #define RTC_CNTL_STATE0_REG (DR_REG_RTCCNTL_BASE + 0x0018) 302 #define RTC_CNTL_TIMER1_REG (DR_REG_RTCCNTL_BASE + 0x001C) 337 #define RTC_CNTL_TIMER2_REG (DR_REG_RTCCNTL_BASE + 0x0020) 345 #define RTC_CNTL_TIMER3_REG (DR_REG_RTCCNTL_BASE + 0x0024) [all …]
D	soc.h	`55 #define DR_REG_RTCCNTL_BASE 0x60008000 macro`
/hal_espressif-3.6.0/components/soc/esp32c3/include/soc/
D	rtc_cntl_reg.h	40 #define RTC_CNTL_OPTIONS0_REG (DR_REG_RTCCNTL_BASE + 0x0000) 182 #define RTC_CNTL_SLP_TIMER0_REG (DR_REG_RTCCNTL_BASE + 0x0004) 190 #define RTC_CNTL_SLP_TIMER1_REG (DR_REG_RTCCNTL_BASE + 0x0008) 204 #define RTC_CNTL_TIME_UPDATE_REG (DR_REG_RTCCNTL_BASE + 0x000C) 230 #define RTC_CNTL_TIME_LOW0_REG (DR_REG_RTCCNTL_BASE + 0x0010) 238 #define RTC_CNTL_TIME_HIGH0_REG (DR_REG_RTCCNTL_BASE + 0x0014) 246 #define RTC_CNTL_STATE0_REG (DR_REG_RTCCNTL_BASE + 0x0018) 290 #define RTC_CNTL_TIMER1_REG (DR_REG_RTCCNTL_BASE + 0x001C) 325 #define RTC_CNTL_TIMER2_REG (DR_REG_RTCCNTL_BASE + 0x0020) 333 #define RTC_CNTL_TIMER3_REG (DR_REG_RTCCNTL_BASE + 0x0024) [all …]
D	soc.h	`48 #define DR_REG_RTCCNTL_BASE 0x60008000 macro`
/hal_espressif-3.6.0/components/soc/esp32/include/soc/
D	rtc_cntl_reg.h	31 #define RTC_CNTL_OPTIONS0_REG (DR_REG_RTCCNTL_BASE + 0x0) 215 #define RTC_CNTL_SLP_TIMER0_REG (DR_REG_RTCCNTL_BASE + 0x4) 223 #define RTC_CNTL_SLP_TIMER1_REG (DR_REG_RTCCNTL_BASE + 0x8) 237 #define RTC_CNTL_TIME_UPDATE_REG (DR_REG_RTCCNTL_BASE + 0xc) 251 #define RTC_CNTL_TIME0_REG (DR_REG_RTCCNTL_BASE + 0x10) 259 #define RTC_CNTL_TIME1_REG (DR_REG_RTCCNTL_BASE + 0x14) 267 #define RTC_CNTL_STATE0_REG (DR_REG_RTCCNTL_BASE + 0x18) 323 #define RTC_CNTL_TIMER1_REG (DR_REG_RTCCNTL_BASE + 0x1c) 358 #define RTC_CNTL_TIMER2_REG (DR_REG_RTCCNTL_BASE + 0x20) 373 #define RTC_CNTL_TIMER3_REG (DR_REG_RTCCNTL_BASE + 0x24) [all …]
D	soc_ulp.h	`33 REG_RD (((rtc_reg) - DR_REG_RTCCNTL_BASE) / 4), ((low_bit) + (bit_width) - 1), (low_bit) 37 …REG_WR (((rtc_reg) - DR_REG_RTCCNTL_BASE) / 4), ((low_bit) + (bit_width) - 1), (low_bit), ((value)…`
D	soc.h	`46 #define DR_REG_RTCCNTL_BASE 0x3ff48000 macro`
/hal_espressif-3.6.0/components/soc/esp32s2/include/soc/
D	rtc_cntl_reg.h	37 #define RTC_CNTL_OPTIONS0_REG (DR_REG_RTCCNTL_BASE + 0x0000) 173 #define RTC_CNTL_SLP_TIMER0_REG (DR_REG_RTCCNTL_BASE + 0x0004) 181 #define RTC_CNTL_SLP_TIMER1_REG (DR_REG_RTCCNTL_BASE + 0x0008) 195 #define RTC_CNTL_TIME_UPDATE_REG (DR_REG_RTCCNTL_BASE + 0x000C) 221 #define RTC_CNTL_TIME_LOW0_REG (DR_REG_RTCCNTL_BASE + 0x0010) 229 #define RTC_CNTL_TIME_HIGH0_REG (DR_REG_RTCCNTL_BASE + 0x0014) 237 #define RTC_CNTL_STATE0_REG (DR_REG_RTCCNTL_BASE + 0x0018) 281 #define RTC_CNTL_TIMER1_REG (DR_REG_RTCCNTL_BASE + 0x001C) 313 #define RTC_CNTL_TIMER2_REG (DR_REG_RTCCNTL_BASE + 0x0020) 328 #define RTC_CNTL_TIMER3_REG (DR_REG_RTCCNTL_BASE + 0x0024) [all …]
D	soc_ulp.h	`33 REG_RD (((rtc_reg) - DR_REG_RTCCNTL_BASE) / 4), ((low_bit) + (bit_width) - 1), (low_bit) 37 …REG_WR (((rtc_reg) - DR_REG_RTCCNTL_BASE) / 4), ((low_bit) + (bit_width) - 1), (low_bit), ((value)…`
D	soc.h	`53 #define DR_REG_RTCCNTL_BASE 0x3f408000 macro`
/hal_espressif-3.6.0/components/soc/esp32s3/include/soc/
D	rtc_cntl_reg.h	22 #define RTC_CNTL_OPTIONS0_REG (DR_REG_RTCCNTL_BASE + 0x0) 158 #define RTC_CNTL_SLP_TIMER0_REG (DR_REG_RTCCNTL_BASE + 0x4) 166 #define RTC_CNTL_SLP_TIMER1_REG (DR_REG_RTCCNTL_BASE + 0x8) 180 #define RTC_CNTL_TIME_UPDATE_REG (DR_REG_RTCCNTL_BASE + 0xC) 206 #define RTC_CNTL_TIME_LOW0_REG (DR_REG_RTCCNTL_BASE + 0x10) 214 #define RTC_CNTL_TIME_HIGH0_REG (DR_REG_RTCCNTL_BASE + 0x14) 222 #define RTC_CNTL_STATE0_REG (DR_REG_RTCCNTL_BASE + 0x18) 266 #define RTC_CNTL_TIMER1_REG (DR_REG_RTCCNTL_BASE + 0x1C) 298 #define RTC_CNTL_TIMER2_REG (DR_REG_RTCCNTL_BASE + 0x20) 313 #define RTC_CNTL_TIMER3_REG (DR_REG_RTCCNTL_BASE + 0x24) [all …]
D	soc_ulp.h	`33 REG_RD (((rtc_reg) - DR_REG_RTCCNTL_BASE) / 4), ((low_bit) + (bit_width) - 1), (low_bit) 37 …REG_WR (((rtc_reg) - DR_REG_RTCCNTL_BASE) / 4), ((low_bit) + (bit_width) - 1), (low_bit), ((value)…`
D	soc.h	`39 #define DR_REG_RTCCNTL_BASE 0x60008000 macro`
/hal_espressif-3.6.0/components/ulp/include/esp32s3/
D	ulp.h	`292 if (reg < DR_REG_RTCCNTL_BASE) { in SOC_REG_TO_ULP_PERIPH_SEL()`
/hal_espressif-3.6.0/components/ulp/include/esp32s2/
D	ulp.h	`291 if (reg < DR_REG_RTCCNTL_BASE) { in SOC_REG_TO_ULP_PERIPH_SEL()`
/hal_espressif-3.6.0/components/ulp/include/esp32/
D	ulp.h	`325 if (reg < DR_REG_RTCCNTL_BASE) { in SOC_REG_TO_ULP_PERIPH_SEL()`
/hal_espressif-3.6.0/docs/en/api-guides/
D	ulp_instruction_set.rst	`866 addr_ulp = (addr_dport - DR_REG_RTCCNTL_BASE) / 4 893 addr_ulp = (addr_dport - DR_REG_RTCCNTL_BASE) / 4`
D	ulps2_instruction_set.rst	`1024 addr_ulp = (addr_peribus1 - DR_REG_RTCCNTL_BASE) / 4 1051 addr_ulp = (addr_peribus1 - DR_REG_RTCCNTL_BASE) / 4`

TraceRecorderSource-2.7.6
TraceRecorderSource-3.4.0
Zephyr-Core-2.7.6
Zephyr-Core-3.4.0
Zephyr-Core-3.5.0
Zephyr-Core-3.6.0
Zephyr-Core-3.7.0
acpica-3.5.0
acpica-3.6.0
acpica-3.7.0
babblesim_base-3.4.0
babblesim_base-3.6.0-3.5.0
babblesim_base-3.7.0
babblesim_ext_2G4_channel_NtNcable-3.7.0-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_channel_multiatt-3.4.0
babblesim_ext_2G4_channel_multiatt-3.7.0-3.6.0-3.5.0
babblesim_ext_2G4_device_WLAN_actmod-3.7.0-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_device_burst_interferer-3.7.0-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_device_playback-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_device_playback-3.7.0
babblesim_ext_2G4_libPhyComv1-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_libPhyComv1-3.7.0
babblesim_ext_2G4_modem_BLE_simple-3.4.0
babblesim_ext_2G4_modem_BLE_simple-3.6.0-3.5.0
babblesim_ext_2G4_modem_BLE_simple-3.7.0
babblesim_ext_2G4_modem_magic-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_modem_magic-3.7.0
babblesim_ext_2G4_phy_v1-3.4.0
babblesim_ext_2G4_phy_v1-3.6.0-3.5.0
babblesim_ext_2G4_phy_v1-3.7.0
babblesim_ext_libCryptov1-3.7.0-3.6.0-3.5.0-3.4.0
bsim-3.4.0
bsim-3.6.0-3.5.0
bsim-3.7.0
canopennode-2.7.6
canopennode-3.5.0-3.4.0
chre-3.4.0
civetweb-2.7.6
cmsis-2.7.6
cmsis-3.4.0
cmsis-3.5.0
cmsis-3.7.0-3.6.0
cmsis-dsp-3.5.0
cmsis-dsp-3.7.0-3.6.0
cmsis-nn-3.6.0-3.5.0
cmsis-nn-3.7.0
edtt-2.7.6
edtt-3.6.0-3.5.0-3.4.0
edtt-3.7.0
fatfs-2.7.6
fatfs-3.7.0-3.6.0-3.5.0-3.4.0
hal_adi-3.7.0
hal_altera-2.7.6
hal_altera-3.6.0-3.5.0-3.4.0
hal_altera-3.7.0
hal_ambiq-3.5.0
hal_ambiq-3.6.0
hal_ambiq-3.7.0
hal_atmel-2.7.6
hal_atmel-3.5.0-3.4.0
hal_atmel-3.6.0
hal_atmel-3.7.0
hal_cypress-2.7.6
hal_espressif-2.7.6
hal_espressif-3.4.0
hal_espressif-3.5.0
hal_espressif-3.6.0
hal_espressif-3.7.0
hal_ethos_u-3.6.0-3.5.0-3.4.0
hal_ethos_u-3.7.0
hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0
hal_infineon-2.7.6
hal_infineon-3.4.0
hal_infineon-3.5.0
hal_infineon-3.6.0
hal_infineon-3.7.0
hal_intel-3.5.0
hal_intel-3.6.0
hal_intel-3.7.0
hal_microchip-2.7.6
hal_microchip-3.6.0-3.5.0-3.4.0
hal_microchip-3.7.0
hal_nordic-2.7.6
hal_nordic-3.4.0
hal_nordic-3.5.0
hal_nordic-3.6.0
hal_nordic-3.7.0
hal_nuvoton-2.7.6
hal_nuvoton-3.4.0
hal_nuvoton-3.5.0
hal_nuvoton-3.6.0
hal_nuvoton-3.7.0
hal_nxp-2.7.6
hal_nxp-3.4.0
hal_nxp-3.5.0
hal_nxp-3.6.0
hal_nxp-3.7.0
hal_openisa-2.7.6
hal_openisa-3.5.0-3.4.0
hal_openisa-3.7.0-3.6.0
hal_quicklogic-3.6.0-3.5.0-3.4.0-2.7.6
hal_quicklogic-3.7.0
hal_renesas-3.4.0
hal_renesas-3.5.0
hal_renesas-3.6.0
hal_renesas-3.7.0
hal_rpi_pico-3.4.0
hal_rpi_pico-3.7.0-3.6.0-3.5.0
hal_silabs-2.7.6
hal_silabs-3.4.0
hal_silabs-3.5.0
hal_silabs-3.6.0
hal_silabs-3.7.0
hal_st-2.7.6
hal_st-3.4.0
hal_st-3.5.0
hal_st-3.6.0
hal_st-3.7.0
hal_stm32-2.7.6
hal_stm32-3.4.0
hal_stm32-3.5.0
hal_stm32-3.6.0
hal_stm32-3.7.0
hal_telink-2.7.6
hal_telink-3.6.0-3.5.0-3.4.0
hal_telink-3.7.0
hal_ti-2.7.6
hal_ti-3.4.0
hal_ti-3.7.0-3.6.0-3.5.0
hal_wurthelektronik-3.5.0-3.4.0
hal_wurthelektronik-3.7.0-3.6.0
hal_xtensa-2.7.6
hal_xtensa-3.4.0
hal_xtensa-3.5.0
hal_xtensa-3.6.0
hal_xtensa-3.7.0
hostap-3.6.0
hostap-3.7.0
liblc3-3.5.0-3.4.0
liblc3-3.7.0-3.6.0
libmetal-2.7.6
libmetal-3.5.0-3.4.0
libmetal-3.6.0
libmetal-3.7.0
littlefs-2.7.6
littlefs-3.5.0-3.4.0
littlefs-3.7.0-3.6.0
loramac-node-2.7.6
loramac-node-3.4.0
loramac-node-3.6.0-3.5.0
loramac-node-3.7.0
lvgl-2.7.6
lvgl-3.4.0
lvgl-3.5.0
lvgl-3.6.0
lvgl-3.7.0
lz4-3.4.0-2.7.6
mbedtls-2.7.6
mbedtls-3.4.0
mbedtls-3.5.0
mbedtls-3.6.0
mbedtls-3.7.0
mcuboot-2.7.6
mcuboot-3.4.0
mcuboot-3.5.0
mcuboot-3.6.0
mcuboot-3.7.0
mcumgr-2.7.6
mipi-sys-t-2.7.6
mipi-sys-t-3.4.0
mipi-sys-t-3.6.0-3.5.0
mipi-sys-t-3.7.0
nanopb-2.7.6
nanopb-3.4.0
net-tools-2.7.6
net-tools-3.4.0
net-tools-3.5.0
net-tools-3.6.0
net-tools-3.7.0
nrf_hw_models-2.7.6
nrf_hw_models-3.4.0
nrf_hw_models-3.5.0
nrf_hw_models-3.6.0
nrf_hw_models-3.7.0
open-amp-2.7.6
open-amp-3.4.0
open-amp-3.5.0
open-amp-3.6.0
open-amp-3.7.0
openthread-2.7.6
openthread-3.4.0
openthread-3.5.0
openthread-3.6.0
openthread-3.7.0
percepio-3.5.0
percepio-3.6.0
percepio-3.7.0
picolibc-3.5.0-3.4.0
picolibc-3.7.0-3.6.0
psa-arch-tests-3.4.0
segger-2.7.6
segger-3.4.0
segger-3.6.0-3.5.0
segger-3.7.0
sof-2.7.6
sof-3.4.0
tf-m-tests-3.4.0
tflite-micro-3.4.0-2.7.6
thrift-3.4.0
tinycbor-2.7.6
tinycrypt-3.6.0-3.5.0-3.4.0-2.7.6
tinycrypt-3.7.0
trusted-firmware-a-3.4.0
trusted-firmware-a-3.6.0-3.5.0
trusted-firmware-a-3.7.0
trusted-firmware-m-3.4.0
trusted-firmware-m-3.5.0
trusted-firmware-m-3.6.0
trusted-firmware-m-3.7.0
uoscore-uedhoc-3.4.0
uoscore-uedhoc-3.5.0
uoscore-uedhoc-3.6.0
uoscore-uedhoc-3.7.0
zcbor-3.5.0-3.4.0
zcbor-3.6.0
zcbor-3.7.0
zscilib-3.4.0