1 // Copyright 2010-2018 Espressif Systems (Shanghai) PTE LTD 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 // 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 15 #pragma once 16 17 #ifndef __ASSEMBLER__ 18 #include <stdint.h> 19 #include "esp_assert.h" 20 #include "esp_bit_defs.h" 21 #endif 22 23 #define PRO_CPU_NUM (0) 24 25 #define SOC_MAX_CONTIGUOUS_RAM_SIZE (SOC_EXTRAM_DATA_HIGH - SOC_EXTRAM_DATA_LOW) ///< Largest span of contiguous memory (DRAM or IRAM) in the address space 26 27 #define DR_REG_SYSTEM_BASE 0x3f4c0000 28 #define DR_REG_SENSITIVE_BASE 0x3f4c1000 29 #define DR_REG_INTERRUPT_BASE 0x3f4c2000 30 #define DR_REG_DMA_COPY_BASE 0x3f4c3000 31 #define DR_REG_EXTMEM_BASE 0x61800000 32 #define DR_REG_MMU_TABLE 0x61801000 33 #define DR_REG_ITAG_TABLE 0x61802000 34 #define DR_REG_DTAG_TABLE 0x61803000 35 #define DR_REG_AES_BASE 0x6003a000 36 #define DR_REG_SHA_BASE 0x6003b000 37 #define DR_REG_RSA_BASE 0x6003c000 38 #define DR_REG_HMAC_BASE 0x6003e000 39 #define DR_REG_DIGITAL_SIGNATURE_BASE 0x6003d000 40 #define DR_REG_CRYPTO_DMA_BASE 0x6003f000 41 #define DR_REG_ASSIST_DEBUG_BASE 0x3f4ce000 42 #define DR_REG_DEDICATED_GPIO_BASE 0x3f4cf000 43 #define DR_REG_INTRUSION_BASE 0x3f4d0000 44 #define DR_REG_DPORT_END 0x3f4d3FFC 45 #define DR_REG_UART_BASE 0x3f400000 46 #define DR_REG_SPI1_BASE 0x3f402000 47 #define DR_REG_SPI0_BASE 0x3f403000 48 #define DR_REG_GPIO_BASE 0x3f404000 49 #define DR_REG_GPIO_SD_BASE 0x3f404f00 50 #define DR_REG_FE2_BASE 0x3f405000 51 #define DR_REG_FE_BASE 0x3f406000 52 #define DR_REG_FRC_TIMER_BASE 0x3f407000 53 #define DR_REG_RTCCNTL_BASE 0x3f408000 54 #define DR_REG_RTCIO_BASE 0x3f408400 55 #define DR_REG_SENS_BASE 0x3f408800 56 #define DR_REG_RTC_I2C_BASE 0x3f408C00 57 #define DR_REG_IO_MUX_BASE 0x3f409000 58 #define DR_REG_HINF_BASE 0x3f40B000 59 #define DR_REG_I2S_BASE 0x3f40F000 60 #define DR_REG_UART1_BASE 0x3f410000 61 #define DR_REG_I2C_EXT_BASE 0x3f413000 62 #define DR_REG_UHCI0_BASE 0x3f414000 63 #define DR_REG_SLCHOST_BASE 0x3f415000 64 #define DR_REG_RMT_BASE 0x3f416000 65 #define DR_REG_PCNT_BASE 0x3f417000 66 #define DR_REG_SLC_BASE 0x3f418000 67 #define DR_REG_LEDC_BASE 0x3f419000 68 #define DR_REG_CP_BASE 0x3f4c3000 69 #define DR_REG_EFUSE_BASE 0x3f41A000 70 #define DR_REG_NRX_BASE 0x3f41CC00 71 #define DR_REG_BB_BASE 0x3f41D000 72 #define DR_REG_TIMERGROUP0_BASE 0x3f41F000 73 #define DR_REG_TIMERGROUP1_BASE 0x3f420000 74 #define DR_REG_RTC_SLOWMEM_BASE 0x3f421000 75 #define DR_REG_SYSTIMER_BASE 0x3f423000 76 #define DR_REG_SPI2_BASE 0x3f424000 77 #define DR_REG_SPI3_BASE 0x3f425000 78 #define DR_REG_SYSCON_BASE 0x3f426000 79 #define DR_REG_APB_CTRL_BASE 0x3f426000 /* Old name for SYSCON, to be removed */ 80 #define DR_REG_I2C1_EXT_BASE 0x3f427000 81 #define DR_REG_SPI4_BASE 0x3f437000 82 #define DR_REG_USB_WRAP_BASE 0x3f439000 83 #define DR_REG_APB_SARADC_BASE 0x3f440000 84 #define DR_REG_USB_BASE 0x60080000 85 86 /* 87 * This macro is defined under esp32's soc file. However, When building 88 * for Zephyr, other SoCs are not able to reach this definition. 89 * That's why it is also declared here. 90 */ 91 #ifndef DR_REG_DPORT_BASE 92 #define DR_REG_DPORT_BASE 0x3ff00000 93 #endif 94 95 #define REG_UHCI_BASE(i) (DR_REG_UHCI0_BASE) 96 #define REG_UART_BASE( i ) (DR_REG_UART_BASE + (i) * 0x10000 ) 97 #define REG_UART_AHB_BASE(i) (0x60000000 + (i) * 0x10000 ) 98 #define UART_FIFO_AHB_REG(i) (REG_UART_AHB_BASE(i) + 0x0) 99 #define REG_I2S_BASE( i ) (DR_REG_I2S_BASE) 100 #define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i)*0x1000) 101 #define REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE - (i) * 0x1000) 102 #define REG_I2C_BASE(i) (DR_REG_I2C_EXT_BASE + (i) * 0x14000 ) 103 104 //Convenient way to replace the register ops when ulp riscv projects 105 //consume this file 106 #ifndef ULP_RISCV_REGISTER_OPS 107 108 //Registers Operation {{ 109 #define ETS_UNCACHED_ADDR(addr) (addr) 110 #define ETS_CACHED_ADDR(addr) (addr) 111 112 #ifndef __ZEPHYR__ 113 #ifndef __ASSEMBLER__ 114 #define BIT(nr) (1UL << (nr)) 115 #else 116 #define BIT(nr) (1 << (nr)) 117 #endif 118 #endif 119 120 #ifndef __ASSEMBLER__ 121 122 #define IS_DPORT_REG(_r) (((_r) >= DR_REG_DPORT_BASE) && (_r) <= DR_REG_DPORT_END) 123 124 #if !defined( BOOTLOADER_BUILD ) && !defined( CONFIG_FREERTOS_UNICORE ) && defined( ESP_PLATFORM ) 125 #define ASSERT_IF_DPORT_REG(_r, OP) TRY_STATIC_ASSERT(!IS_DPORT_REG(_r), (Cannot use OP for DPORT registers use DPORT_##OP)); 126 #else 127 #define ASSERT_IF_DPORT_REG(_r, OP) 128 #endif 129 130 //write value to register 131 #define REG_WRITE(_r, _v) ({ \ 132 ASSERT_IF_DPORT_REG((_r), REG_WRITE); \ 133 (*(volatile uint32_t *)(_r)) = (_v); \ 134 }) 135 136 //read value from register 137 #define REG_READ(_r) ({ \ 138 ASSERT_IF_DPORT_REG((_r), REG_READ); \ 139 (*(volatile uint32_t *)(_r)); \ 140 }) 141 142 //get bit or get bits from register 143 #define REG_GET_BIT(_r, _b) ({ \ 144 ASSERT_IF_DPORT_REG((_r), REG_GET_BIT); \ 145 (*(volatile uint32_t*)(_r) & (_b)); \ 146 }) 147 148 //set bit or set bits to register 149 #define REG_SET_BIT(_r, _b) ({ \ 150 ASSERT_IF_DPORT_REG((_r), REG_SET_BIT); \ 151 (*(volatile uint32_t*)(_r) |= (_b)); \ 152 }) 153 154 //clear bit or clear bits of register 155 #define REG_CLR_BIT(_r, _b) ({ \ 156 ASSERT_IF_DPORT_REG((_r), REG_CLR_BIT); \ 157 (*(volatile uint32_t*)(_r) &= ~(_b)); \ 158 }) 159 160 //set bits of register controlled by mask 161 #define REG_SET_BITS(_r, _b, _m) ({ \ 162 ASSERT_IF_DPORT_REG((_r), REG_SET_BITS); \ 163 (*(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r) & ~(_m)) | ((_b) & (_m))); \ 164 }) 165 166 //get field from register, uses field _S & _V to determine mask 167 #define REG_GET_FIELD(_r, _f) ({ \ 168 ASSERT_IF_DPORT_REG((_r), REG_GET_FIELD); \ 169 ((REG_READ(_r) >> (_f##_S)) & (_f##_V)); \ 170 }) 171 172 //set field of a register from variable, uses field _S & _V to determine mask 173 #define REG_SET_FIELD(_r, _f, _v) ({ \ 174 ASSERT_IF_DPORT_REG((_r), REG_SET_FIELD); \ 175 (REG_WRITE((_r),((REG_READ(_r) & ~((_f##_V) << (_f##_S)))|(((_v) & (_f##_V))<<(_f##_S))))); \ 176 }) 177 178 //get field value from a variable, used when _f is not left shifted by _f##_S 179 #define VALUE_GET_FIELD(_r, _f) (((_r) >> (_f##_S)) & (_f)) 180 181 //get field value from a variable, used when _f is left shifted by _f##_S 182 #define VALUE_GET_FIELD2(_r, _f) (((_r) & (_f))>> (_f##_S)) 183 184 //set field value to a variable, used when _f is not left shifted by _f##_S 185 #define VALUE_SET_FIELD(_r, _f, _v) ((_r)=(((_r) & ~((_f) << (_f##_S)))|((_v)<<(_f##_S)))) 186 187 //set field value to a variable, used when _f is left shifted by _f##_S 188 #define VALUE_SET_FIELD2(_r, _f, _v) ((_r)=(((_r) & ~(_f))|((_v)<<(_f##_S)))) 189 190 //generate a value from a field value, used when _f is not left shifted by _f##_S 191 #define FIELD_TO_VALUE(_f, _v) (((_v)&(_f))<<_f##_S) 192 193 //generate a value from a field value, used when _f is left shifted by _f##_S 194 #define FIELD_TO_VALUE2(_f, _v) (((_v)<<_f##_S) & (_f)) 195 196 //read value from register 197 #define READ_PERI_REG(addr) ({ \ 198 ASSERT_IF_DPORT_REG((addr), READ_PERI_REG); \ 199 (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))); \ 200 }) 201 202 //write value to register 203 #define WRITE_PERI_REG(addr, val) ({ \ 204 ASSERT_IF_DPORT_REG((addr), WRITE_PERI_REG); \ 205 (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))) = (uint32_t)(val); \ 206 }) 207 208 //clear bits of register controlled by mask 209 #define CLEAR_PERI_REG_MASK(reg, mask) ({ \ 210 ASSERT_IF_DPORT_REG((reg), CLEAR_PERI_REG_MASK); \ 211 WRITE_PERI_REG((reg), (READ_PERI_REG(reg)&(~(mask)))); \ 212 }) 213 214 //set bits of register controlled by mask 215 #define SET_PERI_REG_MASK(reg, mask) ({ \ 216 ASSERT_IF_DPORT_REG((reg), SET_PERI_REG_MASK); \ 217 WRITE_PERI_REG((reg), (READ_PERI_REG(reg)|(mask))); \ 218 }) 219 220 //get bits of register controlled by mask 221 #define GET_PERI_REG_MASK(reg, mask) ({ \ 222 ASSERT_IF_DPORT_REG((reg), GET_PERI_REG_MASK); \ 223 (READ_PERI_REG(reg) & (mask)); \ 224 }) 225 226 //get bits of register controlled by highest bit and lowest bit 227 #define GET_PERI_REG_BITS(reg, hipos,lowpos) ({ \ 228 ASSERT_IF_DPORT_REG((reg), GET_PERI_REG_BITS); \ 229 ((READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1)); \ 230 }) 231 232 //set bits of register controlled by mask and shift 233 #define SET_PERI_REG_BITS(reg,bit_map,value,shift) ({ \ 234 ASSERT_IF_DPORT_REG((reg), SET_PERI_REG_BITS); \ 235 (WRITE_PERI_REG((reg),(READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & bit_map)<<(shift)) )); \ 236 }) 237 238 //get field of register 239 #define GET_PERI_REG_BITS2(reg, mask,shift) ({ \ 240 ASSERT_IF_DPORT_REG((reg), GET_PERI_REG_BITS2); \ 241 ((READ_PERI_REG(reg)>>(shift))&(mask)); \ 242 }) 243 244 #endif /* !__ASSEMBLER__ */ 245 //}} 246 #endif /* !ULP_RISCV_REGISTER_OPS */ 247 248 //Periheral Clock {{ 249 #define APB_CLK_FREQ_ROM ( 40*1000000 ) 250 #define CPU_CLK_FREQ_ROM APB_CLK_FREQ_ROM 251 #define UART_CLK_FREQ_ROM APB_CLK_FREQ_ROM 252 #define CPU_CLK_FREQ APB_CLK_FREQ 253 #define APB_CLK_FREQ ( 80*1000000 ) //unit: Hz 254 #define REF_CLK_FREQ ( 1000000 ) 255 #define UART_CLK_FREQ APB_CLK_FREQ 256 #define WDT_CLK_FREQ APB_CLK_FREQ 257 #define TIMER_CLK_FREQ (80000000>>4) //80MHz divided by 16 258 #define SPI_CLK_DIV 4 259 #define TICKS_PER_US_ROM 40 // CPU is 80MHz 260 #define GPIO_MATRIX_DELAY_NS 0 261 //}} 262 263 /* Overall memory map */ 264 #define SOC_DROM_LOW 0x3F000000/*drom0 low address for icache*/ 265 #define SOC_DROM_HIGH 0x3FF80000/*dram0 high address for dcache*/ 266 #define SOC_IROM_LOW 0x40080000 267 #define SOC_IROM_HIGH 0x40800000 268 #define SOC_IROM_MASK_LOW 0x40000000 269 #define SOC_IROM_MASK_HIGH 0x40020000 270 #define SOC_IRAM_LOW 0x40020000 271 #define SOC_IRAM_HIGH 0x40070000 272 #define SOC_DRAM_LOW 0x3FFB0000 273 #define SOC_DRAM_HIGH 0x40000000 274 #define SOC_RTC_IRAM_LOW 0x40070000 275 #define SOC_RTC_IRAM_HIGH 0x40072000 276 #define SOC_RTC_DRAM_LOW 0x3ff9e000 277 #define SOC_RTC_DRAM_HIGH 0x3ffa0000 278 #define SOC_RTC_DATA_LOW 0x50000000 279 #define SOC_RTC_DATA_HIGH 0x50002000 280 #define SOC_EXTRAM_DATA_LOW 0x3F500000 281 #define SOC_EXTRAM_DATA_HIGH 0x3FF80000 282 283 #define SOC_EXTRAM_DATA_SIZE (SOC_EXTRAM_DATA_HIGH - SOC_EXTRAM_DATA_LOW) 284 285 //First and last words of the D/IRAM region, for both the DRAM address as well as the IRAM alias. 286 #define SOC_DIRAM_IRAM_LOW 0x40020000 287 #define SOC_DIRAM_IRAM_HIGH 0x40070000 288 #define SOC_DIRAM_DRAM_LOW 0x3FFB0000 289 #define SOC_DIRAM_DRAM_HIGH 0x40000000 290 291 // Region of memory accessible via DMA in internal memory. See esp_ptr_dma_capable(). 292 #define SOC_DMA_LOW 0x3FFB0000 293 #define SOC_DMA_HIGH 0x40000000 294 295 // Region of memory accessible via DMA in external memory. See esp_ptr_dma_ext_capable(). 296 #define SOC_DMA_EXT_LOW 0x3F500000 297 #define SOC_DMA_EXT_HIGH 0x3FF80000 298 299 // Region of memory that is byte-accessible. See esp_ptr_byte_accessible(). 300 #define SOC_BYTE_ACCESSIBLE_LOW 0x3FF9E000 301 #define SOC_BYTE_ACCESSIBLE_HIGH 0x40000000 302 303 //Region of memory that is internal, as in on the same silicon die as the ESP32 CPUs 304 //(excluding RTC data region, that's checked separately.) See esp_ptr_internal(). 305 #define SOC_MEM_INTERNAL_LOW 0x3FF9E000 306 #define SOC_MEM_INTERNAL_HIGH 0x40072000 307 308 // Start (highest address) of ROM boot stack, only relevant during early boot 309 #define SOC_ROM_STACK_START 0x3fffe70c 310 311 //interrupt cpu using table, Please see the core-isa.h 312 /************************************************************************************************************* 313 * Intr num Level Type PRO CPU usage 314 * 0 1 extern level WMAC 315 * 1 1 extern level BT/BLE Host HCI DMA 316 * 2 1 extern level 317 * 3 1 extern level 318 * 4 1 extern level WBB 319 * 5 1 extern level BT/BLE Controller 320 * 6 1 timer FreeRTOS Tick(L1) 321 * 7 1 software BT/BLE VHCI 322 * 8 1 extern level BT/BLE BB(RX/TX) 323 * 9 1 extern level 324 * 10 1 extern edge 325 * 11 3 profiling 326 * 12 1 extern level 327 * 13 1 extern level 328 * 14 7 nmi Reserved 329 * 15 3 timer FreeRTOS Tick(L3) 330 * 16 5 timer 331 * 17 1 extern level 332 * 18 1 extern level 333 * 19 2 extern level 334 * 20 2 extern level 335 * 21 2 extern level 336 * 22 3 extern edge 337 * 23 3 extern level 338 * 24 4 extern level TG1_WDT 339 * 25 4 extern level CACHEERR 340 * 26 5 extern level 341 * 27 3 extern level Reserved 342 * 28 4 extern edge Reserved 343 * 29 3 software Reserved 344 * 30 4 extern edge Reserved 345 * 31 5 extern level 346 ************************************************************************************************************* 347 */ 348 349 //CPU0 Interrupt number reserved, not touch this. 350 #define ETS_WMAC_INUM 0 351 #define ETS_BT_HOST_INUM 1 352 #define ETS_WBB_INUM 4 353 #define ETS_TG0_T1_INUM 10 /**< use edge interrupt*/ 354 #define ETS_FRC1_INUM 22 355 #define ETS_T1_WDT_INUM 24 356 #define ETS_MEMACCESS_ERR_INUM 25 357 358 //CPU0 Interrupt number used in ROM, should be cancelled in SDK 359 #define ETS_SLC_INUM 1 360 #define ETS_UART0_INUM 5 361 #define ETS_UART1_INUM 5 362 #define ETS_SPI2_INUM 1 363 //CPU0 Interrupt number used in ROM code only when module init function called, should pay attention here. 364 #define ETS_FRC_TIMER2_INUM 10 /* use edge*/ 365 #define ETS_GPIO_INUM 4 366 367 //Other interrupt number should be managed by the user 368 369 //Invalid interrupt for number interrupt matrix 370 #define ETS_INVALID_INUM 6 371
