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Searched refs:DR_REG_AES_BASE (Results 1 – 10 of 10) sorted by relevance

/hal_espressif-3.6.0/components/soc/esp32s2/include/soc/
Dhwcrypto_reg.h73 #define AES_MODE_REG ((DR_REG_AES_BASE) + 0x40)
74 #define AES_ENDIAN_REG ((DR_REG_AES_BASE) + 0x44)
75 #define AES_TRIGGER_REG ((DR_REG_AES_BASE) + 0x48)
76 #define AES_STATE_REG ((DR_REG_AES_BASE) + 0x4c)
77 #define AES_DMA_ENABLE_REG ((DR_REG_AES_BASE) + 0x90)
78 #define AES_BLOCK_MODE_REG ((DR_REG_AES_BASE) + 0x94)
79 #define AES_BLOCK_NUM_REG ((DR_REG_AES_BASE) + 0x98)
80 #define AES_INC_SEL_REG ((DR_REG_AES_BASE) + 0x9C)
81 #define AES_AAD_BLOCK_NUM_REG ((DR_REG_AES_BASE) + 0xA0)
82 #define AES_BIT_VALID_NUM_REG ((DR_REG_AES_BASE) + 0xA4)
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Dsoc.h35 #define DR_REG_AES_BASE 0x6003a000 macro
/hal_espressif-3.6.0/components/soc/esp32c3/include/soc/
Dhwcrypto_reg.h84 #define AES_MODE_REG ((DR_REG_AES_BASE) + 0x40)
85 #define AES_ENDIAN_REG ((DR_REG_AES_BASE) + 0x44)
86 #define AES_TRIGGER_REG ((DR_REG_AES_BASE) + 0x48)
87 #define AES_STATE_REG ((DR_REG_AES_BASE) + 0x4c)
88 #define AES_DMA_ENABLE_REG ((DR_REG_AES_BASE) + 0x90)
89 #define AES_BLOCK_MODE_REG ((DR_REG_AES_BASE) + 0x94)
90 #define AES_BLOCK_NUM_REG ((DR_REG_AES_BASE) + 0x98)
91 #define AES_INC_SEL_REG ((DR_REG_AES_BASE) + 0x9C)
92 #define AES_AAD_BLOCK_NUM_REG ((DR_REG_AES_BASE) + 0xA0)
93 #define AES_BIT_VALID_NUM_REG ((DR_REG_AES_BASE) + 0xA4)
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Dsoc.h32 #define DR_REG_AES_BASE 0x6003a000 macro
/hal_espressif-3.6.0/components/soc/esp32h2/include/soc/
Dhwcrypto_reg.h84 #define AES_MODE_REG ((DR_REG_AES_BASE) + 0x40)
85 #define AES_ENDIAN_REG ((DR_REG_AES_BASE) + 0x44)
86 #define AES_TRIGGER_REG ((DR_REG_AES_BASE) + 0x48)
87 #define AES_STATE_REG ((DR_REG_AES_BASE) + 0x4c)
88 #define AES_DMA_ENABLE_REG ((DR_REG_AES_BASE) + 0x90)
89 #define AES_BLOCK_MODE_REG ((DR_REG_AES_BASE) + 0x94)
90 #define AES_BLOCK_NUM_REG ((DR_REG_AES_BASE) + 0x98)
91 #define AES_INC_SEL_REG ((DR_REG_AES_BASE) + 0x9C)
92 #define AES_AAD_BLOCK_NUM_REG ((DR_REG_AES_BASE) + 0xA0)
93 #define AES_BIT_VALID_NUM_REG ((DR_REG_AES_BASE) + 0xA4)
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Dsoc.h36 #define DR_REG_AES_BASE 0x6003a000 macro
/hal_espressif-3.6.0/components/soc/esp32s3/include/soc/
Dhwcrypto_reg.h64 #define AES_MODE_REG ((DR_REG_AES_BASE) + 0x40)
65 #define AES_ENDIAN_REG ((DR_REG_AES_BASE) + 0x44)
66 #define AES_TRIGGER_REG ((DR_REG_AES_BASE) + 0x48)
67 #define AES_STATE_REG ((DR_REG_AES_BASE) + 0x4c)
68 #define AES_DMA_ENABLE_REG ((DR_REG_AES_BASE) + 0x90)
69 #define AES_BLOCK_MODE_REG ((DR_REG_AES_BASE) + 0x94)
70 #define AES_BLOCK_NUM_REG ((DR_REG_AES_BASE) + 0x98)
71 #define AES_INC_SEL_REG ((DR_REG_AES_BASE) + 0x9C)
72 #define AES_CONTINUE_REG ((DR_REG_AES_BASE) + 0xA8)
73 #define AES_INT_CLR_REG ((DR_REG_AES_BASE) + 0xAC)
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Dsoc.h89 #define DR_REG_AES_BASE 0x6003A000 macro
/hal_espressif-3.6.0/components/soc/esp32/include/soc/
Dhwcrypto_reg.h67 #define AES_START_REG ((DR_REG_AES_BASE) + 0x00)
68 #define AES_IDLE_REG ((DR_REG_AES_BASE) + 0x04)
69 #define AES_MODE_REG ((DR_REG_AES_BASE) + 0x08)
70 #define AES_KEY_BASE ((DR_REG_AES_BASE) + 0x10)
71 #define AES_TEXT_BASE ((DR_REG_AES_BASE) + 0x30)
72 #define AES_ENDIAN ((DR_REG_AES_BASE) + 0x40)
Dsoc.h32 #define DR_REG_AES_BASE 0x3ff01000 macro