Searched refs:DPORT_SYSCLK_CONF_REG (Results 1 – 2 of 2) sorted by relevance
/hal_espressif-3.6.0/components/esp_hw_support/port/esp32s2/ |
D | rtc_clk.c | 291 REG_SET_FIELD(DPORT_SYSCLK_CONF_REG, DPORT_PRE_DIV_CNT, 0); in rtc_clk_cpu_freq_to_pll_mhz() 293 REG_SET_FIELD(DPORT_SYSCLK_CONF_REG, DPORT_SOC_CLK_SEL, DPORT_SOC_CLK_SEL_PLL); in rtc_clk_cpu_freq_to_pll_mhz() 346 uint32_t soc_clk_sel = REG_GET_FIELD(DPORT_SYSCLK_CONF_REG, DPORT_SOC_CLK_SEL); in rtc_clk_cpu_freq_set_config() 372 uint32_t soc_clk_sel = REG_GET_FIELD(DPORT_SYSCLK_CONF_REG, DPORT_SOC_CLK_SEL); in rtc_clk_cpu_freq_get_config() 376 div = REG_GET_FIELD(DPORT_SYSCLK_CONF_REG, DPORT_PRE_DIV_CNT) + 1; in rtc_clk_cpu_freq_get_config() 447 REG_SET_FIELD(DPORT_SYSCLK_CONF_REG, DPORT_PRE_DIV_CNT, 0); in rtc_clk_cpu_freq_to_xtal() 448 REG_SET_FIELD(DPORT_SYSCLK_CONF_REG, DPORT_PRE_DIV_CNT, div - 1); in rtc_clk_cpu_freq_to_xtal() 451 REG_SET_FIELD(DPORT_SYSCLK_CONF_REG, DPORT_SOC_CLK_SEL, DPORT_SOC_CLK_SEL_XTAL); in rtc_clk_cpu_freq_to_xtal() 465 REG_SET_FIELD(DPORT_SYSCLK_CONF_REG, DPORT_PRE_DIV_CNT, 0); in rtc_clk_cpu_freq_to_8m() 466 REG_SET_FIELD(DPORT_SYSCLK_CONF_REG, DPORT_SOC_CLK_SEL, DPORT_SOC_CLK_SEL_8M); in rtc_clk_cpu_freq_to_8m()
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/hal_espressif-3.6.0/components/soc/esp32s2/include/soc/ |
D | system_reg.h | 870 #define DPORT_SYSCLK_CONF_REG (DR_REG_SYSTEM_BASE + 0x08C) macro
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