Searched refs:DPORT_PRO_CACHE_CTRL_REG (Results 1 – 6 of 6) sorted by relevance
| /hal_espressif-3.6.0/components/esp_hw_support/port/esp32/ |
| D | spiram.c | 272 if (DPORT_REG_GET_BIT(DPORT_PRO_CACHE_CTRL_REG, DPORT_PRO_CACHE_ENABLE)==0) { in esp_spiram_writeback_cache()
274 DPORT_SET_PERI_REG_BITS(DPORT_PRO_CACHE_CTRL_REG, 1, 1, DPORT_PRO_CACHE_ENABLE_S); in esp_spiram_writeback_cache()
306 DPORT_SET_PERI_REG_BITS(DPORT_PRO_CACHE_CTRL_REG, 1, 0, DPORT_PRO_CACHE_ENABLE_S); in esp_spiram_writeback_cache()
|
| D | spiram_psram.c | 1085 DPORT_CLEAR_PERI_REG_MASK(DPORT_PRO_CACHE_CTRL_REG, DPORT_PRO_DRAM_HL|DPORT_PRO_DRAM_SPLIT); in psram_cache_init()
1088 DPORT_SET_PERI_REG_MASK(DPORT_PRO_CACHE_CTRL_REG, DPORT_PRO_DRAM_HL); in psram_cache_init()
1091 DPORT_SET_PERI_REG_MASK(DPORT_PRO_CACHE_CTRL_REG, DPORT_PRO_DRAM_SPLIT); in psram_cache_init()
|
| /hal_espressif-3.6.0/zephyr/esp_shared/src/host_flash/ |
| D | cache_utils.c | 43 DPORT_SET_PERI_REG_BITS(DPORT_PRO_CACHE_CTRL_REG, 1, 0, DPORT_PRO_CACHE_ENABLE_S); in spi_flash_disable_cache()
74 DPORT_SET_PERI_REG_BITS(DPORT_PRO_CACHE_CTRL_REG, 1, 1, DPORT_PRO_CACHE_ENABLE_S); in spi_flash_restore_cache()
|
| /hal_espressif-3.6.0/components/esp_hw_support/port/esp32s2/ |
| D | spiram_psram.c | 536 DPORT_CLEAR_PERI_REG_MASK(DPORT_PRO_CACHE_CTRL_REG, DPORT_PRO_DRAM_HL|DPORT_PRO_DRAM_SPLIT); in psram_cache_init()
539 DPORT_SET_PERI_REG_MASK(DPORT_PRO_CACHE_CTRL_REG, DPORT_PRO_DRAM_HL); in psram_cache_init()
542 DPORT_SET_PERI_REG_MASK(DPORT_PRO_CACHE_CTRL_REG, DPORT_PRO_DRAM_SPLIT); in psram_cache_init()
|
| /hal_espressif-3.6.0/components/spi_flash/ |
| D | cache_utils.c | 311 DPORT_SET_PERI_REG_BITS(DPORT_PRO_CACHE_CTRL_REG, 1, 0, DPORT_PRO_CACHE_ENABLE_S); in spi_flash_disable_cache()
342 DPORT_SET_PERI_REG_BITS(DPORT_PRO_CACHE_CTRL_REG, 1, 1, DPORT_PRO_CACHE_ENABLE_S); in spi_flash_restore_cache()
364 bool result = (DPORT_REG_GET_BIT(DPORT_PRO_CACHE_CTRL_REG, DPORT_PRO_CACHE_ENABLE) != 0); in spi_flash_cache_enabled()
|
| /hal_espressif-3.6.0/components/soc/esp32/include/soc/ |
| D | dport_reg.h | 186 #define DPORT_PRO_CACHE_CTRL_REG (DR_REG_DPORT_BASE + 0x040) macro
|
