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Searched refs:DPORT_PMS_PRO_DRAM0_3_REG (Results 1 – 3 of 3) sorted by relevance

/hal_espressif-3.6.0/components/hal/esp32s3/include/hal/
Dmemprot_ll.h420 DPORT_SET_PERI_REG_MASK( DPORT_PMS_PRO_DRAM0_3_REG, DPORT_PMS_PRO_DRAM0_ILG_EN );
422 DPORT_CLEAR_PERI_REG_MASK( DPORT_PMS_PRO_DRAM0_3_REG, DPORT_PMS_PRO_DRAM0_ILG_EN );
428 return DPORT_GET_PERI_REG_MASK(DPORT_PMS_PRO_DRAM0_3_REG, DPORT_PMS_PRO_DRAM0_ILG_INTR) > 0;
433 DPORT_SET_PERI_REG_MASK(DPORT_PMS_PRO_DRAM0_3_REG, DPORT_PMS_PRO_DRAM0_ILG_CLR);
438 return DPORT_REG_GET_FIELD(DPORT_PMS_PRO_DRAM0_3_REG, DPORT_PMS_PRO_DRAM0_ILG_EN);
443 return DPORT_REG_GET_FIELD(DPORT_PMS_PRO_DRAM0_3_REG, DPORT_PMS_PRO_DRAM0_ILG_INTR);
448 return DPORT_REG_GET_FIELD(DPORT_PMS_PRO_DRAM0_3_REG, DPORT_PMS_PRO_DRAM0_ILG_CLR);
556 return DPORT_READ_PERI_REG(DPORT_PMS_PRO_DRAM0_3_REG);
/hal_espressif-3.6.0/components/hal/esp32s2/include/hal/
Dmemprot_ll.h511 DPORT_SET_PERI_REG_MASK(DPORT_PMS_PRO_DRAM0_3_REG, DPORT_PMS_PRO_DRAM0_ILG_EN); in memprot_ll_dram0_intr_ena()
513 DPORT_CLEAR_PERI_REG_MASK(DPORT_PMS_PRO_DRAM0_3_REG, DPORT_PMS_PRO_DRAM0_ILG_EN); in memprot_ll_dram0_intr_ena()
519 return DPORT_GET_PERI_REG_MASK(DPORT_PMS_PRO_DRAM0_3_REG, DPORT_PMS_PRO_DRAM0_ILG_INTR) > 0; in memprot_ll_dram0_is_assoc_intr()
524 DPORT_SET_PERI_REG_MASK(DPORT_PMS_PRO_DRAM0_3_REG, DPORT_PMS_PRO_DRAM0_ILG_CLR); in memprot_ll_dram0_clear_intr()
525 DPORT_CLEAR_PERI_REG_MASK(DPORT_PMS_PRO_DRAM0_3_REG, DPORT_PMS_PRO_DRAM0_ILG_CLR); in memprot_ll_dram0_clear_intr()
530 return DPORT_REG_GET_FIELD(DPORT_PMS_PRO_DRAM0_3_REG, DPORT_PMS_PRO_DRAM0_ILG_EN); in memprot_ll_dram0_get_intr_ena_bit()
535 return DPORT_REG_GET_FIELD(DPORT_PMS_PRO_DRAM0_3_REG, DPORT_PMS_PRO_DRAM0_ILG_INTR); in memprot_ll_dram0_get_intr_on_bit()
540 return DPORT_REG_GET_FIELD(DPORT_PMS_PRO_DRAM0_3_REG, DPORT_PMS_PRO_DRAM0_ILG_CLR); in memprot_ll_dram0_get_intr_clr_bit()
561 return DPORT_READ_PERI_REG(DPORT_PMS_PRO_DRAM0_3_REG); in memprot_ll_dram0_get_conf_reg()
/hal_espressif-3.6.0/components/soc/esp32s2/include/soc/
Dsensitive_reg.h372 #define DPORT_PMS_PRO_DRAM0_3_REG (DR_REG_SENSITIVE_BASE + 0x034) macro