1 /* 2 * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 /* 8 * Soc capabilities file, describing the following chip attributes: 9 * - Peripheral or feature supported or not 10 * - Number of resources (peripheral, channel, etc.) 11 * - Maximum / Minimum value of HW, including: buffer/fifo size, length of transaction, frequency 12 * supported, etc. 13 * 14 * For boolean definitions: 15 * - if true: `#define MODULE_[SUBMODULE_]SUPPORT_FEATURE 1`. 16 * (`#define` blank string causes error when checking by `#if x`) 17 * - if false: not define anything at all. 18 * (`#ifdef x` is true even when `#define 0` is defined before.) 19 * 20 * The code depending on this file uses these boolean definitions as `#if x` or `#if !x`. 21 * (`#ifdef/ifndef x` is not compatible with `#define x 0`. Though we don't suggest to use `#define 22 * x 0`, it's still a risk.) 23 * 24 * ECO & exceptions: 25 * For ECO-ed booleans, `#define x "Not determined"` for them. This will cause error when used by 26 * `#if x` and `#if !x`, making these missing definitions more obvious. 27 */ 28 29 #pragma once 30 31 #ifdef __has_include 32 # if __has_include("sdkconfig.h") 33 # include "sdkconfig.h" 34 # define SOC_CAPS_ECO_VER CONFIG_ESP32_REV_MIN 35 # endif 36 #endif 37 38 #if __DOXYGEN__ && !defined(SOC_CAPS_ECO_VER) 39 #define SOC_CAPS_ECO_VER SOC_CAPS_ECO_VER_MAX 40 #endif 41 42 #ifndef SOC_CAPS_ECO_VER 43 #warning ECO version not determined. Some ECO related caps will not be available. 44 #warning Define SOC_CAPS_ECO_VER before including this header. 45 46 // Define warning strings here for ECO-ed features to show error when they are used without being 47 // defined correctly 48 #define SOC_BROWNOUT_RESET_SUPPORTED "Not determined" 49 #define SOC_TWAI_BRP_DIV_SUPPORTED "Not determined" 50 #endif 51 52 /*-------------------------- COMMON CAPS ---------------------------------------*/ 53 #define SOC_CAPS_ECO_VER_MAX 3 54 55 #define SOC_ADC_SUPPORTED 1 56 #define SOC_DAC_SUPPORTED 1 57 #define SOC_MCPWM_SUPPORTED 1 58 #define SOC_SDMMC_HOST_SUPPORTED 1 59 #define SOC_BT_SUPPORTED 1 60 #define SOC_CLASSIC_BT_SUPPORTED 1 61 #define SOC_PCNT_SUPPORTED 1 62 #define SOC_SDIO_SLAVE_SUPPORTED 1 63 #define SOC_TWAI_SUPPORTED 1 64 #define SOC_EMAC_SUPPORTED 1 65 #define SOC_CPU_CORES_NUM 2 66 #define SOC_ULP_SUPPORTED 1 67 #define SOC_RTC_SLOW_MEM_SUPPORTED 1 68 #define SOC_CCOMP_TIMER_SUPPORTED 1 69 #define SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS 1 70 71 /*-------------------------- ADC CAPS ----------------------------------------*/ 72 /** 73 * TO BE REMOVED 74 * Check if adc support digital controller (DMA) mode. 75 * @value 76 * - 1 : support; 77 * - 0 : not support; 78 */ 79 #define SOC_ADC_SUPPORT_DMA_MODE(PERIPH_NUM) ((PERIPH_NUM==0)? 1: 0) 80 81 /*!< SAR ADC Module*/ 82 #define SOC_ADC_RTC_CTRL_SUPPORTED 1 83 #define SOC_ADC_DIG_CTRL_SUPPORTED 1 84 #define SOC_ADC_PERIPH_NUM (2) 85 #define SOC_ADC_CHANNEL_NUM(PERIPH_NUM) ((PERIPH_NUM==0)? 8: 10) 86 #define SOC_ADC_MAX_CHANNEL_NUM (10) 87 88 /*!< Digital */ 89 #define SOC_ADC_DIGI_CONTROLLER_NUM (2) 90 #define SOC_ADC_PATT_LEN_MAX (16) //Two pattern table, each contains 16 items. Each item takes 1 byte. But only support ADC1 using DMA mode 91 #define SOC_ADC_DIGI_MIN_BITWIDTH (9) 92 #define SOC_ADC_DIGI_MAX_BITWIDTH (12) 93 /*!< F_sample = F_digi_con / 2 / interval. F_digi_con = 5M for now. 30 <= interva <= 4095 */ 94 #define SOC_ADC_SAMPLE_FREQ_THRES_HIGH (2*1000*1000) 95 #define SOC_ADC_SAMPLE_FREQ_THRES_LOW (2000) 96 97 /*!< RTC */ 98 #define SOC_ADC_MAX_BITWIDTH (12) 99 100 101 /*-------------------------- BROWNOUT CAPS -----------------------------------*/ 102 #if SOC_CAPS_ECO_VER >= 1 103 #define SOC_BROWNOUT_RESET_SUPPORTED 1 104 #endif 105 106 /*-------------------------- CPU CAPS ----------------------------------------*/ 107 #define SOC_CPU_BREAKPOINTS_NUM 2 108 #define SOC_CPU_WATCHPOINTS_NUM 2 109 110 #define SOC_CPU_WATCHPOINT_SIZE 64 // bytes 111 112 #define SOC_CPU_HAS_FPU 1 113 114 /*-------------------------- DAC CAPS ----------------------------------------*/ 115 #define SOC_DAC_PERIPH_NUM 2 116 #define SOC_DAC_RESOLUTION 8 // DAC resolution ratio 8 bit 117 118 /*-------------------------- GPIO CAPS ---------------------------------------*/ 119 // ESP32 has 1 GPIO peripheral 120 #define SOC_GPIO_PORT (1) 121 #define SOC_GPIO_PIN_COUNT 40 122 123 // SOC_GPIO_SUPPORT_RTC_INDEPENDENT not defined. On ESP32 those PADs which have RTC functions must 124 // set pullup/down/capability via RTC register. On ESP32-S2, Digital IOs have their own registers to 125 // control pullup/down/capability, independent with RTC registers. 126 127 // 0~39 except from 24, 28~31 are valid 128 #define SOC_GPIO_VALID_GPIO_MASK (0xFFFFFFFFFFULL & ~(0ULL | BIT24 | BIT28 | BIT29 | BIT30 | BIT31)) 129 // GPIO >= 34 are input only 130 #define SOC_GPIO_VALID_OUTPUT_GPIO_MASK (SOC_GPIO_VALID_GPIO_MASK & ~(0ULL | BIT34 | BIT35 | BIT36 | BIT37 | BIT38 | BIT39)) 131 132 // Support to configure slept status 133 #define SOC_GPIO_SUPPORT_SLP_SWITCH (1) 134 135 /*-------------------------- I2C CAPS ----------------------------------------*/ 136 // ESP32 have 2 I2C. 137 #define SOC_I2C_NUM (2) 138 139 #define SOC_I2C_FIFO_LEN (32) /*!< I2C hardware FIFO depth */ 140 141 #define SOC_I2C_SUPPORT_APB (1) 142 143 /*-------------------------- APLL CAPS ----------------------------------------*/ 144 #define SOC_CLK_APLL_SUPPORTED (1) 145 // apll_multiplier_out = xtal_freq * (4 + sdm2 + sdm1/256 + sdm0/65536) 146 #define SOC_APLL_MULTIPLIER_OUT_MIN_HZ (350000000) // 350 MHz 147 #define SOC_APLL_MULTIPLIER_OUT_MAX_HZ (500000000) // 500 MHz 148 #define SOC_APLL_MIN_HZ (5303031) // 5.303031 MHz 149 #define SOC_APLL_MAX_HZ (125000000) // 125MHz 150 151 /*-------------------------- I2S CAPS ----------------------------------------*/ 152 // ESP32 have 2 I2S 153 #define SOC_I2S_NUM (2U) 154 #define SOC_I2S_SUPPORTS_APLL (1) // ESP32 support APLL 155 #define SOC_I2S_SUPPORTS_PDM_TX (1) 156 #define SOC_I2S_SUPPORTS_PDM_RX (1) 157 #define SOC_I2S_SUPPORTS_ADC (1) // ESP32 support ADC and DAC 158 #define SOC_I2S_SUPPORTS_DAC (1) 159 160 #define SOC_I2S_TRANS_SIZE_ALIGN_WORD (1) // I2S DMA transfer size must be aligned to word 161 #define SOC_I2S_LCD_I80_VARIANT (1) // I2S has a special LCD mode that can generate Intel 8080 TX timing 162 163 /*-------------------------- LCD CAPS ----------------------------------------*/ 164 /* Notes: On esp32, LCD intel 8080 timing is generated by I2S peripheral */ 165 #define SOC_LCD_I80_SUPPORTED (1) /*!< Intel 8080 LCD is supported */ 166 #define SOC_LCD_I80_BUSES (1) /*!< Only I2S0 has LCD mode */ 167 #define SOC_LCD_I80_BUS_WIDTH (24) /*!< Intel 8080 bus width */ 168 169 /*-------------------------- LEDC CAPS ---------------------------------------*/ 170 #define SOC_LEDC_SUPPORT_HS_MODE (1) 171 #define SOC_LEDC_SUPPORT_HS_MODE (1) 172 #define SOC_LEDC_CHANNEL_NUM (8) 173 #define SOC_LEDC_TIMER_BIT_WIDE_NUM (20) 174 175 /*-------------------------- MCPWM CAPS --------------------------------------*/ 176 #define SOC_MCPWM_GROUPS (2) ///< 2 MCPWM groups on the chip (i.e., the number of independent MCPWM peripherals) 177 #define SOC_MCPWM_TIMERS_PER_GROUP (3) ///< The number of timers that each group has 178 #define SOC_MCPWM_OPERATORS_PER_GROUP (3) ///< The number of operators that each group has 179 #define SOC_MCPWM_COMPARATORS_PER_OPERATOR (2) ///< The number of comparators that each operator has 180 #define SOC_MCPWM_GENERATORS_PER_OPERATOR (2) ///< The number of generators that each operator has 181 #define SOC_MCPWM_TRIGGERS_PER_OPERATOR (2) ///< The number of triggers that each operator has 182 #define SOC_MCPWM_GPIO_FAULTS_PER_GROUP (3) ///< The number of GPIO fault signals that each group has 183 #define SOC_MCPWM_CAPTURE_TIMERS_PER_GROUP (1) ///< The number of capture timers that each group has 184 #define SOC_MCPWM_CAPTURE_CHANNELS_PER_TIMER (3) ///< The number of capture channels that each capture timer has 185 #define SOC_MCPWM_GPIO_SYNCHROS_PER_GROUP (3) ///< The number of GPIO synchros that each group has 186 #define SOC_MCPWM_BASE_CLK_HZ (160000000ULL) ///< Base Clock frequency of 160MHz 187 188 /*-------------------------- MPU CAPS ----------------------------------------*/ 189 //TODO: correct the caller and remove unsupported lines 190 #define SOC_MPU_CONFIGURABLE_REGIONS_SUPPORTED 0 191 #define SOC_MPU_MIN_REGION_SIZE 0x20000000U 192 #define SOC_MPU_REGIONS_MAX_NUM 8 193 #define SOC_MPU_REGION_RO_SUPPORTED 0 194 #define SOC_MPU_REGION_WO_SUPPORTED 0 195 196 /*-------------------------- PCNT CAPS ---------------------------------------*/ 197 #define SOC_PCNT_GROUPS (1) 198 #define SOC_PCNT_UNITS_PER_GROUP (8) 199 #define SOC_PCNT_CHANNELS_PER_UNIT (2) 200 #define SOC_PCNT_THRES_POINT_PER_UNIT (2) 201 202 /*-------------------------- RMT CAPS ----------------------------------------*/ 203 #define SOC_RMT_GROUPS (1) /*!< One RMT group */ 204 #define SOC_RMT_TX_CANDIDATES_PER_GROUP (8) /*!< Number of channels that capable of Transmit in each group */ 205 #define SOC_RMT_RX_CANDIDATES_PER_GROUP (8) /*!< Number of channels that capable of Receive in each group */ 206 #define SOC_RMT_CHANNELS_PER_GROUP (8) /*!< Total 8 channels */ 207 #define SOC_RMT_MEM_WORDS_PER_CHANNEL (64) /*!< Each channel owns 64 words memory */ 208 #define SOC_RMT_SUPPORT_REF_TICK (1) /*!< Support set REF_TICK as the RMT clock source */ 209 #define SOC_RMT_CHANNEL_CLK_INDEPENDENT (1) /*!< Can select different source clock for each channel */ 210 211 /*-------------------------- RTCIO CAPS --------------------------------------*/ 212 #define SOC_RTCIO_PIN_COUNT 18 213 #define SOC_RTCIO_INPUT_OUTPUT_SUPPORTED 1 214 #define SOC_RTCIO_HOLD_SUPPORTED 1 215 #define SOC_RTCIO_WAKE_SUPPORTED 1 216 217 /*-------------------------- SIGMA DELTA CAPS --------------------------------*/ 218 #define SOC_SIGMADELTA_NUM 1 219 #define SOC_SIGMADELTA_CHANNEL_NUM (8) // 8 channels 220 221 /*-------------------------- SPI CAPS ----------------------------------------*/ 222 #define SOC_SPI_PERIPH_NUM 3 223 #define SOC_SPI_DMA_CHAN_NUM 2 224 225 #define SOC_SPI_PERIPH_CS_NUM(i) 3 226 227 #define SOC_SPI_MAXIMUM_BUFFER_SIZE 64 228 #define SOC_SPI_MAX_PRE_DIVIDER 8192 229 230 #define SOC_SPI_SUPPORT_AS_CS 1 //Support to toggle the CS while the clock toggles 231 232 // Peripheral supports DIO, DOUT, QIO, or QOUT 233 #define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(spi_host) ({(void)spi_host; 1;}) 234 235 /*-------------------------- TIMER GROUP CAPS --------------------------------*/ 236 #define SOC_TIMER_GROUPS (2) 237 #define SOC_TIMER_GROUP_TIMERS_PER_GROUP (2) 238 #define SOC_TIMER_GROUP_COUNTER_BIT_WIDTH (64) 239 #define SOC_TIMER_GROUP_TOTAL_TIMERS (SOC_TIMER_GROUPS * SOC_TIMER_GROUP_TIMERS_PER_GROUP) 240 241 /*-------------------------- TOUCH SENSOR CAPS -------------------------------*/ 242 #define SOC_TOUCH_VERSION_1 (1) /*!<Hardware version of touch sensor */ 243 #define SOC_TOUCH_SENSOR_NUM (10) 244 245 #define SOC_TOUCH_PAD_MEASURE_WAIT_MAX (0xFF) /*!<The timer frequency is 8Mhz, the max value is 0xff */ 246 #define SOC_TOUCH_PAD_THRESHOLD_MAX (0) /*!<If set touch threshold max value, The touch sensor can't be in touched status */ 247 248 /*-------------------------- TWAI CAPS ---------------------------------------*/ 249 #define SOC_TWAI_BRP_MIN 2 250 #if SOC_CAPS_ECO_VER >= 2 251 # define SOC_TWAI_BRP_MAX 256 252 # define SOC_TWAI_BRP_DIV_SUPPORTED 1 253 # define SOC_TWAI_BRP_DIV_THRESH 128 254 #else 255 # define SOC_TWAI_BRP_MAX 128 256 #endif 257 #define SOC_TWAI_SUPPORT_MULTI_ADDRESS_LAYOUT 1 258 259 /*-------------------------- UART CAPS ---------------------------------------*/ 260 // ESP32 have 3 UART. 261 #define SOC_UART_NUM (3) 262 #define SOC_UART_SUPPORT_REF_TICK (1) /*!< Support REF_TICK as the clock source */ 263 #define SOC_UART_FIFO_LEN (128) /*!< The UART hardware FIFO length */ 264 #define SOC_UART_BITRATE_MAX (5000000) /*!< Max bit rate supported by UART */ 265 266 267 /*-------------------------- SPIRAM CAPS -------------------------------------*/ 268 #define SOC_SPIRAM_SUPPORTED 1 269 270 /*--------------------------- SHA CAPS ---------------------------------------*/ 271 /* ESP32 style SHA engine, where multiple states can be stored in parallel */ 272 #define SOC_SHA_SUPPORT_PARALLEL_ENG (1) 273 274 /* Supported HW algorithms */ 275 #define SOC_SHA_SUPPORT_SHA1 (1) 276 #define SOC_SHA_SUPPORT_SHA256 (1) 277 #define SOC_SHA_SUPPORT_SHA384 (1) 278 #define SOC_SHA_SUPPORT_SHA512 (1) 279 280 281 /*--------------------------- RSA CAPS ---------------------------------------*/ 282 #define SOC_RSA_MAX_BIT_LEN (4096) 283 284 285 /*-------------------------- AES CAPS -----------------------------------------*/ 286 #define SOC_AES_SUPPORT_AES_128 (1) 287 #define SOC_AES_SUPPORT_AES_192 (1) 288 #define SOC_AES_SUPPORT_AES_256 (1) 289 290 /*-------------------------- Flash Encryption CAPS----------------------------*/ 291 #define SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX (32) 292 293 /*--------------- PHY REGISTER AND MEMORY SIZE CAPS --------------------------*/ 294 #define SOC_PHY_DIG_REGS_MEM_SIZE (21*4) 295 296 /*-------------------------- Power Management CAPS ---------------------------*/ 297 #define SOC_PM_SUPPORT_EXT_WAKEUP (1) 298 #define SOC_PM_SUPPORT_TOUCH_SENSOR_WAKEUP (1) /*!<Supports waking up from touch pad trigger */ 299 300 /* ---------------------------- Compatibility ------------------------------- */ 301 #define SOC_CAN_SUPPORTED SOC_TWAI_SUPPORTED 302 #define CAN_BRP_MIN SOC_TWAI_BRP_MIN 303 #define CAN_BRP_MAX SOC_TWAI_BRP_MAX 304 #define CAN_SUPPORT_MULTI_ADDRESS_LAYOUT SOC_TWAI_SUPPORT_MULTI_ADDRESS_LAYOUT 305 #if SOC_CAPS_ECO_VER >= 2 306 # define CAN_BRP_DIV_SUPPORTED SOC_TWAI_BRP_DIV_SUPPORTED 307 # define CAN_BRP_DIV_THRESH SOC_TWAI_BRP_DIV_THRESH 308 #endif 309 310 /*-------------------------- SDMMC CAPS -----------------------------------------*/ 311 312 /* On ESP32, clock/cmd/data pins use IO MUX. 313 * Card detect, write protect, interrupt use GPIO Matrix on all chips. 314 */ 315 #define SOC_SDMMC_USE_IOMUX 1 316 #define SOC_SDMMC_NUM_SLOTS 2 317 318 /*------------------------------ BLE --------------------------------------------*/ 319 #define SOC_BLE_DONT_UPDATE_OWN_RPA (1) 320
