1 // Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 #ifndef _CACHE_MEMORY_H_ 15 #define _CACHE_MEMORY_H_ 16 17 #ifdef __cplusplus 18 extern "C" { 19 #endif 20 21 /*IRAM0 is connected with Cache IBUS0*/ 22 #define IRAM0_ADDRESS_LOW 0x40000000 23 #define IRAM0_ADDRESS_HIGH 0x40400000 24 #define IRAM0_CACHE_ADDRESS_LOW 0x40080000 25 #define IRAM0_CACHE_ADDRESS_HIGH 0x40400000 26 27 /*IRAM1 is connected with Cache IBUS1*/ 28 #define IRAM1_ADDRESS_LOW 0x40400000 29 #define IRAM1_ADDRESS_HIGH 0x40800000 30 31 /*DROM0 is connected with Cache IBUS2*/ 32 #define DROM0_ADDRESS_LOW 0x3f000000 33 #define DROM0_ADDRESS_HIGH 0x3f400000 34 35 /*DRAM0 is connected with Cache DBUS0*/ 36 #define DRAM0_ADDRESS_LOW 0x3fc00000 37 #define DRAM0_ADDRESS_HIGH 0x40000000 38 #define DRAM0_CACHE_ADDRESS_LOW 0x3fc00000 39 #define DRAM0_CACHE_ADDRESS_HIGH 0x3ff80000 40 41 /*DRAM1 is connected with Cache DBUS1*/ 42 #define DRAM1_ADDRESS_LOW 0x3f800000 43 #define DRAM1_ADDRESS_HIGH 0x3fc00000 44 45 /*DPORT is connected with Cache DBUS2*/ 46 #define DPORT_ADDRESS_LOW 0x3f400000 47 #define DPORT_ADDRESS_HIGH 0x3f800000 48 #define DPORT_CACHE_ADDRESS_LOW 0x3f500000 49 #define DPORT_CACHE_ADDRESS_HIGH 0x3f800000 50 51 #define BUS_SIZE(bus_name) (bus_name##_ADDRESS_HIGH - bus_name##_ADDRESS_LOW) 52 #define ADDRESS_IN_BUS(bus_name, vaddr) ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name##_ADDRESS_HIGH) 53 54 #define ADDRESS_IN_IRAM0(vaddr) ADDRESS_IN_BUS(IRAM0, vaddr) 55 #define ADDRESS_IN_IRAM0_CACHE(vaddr) ADDRESS_IN_BUS(IRAM0_CACHE, vaddr) 56 #define ADDRESS_IN_IRAM1(vaddr) ADDRESS_IN_BUS(IRAM1, vaddr) 57 #define ADDRESS_IN_DROM0(vaddr) ADDRESS_IN_BUS(DROM0, vaddr) 58 #define ADDRESS_IN_DRAM0(vaddr) ADDRESS_IN_BUS(DRAM0, vaddr) 59 #define ADDRESS_IN_DRAM0_CACHE(vaddr) ADDRESS_IN_BUS(DRAM0_CACHE, vaddr) 60 #define ADDRESS_IN_DRAM1(vaddr) ADDRESS_IN_BUS(DRAM1, vaddr) 61 #define ADDRESS_IN_DPORT(vaddr) ADDRESS_IN_BUS(DPORT, vaddr) 62 #define ADDRESS_IN_DPORT_CACHE(vaddr) ADDRESS_IN_BUS(DPORT_CACHE, vaddr) 63 64 #define BUS_IRAM0_CACHE_SIZE BUS_SIZE(IRAM0_CACHE) 65 #define BUS_IRAM1_CACHE_SIZE BUS_SIZE(IRAM1) 66 #define BUS_IROM0_CACHE_SIZE BUS_SIZE(IROM0) 67 #define BUS_DROM0_CACHE_SIZE BUS_SIZE(DROM0) 68 #define BUS_DRAM0_CACHE_SIZE BUS_SIZE(DRAM0_CACHE) 69 #define BUS_DRAM1_CACHE_SIZE BUS_SIZE(DRAM1) 70 #define BUS_DPORT_CACHE_SIZE BUS_SIZE(DPORT_CACHE) 71 72 #define PRO_CACHE_IBUS0 0 73 #define PRO_CACHE_IBUS0_MMU_START 0 74 #define PRO_CACHE_IBUS0_MMU_END 0x100 75 76 #define PRO_CACHE_IBUS1 1 77 #define PRO_CACHE_IBUS1_MMU_START 0x100 78 #define PRO_CACHE_IBUS1_MMU_END 0x200 79 80 #define PRO_CACHE_IBUS2 2 81 #define PRO_CACHE_IBUS2_MMU_START 0x200 82 #define PRO_CACHE_IBUS2_MMU_END 0x300 83 84 #define PRO_CACHE_DBUS0 3 85 #define PRO_CACHE_DBUS0_MMU_START 0x300 86 #define PRO_CACHE_DBUS0_MMU_END 0x400 87 88 #define PRO_CACHE_DBUS1 4 89 #define PRO_CACHE_DBUS1_MMU_START 0x400 90 #define PRO_CACHE_DBUS1_MMU_END 0x500 91 92 #define PRO_CACHE_DBUS2 5 93 #define PRO_CACHE_DBUS2_MMU_START 0x500 94 #define PRO_CACHE_DBUS2_MMU_END 0x600 95 96 // #define MMU_SIZE 0x600 97 #define ICACHE_MMU_SIZE 0x300 98 #define DCACHE_MMU_SIZE 0x300 99 100 #define MMU_BUS_START(i) ((i) * 0x100) 101 #define MMU_BUS_SIZE 0x100 102 103 #define MMU_INVALID BIT(14) 104 #define MMU_ACCESS_FLASH BIT(15) 105 #define MMU_ACCESS_SPIRAM BIT(16) 106 107 #define FLASH_MMU_TABLE ((volatile uint32_t*) DR_REG_MMU_TABLE) 108 #define FLASH_MMU_TABLE_SIZE (ICACHE_MMU_SIZE/sizeof(uint32_t)) 109 110 #define MMU_TABLE_INVALID_VAL 0x4000 111 #define FLASH_MMU_TABLE_INVALID_VAL DPORT_MMU_TABLE_INVALID_VAL 112 #define MMU_ADDRESS_MASK 0x3fff 113 #define MMU_PAGE_SIZE 0x10000 114 115 #define BUS_ADDR_SIZE 0x400000 116 #define BUS_ADDR_MASK (BUS_ADDR_SIZE - 1) 117 #define BUS_NUM_MASK 0x3 118 119 #define CACHE_MEMORY_BANK_SIZE 8192 120 #define CACHE_MEMORY_BANK_NUM 4 121 #define CACHE_MEMORY_BANK_NUM_MASK 0x3 122 #define CACHE_MEMORY_LAYOUT_SHIFT 4 123 #define CACHE_MEMORY_LAYOUT_SHIFT0 0 124 #define CACHE_MEMORY_LAYOUT_SHIFT1 4 125 #define CACHE_MEMORY_LAYOUT_SHIFT2 8 126 #define CACHE_MEMORY_LAYOUT_SHIFT3 12 127 #define CACHE_MEMORY_LAYOUT_MASK 0xf 128 #define CACHE_MEMORY_BANK0_ADDR 0x3FFB0000 129 #define CACHE_MEMORY_BANK1_ADDR 0x3FFB2000 130 #define CACHE_MEMORY_BANK2_ADDR 0x3FFB4000 131 #define CACHE_MEMORY_BANK3_ADDR 0x3FFB6000 132 133 #ifdef __cplusplus 134 } 135 #endif 136 137 #endif /*_CACHE_MEMORY_H_ */ 138
