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Searched refs:ALIGNUP (Results 1 – 5 of 5) sorted by relevance

/hal_espressif-3.6.0/components/xtensa/include/xtensa/
Dxtensa_context.h51 #define ALIGNUP(n, val) (((val) + (n)-1) & -(n)) macro
157 #define XT_STK_EXTRA ALIGNUP(XCHAL_EXTRA_SA_ALIGN, XT_STK_NEXT1)
160 #define XT_STK_EXTRA (ALIGNUP(XCHAL_EXTRA_SA_ALIGN, XT_STK_NEXT1) + XCHAL_EXTRA_SA_ALIGN)
176 #define XT_STK_FRMSZ (ALIGNUP(0x10, XT_STK_NEXT2) + 0x20)
225 #define XT_SOL_FRMSZ ALIGNUP(0x10, XtSolFrameSize)
294 #define XT_CP1_SA ALIGNUP(XCHAL_CP1_SA_ALIGN, XT_CP0_SA + XCHAL_CP0_SA_SIZE)
295 #define XT_CP2_SA ALIGNUP(XCHAL_CP2_SA_ALIGN, XT_CP1_SA + XCHAL_CP1_SA_SIZE)
296 #define XT_CP3_SA ALIGNUP(XCHAL_CP3_SA_ALIGN, XT_CP2_SA + XCHAL_CP2_SA_SIZE)
297 #define XT_CP4_SA ALIGNUP(XCHAL_CP4_SA_ALIGN, XT_CP3_SA + XCHAL_CP3_SA_SIZE)
298 #define XT_CP5_SA ALIGNUP(XCHAL_CP5_SA_ALIGN, XT_CP4_SA + XCHAL_CP4_SA_SIZE)
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/hal_espressif-3.6.0/components/esp_hw_support/
Dsleep_retention.c58 code_seg_size = ALIGNUP(imode.cache_line_size, code_seg_size); in cache_tagmem_retention_setup()
68 icache_tagmem_blk_gs = ALIGNUP(4, icache_tagmem_blk_gs); in cache_tagmem_retention_setup()
78 data_seg_size = ALIGNUP(dmode.cache_line_size, data_seg_size); in cache_tagmem_retention_setup()
92 dcache_tagmem_blk_gs = ALIGNUP(4, dcache_tagmem_blk_gs); in cache_tagmem_retention_setup()
/hal_espressif-3.6.0/components/riscv/include/riscv/
Drvruntime-frames.h19 #define ALIGNUP(n, val) (((val) + (n) - 1) & -(n)) macro
94 #define RV_STK_FRMSZ (ALIGNUP(0x10, RV_STK_SZ1))
/hal_espressif-3.6.0/components/freertos/port/riscv/
Dport.c221 thread_local_sz = ALIGNUP(0x10, thread_local_sz); in pxPortInitialiseStack()
/hal_espressif-3.6.0/components/freertos/port/xtensa/
Dport.c156 thread_local_sz = ALIGNUP(0x10, thread_local_sz); in pxPortInitialiseStack()