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Searched refs:AES_XTS_SIZE_REG (Results 1 – 8 of 8) sorted by relevance

/hal_espressif-3.6.0/components/hal/esp32h2/include/hal/
Dspi_flash_encrypted_ll.h82 REG_WRITE(AES_XTS_SIZE_REG, size >> 5); in spi_flash_encrypt_ll_buffer_length()
/hal_espressif-3.6.0/components/hal/esp32s3/include/hal/
Dspi_flash_encrypted_ll.h82 REG_WRITE(AES_XTS_SIZE_REG, size >> 5); in spi_flash_encrypt_ll_buffer_length()
/hal_espressif-3.6.0/components/hal/esp32c3/include/hal/
Dspi_flash_encrypted_ll.h82 REG_WRITE(AES_XTS_SIZE_REG, size >> 5); in spi_flash_encrypt_ll_buffer_length()
/hal_espressif-3.6.0/components/hal/esp32s2/include/hal/
Dspi_flash_encrypted_ll.h92 REG_WRITE(AES_XTS_SIZE_REG, size >> 5); in spi_flash_encrypt_ll_buffer_length()
/hal_espressif-3.6.0/components/soc/esp32s3/include/soc/
Dhwcrypto_reg.h117 #define AES_XTS_SIZE_REG ((DR_REG_EXT_MEM_ENC) + 0x40) macro
/hal_espressif-3.6.0/components/soc/esp32c3/include/soc/
Dhwcrypto_reg.h154 #define AES_XTS_SIZE_REG ((DR_REG_AES_XTS_BASE) + 0x40) macro
/hal_espressif-3.6.0/components/soc/esp32h2/include/soc/
Dhwcrypto_reg.h154 #define AES_XTS_SIZE_REG ((DR_REG_AES_XTS_BASE) + 0x40) macro
/hal_espressif-3.6.0/components/soc/esp32s2/include/soc/
Dhwcrypto_reg.h166 #define AES_XTS_SIZE_REG ((DR_REG_AES_BASE) + 0x140) macro