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/hal_espressif-3.5.0/components/mbedtls/port/dynamic/
Desp_mbedtls_dynamic_impl.c238 int cached = 0; in esp_mbedtls_add_tx_buffer() local
253 cached = 1; in esp_mbedtls_add_tx_buffer()
271 if (cached) { in esp_mbedtls_add_tx_buffer()
322 int cached = 0; in esp_mbedtls_add_rx_buffer() local
338 cached = 1; in esp_mbedtls_add_rx_buffer()
366 if (cached) { in esp_mbedtls_add_rx_buffer()
384 if (cached) { in esp_mbedtls_add_rx_buffer()
/hal_espressif-3.5.0/tools/unit-test-app/components/test_utils/test/
Dccomp_timer_test_data.c85 static void prepare_access_pattern(int hit_rate, const uint8_t *cached, ccomp_test_access_t *out) in prepare_access_pattern() argument
97 accesses[i] = (uint8_t*) (cached + CACHE_SIZE + i); in prepare_access_pattern()
100 accesses[i] = (uint8_t*) (cached + i); in prepare_access_pattern()
/hal_espressif-3.5.0/components/spi_flash/include/
Desp_spi_flash.h289 size_t spi_flash_cache2phys(const void *cached);
/hal_espressif-3.5.0/components/spi_flash/
Dflash_mmap.c386 size_t spi_flash_cache2phys(const void *cached) in spi_flash_cache2phys() argument
388 intptr_t c = (intptr_t)cached; in spi_flash_cache2phys()
/hal_espressif-3.5.0/components/usb/
DKconfig27 … maximum number of packets that can be cached at any one time. The hardware contains the following
/hal_espressif-3.5.0/components/esptool_py/esptool/docs/en/advanced-topics/
Dspi-flash-modes.rst10 …r executing code and data from the SPI flash chip. Data is read and then cached internally to the …
99 …ectly from flash, however because reading from flash is slow the data is cached transparently in R…
/hal_espressif-3.5.0/docs/en/api-guides/
Dmemory-types.rst117 … instruction space. Flash accessed via the MMU is cached using some internal SRAM and accessing ca…
Dexternal-ram.rst135 …he external RAM. Moreover, accessing large chunks of data can "push out" cached flash, possibly ma…
Dfatal-errors.rst442 .. |CACHE_ERR_MSG| replace:: Cache disabled but cached memory region accessed
/hal_espressif-3.5.0/examples/peripherals/usb/host/usb_host_lib/
DREADME.md182 …a particular descriptor, it is likely that the string descriptor was not cached during enumeration.
/hal_espressif-3.5.0/components/xtensa/include/xtensa/
Dhal.h992 extern int xthal_static_p2v( unsigned paddr, unsigned *vaddrp, unsigned cached );
/hal_espressif-3.5.0/docs/zh_CN/api-guides/
Dfatal-errors.rst421 .. |CACHE_ERR_MSG| replace:: Cache disabled but cached memory region accessed
/hal_espressif-3.5.0/components/fatfs/src/
D00history.txt85 Fixed cached sector is not flushed when create and close without write.
/hal_espressif-3.5.0/components/esp_wifi/
DKconfig109 size of the cached TX queue.
/hal_espressif-3.5.0/components/lwip/
DKconfig556 … LWIP_TCP_RECCVMBOX_SIZE packets for each TCP socket, so the maximum possible cached TCP packets
659 … UDP_RECCVMBOX_SIZE packets for each UDP socket, so the maximum possible cached UDP packets
/hal_espressif-3.5.0/docs/en/api-reference/peripherals/
Dspi_master.rst355 will cause a `Cache disabled but cached memory region accessed` exception. For differences
/hal_espressif-3.5.0/components/bt/esp_ble_mesh/
DKconfig.in544 Number of messages that are cached for the network. This helps prevent