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Searched refs:REG_SET_BIT (Results 1 – 25 of 87) sorted by relevance

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/hal_espressif-3.5.0/components/driver/test/dac_dma_test/
Dtest_esp32s2.c307 REG_SET_BIT(DPORT_PERIP_CLK_EN_REG, DPORT_APB_SARADC_CLK_EN_M); in adc_dac_dma_linker_start()
308 REG_SET_BIT(DPORT_PERIP_CLK_EN_REG, DPORT_SPI3_DMA_CLK_EN_M); in adc_dac_dma_linker_start()
309 REG_SET_BIT(DPORT_PERIP_CLK_EN_REG, DPORT_SPI3_CLK_EN); in adc_dac_dma_linker_start()
315 REG_SET_BIT(SPI_DMA_IN_LINK_REG(3), SPI_INLINK_STOP); in adc_dac_dma_linker_start()
318 REG_SET_BIT(SPI_DMA_CONF_REG(3), SPI_IN_RST); in adc_dac_dma_linker_start()
321 REG_SET_BIT(SPI_DMA_IN_LINK_REG(3), SPI_INLINK_START); in adc_dac_dma_linker_start()
324 REG_SET_BIT(SPI_DMA_OUT_LINK_REG(3), SPI_OUTLINK_STOP); in adc_dac_dma_linker_start()
327 REG_SET_BIT(SPI_DMA_CONF_REG(3), SPI_OUT_RST); in adc_dac_dma_linker_start()
330 REG_SET_BIT(SPI_DMA_OUT_LINK_REG(3), SPI_OUTLINK_START); in adc_dac_dma_linker_start()
337 REG_SET_BIT(SPI_DMA_IN_LINK_REG(3), SPI_INLINK_STOP); in adc_dac_dma_linker_stop()
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/hal_espressif-3.5.0/components/hal/esp32s3/include/hal/
Drtc_cntl_ll.h52 REG_SET_BIT(RTC_CNTL_EXT_WAKEUP1_REG, RTC_CNTL_EXT_WAKEUP1_STATUS_CLR); in rtc_cntl_ll_ext1_clear_wakeup_pins()
77 REG_SET_BIT(APB_CTRL_RETENTION_CTRL2_REG, APB_CTRL_RET_ICACHE_ENABLE); in rtc_cntl_ll_enable_icache_tagmem_retention()
85 REG_SET_BIT(APB_CTRL_RETENTION_CTRL3_REG, APB_CTRL_RET_DCACHE_ENABLE); in rtc_cntl_ll_enable_dcache_tagmem_retention()
112 REG_SET_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN); /* Enable internal 20 MHz clock */ in rtc_cntl_ll_enable_cpu_retention_clock()
121 REG_SET_BIT(RTC_CNTL_RETENTION_CTRL_REG, RTC_CNTL_RETENTION_EN); in rtc_cntl_ll_enable_cpu_retention()
/hal_espressif-3.5.0/components/bootloader_support/src/esp32c3/
Dbootloader_soc.c15 REG_SET_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_BYPASS_RST); in bootloader_ana_super_wdt_reset_config()
26 REG_SET_BIT(RTC_CNTL_BROWN_OUT_REG, RTC_CNTL_BROWN_OUT_ANA_RST_EN); in bootloader_ana_bod_reset_config()
37 REG_SET_BIT(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_GLITCH_RST_EN); in bootloader_ana_clock_glitch_reset_config()
/hal_espressif-3.5.0/components/bootloader_support/src/esp32h2/
Dbootloader_soc.c15 REG_SET_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_BYPASS_RST); in bootloader_ana_super_wdt_reset_config()
26 REG_SET_BIT(RTC_CNTL_BROWN_OUT_REG, RTC_CNTL_BROWN_OUT_ANA_RST_EN); in bootloader_ana_bod_reset_config()
37 REG_SET_BIT(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_GLITCH_RST_EN); in bootloader_ana_clock_glitch_reset_config()
/hal_espressif-3.5.0/components/bootloader_support/src/esp32s3/
Dbootloader_soc.c17 REG_SET_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_BYPASS_RST); in bootloader_ana_super_wdt_reset_config()
26 REG_SET_BIT(RTC_CNTL_BROWN_OUT_REG, RTC_CNTL_BROWN_OUT_ANA_RST_EN); in bootloader_ana_bod_reset_config()
37 REG_SET_BIT(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_GLITCH_RST_EN); in bootloader_ana_clock_glitch_reset_config()
/hal_espressif-3.5.0/components/esp_hw_support/port/esp32/
Drtc_wdt.c29 REG_SET_BIT(RTC_CNTL_WDTFEED_REG, RTC_CNTL_WDT_FEED); in rtc_wdt_enable()
35 REG_SET_BIT(RTC_CNTL_WDTCONFIG0_REG, RTC_CNTL_WDT_FLASHBOOT_MOD_EN); in rtc_wdt_flashboot_mode_enable()
44 REG_SET_BIT(RTC_CNTL_WDTFEED_REG, RTC_CNTL_WDT_FEED); in rtc_wdt_disable()
62 REG_SET_BIT(RTC_CNTL_WDTFEED_REG, RTC_CNTL_WDT_FEED); in rtc_wdt_feed()
/hal_espressif-3.5.0/components/esp_hw_support/port/esp32s2/
Drtc_wdt.c30 REG_SET_BIT(RTC_CNTL_WDTFEED_REG, RTC_CNTL_WDT_FEED); in rtc_wdt_enable()
36 REG_SET_BIT(RTC_CNTL_WDTCONFIG0_REG, RTC_CNTL_WDT_FLASHBOOT_MOD_EN); in rtc_wdt_flashboot_mode_enable()
45 REG_SET_BIT(RTC_CNTL_WDTFEED_REG, RTC_CNTL_WDT_FEED); in rtc_wdt_disable()
63 REG_SET_BIT(RTC_CNTL_WDTFEED_REG, RTC_CNTL_WDT_FEED); in rtc_wdt_feed()
/hal_espressif-3.5.0/components/hal/esp32c3/include/hal/
Drtc_cntl_ll.h47 REG_SET_BIT(RTC_CNTL_GPIO_WAKEUP_REG, RTC_CNTL_GPIO_WAKEUP_STATUS_CLR); in rtc_cntl_ll_gpio_clear_wakeup_pins()
57 REG_SET_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN); in rtc_cntl_ll_enable_cpu_retention_clock()
63 REG_SET_BIT(RTC_CNTL_RETENTION_CTRL_REG, RTC_CNTL_RETENTION_EN); in rtc_cntl_ll_enable_cpu_retention()
Dgpio_ll.h42 REG_SET_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PU); in gpio_ll_pullup_en()
64 REG_SET_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PD); in gpio_ll_pulldown_en()
343 REG_SET_BIT(RTC_CNTL_PAD_HOLD_REG, BIT(gpio_num)); in gpio_ll_hold_en()
545 REG_SET_BIT(RTC_CNTL_GPIO_WAKEUP_REG, RTC_CNTL_GPIO_PIN_CLK_GATE); in gpio_ll_deepsleep_wakeup_enable()
546 REG_SET_BIT(RTC_CNTL_EXT_WAKEUP_CONF_REG, RTC_CNTL_GPIO_WAKEUP_FILTER); in gpio_ll_deepsleep_wakeup_enable()
Dmemprot_ll.h248 …REG_SET_BIT(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_E… in memprot_ll_iram0_set_monitor_en()
266 …REG_SET_BIT(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_C… in memprot_ll_iram0_set_monitor_intrclr()
533 … REG_SET_BIT(SENSITIVE_CORE_0_PIF_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN); in memprot_ll_rtcfast_set_monitor_en()
551 … REG_SET_BIT(SENSITIVE_CORE_0_PIF_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR); in memprot_ll_rtcfast_set_monitor_intrclr()
768 …REG_SET_BIT(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_E… in memprot_ll_dram0_set_monitor_en()
781 …REG_SET_BIT(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_C… in memprot_ll_dram0_set_monitor_intrclr()
/hal_espressif-3.5.0/components/spi_flash/esp32/
Dspi_flash_rom_patch.c342 REG_SET_BIT(SPI_USER_REG(0), SPI_USR_MISO | SPI_USR_DUMMY | SPI_USR_ADDR); in spi_cache_mode_switch()
348 REG_SET_BIT(SPI_USER_REG(0), SPI_USR_MISO | SPI_USR_DUMMY | SPI_USR_ADDR); in spi_cache_mode_switch()
369 REG_SET_BIT(SPI_USER_REG(0), SPI_USR_DUMMY); in spi_cache_mode_switch()
372 REG_SET_BIT(SPI_USER_REG(0), SPI_USR_MISO | SPI_USR_ADDR); in spi_cache_mode_switch()
562 REG_SET_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_USR_MISO | SPI_USR_DUMMY | SPI_USR_ADDR); in esp_rom_spiflash_read()
569 REG_SET_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_USR_MISO | SPI_USR_ADDR); in esp_rom_spiflash_read()
576 REG_SET_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_USR_DUMMY); in esp_rom_spiflash_read()
592 REG_SET_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_USR_DUMMY); in esp_rom_spiflash_read()
601 REG_SET_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_USR_DUMMY); in esp_rom_spiflash_read()
604 REG_SET_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_USR_MISO | SPI_USR_ADDR); in esp_rom_spiflash_read()
/hal_espressif-3.5.0/components/esp_timer/src/
Desp_timer_impl_lac.c188 REG_SET_BIT(CONFIG_REG, TIMG_LACT_ALARM_EN); in esp_timer_impl_set_alarm_id()
247 REG_SET_BIT(INT_CLR_REG, TIMG_LACT_INT_CLR); in esp_timer_impl_early_init()
249 REG_SET_BIT(CONFIG_REG, TIMG_LACT_INCREASE | in esp_timer_impl_early_init()
276 REG_SET_BIT(INT_ENA_REG, TIMG_LACT_INT_ENA); in esp_timer_impl_init()
291 REG_SET_BIT(INT_CLR_REG, TIMG_LACT_INT_CLR); in esp_timer_impl_deinit()
/hal_espressif-3.5.0/components/hal/esp32h2/include/hal/
Dgpio_ll.h52 REG_SET_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PU); in gpio_ll_pullup_en()
74 REG_SET_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PD); in gpio_ll_pulldown_en()
352 REG_SET_BIT(RTC_CNTL_PAD_HOLD_REG, BIT(gpio_num)); in gpio_ll_hold_en()
553 REG_SET_BIT(RTC_CNTL_GPIO_WAKEUP_REG, RTC_CNTL_GPIO_PIN_CLK_GATE); in gpio_ll_deepsleep_wakeup_enable()
554 REG_SET_BIT(RTC_CNTL_EXT_WAKEUP_CONF_REG, RTC_CNTL_GPIO_WAKEUP_FILTER); in gpio_ll_deepsleep_wakeup_enable()
Dmemprot_ll.h261 …REG_SET_BIT( SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_… in memprot_ll_iram0_set_monitor_en()
274 …REG_SET_BIT( SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_… in memprot_ll_iram0_clear_monitor_intr()
502 …REG_SET_BIT( SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_… in memprot_ll_dram0_set_monitor_en()
515 …REG_SET_BIT( SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_… in memprot_ll_dram0_clear_monitor_intr()
/hal_espressif-3.5.0/zephyr/esp32s3/src/boot/
Dapp_cpu_start.c32 REG_SET_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_CLKGATE_EN); in appcpu_start()
34 REG_SET_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_RESETTING); in appcpu_start()
/hal_espressif-3.5.0/components/esp_eth/src/
Dopeneth.h175 REG_SET_BIT(OPENETH_MODER_REG, OPENETH_TXEN | OPENETH_RXEN | OPENETH_PRO); in openeth_enable()
176 REG_SET_BIT(OPENETH_INT_MASK_REG, OPENETH_INT_RXB); in openeth_enable()
187 REG_SET_BIT(OPENETH_MODER_REG, OPENETH_RST); in openeth_reset()
/hal_espressif-3.5.0/components/bootloader_support/src/
Dbootloader_flash_config_esp32h2.c67 REG_SET_BIT(SPI_MEM_CTRL_REG(0), SPI_MEM_FDUMMY_OUT | SPI_MEM_D_POL | SPI_MEM_Q_POL); in bootloader_flash_set_dummy_out()
68 REG_SET_BIT(SPI_MEM_CTRL_REG(1), SPI_MEM_FDUMMY_OUT | SPI_MEM_D_POL | SPI_MEM_Q_POL); in bootloader_flash_set_dummy_out()
Dbootloader_flash_config_esp32c3.c67 REG_SET_BIT(SPI_MEM_CTRL_REG(0), SPI_MEM_FDUMMY_OUT | SPI_MEM_D_POL | SPI_MEM_Q_POL); in bootloader_flash_set_dummy_out()
68 REG_SET_BIT(SPI_MEM_CTRL_REG(1), SPI_MEM_FDUMMY_OUT | SPI_MEM_D_POL | SPI_MEM_Q_POL); in bootloader_flash_set_dummy_out()
Dbootloader_flash_config_esp32s2.c71 REG_SET_BIT(SPI_MEM_CTRL_REG(0), SPI_MEM_FDUMMY_OUT | SPI_MEM_D_POL | SPI_MEM_Q_POL); in bootloader_flash_set_dummy_out()
72 REG_SET_BIT(SPI_MEM_CTRL_REG(1), SPI_MEM_FDUMMY_OUT | SPI_MEM_D_POL | SPI_MEM_Q_POL); in bootloader_flash_set_dummy_out()
Dbootloader_flash_config_esp32s3.c75 REG_SET_BIT(SPI_MEM_CTRL_REG(0), SPI_MEM_FDUMMY_OUT | SPI_MEM_D_POL | SPI_MEM_Q_POL); in bootloader_flash_set_dummy_out()
76 REG_SET_BIT(SPI_MEM_CTRL_REG(1), SPI_MEM_FDUMMY_OUT | SPI_MEM_D_POL | SPI_MEM_Q_POL); in bootloader_flash_set_dummy_out()
/hal_espressif-3.5.0/components/hal/esp32s2/include/hal/
Dspi_flash_encrypted_ll.h46 REG_SET_BIT(DPORT_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG, in spi_flash_encrypt_ll_enable()
57 REG_SET_BIT(DPORT_CPU_PERIP_CLK_EN1_REG, DPORT_CRYPTO_AES_CLK_EN); in spi_flash_encrypt_ll_aes_accelerator_enable()
/hal_espressif-3.5.0/components/driver/esp32c3/
Drtc_tempsensor.c68 REG_SET_BIT(SYSTEM_PERIP_CLK_EN1_REG, SYSTEM_TSENS_CLK_EN); in temp_sensor_set_config()
105 REG_SET_BIT(SYSTEM_PERIP_CLK_EN1_REG, SYSTEM_TSENS_CLK_EN); in temp_sensor_start()
/hal_espressif-3.5.0/components/driver/esp32h2/
Drtc_tempsensor.c66 REG_SET_BIT(SYSTEM_PERIP_CLK_EN1_REG, SYSTEM_TSENS_CLK_EN); in temp_sensor_set_config()
103 REG_SET_BIT(SYSTEM_PERIP_CLK_EN1_REG, SYSTEM_TSENS_CLK_EN); in temp_sensor_start()
/hal_espressif-3.5.0/components/spi_flash/
Dcache_utils.c447 REG_SET_BIT(EXTMEM_PRO_CACHE_WRAP_AROUND_CTRL_REG, EXTMEM_PRO_CACHE_FLASH_WRAP_AROUND); in esp_enable_cache_flash_wrap()
466 REG_SET_BIT(EXTMEM_PRO_CACHE_WRAP_AROUND_CTRL_REG, EXTMEM_PRO_CACHE_SRAM_RD_WRAP_AROUND); in esp_enable_cache_spiram_wrap()
702 REG_SET_BIT(EXTMEM_CACHE_WRAP_AROUND_CTRL_REG, EXTMEM_CACHE_FLASH_WRAP_AROUND); in esp_enable_cache_flash_wrap()
721 REG_SET_BIT(EXTMEM_CACHE_WRAP_AROUND_CTRL_REG, EXTMEM_CACHE_SRAM_RD_WRAP_AROUND); in esp_enable_cache_spiram_wrap()
894 REG_SET_BIT(EXTMEM_CACHE_WRAP_AROUND_CTRL_REG, EXTMEM_CACHE_FLASH_WRAP_AROUND); in esp_enable_cache_flash_wrap()
/hal_espressif-3.5.0/components/esp_system/port/
Dcpu_start.c242 REG_SET_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_CLKGATE_EN); in start_other_core()
244 REG_SET_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_RESETTING); in start_other_core()
436 REG_SET_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_RUNSTALL);

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