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Searched refs:REG_GET_BIT (Results 1 – 25 of 28) sorted by relevance

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/hal_espressif-3.5.0/components/esp_hw_support/port/esp32s2/
Dregi2c_ctrl.c110 while (REG_GET_BIT(I2C_RTC_CONFIG2, I2C_RTC_BUSY)); in i2c_rtc_read_reg()
122 while (REG_GET_BIT(I2C_RTC_CONFIG2, I2C_RTC_BUSY)); in i2c_rtc_read_reg_mask()
136 while (REG_GET_BIT(I2C_RTC_CONFIG2, I2C_RTC_BUSY)); in i2c_rtc_write_reg()
148 while (REG_GET_BIT(I2C_RTC_CONFIG2, I2C_RTC_BUSY)); in i2c_rtc_write_reg_mask()
158 while (REG_GET_BIT(I2C_RTC_CONFIG2, I2C_RTC_BUSY)); in i2c_rtc_write_reg_mask()
Drtc_wdt.c143 …return (REG_GET_BIT(RTC_CNTL_WDTCONFIG0_REG, RTC_CNTL_WDT_EN) != 0) || (REG_GET_BIT(RTC_CNTL_WDTCO… in rtc_wdt_is_on()
/hal_espressif-3.5.0/components/hal/esp32/include/hal/
Dgpio_ll.h70 return REG_GET_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PU) ? true : false; in gpio_ll_pullup_is_enabled()
104 return REG_GET_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PD) ? true : false; in gpio_ll_pulldown_is_enabled()
138 return REG_GET_BIT(GPIO_PIN_MUX_REG[gpio_num], SLP_SEL) ? true : false; in gpio_ll_sleep_sel_is_enabled()
172 return REG_GET_BIT(GPIO_PIN_MUX_REG[gpio_num], SLP_PU) ? true : false; in gpio_ll_sleep_pullup_is_enabled()
206 return REG_GET_BIT(GPIO_PIN_MUX_REG[gpio_num], SLP_PD) ? true : false; in gpio_ll_sleep_pulldown_is_enabled()
/hal_espressif-3.5.0/components/bootloader_support/src/
Dbootloader_efuse_esp32.c55 if (REG_GET_BIT(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_CPU_FREQ_RATED) && in bootloader_clock_get_rated_freq_mhz()
56 REG_GET_BIT(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_CPU_FREQ_LOW)) { in bootloader_clock_get_rated_freq_mhz()
/hal_espressif-3.5.0/components/efuse/esp32c3/
Desp_efuse_utility.c67 while (REG_GET_BIT(EFUSE_CMD_REG, EFUSE_READ_CMD) != 0) { } in efuse_read()
69 while (REG_GET_BIT(EFUSE_CMD_REG, EFUSE_READ_CMD) != 0) { } in efuse_read()
81 while (REG_GET_BIT(EFUSE_CMD_REG, EFUSE_PGM_CMD) != 0) { }; in efuse_program()
/hal_espressif-3.5.0/components/efuse/esp32s3/
Desp_efuse_utility.c67 while (REG_GET_BIT(EFUSE_CMD_REG, EFUSE_READ_CMD) != 0) { } in efuse_read()
69 while (REG_GET_BIT(EFUSE_CMD_REG, EFUSE_READ_CMD) != 0) { } in efuse_read()
81 while (REG_GET_BIT(EFUSE_CMD_REG, EFUSE_PGM_CMD) != 0) { }; in efuse_program()
/hal_espressif-3.5.0/components/spi_flash/esp32s2/
Dflash_ops_esp32s2.c110 …if (!REG_GET_BIT(SPI_MEM_CTRL_REG(0), SPI_MEM_FREAD_QIO) || !REG_GET_BIT(SPI_MEM_CTRL_REG(0), SPI_… in spi_flash_support_wrap_size()
/hal_espressif-3.5.0/components/spi_flash/esp32s3/
Dflash_ops_esp32s3.c109 …if (!REG_GET_BIT(SPI_MEM_CTRL_REG(0), SPI_MEM_FREAD_QIO) || !REG_GET_BIT(SPI_MEM_CTRL_REG(0), SPI_… in spi_flash_support_wrap_size()
Dspi_timing_config.c369 return REG_GET_BIT(SPI_MEM_USER_REG(0), SPI_MEM_CS_SETUP); in s_get_cs_setup_enable()
374 return REG_GET_BIT(SPI_MEM_USER_REG(0), SPI_MEM_CS_HOLD); in s_get_cs_hold_enable()
/hal_espressif-3.5.0/components/esp_hw_support/port/esp32/
Drtc_wdt.c142 …return (REG_GET_BIT(RTC_CNTL_WDTCONFIG0_REG, RTC_CNTL_WDT_EN) != 0) || (REG_GET_BIT(RTC_CNTL_WDTCO… in rtc_wdt_is_on()
/hal_espressif-3.5.0/components/spi_flash/esp32c3/
Dflash_ops_esp32c3.c136 …if (!REG_GET_BIT(SPI_MEM_CTRL_REG(0), SPI_MEM_FREAD_QIO) || !REG_GET_BIT(SPI_MEM_CTRL_REG(0), SPI_… in spi_flash_support_wrap_size()
/hal_espressif-3.5.0/components/spi_flash/esp32h2/
Dflash_ops_esp32h2.c136 …if (!REG_GET_BIT(SPI_MEM_CTRL_REG(0), SPI_MEM_FREAD_QIO) || !REG_GET_BIT(SPI_MEM_CTRL_REG(0), SPI_… in spi_flash_support_wrap_size()
/hal_espressif-3.5.0/components/esp_hw_support/port/esp32h2/
Drtc_time.c48 bool dig_32k_xtal_state = REG_GET_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN); in rtc_clk_cal_internal()
53 bool dig_rc32k_state = REG_GET_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_RC32K_EN); in rtc_clk_cal_internal()
/hal_espressif-3.5.0/components/hal/esp32c3/include/hal/
Dmemprot_ll.h256 …return REG_GET_BIT(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VI… in memprot_ll_iram0_get_monitor_intrclr()
546 …return REG_GET_BIT(SENSITIVE_CORE_0_PIF_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLAT… in memprot_ll_rtcfast_get_monitor_intrclr()
776 …return REG_GET_BIT(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VI… in memprot_ll_dram0_get_monitor_en()
791 …return REG_GET_BIT(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VI… in memprot_ll_dram0_get_monitor_intrclr()
Dcpu_ll.h137 return REG_GET_BIT(ASSIST_DEBUG_CORE_0_DEBUG_MODE_REG, ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE); in cpu_ll_is_debugger_attached()
/hal_espressif-3.5.0/zephyr/esp32s3/src/boot/
Dapp_cpu_start.c31 if (!REG_GET_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_CLKGATE_EN)) { in appcpu_start()
/hal_espressif-3.5.0/components/ulp/test/esp32/
Dtest_ulp_as.c22 TEST_ASSERT_NOT_EQUAL(0, REG_GET_BIT(RTC_CNTL_INT_RAW_REG, RTC_CNTL_ULP_CP_INT_RAW));
/hal_espressif-3.5.0/components/soc/esp32s2/include/soc/
Dsoc.h143 #define REG_GET_BIT(_r, _b) ({ … macro
144 …ASSERT_IF_DPORT_REG((_r), REG_GET_BIT); …
/hal_espressif-3.5.0/components/soc/esp32/include/soc/
Dsoc.h114 #define REG_GET_BIT(_r, _b) ({ … macro
115 …ASSERT_IF_DPORT_REG((_r), REG_GET_BIT); …
/hal_espressif-3.5.0/components/ulp/ulp_riscv/include/ulp_riscv/
Dulp_riscv_register_ops.h56 #define REG_GET_BIT(_r, _b) ({ … macro
/hal_espressif-3.5.0/components/hal/esp32h2/include/hal/
Dcpu_ll.h135 return REG_GET_BIT(ASSIST_DEBUG_CORE_0_DEBUG_MODE_REG, ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE); in cpu_ll_is_debugger_attached()
/hal_espressif-3.5.0/components/soc/esp32c3/include/soc/
Dsoc.h108 #define REG_GET_BIT(_r, _b) ({ … macro
/hal_espressif-3.5.0/components/soc/esp32h2/include/soc/
Dsoc.h131 #define REG_GET_BIT(_r, _b) ({ … macro
/hal_espressif-3.5.0/components/soc/esp32s3/include/soc/
Dsoc.h141 #define REG_GET_BIT(_r, _b) ({ … macro
/hal_espressif-3.5.0/components/spi_flash/
Dcache_utils.c369 bool result = (REG_GET_BIT(EXTMEM_PRO_ICACHE_CTRL_REG, EXTMEM_PRO_ICACHE_ENABLE) != 0); in spi_flash_cache_enabled()
371 bool result = (REG_GET_BIT(EXTMEM_ICACHE_CTRL_REG, EXTMEM_ICACHE_ENABLE) != 0); in spi_flash_cache_enabled()

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