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Searched refs:REG_CLR_BIT (Results 1 – 25 of 73) sorted by relevance

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/hal_espressif-3.5.0/components/bootloader_support/src/esp32c3/
Dbootloader_soc.c12 REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_SUPER_WDT_RST); in bootloader_ana_super_wdt_reset_config()
17 REG_CLR_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_BYPASS_RST); in bootloader_ana_super_wdt_reset_config()
23 REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_BOR_RST); in bootloader_ana_bod_reset_config()
28 REG_CLR_BIT(RTC_CNTL_BROWN_OUT_REG, RTC_CNTL_BROWN_OUT_ANA_RST_EN); in bootloader_ana_bod_reset_config()
34 REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_GLITCH_RST); in bootloader_ana_clock_glitch_reset_config()
39 REG_CLR_BIT(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_GLITCH_RST_EN); in bootloader_ana_clock_glitch_reset_config()
Dbootloader_esp32c3.c82 REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, EXTMEM_ICACHE_SHUT_IBUS); in bootloader_reset_mmu()
83 REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, EXTMEM_ICACHE_SHUT_DBUS); in bootloader_reset_mmu()
223 REG_CLR_BIT(SYSTEM_CPU_PERI_RST_EN_REG, SYSTEM_RST_EN_ASSIST_DEBUG); in wdt_reset_cpu0_info_enable()
/hal_espressif-3.5.0/components/bootloader_support/src/esp32h2/
Dbootloader_soc.c12 REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_SUPER_WDT_RST); in bootloader_ana_super_wdt_reset_config()
17 REG_CLR_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_BYPASS_RST); in bootloader_ana_super_wdt_reset_config()
23 REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_BOR_RST); in bootloader_ana_bod_reset_config()
28 REG_CLR_BIT(RTC_CNTL_BROWN_OUT_REG, RTC_CNTL_BROWN_OUT_ANA_RST_EN); in bootloader_ana_bod_reset_config()
34 REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_GLITCH_RST); in bootloader_ana_clock_glitch_reset_config()
39 REG_CLR_BIT(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_GLITCH_RST_EN); in bootloader_ana_clock_glitch_reset_config()
Dbootloader_esp32h2.c81 REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, EXTMEM_ICACHE_SHUT_IBUS); in bootloader_reset_mmu()
82 REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, EXTMEM_ICACHE_SHUT_DBUS); in bootloader_reset_mmu()
222 REG_CLR_BIT(SYSTEM_CPU_PERI_RST_EN_REG, SYSTEM_RST_EN_ASSIST_DEBUG); in wdt_reset_cpu0_info_enable()
/hal_espressif-3.5.0/components/bootloader_support/src/esp32s3/
Dbootloader_soc.c12 REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_SUPER_WDT_RST); in bootloader_ana_super_wdt_reset_config()
15 REG_CLR_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_BYPASS_RST); in bootloader_ana_super_wdt_reset_config()
23 REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_BOD_RST); in bootloader_ana_bod_reset_config()
28 REG_CLR_BIT(RTC_CNTL_BROWN_OUT_REG, RTC_CNTL_BROWN_OUT_ANA_RST_EN); in bootloader_ana_bod_reset_config()
34 REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_GLITCH_RST); in bootloader_ana_clock_glitch_reset_config()
39 REG_CLR_BIT(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_GLITCH_RST_EN); in bootloader_ana_clock_glitch_reset_config()
/hal_espressif-3.5.0/components/esp_hw_support/port/esp32s3/
Drtc_sleep.c186 REG_CLR_BIT(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_WIFI_FORCE_NOISO | RTC_CNTL_WIFI_FORCE_ISO); in rtc_sleep_init()
187 REG_CLR_BIT(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_FORCE_PU); in rtc_sleep_init()
193 REG_CLR_BIT(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_BT_FORCE_NOISO | RTC_CNTL_BT_FORCE_ISO); in rtc_sleep_init()
194 REG_CLR_BIT(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_BT_FORCE_PU); in rtc_sleep_init()
200 … REG_CLR_BIT(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_CPU_TOP_FORCE_NOISO | RTC_CNTL_CPU_TOP_FORCE_ISO); in rtc_sleep_init()
201 REG_CLR_BIT(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_CPU_TOP_FORCE_PU); in rtc_sleep_init()
207 … REG_CLR_BIT(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PERI_FORCE_NOISO | RTC_CNTL_DG_PERI_FORCE_ISO); in rtc_sleep_init()
208 REG_CLR_BIT(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_PERI_FORCE_PU); in rtc_sleep_init()
214 … REG_CLR_BIT(RTC_CNTL_PWC_REG, RTC_CNTL_FORCE_NOISO | RTC_CNTL_FORCE_ISO | RTC_CNTL_FORCE_PU); in rtc_sleep_init()
249 REG_CLR_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU); in rtc_sleep_init()
[all …]
Drtc_init.c165 REG_CLR_BIT(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_FORCE_PU); in rtc_init()
166 … REG_CLR_BIT(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_WRAP_FORCE_NOISO | RTC_CNTL_DG_WRAP_FORCE_ISO); in rtc_init()
168 REG_CLR_BIT(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_WIFI_FORCE_NOISO | RTC_CNTL_WIFI_FORCE_ISO); in rtc_init()
169 REG_CLR_BIT(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_FORCE_PU); in rtc_init()
171 REG_CLR_BIT(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_BT_FORCE_NOISO | RTC_CNTL_BT_FORCE_ISO); in rtc_init()
172 REG_CLR_BIT(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_BT_FORCE_PU); in rtc_init()
174 … REG_CLR_BIT(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_CPU_TOP_FORCE_NOISO | RTC_CNTL_CPU_TOP_FORCE_ISO); in rtc_init()
175 REG_CLR_BIT(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_CPU_TOP_FORCE_PU); in rtc_init()
177 … REG_CLR_BIT(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PERI_FORCE_NOISO | RTC_CNTL_DG_PERI_FORCE_ISO); in rtc_init()
178 REG_CLR_BIT(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_PERI_FORCE_PU); in rtc_init()
[all …]
/hal_espressif-3.5.0/components/driver/test/dac_dma_test/
Dtest_esp32s2.c310 REG_CLR_BIT(DPORT_PERIP_RST_EN_REG, DPORT_SPI3_DMA_RST_M); in adc_dac_dma_linker_start()
311 REG_CLR_BIT(DPORT_PERIP_RST_EN_REG, DPORT_SPI3_RST_M); in adc_dac_dma_linker_start()
316 REG_CLR_BIT(SPI_DMA_IN_LINK_REG(3), SPI_INLINK_START); in adc_dac_dma_linker_start()
319 REG_CLR_BIT(SPI_DMA_CONF_REG(3), SPI_IN_RST); in adc_dac_dma_linker_start()
320 REG_CLR_BIT(SPI_DMA_IN_LINK_REG(3), SPI_INLINK_STOP); in adc_dac_dma_linker_start()
325 REG_CLR_BIT(SPI_DMA_OUT_LINK_REG(3), SPI_OUTLINK_START); in adc_dac_dma_linker_start()
328 REG_CLR_BIT(SPI_DMA_CONF_REG(3), SPI_OUT_RST); in adc_dac_dma_linker_start()
329 REG_CLR_BIT(SPI_DMA_OUT_LINK_REG(3), SPI_OUTLINK_STOP); in adc_dac_dma_linker_start()
338 REG_CLR_BIT(SPI_DMA_IN_LINK_REG(3), SPI_INLINK_START); in adc_dac_dma_linker_stop()
342 REG_CLR_BIT(SPI_DMA_OUT_LINK_REG(3), SPI_OUTLINK_START); in adc_dac_dma_linker_stop()
/hal_espressif-3.5.0/components/spi_flash/esp32/
Dspi_flash_rom_patch.c341 REG_CLR_BIT(SPI_USER_REG(0), SPI_USR_MOSI); in spi_cache_mode_switch()
347 REG_CLR_BIT(SPI_USER_REG(0), SPI_USR_MOSI); in spi_cache_mode_switch()
365 REG_CLR_BIT(SPI_USER_REG(0), SPI_USR_MOSI); in spi_cache_mode_switch()
367 REG_CLR_BIT(SPI_USER_REG(0), SPI_USR_DUMMY); in spi_cache_mode_switch()
445 REG_CLR_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_USR_DUMMY); in esp_rom_spiflash_erase_block()
465 REG_CLR_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_USR_DUMMY); in esp_rom_spiflash_erase_sector()
490 REG_CLR_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_USR_DUMMY); in esp_rom_spiflash_write()
561 REG_CLR_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_USR_MOSI); in esp_rom_spiflash_read()
568 REG_CLR_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_USR_MOSI); in esp_rom_spiflash_read()
572 REG_CLR_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_USR_DUMMY); in esp_rom_spiflash_read()
[all …]
/hal_espressif-3.5.0/components/esp_hw_support/port/esp32s2/
Dregi2c_ctrl.c89 REG_CLR_BIT(I2C_RTC_CONFIG1, I2C_RTC_APLL_MASK); in i2c_rtc_enable_block()
92 REG_CLR_BIT(I2C_RTC_CONFIG1, I2C_RTC_BBPLL_MASK); in i2c_rtc_enable_block()
95 REG_CLR_BIT(I2C_RTC_CONFIG1, I2C_RTC_SAR_MASK); in i2c_rtc_enable_block()
98 REG_CLR_BIT(I2C_RTC_CONFIG1, I2C_RTC_BOD_MASK); in i2c_rtc_enable_block()
Dspiram.c108 REG_CLR_BIT(EXTMEM_PRO_DCACHE_CTRL1_REG, EXTMEM_PRO_DCACHE_MASK_DPORT); in esp_spiram_init_cache()
117 REG_CLR_BIT(EXTMEM_PRO_DCACHE_CTRL1_REG, EXTMEM_PRO_DCACHE_MASK_DRAM0); in esp_spiram_init_cache()
121 …REG_CLR_BIT(EXTMEM_PRO_DCACHE_CTRL1_REG, EXTMEM_PRO_DCACHE_MASK_DRAM1 | EXTMEM_PRO_DCACHE_MASK_DRA… in esp_spiram_init_cache()
125 …REG_CLR_BIT(EXTMEM_PRO_DCACHE_CTRL1_REG, EXTMEM_PRO_DCACHE_MASK_DRAM1 | EXTMEM_PRO_DCACHE_MASK_DRA… in esp_spiram_init_cache()
129 …REG_CLR_BIT(EXTMEM_PRO_DCACHE_CTRL1_REG, EXTMEM_PRO_DCACHE_MASK_DRAM1 | EXTMEM_PRO_DCACHE_MASK_DRA… in esp_spiram_init_cache()
Drtc_sleep.c116 REG_CLR_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PD); in rtc_sleep_init()
119 REG_CLR_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU); in rtc_sleep_init()
123 REG_CLR_BIT(RTC_CNTL_SDIO_CONF_REG, RTC_CNTL_SDIO_FORCE); in rtc_sleep_init()
Drtc_wdt.c50 REG_CLR_BIT(RTC_CNTL_WDTCONFIG0_REG, RTC_CNTL_WDT_FLASHBOOT_MOD_EN); in rtc_wdt_disable()
51 REG_CLR_BIT(RTC_CNTL_WDTCONFIG0_REG, RTC_CNTL_WDT_EN); in rtc_wdt_disable()
/hal_espressif-3.5.0/components/hal/esp32s3/include/hal/
Drtc_cntl_ll.h97 REG_CLR_BIT(APB_CTRL_RETENTION_CTRL2_REG, APB_CTRL_RET_ICACHE_ENABLE); in rtc_cntl_ll_disable_icache_tagmem_retention()
102 REG_CLR_BIT(APB_CTRL_RETENTION_CTRL3_REG, APB_CTRL_RET_DCACHE_ENABLE); in rtc_cntl_ll_disable_dcache_tagmem_retention()
133 REG_CLR_BIT(RTC_CNTL_RETENTION_CTRL_REG, RTC_CNTL_RETENTION_EN); in rtc_cntl_ll_disable_cpu_retention()
/hal_espressif-3.5.0/zephyr/esp32s3/src/boot/
Dapp_cpu_start.c33 REG_CLR_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_RUNSTALL); in appcpu_start()
35 REG_CLR_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_RESETTING); in appcpu_start()
Dbootloader_init.c60 REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, EXTMEM_ICACHE_SHUT_CORE0_BUS); in bootloader_reset_mmu()
61 REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, EXTMEM_ICACHE_SHUT_CORE1_BUS); in bootloader_reset_mmu()
155 REG_CLR_BIT(SYSTEM_CPU_PERI_RST_EN_REG, SYSTEM_RST_EN_ASSIST_DEBUG); in wdt_reset_cpu0_info_enable()
/hal_espressif-3.5.0/components/esp_eth/src/
Dopeneth.h181 REG_CLR_BIT(OPENETH_INT_MASK_REG, OPENETH_INT_RXB); in openeth_disable()
182 REG_CLR_BIT(OPENETH_MODER_REG, OPENETH_TXEN | OPENETH_RXEN | OPENETH_PRO); in openeth_disable()
188 REG_CLR_BIT(OPENETH_MODER_REG, OPENETH_RST); in openeth_reset()
/hal_espressif-3.5.0/components/hal/esp32c3/include/hal/
Drtc_cntl_ll.h42 REG_CLR_BIT(RTC_CNTL_GPIO_WAKEUP_REG, RTC_CNTL_GPIO_WAKEUP_STATUS_CLR); in rtc_cntl_ll_gpio_set_wakeup_pins()
68 REG_CLR_BIT(RTC_CNTL_RETENTION_CTRL_REG, RTC_CNTL_RETENTION_EN); in rtc_cntl_ll_disable_cpu_retention()
Dmemprot_ll.h250 …REG_CLR_BIT(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_E… in memprot_ll_iram0_set_monitor_en()
271 …REG_CLR_BIT(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_C… in memprot_ll_iram0_reset_monitor_intrclr()
535 … REG_CLR_BIT(SENSITIVE_CORE_0_PIF_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN); in memprot_ll_rtcfast_set_monitor_en()
556 … REG_CLR_BIT(SENSITIVE_CORE_0_PIF_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR); in memprot_ll_rtcfast_reset_monitor_intrclr()
770 …REG_CLR_BIT(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_E… in memprot_ll_dram0_set_monitor_en()
786 …REG_CLR_BIT(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_C… in memprot_ll_dram0_reset_monitor_intrclr()
/hal_espressif-3.5.0/components/esp_hw_support/port/esp32/
Drtc_sleep.c186 REG_CLR_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU); in rtc_sleep_init()
190 REG_CLR_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PD); in rtc_sleep_init()
193 REG_CLR_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU); in rtc_sleep_init()
197 REG_CLR_BIT(RTC_CNTL_SDIO_CONF_REG, RTC_CNTL_SDIO_FORCE); in rtc_sleep_init()
Drtc_wdt.c49 REG_CLR_BIT(RTC_CNTL_WDTCONFIG0_REG, RTC_CNTL_WDT_FLASHBOOT_MOD_EN); in rtc_wdt_disable()
50 REG_CLR_BIT(RTC_CNTL_WDTCONFIG0_REG, RTC_CNTL_WDT_EN); in rtc_wdt_disable()
/hal_espressif-3.5.0/components/hal/esp32s2/include/hal/
Dspi_flash_encrypted_ll.h58 REG_CLR_BIT(DPORT_CPU_PERIP_RST_EN1_REG, DPORT_CRYPTO_AES_RST | DPORT_CRYPTO_DS_RST); in spi_flash_encrypt_ll_aes_accelerator_enable()
66 REG_CLR_BIT(DPORT_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG, in spi_flash_encrypt_ll_disable()
/hal_espressif-3.5.0/components/bootloader_support/src/
Dbootloader_utility.c781 REG_CLR_BIT(EXTMEM_PRO_ICACHE_CTRL1_REG, EXTMEM_PRO_ICACHE_MASK_IRAM1);
804 …REG_CLR_BIT( EXTMEM_PRO_ICACHE_CTRL1_REG, (EXTMEM_PRO_ICACHE_MASK_IRAM0) | (EXTMEM_PRO_ICACHE_MASK…
806 REG_CLR_BIT(EXTMEM_DCACHE_CTRL1_REG, EXTMEM_DCACHE_SHUT_CORE0_BUS);
808 REG_CLR_BIT(EXTMEM_DCACHE_CTRL1_REG, EXTMEM_DCACHE_SHUT_CORE1_BUS);
811 REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, EXTMEM_ICACHE_SHUT_IBUS);
812 REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, EXTMEM_ICACHE_SHUT_DBUS);
814 REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, EXTMEM_ICACHE_SHUT_IBUS);
815 REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, EXTMEM_ICACHE_SHUT_DBUS);
/hal_espressif-3.5.0/components/esp_system/port/
Dcpu_start.c243 REG_CLR_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_RUNSTALL); in start_other_core()
245 REG_CLR_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_RESETTING); in start_other_core()
432 REG_CLR_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_CLKGATE_EN);
437 REG_CLR_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_RESETTING);
/hal_espressif-3.5.0/components/hal/esp32h2/include/hal/
Dmemprot_ll.h263 …REG_CLR_BIT( SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_… in memprot_ll_iram0_set_monitor_en()
279 …REG_CLR_BIT( SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_… in memprot_ll_iram0_reset_clear_monitor_intr()
504 …REG_CLR_BIT( SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_… in memprot_ll_dram0_set_monitor_en()
520 …REG_CLR_BIT( SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_… in memprot_ll_dram0_reset_clear_monitor_intr()

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