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Searched refs:READ_PERI_REG (Results 1 – 25 of 44) sorted by relevance

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/hal_espressif-3.5.0/components/esp_hw_support/port/esp32c3/
Drtc_time.c155 uint64_t t = READ_PERI_REG(RTC_CNTL_TIME0_REG); in rtc_time_get()
156 t |= ((uint64_t) READ_PERI_REG(RTC_CNTL_TIME1_REG)) << 32; in rtc_time_get()
162 uint64_t t_wake = READ_PERI_REG(RTC_CNTL_TIME_LOW0_REG); in rtc_light_slp_time_get()
163 t_wake |= ((uint64_t) READ_PERI_REG(RTC_CNTL_TIME_HIGH0_REG)) << 32; in rtc_light_slp_time_get()
164 uint64_t t_slp = READ_PERI_REG(RTC_CNTL_TIME_LOW1_REG); in rtc_light_slp_time_get()
165 t_slp |= ((uint64_t) READ_PERI_REG(RTC_CNTL_TIME_HIGH1_REG)) << 32; in rtc_light_slp_time_get()
171 uint64_t t_slp = READ_PERI_REG(RTC_CNTL_TIME_LOW1_REG); in rtc_deep_slp_time_get()
172 t_slp |= ((uint64_t) READ_PERI_REG(RTC_CNTL_TIME_HIGH1_REG)) << 32; in rtc_deep_slp_time_get()
Drtc_clk.c76 uint32_t xtal_conf = READ_PERI_REG(RTC_CNTL_EXT_XTL_CONF_REG); in rtc_clk_32k_enabled()
456 uint32_t xtal_freq_reg = READ_PERI_REG(RTC_XTAL_FREQ_REG); in rtc_clk_xtal_freq_get()
476 uint32_t freq_hz = reg_val_to_clk_val(READ_PERI_REG(RTC_APB_FREQ_REG)) << 12; in rtc_clk_apb_freq_get()
/hal_espressif-3.5.0/components/esp_hw_support/port/esp32h2/
Drtc_time.c147 uint64_t t = READ_PERI_REG(RTC_CNTL_TIME0_REG); in rtc_time_get()
148 t |= ((uint64_t) READ_PERI_REG(RTC_CNTL_TIME1_REG)) << 32; in rtc_time_get()
154 uint64_t t_wake = READ_PERI_REG(RTC_CNTL_TIME_LOW0_REG); in rtc_light_slp_time_get()
155 t_wake |= ((uint64_t) READ_PERI_REG(RTC_CNTL_TIME_HIGH0_REG)) << 32; in rtc_light_slp_time_get()
156 uint64_t t_slp = READ_PERI_REG(RTC_CNTL_TIME_LOW1_REG); in rtc_light_slp_time_get()
157 t_slp |= ((uint64_t) READ_PERI_REG(RTC_CNTL_TIME_HIGH1_REG)) << 32; in rtc_light_slp_time_get()
163 uint64_t t_slp = READ_PERI_REG(RTC_CNTL_TIME_LOW1_REG); in rtc_deep_slp_time_get()
164 t_slp |= ((uint64_t) READ_PERI_REG(RTC_CNTL_TIME_HIGH1_REG)) << 32; in rtc_deep_slp_time_get()
/hal_espressif-3.5.0/components/esp_hw_support/port/esp32s3/
Drtc_time.c161 uint64_t t = READ_PERI_REG(RTC_CNTL_TIME0_REG); in rtc_time_get()
162 t |= ((uint64_t) READ_PERI_REG(RTC_CNTL_TIME1_REG)) << 32; in rtc_time_get()
168 uint64_t t_wake = READ_PERI_REG(RTC_CNTL_TIME_LOW0_REG); in rtc_light_slp_time_get()
169 t_wake |= ((uint64_t) READ_PERI_REG(RTC_CNTL_TIME_HIGH0_REG)) << 32; in rtc_light_slp_time_get()
170 uint64_t t_slp = READ_PERI_REG(RTC_CNTL_TIME_LOW1_REG); in rtc_light_slp_time_get()
171 t_slp |= ((uint64_t) READ_PERI_REG(RTC_CNTL_TIME_HIGH1_REG)) << 32; in rtc_light_slp_time_get()
177 uint64_t t_slp = READ_PERI_REG(RTC_CNTL_TIME_LOW1_REG); in rtc_deep_slp_time_get()
178 t_slp |= ((uint64_t) READ_PERI_REG(RTC_CNTL_TIME_HIGH1_REG)) << 32; in rtc_deep_slp_time_get()
Dspiram_psram.c175 uint32_t backup_usr = READ_PERI_REG(SPI_MEM_USER_REG(spi_num)); in psram_exec_cmd()
176 uint32_t backup_usr1 = READ_PERI_REG(SPI_MEM_USER1_REG(spi_num)); in psram_exec_cmd()
177 uint32_t backup_usr2 = READ_PERI_REG(SPI_MEM_USER2_REG(spi_num)); in psram_exec_cmd()
178 uint32_t backup_ctrl = READ_PERI_REG(SPI_MEM_CTRL_REG(spi_num)); in psram_exec_cmd()
/hal_espressif-3.5.0/components/ulp/ulp_riscv/include/ulp_riscv/
Dulp_riscv_register_ops.h104 #define READ_PERI_REG(addr) ({ … macro
115 …WRITE_PERI_REG((reg), (READ_PERI_REG(reg)&(~(mask)))); …
120 …WRITE_PERI_REG((reg), (READ_PERI_REG(reg)|(mask))); …
125 …(READ_PERI_REG(reg) & (mask)); …
133 #define GET_PERI_REG_BITS(reg, bit_map, shift) ((READ_PERI_REG(reg))&((bit_map)<<(shift)))>>shift
137 …(WRITE_PERI_REG((reg),(READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & bit_map)<<(shift)) …
142 …((READ_PERI_REG(reg)>>(shift))&(mask)); …
/hal_espressif-3.5.0/components/esp_hw_support/port/esp32s2/
Drtc_time.c228 uint64_t t = READ_PERI_REG(RTC_CNTL_TIME0_REG); in rtc_time_get()
229 t |= ((uint64_t) READ_PERI_REG(RTC_CNTL_TIME1_REG)) << 32; in rtc_time_get()
235 uint64_t t_wake = READ_PERI_REG(RTC_CNTL_TIME_LOW0_REG); in rtc_light_slp_time_get()
236 t_wake |= ((uint64_t) READ_PERI_REG(RTC_CNTL_TIME_HIGH0_REG)) << 32; in rtc_light_slp_time_get()
237 uint64_t t_slp = READ_PERI_REG(RTC_CNTL_TIME_LOW1_REG); in rtc_light_slp_time_get()
238 t_slp |= ((uint64_t) READ_PERI_REG(RTC_CNTL_TIME_HIGH1_REG)) << 32; in rtc_light_slp_time_get()
244 uint64_t t_slp = READ_PERI_REG(RTC_CNTL_TIME_LOW1_REG); in rtc_deep_slp_time_get()
245 t_slp |= ((uint64_t) READ_PERI_REG(RTC_CNTL_TIME_HIGH1_REG)) << 32; in rtc_deep_slp_time_get()
Drtc_wdt.c14 return READ_PERI_REG(RTC_CNTL_WDTWPROTECT_REG) != RTC_CNTL_WDT_WKEY_VALUE; in rtc_wdt_get_protect_status()
103 time_tick = READ_PERI_REG(get_addr_reg(stage)); in rtc_wdt_get_timeout()
Dspiram_psram.c214 uint32_t backup_usr = READ_PERI_REG(SPI_MEM_USER_REG(spi_num)); in psram_exec_cmd()
215 uint32_t backup_usr1 = READ_PERI_REG(SPI_MEM_USER1_REG(spi_num)); in psram_exec_cmd()
216 uint32_t backup_usr2 = READ_PERI_REG(SPI_MEM_USER2_REG(spi_num)); in psram_exec_cmd()
217 uint32_t backup_ctrl = READ_PERI_REG(SPI_MEM_CTRL_REG(spi_num)); in psram_exec_cmd()
/hal_espressif-3.5.0/components/soc/esp32s2/include/soc/
Dsoc.h197 #define READ_PERI_REG(addr) ({ … macro
198 …ASSERT_IF_DPORT_REG((addr), READ_PERI_REG); …
211 …WRITE_PERI_REG((reg), (READ_PERI_REG(reg)&(~(mask)))); …
217 …WRITE_PERI_REG((reg), (READ_PERI_REG(reg)|(mask))); …
223 …(READ_PERI_REG(reg) & (mask)); …
229 …((READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1)); …
235 …(WRITE_PERI_REG((reg),(READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & bit_map)<<(shift)) …
241 …((READ_PERI_REG(reg)>>(shift))&(mask)); …
/hal_espressif-3.5.0/components/soc/esp32c3/include/soc/
Dsoc.h156 #define READ_PERI_REG(addr) ({ … macro
167 …WRITE_PERI_REG((reg), (READ_PERI_REG(reg)&(~(mask)))); …
172 …WRITE_PERI_REG((reg), (READ_PERI_REG(reg)|(mask))); …
177 …(READ_PERI_REG(reg) & (mask)); …
182 …((READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1)); …
187 …(WRITE_PERI_REG((reg),(READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & bit_map)<<(shift)) …
192 …((READ_PERI_REG(reg)>>(shift))&(mask)); …
/hal_espressif-3.5.0/components/soc/esp32h2/include/soc/
Dsoc.h179 #define READ_PERI_REG(addr) ({ … macro
190 …WRITE_PERI_REG((reg), (READ_PERI_REG(reg)&(~(mask)))); …
195 …WRITE_PERI_REG((reg), (READ_PERI_REG(reg)|(mask))); …
200 …(READ_PERI_REG(reg) & (mask)); …
205 …((READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1)); …
210 …(WRITE_PERI_REG((reg),(READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & bit_map)<<(shift)) …
215 …((READ_PERI_REG(reg)>>(shift))&(mask)); …
/hal_espressif-3.5.0/components/soc/esp32s3/include/soc/
Dsoc.h189 #define READ_PERI_REG(addr) ({ … macro
200 …WRITE_PERI_REG((reg), (READ_PERI_REG(reg)&(~(mask)))); …
205 …WRITE_PERI_REG((reg), (READ_PERI_REG(reg)|(mask))); …
210 …(READ_PERI_REG(reg) & (mask)); …
215 …((READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1)); …
220 …(WRITE_PERI_REG((reg),(READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & bit_map)<<(shift)) …
225 …((READ_PERI_REG(reg)>>(shift))&(mask)); …
/hal_espressif-3.5.0/components/esp_hw_support/port/esp32/
Drtc_wdt.c13 return READ_PERI_REG(RTC_CNTL_WDTWPROTECT_REG) != RTC_CNTL_WDT_WKEY_VALUE; in rtc_wdt_get_protect_status()
94 time_tick = READ_PERI_REG(RTC_CNTL_WDTCONFIG1_REG); in rtc_wdt_get_timeout()
96 time_tick = READ_PERI_REG(RTC_CNTL_WDTCONFIG2_REG); in rtc_wdt_get_timeout()
98 time_tick = READ_PERI_REG(RTC_CNTL_WDTCONFIG3_REG); in rtc_wdt_get_timeout()
100 time_tick = READ_PERI_REG(RTC_CNTL_WDTCONFIG4_REG); in rtc_wdt_get_timeout()
Dspiram_psram.c267 uint32_t mode_backup = (READ_PERI_REG(SPI_USER_REG(spi_num)) >> SPI_FWRITE_DUAL_S) & 0xf; in psram_cmd_recv_start()
268 …uint32_t rd_mode_backup = READ_PERI_REG(SPI_CTRL_REG(spi_num)) & (SPI_FREAD_DIO_M | SPI_FREAD_DUAL… in psram_cmd_recv_start()
278 while ( READ_PERI_REG(SPI_EXT2_REG(0)) != 0); in psram_cmd_recv_start()
283 while ((READ_PERI_REG(SPI_CMD_REG(spi_num)) & SPI_USR)); in psram_cmd_recv_start()
299 *pRxData++ = READ_PERI_REG(SPI_W0_REG(spi_num) + (idx << 2)); in psram_cmd_recv_start()
311 while (READ_PERI_REG(SPI_CMD_REG(spi_num)) & SPI_USR); in psram_cmd_config()
312 backup_usr[spi_num]=READ_PERI_REG(SPI_USER_REG(spi_num)); in psram_cmd_config()
313 backup_usr1[spi_num]=READ_PERI_REG(SPI_USER1_REG(spi_num)); in psram_cmd_config()
314 backup_usr2[spi_num]=READ_PERI_REG(SPI_USER2_REG(spi_num)); in psram_cmd_config()
379 while (READ_PERI_REG(SPI_CMD_REG(spi_num)) & SPI_USR); in psram_cmd_end()
[all …]
Drtc_clk_init.c78 if (clk_val_is_valid(READ_PERI_REG(RTC_XTAL_FREQ_REG))) { in rtc_clk_init()
89 } else if (!clk_val_is_valid(READ_PERI_REG(RTC_XTAL_FREQ_REG))) { in rtc_clk_init()
Drtc_time.c149 uint64_t t = READ_PERI_REG(RTC_CNTL_TIME0_REG); in rtc_time_get()
150 t |= ((uint64_t) READ_PERI_REG(RTC_CNTL_TIME1_REG)) << 32; in rtc_time_get()
/hal_espressif-3.5.0/components/soc/esp32/include/soc/
Dsoc.h168 #define READ_PERI_REG(addr) ({ … macro
169 …ASSERT_IF_DPORT_REG((addr), READ_PERI_REG); …
182 …WRITE_PERI_REG((reg), (READ_PERI_REG(reg)&(~(mask)))); …
188 …WRITE_PERI_REG((reg), (READ_PERI_REG(reg)|(mask))); …
194 …(READ_PERI_REG(reg) & (mask)); …
200 …((READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1)); …
206 …(WRITE_PERI_REG((reg),(READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & bit_map)<<(shift)) …
212 …((READ_PERI_REG(reg)>>(shift))&(mask)); …
/hal_espressif-3.5.0/components/spi_flash/esp32/
Dspi_flash_rom_patch.c128 while (READ_PERI_REG(PERIPHS_SPI_FLASH_CMD) != 0); in esp_rom_spiflash_erase_chip_internal()
149 while (READ_PERI_REG(PERIPHS_SPI_FLASH_CMD) != 0); in esp_rom_spiflash_erase_sector_internal()
164 while (READ_PERI_REG(PERIPHS_SPI_FLASH_CMD) != 0); in esp_rom_spiflash_erase_block_internal()
218 while ( READ_PERI_REG(PERIPHS_SPI_FLASH_CMD ) != 0 ); in esp_rom_spiflash_program_page_internal()
234 while (READ_PERI_REG(PERIPHS_SPI_FLASH_CMD) != 0); in esp_rom_spiflash_read_status()
236 status_value = READ_PERI_REG(PERIPHS_SPI_FLASH_STATUS) & (spi->status_mask); in esp_rom_spiflash_read_status()
264 while (READ_PERI_REG(PERIPHS_SPI_FLASH_CMD) != 0); in esp_rom_spiflash_write_status()
298 *addr_dest++ = READ_PERI_REG(PERIPHS_SPI_FLASH_C0 + i * 4); in esp_rom_spiflash_read_data()
311 *addr_dest++ = READ_PERI_REG(PERIPHS_SPI_FLASH_C0 + i * 4); in esp_rom_spiflash_read_data()
328 while (READ_PERI_REG(PERIPHS_SPI_FLASH_CMD) != 0); in esp_rom_spiflash_enable_write()
[all …]
/hal_espressif-3.5.0/components/esp_hw_support/test/
Dtest_unal_dma.c68 …WRITE_PERI_REG(GPIO_FUNC11_OUT_SEL_CFG_REG, READ_PERI_REG(GPIO_FUNC11_OUT_SEL_CFG_REG) | GPIO_FUNC… in dmaMemcpy()
151 if (!(READ_PERI_REG(I2S_FIFO_CONF_REG(0))&I2S_DSCR_EN)) { in dmaMemcpy()
156 while (!(READ_PERI_REG(I2S_INT_RAW_REG(0))&I2S_TX_REMPTY_INT_RAW)) ; in dmaMemcpy()
160 while (!(READ_PERI_REG(I2S_STATE_REG(0))&I2S_TX_IDLE)); in dmaMemcpy()
170 while ((READ_PERI_REG(I2S_STATE_REG(0))&I2S_TX_FIFO_RESET_BACK)); in dmaMemcpy()
Dtest_ahb_arb.c73 …WRITE_PERI_REG(GPIO_FUNC11_OUT_SEL_CFG_REG, READ_PERI_REG(GPIO_FUNC11_OUT_SEL_CFG_REG) | GPIO_FUNC… in lcdIfaceInit()
112 if (!(READ_PERI_REG(I2S_FIFO_CONF_REG(0))&I2S_DSCR_EN)) { in finishDma()
117 while (!(READ_PERI_REG(I2S_INT_RAW_REG(0))&I2S_TX_REMPTY_INT_RAW)) ; in finishDma()
121 while (!(READ_PERI_REG(I2S_STATE_REG(0))&I2S_TX_IDLE)); in finishDma()
131 while ((READ_PERI_REG(I2S_STATE_REG(0))&I2S_TX_FIFO_RESET_BACK)); in finishDma()
/hal_espressif-3.5.0/components/esp_system/port/soc/esp32c3/
Dclk.c219 common_perip_clk = ~READ_PERI_REG(SYSTEM_PERIP_CLK_EN0_REG); in esp_perip_clk_init()
220 hwcrypto_perip_clk = ~READ_PERI_REG(SYSTEM_PERIP_CLK_EN1_REG); in esp_perip_clk_init()
221 wifi_bt_sdio_clk = ~READ_PERI_REG(SYSTEM_WIFI_CLK_EN_REG); in esp_perip_clk_init()
/hal_espressif-3.5.0/components/esp_system/port/soc/esp32s3/
Dclk.c236 common_perip_clk = ~READ_PERI_REG(SYSTEM_PERIP_CLK_EN0_REG); in esp_perip_clk_init()
237 hwcrypto_perip_clk = ~READ_PERI_REG(SYSTEM_PERIP_CLK_EN1_REG); in esp_perip_clk_init()
238 wifi_bt_sdio_clk = ~READ_PERI_REG(SYSTEM_WIFI_CLK_EN_REG); in esp_perip_clk_init()
/hal_espressif-3.5.0/components/espcoredump/src/
Dcore_dump_uart.c126 uint32_t reg = (READ_PERI_REG(UART_STATUS_REG(0)) >> UART_RXFIFO_CNT_S) & UART_RXFIFO_CNT; in esp_core_dump_uart_get_char()
128 i = READ_PERI_REG(UART_FIFO_REG(0)); in esp_core_dump_uart_get_char()
/hal_espressif-3.5.0/components/esp_system/port/soc/esp32h2/
Dclk.c211 common_perip_clk = ~READ_PERI_REG(SYSTEM_PERIP_CLK_EN0_REG); in esp_perip_clk_init()
212 hwcrypto_perip_clk = ~READ_PERI_REG(SYSTEM_PERIP_CLK_EN1_REG); in esp_perip_clk_init()

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