1 // Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 #ifndef _SOC_GPIO_REG_H_ 15 #define _SOC_GPIO_REG_H_ 16 17 #include "soc.h" 18 #define GPIO_BT_SELECT_REG (DR_REG_GPIO_BASE + 0x0000) 19 /* GPIO_BT_SEL : R/W ;bitpos:[31:0] ;default: x ; */ 20 /*description: NA*/ 21 #define GPIO_BT_SEL 0xFFFFFFFF 22 #define GPIO_BT_SEL_M ((GPIO_BT_SEL_V)<<(GPIO_BT_SEL_S)) 23 #define GPIO_BT_SEL_V 0xFFFFFFFF 24 #define GPIO_BT_SEL_S 0 25 26 #define GPIO_OUT_REG (DR_REG_GPIO_BASE + 0x0004) 27 /* GPIO_OUT_DATA : R/W ;bitpos:[31:0] ;default: x ; */ 28 /*description: GPIO0~31 output value*/ 29 #define GPIO_OUT_DATA 0xFFFFFFFF 30 #define GPIO_OUT_DATA_M ((GPIO_OUT_DATA_V)<<(GPIO_OUT_DATA_S)) 31 #define GPIO_OUT_DATA_V 0xFFFFFFFF 32 #define GPIO_OUT_DATA_S 0 33 34 #define GPIO_OUT_W1TS_REG (DR_REG_GPIO_BASE + 0x0008) 35 /* GPIO_OUT_DATA_W1TS : R/W ;bitpos:[31:0] ;default: x ; */ 36 /*description: GPIO0~31 output value write 1 to set*/ 37 #define GPIO_OUT_DATA_W1TS 0xFFFFFFFF 38 #define GPIO_OUT_DATA_W1TS_M ((GPIO_OUT_DATA_W1TS_V)<<(GPIO_OUT_DATA_W1TS_S)) 39 #define GPIO_OUT_DATA_W1TS_V 0xFFFFFFFF 40 #define GPIO_OUT_DATA_W1TS_S 0 41 42 #define GPIO_OUT_W1TC_REG (DR_REG_GPIO_BASE + 0x000c) 43 /* GPIO_OUT_DATA_W1TC : R/W ;bitpos:[31:0] ;default: x ; */ 44 /*description: GPIO0~31 output value write 1 to clear*/ 45 #define GPIO_OUT_DATA_W1TC 0xFFFFFFFF 46 #define GPIO_OUT_DATA_W1TC_M ((GPIO_OUT_DATA_W1TC_V)<<(GPIO_OUT_DATA_W1TC_S)) 47 #define GPIO_OUT_DATA_W1TC_V 0xFFFFFFFF 48 #define GPIO_OUT_DATA_W1TC_S 0 49 50 #define GPIO_OUT1_REG (DR_REG_GPIO_BASE + 0x0010) 51 /* GPIO_OUT1_DATA : R/W ;bitpos:[7:0] ;default: x ; */ 52 /*description: GPIO32~39 output value*/ 53 #define GPIO_OUT1_DATA 0x000000FF 54 #define GPIO_OUT1_DATA_M ((GPIO_OUT1_DATA_V)<<(GPIO_OUT1_DATA_S)) 55 #define GPIO_OUT1_DATA_V 0xFF 56 #define GPIO_OUT1_DATA_S 0 57 58 #define GPIO_OUT1_W1TS_REG (DR_REG_GPIO_BASE + 0x0014) 59 /* GPIO_OUT1_DATA_W1TS : R/W ;bitpos:[7:0] ;default: x ; */ 60 /*description: GPIO32~39 output value write 1 to set*/ 61 #define GPIO_OUT1_DATA_W1TS 0x000000FF 62 #define GPIO_OUT1_DATA_W1TS_M ((GPIO_OUT1_DATA_W1TS_V)<<(GPIO_OUT1_DATA_W1TS_S)) 63 #define GPIO_OUT1_DATA_W1TS_V 0xFF 64 #define GPIO_OUT1_DATA_W1TS_S 0 65 66 #define GPIO_OUT1_W1TC_REG (DR_REG_GPIO_BASE + 0x0018) 67 /* GPIO_OUT1_DATA_W1TC : R/W ;bitpos:[7:0] ;default: x ; */ 68 /*description: GPIO32~39 output value write 1 to clear*/ 69 #define GPIO_OUT1_DATA_W1TC 0x000000FF 70 #define GPIO_OUT1_DATA_W1TC_M ((GPIO_OUT1_DATA_W1TC_V)<<(GPIO_OUT1_DATA_W1TC_S)) 71 #define GPIO_OUT1_DATA_W1TC_V 0xFF 72 #define GPIO_OUT1_DATA_W1TC_S 0 73 74 #define GPIO_SDIO_SELECT_REG (DR_REG_GPIO_BASE + 0x001c) 75 /* GPIO_SDIO_SEL : R/W ;bitpos:[7:0] ;default: x ; */ 76 /*description: SDIO PADS on/off control from outside*/ 77 #define GPIO_SDIO_SEL 0x000000FF 78 #define GPIO_SDIO_SEL_M ((GPIO_SDIO_SEL_V)<<(GPIO_SDIO_SEL_S)) 79 #define GPIO_SDIO_SEL_V 0xFF 80 #define GPIO_SDIO_SEL_S 0 81 82 #define GPIO_ENABLE_REG (DR_REG_GPIO_BASE + 0x0020) 83 /* GPIO_ENABLE_DATA : R/W ;bitpos:[31:0] ;default: x ; */ 84 /*description: GPIO0~31 output enable*/ 85 #define GPIO_ENABLE_DATA 0xFFFFFFFF 86 #define GPIO_ENABLE_DATA_M ((GPIO_ENABLE_DATA_V)<<(GPIO_ENABLE_DATA_S)) 87 #define GPIO_ENABLE_DATA_V 0xFFFFFFFF 88 #define GPIO_ENABLE_DATA_S 0 89 90 #define GPIO_ENABLE_W1TS_REG (DR_REG_GPIO_BASE + 0x0024) 91 /* GPIO_ENABLE_DATA_W1TS : R/W ;bitpos:[31:0] ;default: x ; */ 92 /*description: GPIO0~31 output enable write 1 to set*/ 93 #define GPIO_ENABLE_DATA_W1TS 0xFFFFFFFF 94 #define GPIO_ENABLE_DATA_W1TS_M ((GPIO_ENABLE_DATA_W1TS_V)<<(GPIO_ENABLE_DATA_W1TS_S)) 95 #define GPIO_ENABLE_DATA_W1TS_V 0xFFFFFFFF 96 #define GPIO_ENABLE_DATA_W1TS_S 0 97 98 #define GPIO_ENABLE_W1TC_REG (DR_REG_GPIO_BASE + 0x0028) 99 /* GPIO_ENABLE_DATA_W1TC : R/W ;bitpos:[31:0] ;default: x ; */ 100 /*description: GPIO0~31 output enable write 1 to clear*/ 101 #define GPIO_ENABLE_DATA_W1TC 0xFFFFFFFF 102 #define GPIO_ENABLE_DATA_W1TC_M ((GPIO_ENABLE_DATA_W1TC_V)<<(GPIO_ENABLE_DATA_W1TC_S)) 103 #define GPIO_ENABLE_DATA_W1TC_V 0xFFFFFFFF 104 #define GPIO_ENABLE_DATA_W1TC_S 0 105 106 #define GPIO_ENABLE1_REG (DR_REG_GPIO_BASE + 0x002c) 107 /* GPIO_ENABLE1_DATA : R/W ;bitpos:[7:0] ;default: x ; */ 108 /*description: GPIO32~39 output enable*/ 109 #define GPIO_ENABLE1_DATA 0x000000FF 110 #define GPIO_ENABLE1_DATA_M ((GPIO_ENABLE1_DATA_V)<<(GPIO_ENABLE1_DATA_S)) 111 #define GPIO_ENABLE1_DATA_V 0xFF 112 #define GPIO_ENABLE1_DATA_S 0 113 114 #define GPIO_ENABLE1_W1TS_REG (DR_REG_GPIO_BASE + 0x0030) 115 /* GPIO_ENABLE1_DATA_W1TS : R/W ;bitpos:[7:0] ;default: x ; */ 116 /*description: GPIO32~39 output enable write 1 to set*/ 117 #define GPIO_ENABLE1_DATA_W1TS 0x000000FF 118 #define GPIO_ENABLE1_DATA_W1TS_M ((GPIO_ENABLE1_DATA_W1TS_V)<<(GPIO_ENABLE1_DATA_W1TS_S)) 119 #define GPIO_ENABLE1_DATA_W1TS_V 0xFF 120 #define GPIO_ENABLE1_DATA_W1TS_S 0 121 122 #define GPIO_ENABLE1_W1TC_REG (DR_REG_GPIO_BASE + 0x0034) 123 /* GPIO_ENABLE1_DATA_W1TC : R/W ;bitpos:[7:0] ;default: x ; */ 124 /*description: GPIO32~39 output enable write 1 to clear*/ 125 #define GPIO_ENABLE1_DATA_W1TC 0x000000FF 126 #define GPIO_ENABLE1_DATA_W1TC_M ((GPIO_ENABLE1_DATA_W1TC_V)<<(GPIO_ENABLE1_DATA_W1TC_S)) 127 #define GPIO_ENABLE1_DATA_W1TC_V 0xFF 128 #define GPIO_ENABLE1_DATA_W1TC_S 0 129 130 #define GPIO_STRAP_REG (DR_REG_GPIO_BASE + 0x0038) 131 /* GPIO_STRAPPING : RO ;bitpos:[15:0] ;default: ; */ 132 /*description: {10'b0, MTDI, GPIO0, GPIO2, GPIO4, MTDO, GPIO5} */ 133 #define GPIO_STRAPPING 0x0000FFFF 134 #define GPIO_STRAPPING_M ((GPIO_STRAPPING_V)<<(GPIO_STRAPPING_S)) 135 #define GPIO_STRAPPING_V 0xFFFF 136 #define GPIO_STRAPPING_S 0 137 138 #define GPIO_IN_REG (DR_REG_GPIO_BASE + 0x003c) 139 /* GPIO_IN_DATA : RO ;bitpos:[31:0] ;default: ; */ 140 /*description: GPIO0~31 input value*/ 141 #define GPIO_IN_DATA 0xFFFFFFFF 142 #define GPIO_IN_DATA_M ((GPIO_IN_DATA_V)<<(GPIO_IN_DATA_S)) 143 #define GPIO_IN_DATA_V 0xFFFFFFFF 144 #define GPIO_IN_DATA_S 0 145 146 #define GPIO_IN1_REG (DR_REG_GPIO_BASE + 0x0040) 147 /* GPIO_IN1_DATA : RO ;bitpos:[7:0] ;default: ; */ 148 /*description: GPIO32~39 input value*/ 149 #define GPIO_IN1_DATA 0x000000FF 150 #define GPIO_IN1_DATA_M ((GPIO_IN1_DATA_V)<<(GPIO_IN1_DATA_S)) 151 #define GPIO_IN1_DATA_V 0xFF 152 #define GPIO_IN1_DATA_S 0 153 154 #define GPIO_STATUS_REG (DR_REG_GPIO_BASE + 0x0044) 155 /* GPIO_STATUS_INT : R/W ;bitpos:[31:0] ;default: x ; */ 156 /*description: GPIO0~31 interrupt status*/ 157 #define GPIO_STATUS_INT 0xFFFFFFFF 158 #define GPIO_STATUS_INT_M ((GPIO_STATUS_INT_V)<<(GPIO_STATUS_INT_S)) 159 #define GPIO_STATUS_INT_V 0xFFFFFFFF 160 #define GPIO_STATUS_INT_S 0 161 162 #define GPIO_STATUS_W1TS_REG (DR_REG_GPIO_BASE + 0x0048) 163 /* GPIO_STATUS_INT_W1TS : R/W ;bitpos:[31:0] ;default: x ; */ 164 /*description: GPIO0~31 interrupt status write 1 to set*/ 165 #define GPIO_STATUS_INT_W1TS 0xFFFFFFFF 166 #define GPIO_STATUS_INT_W1TS_M ((GPIO_STATUS_INT_W1TS_V)<<(GPIO_STATUS_INT_W1TS_S)) 167 #define GPIO_STATUS_INT_W1TS_V 0xFFFFFFFF 168 #define GPIO_STATUS_INT_W1TS_S 0 169 170 #define GPIO_STATUS_W1TC_REG (DR_REG_GPIO_BASE + 0x004c) 171 /* GPIO_STATUS_INT_W1TC : R/W ;bitpos:[31:0] ;default: x ; */ 172 /*description: GPIO0~31 interrupt status write 1 to clear*/ 173 #define GPIO_STATUS_INT_W1TC 0xFFFFFFFF 174 #define GPIO_STATUS_INT_W1TC_M ((GPIO_STATUS_INT_W1TC_V)<<(GPIO_STATUS_INT_W1TC_S)) 175 #define GPIO_STATUS_INT_W1TC_V 0xFFFFFFFF 176 #define GPIO_STATUS_INT_W1TC_S 0 177 178 #define GPIO_STATUS1_REG (DR_REG_GPIO_BASE + 0x0050) 179 /* GPIO_STATUS1_INT : R/W ;bitpos:[7:0] ;default: x ; */ 180 /*description: GPIO32~39 interrupt status*/ 181 #define GPIO_STATUS1_INT 0x000000FF 182 #define GPIO_STATUS1_INT_M ((GPIO_STATUS1_INT_V)<<(GPIO_STATUS1_INT_S)) 183 #define GPIO_STATUS1_INT_V 0xFF 184 #define GPIO_STATUS1_INT_S 0 185 186 #define GPIO_STATUS1_W1TS_REG (DR_REG_GPIO_BASE + 0x0054) 187 /* GPIO_STATUS1_INT_W1TS : R/W ;bitpos:[7:0] ;default: x ; */ 188 /*description: GPIO32~39 interrupt status write 1 to set*/ 189 #define GPIO_STATUS1_INT_W1TS 0x000000FF 190 #define GPIO_STATUS1_INT_W1TS_M ((GPIO_STATUS1_INT_W1TS_V)<<(GPIO_STATUS1_INT_W1TS_S)) 191 #define GPIO_STATUS1_INT_W1TS_V 0xFF 192 #define GPIO_STATUS1_INT_W1TS_S 0 193 194 #define GPIO_STATUS1_W1TC_REG (DR_REG_GPIO_BASE + 0x0058) 195 /* GPIO_STATUS1_INT_W1TC : R/W ;bitpos:[7:0] ;default: x ; */ 196 /*description: GPIO32~39 interrupt status write 1 to clear*/ 197 #define GPIO_STATUS1_INT_W1TC 0x000000FF 198 #define GPIO_STATUS1_INT_W1TC_M ((GPIO_STATUS1_INT_W1TC_V)<<(GPIO_STATUS1_INT_W1TC_S)) 199 #define GPIO_STATUS1_INT_W1TC_V 0xFF 200 #define GPIO_STATUS1_INT_W1TC_S 0 201 202 #define GPIO_ACPU_INT_REG (DR_REG_GPIO_BASE + 0x0060) 203 /* GPIO_APPCPU_INT : RO ;bitpos:[31:0] ;default: x ; */ 204 /*description: GPIO0~31 APP CPU interrupt status*/ 205 #define GPIO_APPCPU_INT 0xFFFFFFFF 206 #define GPIO_APPCPU_INT_M ((GPIO_APPCPU_INT_V)<<(GPIO_APPCPU_INT_S)) 207 #define GPIO_APPCPU_INT_V 0xFFFFFFFF 208 #define GPIO_APPCPU_INT_S 0 209 210 #define GPIO_ACPU_NMI_INT_REG (DR_REG_GPIO_BASE + 0x0064) 211 /* GPIO_APPCPU_NMI_INT : RO ;bitpos:[31:0] ;default: x ; */ 212 /*description: GPIO0~31 APP CPU non-maskable interrupt status*/ 213 #define GPIO_APPCPU_NMI_INT 0xFFFFFFFF 214 #define GPIO_APPCPU_NMI_INT_M ((GPIO_APPCPU_NMI_INT_V)<<(GPIO_APPCPU_NMI_INT_S)) 215 #define GPIO_APPCPU_NMI_INT_V 0xFFFFFFFF 216 #define GPIO_APPCPU_NMI_INT_S 0 217 218 #define GPIO_PCPU_INT_REG (DR_REG_GPIO_BASE + 0x0068) 219 /* GPIO_PROCPU_INT : RO ;bitpos:[31:0] ;default: x ; */ 220 /*description: GPIO0~31 PRO CPU interrupt status*/ 221 #define GPIO_PROCPU_INT 0xFFFFFFFF 222 #define GPIO_PROCPU_INT_M ((GPIO_PROCPU_INT_V)<<(GPIO_PROCPU_INT_S)) 223 #define GPIO_PROCPU_INT_V 0xFFFFFFFF 224 #define GPIO_PROCPU_INT_S 0 225 226 #define GPIO_PCPU_NMI_INT_REG (DR_REG_GPIO_BASE + 0x006c) 227 /* GPIO_PROCPU_NMI_INT : RO ;bitpos:[31:0] ;default: x ; */ 228 /*description: GPIO0~31 PRO CPU non-maskable interrupt status*/ 229 #define GPIO_PROCPU_NMI_INT 0xFFFFFFFF 230 #define GPIO_PROCPU_NMI_INT_M ((GPIO_PROCPU_NMI_INT_V)<<(GPIO_PROCPU_NMI_INT_S)) 231 #define GPIO_PROCPU_NMI_INT_V 0xFFFFFFFF 232 #define GPIO_PROCPU_NMI_INT_S 0 233 234 #define GPIO_CPUSDIO_INT_REG (DR_REG_GPIO_BASE + 0x0070) 235 /* GPIO_SDIO_INT : RO ;bitpos:[31:0] ;default: x ; */ 236 /*description: SDIO's extent GPIO0~31 interrupt*/ 237 #define GPIO_SDIO_INT 0xFFFFFFFF 238 #define GPIO_SDIO_INT_M ((GPIO_SDIO_INT_V)<<(GPIO_SDIO_INT_S)) 239 #define GPIO_SDIO_INT_V 0xFFFFFFFF 240 #define GPIO_SDIO_INT_S 0 241 242 #define GPIO_ACPU_INT1_REG (DR_REG_GPIO_BASE + 0x0074) 243 /* GPIO_APPCPU_INT_H : RO ;bitpos:[7:0] ;default: x ; */ 244 /*description: GPIO32~39 APP CPU interrupt status*/ 245 #define GPIO_APPCPU_INT_H 0x000000FF 246 #define GPIO_APPCPU_INT_H_M ((GPIO_APPCPU_INT_H_V)<<(GPIO_APPCPU_INT_H_S)) 247 #define GPIO_APPCPU_INT_H_V 0xFF 248 #define GPIO_APPCPU_INT_H_S 0 249 250 #define GPIO_ACPU_NMI_INT1_REG (DR_REG_GPIO_BASE + 0x0078) 251 /* GPIO_APPCPU_NMI_INT_H : RO ;bitpos:[7:0] ;default: x ; */ 252 /*description: GPIO32~39 APP CPU non-maskable interrupt status*/ 253 #define GPIO_APPCPU_NMI_INT_H 0x000000FF 254 #define GPIO_APPCPU_NMI_INT_H_M ((GPIO_APPCPU_NMI_INT_H_V)<<(GPIO_APPCPU_NMI_INT_H_S)) 255 #define GPIO_APPCPU_NMI_INT_H_V 0xFF 256 #define GPIO_APPCPU_NMI_INT_H_S 0 257 258 #define GPIO_PCPU_INT1_REG (DR_REG_GPIO_BASE + 0x007c) 259 /* GPIO_PROCPU_INT_H : RO ;bitpos:[7:0] ;default: x ; */ 260 /*description: GPIO32~39 PRO CPU interrupt status*/ 261 #define GPIO_PROCPU_INT_H 0x000000FF 262 #define GPIO_PROCPU_INT_H_M ((GPIO_PROCPU_INT_H_V)<<(GPIO_PROCPU_INT_H_S)) 263 #define GPIO_PROCPU_INT_H_V 0xFF 264 #define GPIO_PROCPU_INT_H_S 0 265 266 #define GPIO_PCPU_NMI_INT1_REG (DR_REG_GPIO_BASE + 0x0080) 267 /* GPIO_PROCPU_NMI_INT_H : RO ;bitpos:[7:0] ;default: x ; */ 268 /*description: GPIO32~39 PRO CPU non-maskable interrupt status*/ 269 #define GPIO_PROCPU_NMI_INT_H 0x000000FF 270 #define GPIO_PROCPU_NMI_INT_H_M ((GPIO_PROCPU_NMI_INT_H_V)<<(GPIO_PROCPU_NMI_INT_H_S)) 271 #define GPIO_PROCPU_NMI_INT_H_V 0xFF 272 #define GPIO_PROCPU_NMI_INT_H_S 0 273 274 #define GPIO_CPUSDIO_INT1_REG (DR_REG_GPIO_BASE + 0x0084) 275 /* GPIO_SDIO_INT_H : RO ;bitpos:[7:0] ;default: x ; */ 276 /*description: SDIO's extent GPIO32~39 interrupt*/ 277 #define GPIO_SDIO_INT_H 0x000000FF 278 #define GPIO_SDIO_INT_H_M ((GPIO_SDIO_INT_H_V)<<(GPIO_SDIO_INT_H_S)) 279 #define GPIO_SDIO_INT_H_V 0xFF 280 #define GPIO_SDIO_INT_H_S 0 281 282 #define GPIO_REG(io_num) (GPIO_PIN0_REG + (io_num)*0x4) 283 #define GPIO_PIN_INT_ENA 0x0000001F 284 #define GPIO_PIN_INT_ENA_M ((GPIO_PIN_INT_ENA_V)<<(GPIO_PIN_INT_ENA_S)) 285 #define GPIO_PIN_INT_ENA_V 0x0000001F 286 #define GPIO_PIN_INT_ENA_S 13 287 #define GPIO_PIN_CONFIG 0x00000003 288 #define GPIO_PIN_CONFIG_M ((GPIO_PIN_CONFIG_V)<<(GPIO_PIN_CONFIG_S)) 289 #define GPIO_PIN_CONFIG_V 0x00000003 290 #define GPIO_PIN_CONFIG_S 11 291 #define GPIO_PIN_WAKEUP_ENABLE (BIT(10)) 292 #define GPIO_PIN_WAKEUP_ENABLE_M (BIT(10)) 293 #define GPIO_PIN_WAKEUP_ENABLE_V 0x1 294 #define GPIO_PIN_WAKEUP_ENABLE_S 10 295 #define GPIO_PIN_INT_TYPE 0x00000007 296 #define GPIO_PIN_INT_TYPE_M ((GPIO_PIN_INT_TYPE_V)<<(GPIO_PIN_INT_TYPE_S)) 297 #define GPIO_PIN_INT_TYPE_V 0x00000007 298 #define GPIO_PIN_INT_TYPE_S 7 299 #define GPIO_PIN_PAD_DRIVER (BIT(2)) 300 #define GPIO_PIN_PAD_DRIVER_M (BIT(2)) 301 #define GPIO_PIN_PAD_DRIVER_V 0x1 302 #define GPIO_PIN_PAD_DRIVER_S 2 303 304 #define GPIO_PIN0_REG (DR_REG_GPIO_BASE + 0x0088) 305 /* GPIO_PIN0_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ 306 /*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt 307 enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ 308 #define GPIO_PIN0_INT_ENA 0x0000001F 309 #define GPIO_PIN0_INT_ENA_M ((GPIO_PIN0_INT_ENA_V)<<(GPIO_PIN0_INT_ENA_S)) 310 #define GPIO_PIN0_INT_ENA_V 0x1F 311 #define GPIO_PIN0_INT_ENA_S 13 312 /* GPIO_PIN0_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ 313 /*description: NA*/ 314 #define GPIO_PIN0_CONFIG 0x00000003 315 #define GPIO_PIN0_CONFIG_M ((GPIO_PIN0_CONFIG_V)<<(GPIO_PIN0_CONFIG_S)) 316 #define GPIO_PIN0_CONFIG_V 0x3 317 #define GPIO_PIN0_CONFIG_S 11 318 /* GPIO_PIN0_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ 319 /*description: GPIO wake up enable only available in light sleep*/ 320 #define GPIO_PIN0_WAKEUP_ENABLE (BIT(10)) 321 #define GPIO_PIN0_WAKEUP_ENABLE_M (BIT(10)) 322 #define GPIO_PIN0_WAKEUP_ENABLE_V 0x1 323 #define GPIO_PIN0_WAKEUP_ENABLE_S 10 324 /* GPIO_PIN0_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ 325 /*description: if set to 0: GPIO interrupt disable if set to 1: rising edge 326 trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ 327 #define GPIO_PIN0_INT_TYPE 0x00000007 328 #define GPIO_PIN0_INT_TYPE_M ((GPIO_PIN0_INT_TYPE_V)<<(GPIO_PIN0_INT_TYPE_S)) 329 #define GPIO_PIN0_INT_TYPE_V 0x7 330 #define GPIO_PIN0_INT_TYPE_S 7 331 /* GPIO_PIN0_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ 332 /*description: if set to 0: normal output if set to 1: open drain*/ 333 #define GPIO_PIN0_PAD_DRIVER (BIT(2)) 334 #define GPIO_PIN0_PAD_DRIVER_M (BIT(2)) 335 #define GPIO_PIN0_PAD_DRIVER_V 0x1 336 #define GPIO_PIN0_PAD_DRIVER_S 2 337 338 #define GPIO_PIN1_REG (DR_REG_GPIO_BASE + 0x008c) 339 /* GPIO_PIN1_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ 340 /*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt 341 enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ 342 #define GPIO_PIN1_INT_ENA 0x0000001F 343 #define GPIO_PIN1_INT_ENA_M ((GPIO_PIN1_INT_ENA_V)<<(GPIO_PIN1_INT_ENA_S)) 344 #define GPIO_PIN1_INT_ENA_V 0x1F 345 #define GPIO_PIN1_INT_ENA_S 13 346 /* GPIO_PIN1_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ 347 /*description: NA*/ 348 #define GPIO_PIN1_CONFIG 0x00000003 349 #define GPIO_PIN1_CONFIG_M ((GPIO_PIN1_CONFIG_V)<<(GPIO_PIN1_CONFIG_S)) 350 #define GPIO_PIN1_CONFIG_V 0x3 351 #define GPIO_PIN1_CONFIG_S 11 352 /* GPIO_PIN1_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ 353 /*description: GPIO wake up enable only available in light sleep*/ 354 #define GPIO_PIN1_WAKEUP_ENABLE (BIT(10)) 355 #define GPIO_PIN1_WAKEUP_ENABLE_M (BIT(10)) 356 #define GPIO_PIN1_WAKEUP_ENABLE_V 0x1 357 #define GPIO_PIN1_WAKEUP_ENABLE_S 10 358 /* GPIO_PIN1_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ 359 /*description: if set to 0: GPIO interrupt disable if set to 1: rising edge 360 trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ 361 #define GPIO_PIN1_INT_TYPE 0x00000007 362 #define GPIO_PIN1_INT_TYPE_M ((GPIO_PIN1_INT_TYPE_V)<<(GPIO_PIN1_INT_TYPE_S)) 363 #define GPIO_PIN1_INT_TYPE_V 0x7 364 #define GPIO_PIN1_INT_TYPE_S 7 365 /* GPIO_PIN1_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ 366 /*description: if set to 0: normal output if set to 1: open drain*/ 367 #define GPIO_PIN1_PAD_DRIVER (BIT(2)) 368 #define GPIO_PIN1_PAD_DRIVER_M (BIT(2)) 369 #define GPIO_PIN1_PAD_DRIVER_V 0x1 370 #define GPIO_PIN1_PAD_DRIVER_S 2 371 372 #define GPIO_PIN2_REG (DR_REG_GPIO_BASE + 0x0090) 373 /* GPIO_PIN2_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ 374 /*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt 375 enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ 376 #define GPIO_PIN2_INT_ENA 0x0000001F 377 #define GPIO_PIN2_INT_ENA_M ((GPIO_PIN2_INT_ENA_V)<<(GPIO_PIN2_INT_ENA_S)) 378 #define GPIO_PIN2_INT_ENA_V 0x1F 379 #define GPIO_PIN2_INT_ENA_S 13 380 /* GPIO_PIN2_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ 381 /*description: NA*/ 382 #define GPIO_PIN2_CONFIG 0x00000003 383 #define GPIO_PIN2_CONFIG_M ((GPIO_PIN2_CONFIG_V)<<(GPIO_PIN2_CONFIG_S)) 384 #define GPIO_PIN2_CONFIG_V 0x3 385 #define GPIO_PIN2_CONFIG_S 11 386 /* GPIO_PIN2_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ 387 /*description: GPIO wake up enable only available in light sleep*/ 388 #define GPIO_PIN2_WAKEUP_ENABLE (BIT(10)) 389 #define GPIO_PIN2_WAKEUP_ENABLE_M (BIT(10)) 390 #define GPIO_PIN2_WAKEUP_ENABLE_V 0x1 391 #define GPIO_PIN2_WAKEUP_ENABLE_S 10 392 /* GPIO_PIN2_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ 393 /*description: if set to 0: GPIO interrupt disable if set to 1: rising edge 394 trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ 395 #define GPIO_PIN2_INT_TYPE 0x00000007 396 #define GPIO_PIN2_INT_TYPE_M ((GPIO_PIN2_INT_TYPE_V)<<(GPIO_PIN2_INT_TYPE_S)) 397 #define GPIO_PIN2_INT_TYPE_V 0x7 398 #define GPIO_PIN2_INT_TYPE_S 7 399 /* GPIO_PIN2_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ 400 /*description: if set to 0: normal output if set to 1: open drain*/ 401 #define GPIO_PIN2_PAD_DRIVER (BIT(2)) 402 #define GPIO_PIN2_PAD_DRIVER_M (BIT(2)) 403 #define GPIO_PIN2_PAD_DRIVER_V 0x1 404 #define GPIO_PIN2_PAD_DRIVER_S 2 405 406 #define GPIO_PIN3_REG (DR_REG_GPIO_BASE + 0x0094) 407 /* GPIO_PIN3_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ 408 /*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt 409 enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ 410 #define GPIO_PIN3_INT_ENA 0x0000001F 411 #define GPIO_PIN3_INT_ENA_M ((GPIO_PIN3_INT_ENA_V)<<(GPIO_PIN3_INT_ENA_S)) 412 #define GPIO_PIN3_INT_ENA_V 0x1F 413 #define GPIO_PIN3_INT_ENA_S 13 414 /* GPIO_PIN3_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ 415 /*description: NA*/ 416 #define GPIO_PIN3_CONFIG 0x00000003 417 #define GPIO_PIN3_CONFIG_M ((GPIO_PIN3_CONFIG_V)<<(GPIO_PIN3_CONFIG_S)) 418 #define GPIO_PIN3_CONFIG_V 0x3 419 #define GPIO_PIN3_CONFIG_S 11 420 /* GPIO_PIN3_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ 421 /*description: GPIO wake up enable only available in light sleep*/ 422 #define GPIO_PIN3_WAKEUP_ENABLE (BIT(10)) 423 #define GPIO_PIN3_WAKEUP_ENABLE_M (BIT(10)) 424 #define GPIO_PIN3_WAKEUP_ENABLE_V 0x1 425 #define GPIO_PIN3_WAKEUP_ENABLE_S 10 426 /* GPIO_PIN3_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ 427 /*description: if set to 0: GPIO interrupt disable if set to 1: rising edge 428 trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ 429 #define GPIO_PIN3_INT_TYPE 0x00000007 430 #define GPIO_PIN3_INT_TYPE_M ((GPIO_PIN3_INT_TYPE_V)<<(GPIO_PIN3_INT_TYPE_S)) 431 #define GPIO_PIN3_INT_TYPE_V 0x7 432 #define GPIO_PIN3_INT_TYPE_S 7 433 /* GPIO_PIN3_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ 434 /*description: if set to 0: normal output if set to 1: open drain*/ 435 #define GPIO_PIN3_PAD_DRIVER (BIT(2)) 436 #define GPIO_PIN3_PAD_DRIVER_M (BIT(2)) 437 #define GPIO_PIN3_PAD_DRIVER_V 0x1 438 #define GPIO_PIN3_PAD_DRIVER_S 2 439 440 #define GPIO_PIN4_REG (DR_REG_GPIO_BASE + 0x0098) 441 /* GPIO_PIN4_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ 442 /*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt 443 enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ 444 #define GPIO_PIN4_INT_ENA 0x0000001F 445 #define GPIO_PIN4_INT_ENA_M ((GPIO_PIN4_INT_ENA_V)<<(GPIO_PIN4_INT_ENA_S)) 446 #define GPIO_PIN4_INT_ENA_V 0x1F 447 #define GPIO_PIN4_INT_ENA_S 13 448 /* GPIO_PIN4_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ 449 /*description: NA*/ 450 #define GPIO_PIN4_CONFIG 0x00000003 451 #define GPIO_PIN4_CONFIG_M ((GPIO_PIN4_CONFIG_V)<<(GPIO_PIN4_CONFIG_S)) 452 #define GPIO_PIN4_CONFIG_V 0x3 453 #define GPIO_PIN4_CONFIG_S 11 454 /* GPIO_PIN4_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ 455 /*description: GPIO wake up enable only available in light sleep*/ 456 #define GPIO_PIN4_WAKEUP_ENABLE (BIT(10)) 457 #define GPIO_PIN4_WAKEUP_ENABLE_M (BIT(10)) 458 #define GPIO_PIN4_WAKEUP_ENABLE_V 0x1 459 #define GPIO_PIN4_WAKEUP_ENABLE_S 10 460 /* GPIO_PIN4_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ 461 /*description: if set to 0: GPIO interrupt disable if set to 1: rising edge 462 trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ 463 #define GPIO_PIN4_INT_TYPE 0x00000007 464 #define GPIO_PIN4_INT_TYPE_M ((GPIO_PIN4_INT_TYPE_V)<<(GPIO_PIN4_INT_TYPE_S)) 465 #define GPIO_PIN4_INT_TYPE_V 0x7 466 #define GPIO_PIN4_INT_TYPE_S 7 467 /* GPIO_PIN4_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ 468 /*description: if set to 0: normal output if set to 1: open drain*/ 469 #define GPIO_PIN4_PAD_DRIVER (BIT(2)) 470 #define GPIO_PIN4_PAD_DRIVER_M (BIT(2)) 471 #define GPIO_PIN4_PAD_DRIVER_V 0x1 472 #define GPIO_PIN4_PAD_DRIVER_S 2 473 474 #define GPIO_PIN5_REG (DR_REG_GPIO_BASE + 0x009c) 475 /* GPIO_PIN5_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ 476 /*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt 477 enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ 478 #define GPIO_PIN5_INT_ENA 0x0000001F 479 #define GPIO_PIN5_INT_ENA_M ((GPIO_PIN5_INT_ENA_V)<<(GPIO_PIN5_INT_ENA_S)) 480 #define GPIO_PIN5_INT_ENA_V 0x1F 481 #define GPIO_PIN5_INT_ENA_S 13 482 /* GPIO_PIN5_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ 483 /*description: NA*/ 484 #define GPIO_PIN5_CONFIG 0x00000003 485 #define GPIO_PIN5_CONFIG_M ((GPIO_PIN5_CONFIG_V)<<(GPIO_PIN5_CONFIG_S)) 486 #define GPIO_PIN5_CONFIG_V 0x3 487 #define GPIO_PIN5_CONFIG_S 11 488 /* GPIO_PIN5_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ 489 /*description: GPIO wake up enable only available in light sleep*/ 490 #define GPIO_PIN5_WAKEUP_ENABLE (BIT(10)) 491 #define GPIO_PIN5_WAKEUP_ENABLE_M (BIT(10)) 492 #define GPIO_PIN5_WAKEUP_ENABLE_V 0x1 493 #define GPIO_PIN5_WAKEUP_ENABLE_S 10 494 /* GPIO_PIN5_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ 495 /*description: if set to 0: GPIO interrupt disable if set to 1: rising edge 496 trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ 497 #define GPIO_PIN5_INT_TYPE 0x00000007 498 #define GPIO_PIN5_INT_TYPE_M ((GPIO_PIN5_INT_TYPE_V)<<(GPIO_PIN5_INT_TYPE_S)) 499 #define GPIO_PIN5_INT_TYPE_V 0x7 500 #define GPIO_PIN5_INT_TYPE_S 7 501 /* GPIO_PIN5_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ 502 /*description: if set to 0: normal output if set to 1: open drain*/ 503 #define GPIO_PIN5_PAD_DRIVER (BIT(2)) 504 #define GPIO_PIN5_PAD_DRIVER_M (BIT(2)) 505 #define GPIO_PIN5_PAD_DRIVER_V 0x1 506 #define GPIO_PIN5_PAD_DRIVER_S 2 507 508 #define GPIO_PIN6_REG (DR_REG_GPIO_BASE + 0x00a0) 509 /* GPIO_PIN6_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ 510 /*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt 511 enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ 512 #define GPIO_PIN6_INT_ENA 0x0000001F 513 #define GPIO_PIN6_INT_ENA_M ((GPIO_PIN6_INT_ENA_V)<<(GPIO_PIN6_INT_ENA_S)) 514 #define GPIO_PIN6_INT_ENA_V 0x1F 515 #define GPIO_PIN6_INT_ENA_S 13 516 /* GPIO_PIN6_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ 517 /*description: NA*/ 518 #define GPIO_PIN6_CONFIG 0x00000003 519 #define GPIO_PIN6_CONFIG_M ((GPIO_PIN6_CONFIG_V)<<(GPIO_PIN6_CONFIG_S)) 520 #define GPIO_PIN6_CONFIG_V 0x3 521 #define GPIO_PIN6_CONFIG_S 11 522 /* GPIO_PIN6_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ 523 /*description: GPIO wake up enable only available in light sleep*/ 524 #define GPIO_PIN6_WAKEUP_ENABLE (BIT(10)) 525 #define GPIO_PIN6_WAKEUP_ENABLE_M (BIT(10)) 526 #define GPIO_PIN6_WAKEUP_ENABLE_V 0x1 527 #define GPIO_PIN6_WAKEUP_ENABLE_S 10 528 /* GPIO_PIN6_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ 529 /*description: if set to 0: GPIO interrupt disable if set to 1: rising edge 530 trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ 531 #define GPIO_PIN6_INT_TYPE 0x00000007 532 #define GPIO_PIN6_INT_TYPE_M ((GPIO_PIN6_INT_TYPE_V)<<(GPIO_PIN6_INT_TYPE_S)) 533 #define GPIO_PIN6_INT_TYPE_V 0x7 534 #define GPIO_PIN6_INT_TYPE_S 7 535 /* GPIO_PIN6_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ 536 /*description: if set to 0: normal output if set to 1: open drain*/ 537 #define GPIO_PIN6_PAD_DRIVER (BIT(2)) 538 #define GPIO_PIN6_PAD_DRIVER_M (BIT(2)) 539 #define GPIO_PIN6_PAD_DRIVER_V 0x1 540 #define GPIO_PIN6_PAD_DRIVER_S 2 541 542 #define GPIO_PIN7_REG (DR_REG_GPIO_BASE + 0x00a4) 543 /* GPIO_PIN7_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ 544 /*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt 545 enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ 546 #define GPIO_PIN7_INT_ENA 0x0000001F 547 #define GPIO_PIN7_INT_ENA_M ((GPIO_PIN7_INT_ENA_V)<<(GPIO_PIN7_INT_ENA_S)) 548 #define GPIO_PIN7_INT_ENA_V 0x1F 549 #define GPIO_PIN7_INT_ENA_S 13 550 /* GPIO_PIN7_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ 551 /*description: NA*/ 552 #define GPIO_PIN7_CONFIG 0x00000003 553 #define GPIO_PIN7_CONFIG_M ((GPIO_PIN7_CONFIG_V)<<(GPIO_PIN7_CONFIG_S)) 554 #define GPIO_PIN7_CONFIG_V 0x3 555 #define GPIO_PIN7_CONFIG_S 11 556 /* GPIO_PIN7_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ 557 /*description: GPIO wake up enable only available in light sleep*/ 558 #define GPIO_PIN7_WAKEUP_ENABLE (BIT(10)) 559 #define GPIO_PIN7_WAKEUP_ENABLE_M (BIT(10)) 560 #define GPIO_PIN7_WAKEUP_ENABLE_V 0x1 561 #define GPIO_PIN7_WAKEUP_ENABLE_S 10 562 /* GPIO_PIN7_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ 563 /*description: if set to 0: GPIO interrupt disable if set to 1: rising edge 564 trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ 565 #define GPIO_PIN7_INT_TYPE 0x00000007 566 #define GPIO_PIN7_INT_TYPE_M ((GPIO_PIN7_INT_TYPE_V)<<(GPIO_PIN7_INT_TYPE_S)) 567 #define GPIO_PIN7_INT_TYPE_V 0x7 568 #define GPIO_PIN7_INT_TYPE_S 7 569 /* GPIO_PIN7_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ 570 /*description: if set to 0: normal output if set to 1: open drain*/ 571 #define GPIO_PIN7_PAD_DRIVER (BIT(2)) 572 #define GPIO_PIN7_PAD_DRIVER_M (BIT(2)) 573 #define GPIO_PIN7_PAD_DRIVER_V 0x1 574 #define GPIO_PIN7_PAD_DRIVER_S 2 575 576 #define GPIO_PIN8_REG (DR_REG_GPIO_BASE + 0x00a8) 577 /* GPIO_PIN8_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ 578 /*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt 579 enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ 580 #define GPIO_PIN8_INT_ENA 0x0000001F 581 #define GPIO_PIN8_INT_ENA_M ((GPIO_PIN8_INT_ENA_V)<<(GPIO_PIN8_INT_ENA_S)) 582 #define GPIO_PIN8_INT_ENA_V 0x1F 583 #define GPIO_PIN8_INT_ENA_S 13 584 /* GPIO_PIN8_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ 585 /*description: NA*/ 586 #define GPIO_PIN8_CONFIG 0x00000003 587 #define GPIO_PIN8_CONFIG_M ((GPIO_PIN8_CONFIG_V)<<(GPIO_PIN8_CONFIG_S)) 588 #define GPIO_PIN8_CONFIG_V 0x3 589 #define GPIO_PIN8_CONFIG_S 11 590 /* GPIO_PIN8_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ 591 /*description: GPIO wake up enable only available in light sleep*/ 592 #define GPIO_PIN8_WAKEUP_ENABLE (BIT(10)) 593 #define GPIO_PIN8_WAKEUP_ENABLE_M (BIT(10)) 594 #define GPIO_PIN8_WAKEUP_ENABLE_V 0x1 595 #define GPIO_PIN8_WAKEUP_ENABLE_S 10 596 /* GPIO_PIN8_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ 597 /*description: if set to 0: GPIO interrupt disable if set to 1: rising edge 598 trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ 599 #define GPIO_PIN8_INT_TYPE 0x00000007 600 #define GPIO_PIN8_INT_TYPE_M ((GPIO_PIN8_INT_TYPE_V)<<(GPIO_PIN8_INT_TYPE_S)) 601 #define GPIO_PIN8_INT_TYPE_V 0x7 602 #define GPIO_PIN8_INT_TYPE_S 7 603 /* GPIO_PIN8_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ 604 /*description: if set to 0: normal output if set to 1: open drain*/ 605 #define GPIO_PIN8_PAD_DRIVER (BIT(2)) 606 #define GPIO_PIN8_PAD_DRIVER_M (BIT(2)) 607 #define GPIO_PIN8_PAD_DRIVER_V 0x1 608 #define GPIO_PIN8_PAD_DRIVER_S 2 609 610 #define GPIO_PIN9_REG (DR_REG_GPIO_BASE + 0x00ac) 611 /* GPIO_PIN9_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ 612 /*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt 613 enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ 614 #define GPIO_PIN9_INT_ENA 0x0000001F 615 #define GPIO_PIN9_INT_ENA_M ((GPIO_PIN9_INT_ENA_V)<<(GPIO_PIN9_INT_ENA_S)) 616 #define GPIO_PIN9_INT_ENA_V 0x1F 617 #define GPIO_PIN9_INT_ENA_S 13 618 /* GPIO_PIN9_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ 619 /*description: NA*/ 620 #define GPIO_PIN9_CONFIG 0x00000003 621 #define GPIO_PIN9_CONFIG_M ((GPIO_PIN9_CONFIG_V)<<(GPIO_PIN9_CONFIG_S)) 622 #define GPIO_PIN9_CONFIG_V 0x3 623 #define GPIO_PIN9_CONFIG_S 11 624 /* GPIO_PIN9_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ 625 /*description: GPIO wake up enable only available in light sleep*/ 626 #define GPIO_PIN9_WAKEUP_ENABLE (BIT(10)) 627 #define GPIO_PIN9_WAKEUP_ENABLE_M (BIT(10)) 628 #define GPIO_PIN9_WAKEUP_ENABLE_V 0x1 629 #define GPIO_PIN9_WAKEUP_ENABLE_S 10 630 /* GPIO_PIN9_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ 631 /*description: if set to 0: GPIO interrupt disable if set to 1: rising edge 632 trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ 633 #define GPIO_PIN9_INT_TYPE 0x00000007 634 #define GPIO_PIN9_INT_TYPE_M ((GPIO_PIN9_INT_TYPE_V)<<(GPIO_PIN9_INT_TYPE_S)) 635 #define GPIO_PIN9_INT_TYPE_V 0x7 636 #define GPIO_PIN9_INT_TYPE_S 7 637 /* GPIO_PIN9_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ 638 /*description: if set to 0: normal output if set to 1: open drain*/ 639 #define GPIO_PIN9_PAD_DRIVER (BIT(2)) 640 #define GPIO_PIN9_PAD_DRIVER_M (BIT(2)) 641 #define GPIO_PIN9_PAD_DRIVER_V 0x1 642 #define GPIO_PIN9_PAD_DRIVER_S 2 643 644 #define GPIO_PIN10_REG (DR_REG_GPIO_BASE + 0x00b0) 645 /* GPIO_PIN10_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ 646 /*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt 647 enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ 648 #define GPIO_PIN10_INT_ENA 0x0000001F 649 #define GPIO_PIN10_INT_ENA_M ((GPIO_PIN10_INT_ENA_V)<<(GPIO_PIN10_INT_ENA_S)) 650 #define GPIO_PIN10_INT_ENA_V 0x1F 651 #define GPIO_PIN10_INT_ENA_S 13 652 /* GPIO_PIN10_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ 653 /*description: NA*/ 654 #define GPIO_PIN10_CONFIG 0x00000003 655 #define GPIO_PIN10_CONFIG_M ((GPIO_PIN10_CONFIG_V)<<(GPIO_PIN10_CONFIG_S)) 656 #define GPIO_PIN10_CONFIG_V 0x3 657 #define GPIO_PIN10_CONFIG_S 11 658 /* GPIO_PIN10_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ 659 /*description: GPIO wake up enable only available in light sleep*/ 660 #define GPIO_PIN10_WAKEUP_ENABLE (BIT(10)) 661 #define GPIO_PIN10_WAKEUP_ENABLE_M (BIT(10)) 662 #define GPIO_PIN10_WAKEUP_ENABLE_V 0x1 663 #define GPIO_PIN10_WAKEUP_ENABLE_S 10 664 /* GPIO_PIN10_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ 665 /*description: if set to 0: GPIO interrupt disable if set to 1: rising edge 666 trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ 667 #define GPIO_PIN10_INT_TYPE 0x00000007 668 #define GPIO_PIN10_INT_TYPE_M ((GPIO_PIN10_INT_TYPE_V)<<(GPIO_PIN10_INT_TYPE_S)) 669 #define GPIO_PIN10_INT_TYPE_V 0x7 670 #define GPIO_PIN10_INT_TYPE_S 7 671 /* GPIO_PIN10_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ 672 /*description: if set to 0: normal output if set to 1: open drain*/ 673 #define GPIO_PIN10_PAD_DRIVER (BIT(2)) 674 #define GPIO_PIN10_PAD_DRIVER_M (BIT(2)) 675 #define GPIO_PIN10_PAD_DRIVER_V 0x1 676 #define GPIO_PIN10_PAD_DRIVER_S 2 677 678 #define GPIO_PIN11_REG (DR_REG_GPIO_BASE + 0x00b4) 679 /* GPIO_PIN11_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ 680 /*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt 681 enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ 682 #define GPIO_PIN11_INT_ENA 0x0000001F 683 #define GPIO_PIN11_INT_ENA_M ((GPIO_PIN11_INT_ENA_V)<<(GPIO_PIN11_INT_ENA_S)) 684 #define GPIO_PIN11_INT_ENA_V 0x1F 685 #define GPIO_PIN11_INT_ENA_S 13 686 /* GPIO_PIN11_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ 687 /*description: NA*/ 688 #define GPIO_PIN11_CONFIG 0x00000003 689 #define GPIO_PIN11_CONFIG_M ((GPIO_PIN11_CONFIG_V)<<(GPIO_PIN11_CONFIG_S)) 690 #define GPIO_PIN11_CONFIG_V 0x3 691 #define GPIO_PIN11_CONFIG_S 11 692 /* GPIO_PIN11_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ 693 /*description: GPIO wake up enable only available in light sleep*/ 694 #define GPIO_PIN11_WAKEUP_ENABLE (BIT(10)) 695 #define GPIO_PIN11_WAKEUP_ENABLE_M (BIT(10)) 696 #define GPIO_PIN11_WAKEUP_ENABLE_V 0x1 697 #define GPIO_PIN11_WAKEUP_ENABLE_S 10 698 /* GPIO_PIN11_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ 699 /*description: if set to 0: GPIO interrupt disable if set to 1: rising edge 700 trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ 701 #define GPIO_PIN11_INT_TYPE 0x00000007 702 #define GPIO_PIN11_INT_TYPE_M ((GPIO_PIN11_INT_TYPE_V)<<(GPIO_PIN11_INT_TYPE_S)) 703 #define GPIO_PIN11_INT_TYPE_V 0x7 704 #define GPIO_PIN11_INT_TYPE_S 7 705 /* GPIO_PIN11_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ 706 /*description: if set to 0: normal output if set to 1: open drain*/ 707 #define GPIO_PIN11_PAD_DRIVER (BIT(2)) 708 #define GPIO_PIN11_PAD_DRIVER_M (BIT(2)) 709 #define GPIO_PIN11_PAD_DRIVER_V 0x1 710 #define GPIO_PIN11_PAD_DRIVER_S 2 711 712 #define GPIO_PIN12_REG (DR_REG_GPIO_BASE + 0x00b8) 713 /* GPIO_PIN12_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ 714 /*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt 715 enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ 716 #define GPIO_PIN12_INT_ENA 0x0000001F 717 #define GPIO_PIN12_INT_ENA_M ((GPIO_PIN12_INT_ENA_V)<<(GPIO_PIN12_INT_ENA_S)) 718 #define GPIO_PIN12_INT_ENA_V 0x1F 719 #define GPIO_PIN12_INT_ENA_S 13 720 /* GPIO_PIN12_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ 721 /*description: NA*/ 722 #define GPIO_PIN12_CONFIG 0x00000003 723 #define GPIO_PIN12_CONFIG_M ((GPIO_PIN12_CONFIG_V)<<(GPIO_PIN12_CONFIG_S)) 724 #define GPIO_PIN12_CONFIG_V 0x3 725 #define GPIO_PIN12_CONFIG_S 11 726 /* GPIO_PIN12_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ 727 /*description: GPIO wake up enable only available in light sleep*/ 728 #define GPIO_PIN12_WAKEUP_ENABLE (BIT(10)) 729 #define GPIO_PIN12_WAKEUP_ENABLE_M (BIT(10)) 730 #define GPIO_PIN12_WAKEUP_ENABLE_V 0x1 731 #define GPIO_PIN12_WAKEUP_ENABLE_S 10 732 /* GPIO_PIN12_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ 733 /*description: if set to 0: GPIO interrupt disable if set to 1: rising edge 734 trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ 735 #define GPIO_PIN12_INT_TYPE 0x00000007 736 #define GPIO_PIN12_INT_TYPE_M ((GPIO_PIN12_INT_TYPE_V)<<(GPIO_PIN12_INT_TYPE_S)) 737 #define GPIO_PIN12_INT_TYPE_V 0x7 738 #define GPIO_PIN12_INT_TYPE_S 7 739 /* GPIO_PIN12_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ 740 /*description: if set to 0: normal output if set to 1: open drain*/ 741 #define GPIO_PIN12_PAD_DRIVER (BIT(2)) 742 #define GPIO_PIN12_PAD_DRIVER_M (BIT(2)) 743 #define GPIO_PIN12_PAD_DRIVER_V 0x1 744 #define GPIO_PIN12_PAD_DRIVER_S 2 745 746 #define GPIO_PIN13_REG (DR_REG_GPIO_BASE + 0x00bc) 747 /* GPIO_PIN13_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ 748 /*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt 749 enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ 750 #define GPIO_PIN13_INT_ENA 0x0000001F 751 #define GPIO_PIN13_INT_ENA_M ((GPIO_PIN13_INT_ENA_V)<<(GPIO_PIN13_INT_ENA_S)) 752 #define GPIO_PIN13_INT_ENA_V 0x1F 753 #define GPIO_PIN13_INT_ENA_S 13 754 /* GPIO_PIN13_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ 755 /*description: NA*/ 756 #define GPIO_PIN13_CONFIG 0x00000003 757 #define GPIO_PIN13_CONFIG_M ((GPIO_PIN13_CONFIG_V)<<(GPIO_PIN13_CONFIG_S)) 758 #define GPIO_PIN13_CONFIG_V 0x3 759 #define GPIO_PIN13_CONFIG_S 11 760 /* GPIO_PIN13_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ 761 /*description: GPIO wake up enable only available in light sleep*/ 762 #define GPIO_PIN13_WAKEUP_ENABLE (BIT(10)) 763 #define GPIO_PIN13_WAKEUP_ENABLE_M (BIT(10)) 764 #define GPIO_PIN13_WAKEUP_ENABLE_V 0x1 765 #define GPIO_PIN13_WAKEUP_ENABLE_S 10 766 /* GPIO_PIN13_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ 767 /*description: if set to 0: GPIO interrupt disable if set to 1: rising edge 768 trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ 769 #define GPIO_PIN13_INT_TYPE 0x00000007 770 #define GPIO_PIN13_INT_TYPE_M ((GPIO_PIN13_INT_TYPE_V)<<(GPIO_PIN13_INT_TYPE_S)) 771 #define GPIO_PIN13_INT_TYPE_V 0x7 772 #define GPIO_PIN13_INT_TYPE_S 7 773 /* GPIO_PIN13_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ 774 /*description: if set to 0: normal output if set to 1: open drain*/ 775 #define GPIO_PIN13_PAD_DRIVER (BIT(2)) 776 #define GPIO_PIN13_PAD_DRIVER_M (BIT(2)) 777 #define GPIO_PIN13_PAD_DRIVER_V 0x1 778 #define GPIO_PIN13_PAD_DRIVER_S 2 779 780 #define GPIO_PIN14_REG (DR_REG_GPIO_BASE + 0x00c0) 781 /* GPIO_PIN14_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ 782 /*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt 783 enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ 784 #define GPIO_PIN14_INT_ENA 0x0000001F 785 #define GPIO_PIN14_INT_ENA_M ((GPIO_PIN14_INT_ENA_V)<<(GPIO_PIN14_INT_ENA_S)) 786 #define GPIO_PIN14_INT_ENA_V 0x1F 787 #define GPIO_PIN14_INT_ENA_S 13 788 /* GPIO_PIN14_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ 789 /*description: NA*/ 790 #define GPIO_PIN14_CONFIG 0x00000003 791 #define GPIO_PIN14_CONFIG_M ((GPIO_PIN14_CONFIG_V)<<(GPIO_PIN14_CONFIG_S)) 792 #define GPIO_PIN14_CONFIG_V 0x3 793 #define GPIO_PIN14_CONFIG_S 11 794 /* GPIO_PIN14_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ 795 /*description: GPIO wake up enable only available in light sleep*/ 796 #define GPIO_PIN14_WAKEUP_ENABLE (BIT(10)) 797 #define GPIO_PIN14_WAKEUP_ENABLE_M (BIT(10)) 798 #define GPIO_PIN14_WAKEUP_ENABLE_V 0x1 799 #define GPIO_PIN14_WAKEUP_ENABLE_S 10 800 /* GPIO_PIN14_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ 801 /*description: if set to 0: GPIO interrupt disable if set to 1: rising edge 802 trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ 803 #define GPIO_PIN14_INT_TYPE 0x00000007 804 #define GPIO_PIN14_INT_TYPE_M ((GPIO_PIN14_INT_TYPE_V)<<(GPIO_PIN14_INT_TYPE_S)) 805 #define GPIO_PIN14_INT_TYPE_V 0x7 806 #define GPIO_PIN14_INT_TYPE_S 7 807 /* GPIO_PIN14_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ 808 /*description: if set to 0: normal output if set to 1: open drain*/ 809 #define GPIO_PIN14_PAD_DRIVER (BIT(2)) 810 #define GPIO_PIN14_PAD_DRIVER_M (BIT(2)) 811 #define GPIO_PIN14_PAD_DRIVER_V 0x1 812 #define GPIO_PIN14_PAD_DRIVER_S 2 813 814 #define GPIO_PIN15_REG (DR_REG_GPIO_BASE + 0x00c4) 815 /* GPIO_PIN15_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ 816 /*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt 817 enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ 818 #define GPIO_PIN15_INT_ENA 0x0000001F 819 #define GPIO_PIN15_INT_ENA_M ((GPIO_PIN15_INT_ENA_V)<<(GPIO_PIN15_INT_ENA_S)) 820 #define GPIO_PIN15_INT_ENA_V 0x1F 821 #define GPIO_PIN15_INT_ENA_S 13 822 /* GPIO_PIN15_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ 823 /*description: NA*/ 824 #define GPIO_PIN15_CONFIG 0x00000003 825 #define GPIO_PIN15_CONFIG_M ((GPIO_PIN15_CONFIG_V)<<(GPIO_PIN15_CONFIG_S)) 826 #define GPIO_PIN15_CONFIG_V 0x3 827 #define GPIO_PIN15_CONFIG_S 11 828 /* GPIO_PIN15_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ 829 /*description: GPIO wake up enable only available in light sleep*/ 830 #define GPIO_PIN15_WAKEUP_ENABLE (BIT(10)) 831 #define GPIO_PIN15_WAKEUP_ENABLE_M (BIT(10)) 832 #define GPIO_PIN15_WAKEUP_ENABLE_V 0x1 833 #define GPIO_PIN15_WAKEUP_ENABLE_S 10 834 /* GPIO_PIN15_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ 835 /*description: if set to 0: GPIO interrupt disable if set to 1: rising edge 836 trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ 837 #define GPIO_PIN15_INT_TYPE 0x00000007 838 #define GPIO_PIN15_INT_TYPE_M ((GPIO_PIN15_INT_TYPE_V)<<(GPIO_PIN15_INT_TYPE_S)) 839 #define GPIO_PIN15_INT_TYPE_V 0x7 840 #define GPIO_PIN15_INT_TYPE_S 7 841 /* GPIO_PIN15_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ 842 /*description: if set to 0: normal output if set to 1: open drain*/ 843 #define GPIO_PIN15_PAD_DRIVER (BIT(2)) 844 #define GPIO_PIN15_PAD_DRIVER_M (BIT(2)) 845 #define GPIO_PIN15_PAD_DRIVER_V 0x1 846 #define GPIO_PIN15_PAD_DRIVER_S 2 847 848 #define GPIO_PIN16_REG (DR_REG_GPIO_BASE + 0x00c8) 849 /* GPIO_PIN16_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ 850 /*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt 851 enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ 852 #define GPIO_PIN16_INT_ENA 0x0000001F 853 #define GPIO_PIN16_INT_ENA_M ((GPIO_PIN16_INT_ENA_V)<<(GPIO_PIN16_INT_ENA_S)) 854 #define GPIO_PIN16_INT_ENA_V 0x1F 855 #define GPIO_PIN16_INT_ENA_S 13 856 /* GPIO_PIN16_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ 857 /*description: NA*/ 858 #define GPIO_PIN16_CONFIG 0x00000003 859 #define GPIO_PIN16_CONFIG_M ((GPIO_PIN16_CONFIG_V)<<(GPIO_PIN16_CONFIG_S)) 860 #define GPIO_PIN16_CONFIG_V 0x3 861 #define GPIO_PIN16_CONFIG_S 11 862 /* GPIO_PIN16_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ 863 /*description: GPIO wake up enable only available in light sleep*/ 864 #define GPIO_PIN16_WAKEUP_ENABLE (BIT(10)) 865 #define GPIO_PIN16_WAKEUP_ENABLE_M (BIT(10)) 866 #define GPIO_PIN16_WAKEUP_ENABLE_V 0x1 867 #define GPIO_PIN16_WAKEUP_ENABLE_S 10 868 /* GPIO_PIN16_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ 869 /*description: if set to 0: GPIO interrupt disable if set to 1: rising edge 870 trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ 871 #define GPIO_PIN16_INT_TYPE 0x00000007 872 #define GPIO_PIN16_INT_TYPE_M ((GPIO_PIN16_INT_TYPE_V)<<(GPIO_PIN16_INT_TYPE_S)) 873 #define GPIO_PIN16_INT_TYPE_V 0x7 874 #define GPIO_PIN16_INT_TYPE_S 7 875 /* GPIO_PIN16_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ 876 /*description: if set to 0: normal output if set to 1: open drain*/ 877 #define GPIO_PIN16_PAD_DRIVER (BIT(2)) 878 #define GPIO_PIN16_PAD_DRIVER_M (BIT(2)) 879 #define GPIO_PIN16_PAD_DRIVER_V 0x1 880 #define GPIO_PIN16_PAD_DRIVER_S 2 881 882 #define GPIO_PIN17_REG (DR_REG_GPIO_BASE + 0x00cc) 883 /* GPIO_PIN17_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ 884 /*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt 885 enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ 886 #define GPIO_PIN17_INT_ENA 0x0000001F 887 #define GPIO_PIN17_INT_ENA_M ((GPIO_PIN17_INT_ENA_V)<<(GPIO_PIN17_INT_ENA_S)) 888 #define GPIO_PIN17_INT_ENA_V 0x1F 889 #define GPIO_PIN17_INT_ENA_S 13 890 /* GPIO_PIN17_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ 891 /*description: NA*/ 892 #define GPIO_PIN17_CONFIG 0x00000003 893 #define GPIO_PIN17_CONFIG_M ((GPIO_PIN17_CONFIG_V)<<(GPIO_PIN17_CONFIG_S)) 894 #define GPIO_PIN17_CONFIG_V 0x3 895 #define GPIO_PIN17_CONFIG_S 11 896 /* GPIO_PIN17_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ 897 /*description: GPIO wake up enable only available in light sleep*/ 898 #define GPIO_PIN17_WAKEUP_ENABLE (BIT(10)) 899 #define GPIO_PIN17_WAKEUP_ENABLE_M (BIT(10)) 900 #define GPIO_PIN17_WAKEUP_ENABLE_V 0x1 901 #define GPIO_PIN17_WAKEUP_ENABLE_S 10 902 /* GPIO_PIN17_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ 903 /*description: if set to 0: GPIO interrupt disable if set to 1: rising edge 904 trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ 905 #define GPIO_PIN17_INT_TYPE 0x00000007 906 #define GPIO_PIN17_INT_TYPE_M ((GPIO_PIN17_INT_TYPE_V)<<(GPIO_PIN17_INT_TYPE_S)) 907 #define GPIO_PIN17_INT_TYPE_V 0x7 908 #define GPIO_PIN17_INT_TYPE_S 7 909 /* GPIO_PIN17_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ 910 /*description: if set to 0: normal output if set to 1: open drain*/ 911 #define GPIO_PIN17_PAD_DRIVER (BIT(2)) 912 #define GPIO_PIN17_PAD_DRIVER_M (BIT(2)) 913 #define GPIO_PIN17_PAD_DRIVER_V 0x1 914 #define GPIO_PIN17_PAD_DRIVER_S 2 915 916 #define GPIO_PIN18_REG (DR_REG_GPIO_BASE + 0x00d0) 917 /* GPIO_PIN18_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ 918 /*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt 919 enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ 920 #define GPIO_PIN18_INT_ENA 0x0000001F 921 #define GPIO_PIN18_INT_ENA_M ((GPIO_PIN18_INT_ENA_V)<<(GPIO_PIN18_INT_ENA_S)) 922 #define GPIO_PIN18_INT_ENA_V 0x1F 923 #define GPIO_PIN18_INT_ENA_S 13 924 /* GPIO_PIN18_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ 925 /*description: NA*/ 926 #define GPIO_PIN18_CONFIG 0x00000003 927 #define GPIO_PIN18_CONFIG_M ((GPIO_PIN18_CONFIG_V)<<(GPIO_PIN18_CONFIG_S)) 928 #define GPIO_PIN18_CONFIG_V 0x3 929 #define GPIO_PIN18_CONFIG_S 11 930 /* GPIO_PIN18_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ 931 /*description: GPIO wake up enable only available in light sleep*/ 932 #define GPIO_PIN18_WAKEUP_ENABLE (BIT(10)) 933 #define GPIO_PIN18_WAKEUP_ENABLE_M (BIT(10)) 934 #define GPIO_PIN18_WAKEUP_ENABLE_V 0x1 935 #define GPIO_PIN18_WAKEUP_ENABLE_S 10 936 /* GPIO_PIN18_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ 937 /*description: if set to 0: GPIO interrupt disable if set to 1: rising edge 938 trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ 939 #define GPIO_PIN18_INT_TYPE 0x00000007 940 #define GPIO_PIN18_INT_TYPE_M ((GPIO_PIN18_INT_TYPE_V)<<(GPIO_PIN18_INT_TYPE_S)) 941 #define GPIO_PIN18_INT_TYPE_V 0x7 942 #define GPIO_PIN18_INT_TYPE_S 7 943 /* GPIO_PIN18_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ 944 /*description: if set to 0: normal output if set to 1: open drain*/ 945 #define GPIO_PIN18_PAD_DRIVER (BIT(2)) 946 #define GPIO_PIN18_PAD_DRIVER_M (BIT(2)) 947 #define GPIO_PIN18_PAD_DRIVER_V 0x1 948 #define GPIO_PIN18_PAD_DRIVER_S 2 949 950 #define GPIO_PIN19_REG (DR_REG_GPIO_BASE + 0x00d4) 951 /* GPIO_PIN19_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ 952 /*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt 953 enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ 954 #define GPIO_PIN19_INT_ENA 0x0000001F 955 #define GPIO_PIN19_INT_ENA_M ((GPIO_PIN19_INT_ENA_V)<<(GPIO_PIN19_INT_ENA_S)) 956 #define GPIO_PIN19_INT_ENA_V 0x1F 957 #define GPIO_PIN19_INT_ENA_S 13 958 /* GPIO_PIN19_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ 959 /*description: NA*/ 960 #define GPIO_PIN19_CONFIG 0x00000003 961 #define GPIO_PIN19_CONFIG_M ((GPIO_PIN19_CONFIG_V)<<(GPIO_PIN19_CONFIG_S)) 962 #define GPIO_PIN19_CONFIG_V 0x3 963 #define GPIO_PIN19_CONFIG_S 11 964 /* GPIO_PIN19_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ 965 /*description: GPIO wake up enable only available in light sleep*/ 966 #define GPIO_PIN19_WAKEUP_ENABLE (BIT(10)) 967 #define GPIO_PIN19_WAKEUP_ENABLE_M (BIT(10)) 968 #define GPIO_PIN19_WAKEUP_ENABLE_V 0x1 969 #define GPIO_PIN19_WAKEUP_ENABLE_S 10 970 /* GPIO_PIN19_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ 971 /*description: if set to 0: GPIO interrupt disable if set to 1: rising edge 972 trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ 973 #define GPIO_PIN19_INT_TYPE 0x00000007 974 #define GPIO_PIN19_INT_TYPE_M ((GPIO_PIN19_INT_TYPE_V)<<(GPIO_PIN19_INT_TYPE_S)) 975 #define GPIO_PIN19_INT_TYPE_V 0x7 976 #define GPIO_PIN19_INT_TYPE_S 7 977 /* GPIO_PIN19_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ 978 /*description: if set to 0: normal output if set to 1: open drain*/ 979 #define GPIO_PIN19_PAD_DRIVER (BIT(2)) 980 #define GPIO_PIN19_PAD_DRIVER_M (BIT(2)) 981 #define GPIO_PIN19_PAD_DRIVER_V 0x1 982 #define GPIO_PIN19_PAD_DRIVER_S 2 983 984 #define GPIO_PIN20_REG (DR_REG_GPIO_BASE + 0x00d8) 985 /* GPIO_PIN20_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ 986 /*description: bit0: APP CPU interrupt enable bit1: APP CPU non-mask interrupt 987 enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-mask interrupt enable bit5: SDIO's extent interrupt enable*/ 988 #define GPIO_PIN20_INT_ENA 0x0000001F 989 #define GPIO_PIN20_INT_ENA_M ((GPIO_PIN20_INT_ENA_V)<<(GPIO_PIN20_INT_ENA_S)) 990 #define GPIO_PIN20_INT_ENA_V 0x1F 991 #define GPIO_PIN20_INT_ENA_S 13 992 /* GPIO_PIN20_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ 993 /*description: NA*/ 994 #define GPIO_PIN20_CONFIG 0x00000003 995 #define GPIO_PIN20_CONFIG_M ((GPIO_PIN20_CONFIG_V)<<(GPIO_PIN20_CONFIG_S)) 996 #define GPIO_PIN20_CONFIG_V 0x3 997 #define GPIO_PIN20_CONFIG_S 11 998 /* GPIO_PIN20_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ 999 /*description: GPIO wake up enable only available in light sleep*/ 1000 #define GPIO_PIN20_WAKEUP_ENABLE (BIT(10)) 1001 #define GPIO_PIN20_WAKEUP_ENABLE_M (BIT(10)) 1002 #define GPIO_PIN20_WAKEUP_ENABLE_V 0x1 1003 #define GPIO_PIN20_WAKEUP_ENABLE_S 10 1004 /* GPIO_PIN20_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ 1005 /*description: if set to 0: GPIO interrupt disable if set to 1: rising edge 1006 trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ 1007 #define GPIO_PIN20_INT_TYPE 0x00000007 1008 #define GPIO_PIN20_INT_TYPE_M ((GPIO_PIN20_INT_TYPE_V)<<(GPIO_PIN20_INT_TYPE_S)) 1009 #define GPIO_PIN20_INT_TYPE_V 0x7 1010 #define GPIO_PIN20_INT_TYPE_S 7 1011 /* GPIO_PIN20_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ 1012 /*description: if set to 0: normal output if set to 1: open drain*/ 1013 #define GPIO_PIN20_PAD_DRIVER (BIT(2)) 1014 #define GPIO_PIN20_PAD_DRIVER_M (BIT(2)) 1015 #define GPIO_PIN20_PAD_DRIVER_V 0x1 1016 #define GPIO_PIN20_PAD_DRIVER_S 2 1017 1018 #define GPIO_PIN21_REG (DR_REG_GPIO_BASE + 0x00dc) 1019 /* GPIO_PIN21_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ 1020 /*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt 1021 enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ 1022 #define GPIO_PIN21_INT_ENA 0x0000001F 1023 #define GPIO_PIN21_INT_ENA_M ((GPIO_PIN21_INT_ENA_V)<<(GPIO_PIN21_INT_ENA_S)) 1024 #define GPIO_PIN21_INT_ENA_V 0x1F 1025 #define GPIO_PIN21_INT_ENA_S 13 1026 /* GPIO_PIN21_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ 1027 /*description: NA*/ 1028 #define GPIO_PIN21_CONFIG 0x00000003 1029 #define GPIO_PIN21_CONFIG_M ((GPIO_PIN21_CONFIG_V)<<(GPIO_PIN21_CONFIG_S)) 1030 #define GPIO_PIN21_CONFIG_V 0x3 1031 #define GPIO_PIN21_CONFIG_S 11 1032 /* GPIO_PIN21_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ 1033 /*description: GPIO wake up enable only available in light sleep*/ 1034 #define GPIO_PIN21_WAKEUP_ENABLE (BIT(10)) 1035 #define GPIO_PIN21_WAKEUP_ENABLE_M (BIT(10)) 1036 #define GPIO_PIN21_WAKEUP_ENABLE_V 0x1 1037 #define GPIO_PIN21_WAKEUP_ENABLE_S 10 1038 /* GPIO_PIN21_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ 1039 /*description: if set to 0: GPIO interrupt disable if set to 1: rising edge 1040 trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ 1041 #define GPIO_PIN21_INT_TYPE 0x00000007 1042 #define GPIO_PIN21_INT_TYPE_M ((GPIO_PIN21_INT_TYPE_V)<<(GPIO_PIN21_INT_TYPE_S)) 1043 #define GPIO_PIN21_INT_TYPE_V 0x7 1044 #define GPIO_PIN21_INT_TYPE_S 7 1045 /* GPIO_PIN21_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ 1046 /*description: if set to 0: normal output if set to 1: open drain*/ 1047 #define GPIO_PIN21_PAD_DRIVER (BIT(2)) 1048 #define GPIO_PIN21_PAD_DRIVER_M (BIT(2)) 1049 #define GPIO_PIN21_PAD_DRIVER_V 0x1 1050 #define GPIO_PIN21_PAD_DRIVER_S 2 1051 1052 #define GPIO_PIN22_REG (DR_REG_GPIO_BASE + 0x00e0) 1053 /* GPIO_PIN22_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ 1054 /*description: */ 1055 #define GPIO_PIN22_INT_ENA 0x0000001F 1056 #define GPIO_PIN22_INT_ENA_M ((GPIO_PIN22_INT_ENA_V)<<(GPIO_PIN22_INT_ENA_S)) 1057 #define GPIO_PIN22_INT_ENA_V 0x1F 1058 #define GPIO_PIN22_INT_ENA_S 13 1059 /* GPIO_PIN22_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ 1060 /*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt 1061 enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ 1062 #define GPIO_PIN22_CONFIG 0x00000003 1063 #define GPIO_PIN22_CONFIG_M ((GPIO_PIN22_CONFIG_V)<<(GPIO_PIN22_CONFIG_S)) 1064 #define GPIO_PIN22_CONFIG_V 0x3 1065 #define GPIO_PIN22_CONFIG_S 11 1066 /* GPIO_PIN22_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ 1067 /*description: NA*/ 1068 #define GPIO_PIN22_WAKEUP_ENABLE (BIT(10)) 1069 #define GPIO_PIN22_WAKEUP_ENABLE_M (BIT(10)) 1070 #define GPIO_PIN22_WAKEUP_ENABLE_V 0x1 1071 #define GPIO_PIN22_WAKEUP_ENABLE_S 10 1072 /* GPIO_PIN22_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ 1073 /*description: GPIO wake up enable only available in light sleep*/ 1074 #define GPIO_PIN22_INT_TYPE 0x00000007 1075 #define GPIO_PIN22_INT_TYPE_M ((GPIO_PIN22_INT_TYPE_V)<<(GPIO_PIN22_INT_TYPE_S)) 1076 #define GPIO_PIN22_INT_TYPE_V 0x7 1077 #define GPIO_PIN22_INT_TYPE_S 7 1078 /* GPIO_PIN22_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ 1079 /*description: */ 1080 #define GPIO_PIN22_PAD_DRIVER (BIT(2)) 1081 #define GPIO_PIN22_PAD_DRIVER_M (BIT(2)) 1082 #define GPIO_PIN22_PAD_DRIVER_V 0x1 1083 #define GPIO_PIN22_PAD_DRIVER_S 2 1084 1085 #define GPIO_PIN23_REG (DR_REG_GPIO_BASE + 0x00e4) 1086 /* GPIO_PIN23_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ 1087 /*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt 1088 enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ 1089 #define GPIO_PIN23_INT_ENA 0x0000001F 1090 #define GPIO_PIN23_INT_ENA_M ((GPIO_PIN23_INT_ENA_V)<<(GPIO_PIN23_INT_ENA_S)) 1091 #define GPIO_PIN23_INT_ENA_V 0x1F 1092 #define GPIO_PIN23_INT_ENA_S 13 1093 /* GPIO_PIN23_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ 1094 /*description: NA*/ 1095 #define GPIO_PIN23_CONFIG 0x00000003 1096 #define GPIO_PIN23_CONFIG_M ((GPIO_PIN23_CONFIG_V)<<(GPIO_PIN23_CONFIG_S)) 1097 #define GPIO_PIN23_CONFIG_V 0x3 1098 #define GPIO_PIN23_CONFIG_S 11 1099 /* GPIO_PIN23_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ 1100 /*description: GPIO wake up enable only available in light sleep*/ 1101 #define GPIO_PIN23_WAKEUP_ENABLE (BIT(10)) 1102 #define GPIO_PIN23_WAKEUP_ENABLE_M (BIT(10)) 1103 #define GPIO_PIN23_WAKEUP_ENABLE_V 0x1 1104 #define GPIO_PIN23_WAKEUP_ENABLE_S 10 1105 /* GPIO_PIN23_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ 1106 /*description: if set to 0: GPIO interrupt disable if set to 1: rising edge 1107 trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ 1108 #define GPIO_PIN23_INT_TYPE 0x00000007 1109 #define GPIO_PIN23_INT_TYPE_M ((GPIO_PIN23_INT_TYPE_V)<<(GPIO_PIN23_INT_TYPE_S)) 1110 #define GPIO_PIN23_INT_TYPE_V 0x7 1111 #define GPIO_PIN23_INT_TYPE_S 7 1112 /* GPIO_PIN23_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ 1113 /*description: if set to 0: normal output if set to 1: open drain*/ 1114 #define GPIO_PIN23_PAD_DRIVER (BIT(2)) 1115 #define GPIO_PIN23_PAD_DRIVER_M (BIT(2)) 1116 #define GPIO_PIN23_PAD_DRIVER_V 0x1 1117 #define GPIO_PIN23_PAD_DRIVER_S 2 1118 1119 #define GPIO_PIN24_REG (DR_REG_GPIO_BASE + 0x00e8) 1120 /* GPIO_PIN24_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ 1121 /*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt 1122 enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ 1123 #define GPIO_PIN24_INT_ENA 0x0000001F 1124 #define GPIO_PIN24_INT_ENA_M ((GPIO_PIN24_INT_ENA_V)<<(GPIO_PIN24_INT_ENA_S)) 1125 #define GPIO_PIN24_INT_ENA_V 0x1F 1126 #define GPIO_PIN24_INT_ENA_S 13 1127 /* GPIO_PIN24_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ 1128 /*description: NA*/ 1129 #define GPIO_PIN24_CONFIG 0x00000003 1130 #define GPIO_PIN24_CONFIG_M ((GPIO_PIN24_CONFIG_V)<<(GPIO_PIN24_CONFIG_S)) 1131 #define GPIO_PIN24_CONFIG_V 0x3 1132 #define GPIO_PIN24_CONFIG_S 11 1133 /* GPIO_PIN24_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ 1134 /*description: GPIO wake up enable only available in light sleep*/ 1135 #define GPIO_PIN24_WAKEUP_ENABLE (BIT(10)) 1136 #define GPIO_PIN24_WAKEUP_ENABLE_M (BIT(10)) 1137 #define GPIO_PIN24_WAKEUP_ENABLE_V 0x1 1138 #define GPIO_PIN24_WAKEUP_ENABLE_S 10 1139 /* GPIO_PIN24_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ 1140 /*description: if set to 0: GPIO interrupt disable if set to 1: rising edge 1141 trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ 1142 #define GPIO_PIN24_INT_TYPE 0x00000007 1143 #define GPIO_PIN24_INT_TYPE_M ((GPIO_PIN24_INT_TYPE_V)<<(GPIO_PIN24_INT_TYPE_S)) 1144 #define GPIO_PIN24_INT_TYPE_V 0x7 1145 #define GPIO_PIN24_INT_TYPE_S 7 1146 /* GPIO_PIN24_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ 1147 /*description: if set to 0: normal output if set to 1: open drain*/ 1148 #define GPIO_PIN24_PAD_DRIVER (BIT(2)) 1149 #define GPIO_PIN24_PAD_DRIVER_M (BIT(2)) 1150 #define GPIO_PIN24_PAD_DRIVER_V 0x1 1151 #define GPIO_PIN24_PAD_DRIVER_S 2 1152 1153 #define GPIO_PIN25_REG (DR_REG_GPIO_BASE + 0x00ec) 1154 /* GPIO_PIN25_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ 1155 /*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt 1156 enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ 1157 #define GPIO_PIN25_INT_ENA 0x0000001F 1158 #define GPIO_PIN25_INT_ENA_M ((GPIO_PIN25_INT_ENA_V)<<(GPIO_PIN25_INT_ENA_S)) 1159 #define GPIO_PIN25_INT_ENA_V 0x1F 1160 #define GPIO_PIN25_INT_ENA_S 13 1161 /* GPIO_PIN25_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ 1162 /*description: NA*/ 1163 #define GPIO_PIN25_CONFIG 0x00000003 1164 #define GPIO_PIN25_CONFIG_M ((GPIO_PIN25_CONFIG_V)<<(GPIO_PIN25_CONFIG_S)) 1165 #define GPIO_PIN25_CONFIG_V 0x3 1166 #define GPIO_PIN25_CONFIG_S 11 1167 /* GPIO_PIN25_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ 1168 /*description: GPIO wake up enable only available in light sleep*/ 1169 #define GPIO_PIN25_WAKEUP_ENABLE (BIT(10)) 1170 #define GPIO_PIN25_WAKEUP_ENABLE_M (BIT(10)) 1171 #define GPIO_PIN25_WAKEUP_ENABLE_V 0x1 1172 #define GPIO_PIN25_WAKEUP_ENABLE_S 10 1173 /* GPIO_PIN25_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ 1174 /*description: if set to 0: GPIO interrupt disable if set to 1: rising edge 1175 trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ 1176 #define GPIO_PIN25_INT_TYPE 0x00000007 1177 #define GPIO_PIN25_INT_TYPE_M ((GPIO_PIN25_INT_TYPE_V)<<(GPIO_PIN25_INT_TYPE_S)) 1178 #define GPIO_PIN25_INT_TYPE_V 0x7 1179 #define GPIO_PIN25_INT_TYPE_S 7 1180 /* GPIO_PIN25_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ 1181 /*description: if set to 0: normal output if set to 1: open drain*/ 1182 #define GPIO_PIN25_PAD_DRIVER (BIT(2)) 1183 #define GPIO_PIN25_PAD_DRIVER_M (BIT(2)) 1184 #define GPIO_PIN25_PAD_DRIVER_V 0x1 1185 #define GPIO_PIN25_PAD_DRIVER_S 2 1186 1187 #define GPIO_PIN26_REG (DR_REG_GPIO_BASE + 0x00f0) 1188 /* GPIO_PIN26_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ 1189 /*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt 1190 enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ 1191 #define GPIO_PIN26_INT_ENA 0x0000001F 1192 #define GPIO_PIN26_INT_ENA_M ((GPIO_PIN26_INT_ENA_V)<<(GPIO_PIN26_INT_ENA_S)) 1193 #define GPIO_PIN26_INT_ENA_V 0x1F 1194 #define GPIO_PIN26_INT_ENA_S 13 1195 /* GPIO_PIN26_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ 1196 /*description: NA*/ 1197 #define GPIO_PIN26_CONFIG 0x00000003 1198 #define GPIO_PIN26_CONFIG_M ((GPIO_PIN26_CONFIG_V)<<(GPIO_PIN26_CONFIG_S)) 1199 #define GPIO_PIN26_CONFIG_V 0x3 1200 #define GPIO_PIN26_CONFIG_S 11 1201 /* GPIO_PIN26_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ 1202 /*description: GPIO wake up enable only available in light sleep*/ 1203 #define GPIO_PIN26_WAKEUP_ENABLE (BIT(10)) 1204 #define GPIO_PIN26_WAKEUP_ENABLE_M (BIT(10)) 1205 #define GPIO_PIN26_WAKEUP_ENABLE_V 0x1 1206 #define GPIO_PIN26_WAKEUP_ENABLE_S 10 1207 /* GPIO_PIN26_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ 1208 /*description: if set to 0: GPIO interrupt disable if set to 1: rising edge 1209 trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ 1210 #define GPIO_PIN26_INT_TYPE 0x00000007 1211 #define GPIO_PIN26_INT_TYPE_M ((GPIO_PIN26_INT_TYPE_V)<<(GPIO_PIN26_INT_TYPE_S)) 1212 #define GPIO_PIN26_INT_TYPE_V 0x7 1213 #define GPIO_PIN26_INT_TYPE_S 7 1214 /* GPIO_PIN26_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ 1215 /*description: if set to 0: normal output if set to 1: open drain*/ 1216 #define GPIO_PIN26_PAD_DRIVER (BIT(2)) 1217 #define GPIO_PIN26_PAD_DRIVER_M (BIT(2)) 1218 #define GPIO_PIN26_PAD_DRIVER_V 0x1 1219 #define GPIO_PIN26_PAD_DRIVER_S 2 1220 1221 #define GPIO_PIN27_REG (DR_REG_GPIO_BASE + 0x00f4) 1222 /* GPIO_PIN27_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ 1223 /*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt 1224 enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ 1225 #define GPIO_PIN27_INT_ENA 0x0000001F 1226 #define GPIO_PIN27_INT_ENA_M ((GPIO_PIN27_INT_ENA_V)<<(GPIO_PIN27_INT_ENA_S)) 1227 #define GPIO_PIN27_INT_ENA_V 0x1F 1228 #define GPIO_PIN27_INT_ENA_S 13 1229 /* GPIO_PIN27_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ 1230 /*description: NA*/ 1231 #define GPIO_PIN27_CONFIG 0x00000003 1232 #define GPIO_PIN27_CONFIG_M ((GPIO_PIN27_CONFIG_V)<<(GPIO_PIN27_CONFIG_S)) 1233 #define GPIO_PIN27_CONFIG_V 0x3 1234 #define GPIO_PIN27_CONFIG_S 11 1235 /* GPIO_PIN27_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ 1236 /*description: GPIO wake up enable only available in light sleep*/ 1237 #define GPIO_PIN27_WAKEUP_ENABLE (BIT(10)) 1238 #define GPIO_PIN27_WAKEUP_ENABLE_M (BIT(10)) 1239 #define GPIO_PIN27_WAKEUP_ENABLE_V 0x1 1240 #define GPIO_PIN27_WAKEUP_ENABLE_S 10 1241 /* GPIO_PIN27_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ 1242 /*description: if set to 0: GPIO interrupt disable if set to 1: rising edge 1243 trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ 1244 #define GPIO_PIN27_INT_TYPE 0x00000007 1245 #define GPIO_PIN27_INT_TYPE_M ((GPIO_PIN27_INT_TYPE_V)<<(GPIO_PIN27_INT_TYPE_S)) 1246 #define GPIO_PIN27_INT_TYPE_V 0x7 1247 #define GPIO_PIN27_INT_TYPE_S 7 1248 /* GPIO_PIN27_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ 1249 /*description: if set to 0: normal output if set to 1: open drain*/ 1250 #define GPIO_PIN27_PAD_DRIVER (BIT(2)) 1251 #define GPIO_PIN27_PAD_DRIVER_M (BIT(2)) 1252 #define GPIO_PIN27_PAD_DRIVER_V 0x1 1253 #define GPIO_PIN27_PAD_DRIVER_S 2 1254 1255 #define GPIO_PIN28_REG (DR_REG_GPIO_BASE + 0x00f8) 1256 /* GPIO_PIN28_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ 1257 /*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt 1258 enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ 1259 #define GPIO_PIN28_INT_ENA 0x0000001F 1260 #define GPIO_PIN28_INT_ENA_M ((GPIO_PIN28_INT_ENA_V)<<(GPIO_PIN28_INT_ENA_S)) 1261 #define GPIO_PIN28_INT_ENA_V 0x1F 1262 #define GPIO_PIN28_INT_ENA_S 13 1263 /* GPIO_PIN28_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ 1264 /*description: NA*/ 1265 #define GPIO_PIN28_CONFIG 0x00000003 1266 #define GPIO_PIN28_CONFIG_M ((GPIO_PIN28_CONFIG_V)<<(GPIO_PIN28_CONFIG_S)) 1267 #define GPIO_PIN28_CONFIG_V 0x3 1268 #define GPIO_PIN28_CONFIG_S 11 1269 /* GPIO_PIN28_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ 1270 /*description: GPIO wake up enable only available in light sleep*/ 1271 #define GPIO_PIN28_WAKEUP_ENABLE (BIT(10)) 1272 #define GPIO_PIN28_WAKEUP_ENABLE_M (BIT(10)) 1273 #define GPIO_PIN28_WAKEUP_ENABLE_V 0x1 1274 #define GPIO_PIN28_WAKEUP_ENABLE_S 10 1275 /* GPIO_PIN28_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ 1276 /*description: if set to 0: GPIO interrupt disable if set to 1: rising edge 1277 trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ 1278 #define GPIO_PIN28_INT_TYPE 0x00000007 1279 #define GPIO_PIN28_INT_TYPE_M ((GPIO_PIN28_INT_TYPE_V)<<(GPIO_PIN28_INT_TYPE_S)) 1280 #define GPIO_PIN28_INT_TYPE_V 0x7 1281 #define GPIO_PIN28_INT_TYPE_S 7 1282 /* GPIO_PIN28_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ 1283 /*description: if set to 0: normal output if set to 1: open drain*/ 1284 #define GPIO_PIN28_PAD_DRIVER (BIT(2)) 1285 #define GPIO_PIN28_PAD_DRIVER_M (BIT(2)) 1286 #define GPIO_PIN28_PAD_DRIVER_V 0x1 1287 #define GPIO_PIN28_PAD_DRIVER_S 2 1288 1289 #define GPIO_PIN29_REG (DR_REG_GPIO_BASE + 0x00fc) 1290 /* GPIO_PIN29_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ 1291 /*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt 1292 enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ 1293 #define GPIO_PIN29_INT_ENA 0x0000001F 1294 #define GPIO_PIN29_INT_ENA_M ((GPIO_PIN29_INT_ENA_V)<<(GPIO_PIN29_INT_ENA_S)) 1295 #define GPIO_PIN29_INT_ENA_V 0x1F 1296 #define GPIO_PIN29_INT_ENA_S 13 1297 /* GPIO_PIN29_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ 1298 /*description: NA*/ 1299 #define GPIO_PIN29_CONFIG 0x00000003 1300 #define GPIO_PIN29_CONFIG_M ((GPIO_PIN29_CONFIG_V)<<(GPIO_PIN29_CONFIG_S)) 1301 #define GPIO_PIN29_CONFIG_V 0x3 1302 #define GPIO_PIN29_CONFIG_S 11 1303 /* GPIO_PIN29_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ 1304 /*description: GPIO wake up enable only available in light sleep*/ 1305 #define GPIO_PIN29_WAKEUP_ENABLE (BIT(10)) 1306 #define GPIO_PIN29_WAKEUP_ENABLE_M (BIT(10)) 1307 #define GPIO_PIN29_WAKEUP_ENABLE_V 0x1 1308 #define GPIO_PIN29_WAKEUP_ENABLE_S 10 1309 /* GPIO_PIN29_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ 1310 /*description: if set to 0: GPIO interrupt disable if set to 1: rising edge 1311 trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ 1312 #define GPIO_PIN29_INT_TYPE 0x00000007 1313 #define GPIO_PIN29_INT_TYPE_M ((GPIO_PIN29_INT_TYPE_V)<<(GPIO_PIN29_INT_TYPE_S)) 1314 #define GPIO_PIN29_INT_TYPE_V 0x7 1315 #define GPIO_PIN29_INT_TYPE_S 7 1316 /* GPIO_PIN29_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ 1317 /*description: if set to 0: normal output if set to 1: open drain*/ 1318 #define GPIO_PIN29_PAD_DRIVER (BIT(2)) 1319 #define GPIO_PIN29_PAD_DRIVER_M (BIT(2)) 1320 #define GPIO_PIN29_PAD_DRIVER_V 0x1 1321 #define GPIO_PIN29_PAD_DRIVER_S 2 1322 1323 #define GPIO_PIN30_REG (DR_REG_GPIO_BASE + 0x0100) 1324 /* GPIO_PIN30_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ 1325 /*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt 1326 enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ 1327 #define GPIO_PIN30_INT_ENA 0x0000001F 1328 #define GPIO_PIN30_INT_ENA_M ((GPIO_PIN30_INT_ENA_V)<<(GPIO_PIN30_INT_ENA_S)) 1329 #define GPIO_PIN30_INT_ENA_V 0x1F 1330 #define GPIO_PIN30_INT_ENA_S 13 1331 /* GPIO_PIN30_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ 1332 /*description: NA*/ 1333 #define GPIO_PIN30_CONFIG 0x00000003 1334 #define GPIO_PIN30_CONFIG_M ((GPIO_PIN30_CONFIG_V)<<(GPIO_PIN30_CONFIG_S)) 1335 #define GPIO_PIN30_CONFIG_V 0x3 1336 #define GPIO_PIN30_CONFIG_S 11 1337 /* GPIO_PIN30_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ 1338 /*description: GPIO wake up enable only available in light sleep*/ 1339 #define GPIO_PIN30_WAKEUP_ENABLE (BIT(10)) 1340 #define GPIO_PIN30_WAKEUP_ENABLE_M (BIT(10)) 1341 #define GPIO_PIN30_WAKEUP_ENABLE_V 0x1 1342 #define GPIO_PIN30_WAKEUP_ENABLE_S 10 1343 /* GPIO_PIN30_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ 1344 /*description: if set to 0: GPIO interrupt disable if set to 1: rising edge 1345 trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ 1346 #define GPIO_PIN30_INT_TYPE 0x00000007 1347 #define GPIO_PIN30_INT_TYPE_M ((GPIO_PIN30_INT_TYPE_V)<<(GPIO_PIN30_INT_TYPE_S)) 1348 #define GPIO_PIN30_INT_TYPE_V 0x7 1349 #define GPIO_PIN30_INT_TYPE_S 7 1350 /* GPIO_PIN30_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ 1351 /*description: if set to 0: normal output if set to 1: open drain*/ 1352 #define GPIO_PIN30_PAD_DRIVER (BIT(2)) 1353 #define GPIO_PIN30_PAD_DRIVER_M (BIT(2)) 1354 #define GPIO_PIN30_PAD_DRIVER_V 0x1 1355 #define GPIO_PIN30_PAD_DRIVER_S 2 1356 1357 #define GPIO_PIN31_REG (DR_REG_GPIO_BASE + 0x0104) 1358 /* GPIO_PIN31_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ 1359 /*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt 1360 enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ 1361 #define GPIO_PIN31_INT_ENA 0x0000001F 1362 #define GPIO_PIN31_INT_ENA_M ((GPIO_PIN31_INT_ENA_V)<<(GPIO_PIN31_INT_ENA_S)) 1363 #define GPIO_PIN31_INT_ENA_V 0x1F 1364 #define GPIO_PIN31_INT_ENA_S 13 1365 /* GPIO_PIN31_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ 1366 /*description: NA*/ 1367 #define GPIO_PIN31_CONFIG 0x00000003 1368 #define GPIO_PIN31_CONFIG_M ((GPIO_PIN31_CONFIG_V)<<(GPIO_PIN31_CONFIG_S)) 1369 #define GPIO_PIN31_CONFIG_V 0x3 1370 #define GPIO_PIN31_CONFIG_S 11 1371 /* GPIO_PIN31_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ 1372 /*description: GPIO wake up enable only available in light sleep*/ 1373 #define GPIO_PIN31_WAKEUP_ENABLE (BIT(10)) 1374 #define GPIO_PIN31_WAKEUP_ENABLE_M (BIT(10)) 1375 #define GPIO_PIN31_WAKEUP_ENABLE_V 0x1 1376 #define GPIO_PIN31_WAKEUP_ENABLE_S 10 1377 /* GPIO_PIN31_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ 1378 /*description: if set to 0: GPIO interrupt disable if set to 1: rising edge 1379 trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ 1380 #define GPIO_PIN31_INT_TYPE 0x00000007 1381 #define GPIO_PIN31_INT_TYPE_M ((GPIO_PIN31_INT_TYPE_V)<<(GPIO_PIN31_INT_TYPE_S)) 1382 #define GPIO_PIN31_INT_TYPE_V 0x7 1383 #define GPIO_PIN31_INT_TYPE_S 7 1384 /* GPIO_PIN31_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ 1385 /*description: if set to 0: normal output if set to 1: open drain*/ 1386 #define GPIO_PIN31_PAD_DRIVER (BIT(2)) 1387 #define GPIO_PIN31_PAD_DRIVER_M (BIT(2)) 1388 #define GPIO_PIN31_PAD_DRIVER_V 0x1 1389 #define GPIO_PIN31_PAD_DRIVER_S 2 1390 1391 #define GPIO_PIN32_REG (DR_REG_GPIO_BASE + 0x0108) 1392 /* GPIO_PIN32_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ 1393 /*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt 1394 enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ 1395 #define GPIO_PIN32_INT_ENA 0x0000001F 1396 #define GPIO_PIN32_INT_ENA_M ((GPIO_PIN32_INT_ENA_V)<<(GPIO_PIN32_INT_ENA_S)) 1397 #define GPIO_PIN32_INT_ENA_V 0x1F 1398 #define GPIO_PIN32_INT_ENA_S 13 1399 /* GPIO_PIN32_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ 1400 /*description: NA*/ 1401 #define GPIO_PIN32_CONFIG 0x00000003 1402 #define GPIO_PIN32_CONFIG_M ((GPIO_PIN32_CONFIG_V)<<(GPIO_PIN32_CONFIG_S)) 1403 #define GPIO_PIN32_CONFIG_V 0x3 1404 #define GPIO_PIN32_CONFIG_S 11 1405 /* GPIO_PIN32_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ 1406 /*description: GPIO wake up enable only available in light sleep*/ 1407 #define GPIO_PIN32_WAKEUP_ENABLE (BIT(10)) 1408 #define GPIO_PIN32_WAKEUP_ENABLE_M (BIT(10)) 1409 #define GPIO_PIN32_WAKEUP_ENABLE_V 0x1 1410 #define GPIO_PIN32_WAKEUP_ENABLE_S 10 1411 /* GPIO_PIN32_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ 1412 /*description: if set to 0: GPIO interrupt disable if set to 1: rising edge 1413 trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ 1414 #define GPIO_PIN32_INT_TYPE 0x00000007 1415 #define GPIO_PIN32_INT_TYPE_M ((GPIO_PIN32_INT_TYPE_V)<<(GPIO_PIN32_INT_TYPE_S)) 1416 #define GPIO_PIN32_INT_TYPE_V 0x7 1417 #define GPIO_PIN32_INT_TYPE_S 7 1418 /* GPIO_PIN32_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ 1419 /*description: if set to 0: normal output if set to 1: open drain*/ 1420 #define GPIO_PIN32_PAD_DRIVER (BIT(2)) 1421 #define GPIO_PIN32_PAD_DRIVER_M (BIT(2)) 1422 #define GPIO_PIN32_PAD_DRIVER_V 0x1 1423 #define GPIO_PIN32_PAD_DRIVER_S 2 1424 1425 #define GPIO_PIN33_REG (DR_REG_GPIO_BASE + 0x010c) 1426 /* GPIO_PIN33_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ 1427 /*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt 1428 enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ 1429 #define GPIO_PIN33_INT_ENA 0x0000001F 1430 #define GPIO_PIN33_INT_ENA_M ((GPIO_PIN33_INT_ENA_V)<<(GPIO_PIN33_INT_ENA_S)) 1431 #define GPIO_PIN33_INT_ENA_V 0x1F 1432 #define GPIO_PIN33_INT_ENA_S 13 1433 /* GPIO_PIN33_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ 1434 /*description: NA*/ 1435 #define GPIO_PIN33_CONFIG 0x00000003 1436 #define GPIO_PIN33_CONFIG_M ((GPIO_PIN33_CONFIG_V)<<(GPIO_PIN33_CONFIG_S)) 1437 #define GPIO_PIN33_CONFIG_V 0x3 1438 #define GPIO_PIN33_CONFIG_S 11 1439 /* GPIO_PIN33_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ 1440 /*description: GPIO wake up enable only available in light sleep*/ 1441 #define GPIO_PIN33_WAKEUP_ENABLE (BIT(10)) 1442 #define GPIO_PIN33_WAKEUP_ENABLE_M (BIT(10)) 1443 #define GPIO_PIN33_WAKEUP_ENABLE_V 0x1 1444 #define GPIO_PIN33_WAKEUP_ENABLE_S 10 1445 /* GPIO_PIN33_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ 1446 /*description: if set to 0: GPIO interrupt disable if set to 1: rising edge 1447 trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ 1448 #define GPIO_PIN33_INT_TYPE 0x00000007 1449 #define GPIO_PIN33_INT_TYPE_M ((GPIO_PIN33_INT_TYPE_V)<<(GPIO_PIN33_INT_TYPE_S)) 1450 #define GPIO_PIN33_INT_TYPE_V 0x7 1451 #define GPIO_PIN33_INT_TYPE_S 7 1452 /* GPIO_PIN33_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ 1453 /*description: if set to 0: normal output if set to 1: open drain*/ 1454 #define GPIO_PIN33_PAD_DRIVER (BIT(2)) 1455 #define GPIO_PIN33_PAD_DRIVER_M (BIT(2)) 1456 #define GPIO_PIN33_PAD_DRIVER_V 0x1 1457 #define GPIO_PIN33_PAD_DRIVER_S 2 1458 1459 #define GPIO_PIN34_REG (DR_REG_GPIO_BASE + 0x0110) 1460 /* GPIO_PIN34_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ 1461 /*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt 1462 enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ 1463 #define GPIO_PIN34_INT_ENA 0x0000001F 1464 #define GPIO_PIN34_INT_ENA_M ((GPIO_PIN34_INT_ENA_V)<<(GPIO_PIN34_INT_ENA_S)) 1465 #define GPIO_PIN34_INT_ENA_V 0x1F 1466 #define GPIO_PIN34_INT_ENA_S 13 1467 /* GPIO_PIN34_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ 1468 /*description: NA*/ 1469 #define GPIO_PIN34_CONFIG 0x00000003 1470 #define GPIO_PIN34_CONFIG_M ((GPIO_PIN34_CONFIG_V)<<(GPIO_PIN34_CONFIG_S)) 1471 #define GPIO_PIN34_CONFIG_V 0x3 1472 #define GPIO_PIN34_CONFIG_S 11 1473 /* GPIO_PIN34_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ 1474 /*description: GPIO wake up enable only available in light sleep*/ 1475 #define GPIO_PIN34_WAKEUP_ENABLE (BIT(10)) 1476 #define GPIO_PIN34_WAKEUP_ENABLE_M (BIT(10)) 1477 #define GPIO_PIN34_WAKEUP_ENABLE_V 0x1 1478 #define GPIO_PIN34_WAKEUP_ENABLE_S 10 1479 /* GPIO_PIN34_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ 1480 /*description: if set to 0: GPIO interrupt disable if set to 1: rising edge 1481 trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ 1482 #define GPIO_PIN34_INT_TYPE 0x00000007 1483 #define GPIO_PIN34_INT_TYPE_M ((GPIO_PIN34_INT_TYPE_V)<<(GPIO_PIN34_INT_TYPE_S)) 1484 #define GPIO_PIN34_INT_TYPE_V 0x7 1485 #define GPIO_PIN34_INT_TYPE_S 7 1486 /* GPIO_PIN34_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ 1487 /*description: if set to 0: normal output if set to 1: open drain*/ 1488 #define GPIO_PIN34_PAD_DRIVER (BIT(2)) 1489 #define GPIO_PIN34_PAD_DRIVER_M (BIT(2)) 1490 #define GPIO_PIN34_PAD_DRIVER_V 0x1 1491 #define GPIO_PIN34_PAD_DRIVER_S 2 1492 1493 #define GPIO_PIN35_REG (DR_REG_GPIO_BASE + 0x0114) 1494 /* GPIO_PIN35_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ 1495 /*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt 1496 enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ 1497 #define GPIO_PIN35_INT_ENA 0x0000001F 1498 #define GPIO_PIN35_INT_ENA_M ((GPIO_PIN35_INT_ENA_V)<<(GPIO_PIN35_INT_ENA_S)) 1499 #define GPIO_PIN35_INT_ENA_V 0x1F 1500 #define GPIO_PIN35_INT_ENA_S 13 1501 /* GPIO_PIN35_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ 1502 /*description: NA*/ 1503 #define GPIO_PIN35_CONFIG 0x00000003 1504 #define GPIO_PIN35_CONFIG_M ((GPIO_PIN35_CONFIG_V)<<(GPIO_PIN35_CONFIG_S)) 1505 #define GPIO_PIN35_CONFIG_V 0x3 1506 #define GPIO_PIN35_CONFIG_S 11 1507 /* GPIO_PIN35_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ 1508 /*description: GPIO wake up enable only available in light sleep*/ 1509 #define GPIO_PIN35_WAKEUP_ENABLE (BIT(10)) 1510 #define GPIO_PIN35_WAKEUP_ENABLE_M (BIT(10)) 1511 #define GPIO_PIN35_WAKEUP_ENABLE_V 0x1 1512 #define GPIO_PIN35_WAKEUP_ENABLE_S 10 1513 /* GPIO_PIN35_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ 1514 /*description: if set to 0: GPIO interrupt disable if set to 1: rising edge 1515 trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ 1516 #define GPIO_PIN35_INT_TYPE 0x00000007 1517 #define GPIO_PIN35_INT_TYPE_M ((GPIO_PIN35_INT_TYPE_V)<<(GPIO_PIN35_INT_TYPE_S)) 1518 #define GPIO_PIN35_INT_TYPE_V 0x7 1519 #define GPIO_PIN35_INT_TYPE_S 7 1520 /* GPIO_PIN35_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ 1521 /*description: if set to 0: normal output if set to 1: open drain*/ 1522 #define GPIO_PIN35_PAD_DRIVER (BIT(2)) 1523 #define GPIO_PIN35_PAD_DRIVER_M (BIT(2)) 1524 #define GPIO_PIN35_PAD_DRIVER_V 0x1 1525 #define GPIO_PIN35_PAD_DRIVER_S 2 1526 1527 #define GPIO_PIN36_REG (DR_REG_GPIO_BASE + 0x0118) 1528 /* GPIO_PIN36_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ 1529 /*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt 1530 enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ 1531 #define GPIO_PIN36_INT_ENA 0x0000001F 1532 #define GPIO_PIN36_INT_ENA_M ((GPIO_PIN36_INT_ENA_V)<<(GPIO_PIN36_INT_ENA_S)) 1533 #define GPIO_PIN36_INT_ENA_V 0x1F 1534 #define GPIO_PIN36_INT_ENA_S 13 1535 /* GPIO_PIN36_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ 1536 /*description: NA*/ 1537 #define GPIO_PIN36_CONFIG 0x00000003 1538 #define GPIO_PIN36_CONFIG_M ((GPIO_PIN36_CONFIG_V)<<(GPIO_PIN36_CONFIG_S)) 1539 #define GPIO_PIN36_CONFIG_V 0x3 1540 #define GPIO_PIN36_CONFIG_S 11 1541 /* GPIO_PIN36_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ 1542 /*description: GPIO wake up enable only available in light sleep*/ 1543 #define GPIO_PIN36_WAKEUP_ENABLE (BIT(10)) 1544 #define GPIO_PIN36_WAKEUP_ENABLE_M (BIT(10)) 1545 #define GPIO_PIN36_WAKEUP_ENABLE_V 0x1 1546 #define GPIO_PIN36_WAKEUP_ENABLE_S 10 1547 /* GPIO_PIN36_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ 1548 /*description: if set to 0: GPIO interrupt disable if set to 1: rising edge 1549 trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ 1550 #define GPIO_PIN36_INT_TYPE 0x00000007 1551 #define GPIO_PIN36_INT_TYPE_M ((GPIO_PIN36_INT_TYPE_V)<<(GPIO_PIN36_INT_TYPE_S)) 1552 #define GPIO_PIN36_INT_TYPE_V 0x7 1553 #define GPIO_PIN36_INT_TYPE_S 7 1554 /* GPIO_PIN36_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ 1555 /*description: if set to 0: normal output if set to 1: open drain*/ 1556 #define GPIO_PIN36_PAD_DRIVER (BIT(2)) 1557 #define GPIO_PIN36_PAD_DRIVER_M (BIT(2)) 1558 #define GPIO_PIN36_PAD_DRIVER_V 0x1 1559 #define GPIO_PIN36_PAD_DRIVER_S 2 1560 1561 #define GPIO_PIN37_REG (DR_REG_GPIO_BASE + 0x011c) 1562 /* GPIO_PIN37_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ 1563 /*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt 1564 enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ 1565 #define GPIO_PIN37_INT_ENA 0x0000001F 1566 #define GPIO_PIN37_INT_ENA_M ((GPIO_PIN37_INT_ENA_V)<<(GPIO_PIN37_INT_ENA_S)) 1567 #define GPIO_PIN37_INT_ENA_V 0x1F 1568 #define GPIO_PIN37_INT_ENA_S 13 1569 /* GPIO_PIN37_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ 1570 /*description: NA*/ 1571 #define GPIO_PIN37_CONFIG 0x00000003 1572 #define GPIO_PIN37_CONFIG_M ((GPIO_PIN37_CONFIG_V)<<(GPIO_PIN37_CONFIG_S)) 1573 #define GPIO_PIN37_CONFIG_V 0x3 1574 #define GPIO_PIN37_CONFIG_S 11 1575 /* GPIO_PIN37_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ 1576 /*description: GPIO wake up enable only available in light sleep*/ 1577 #define GPIO_PIN37_WAKEUP_ENABLE (BIT(10)) 1578 #define GPIO_PIN37_WAKEUP_ENABLE_M (BIT(10)) 1579 #define GPIO_PIN37_WAKEUP_ENABLE_V 0x1 1580 #define GPIO_PIN37_WAKEUP_ENABLE_S 10 1581 /* GPIO_PIN37_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ 1582 /*description: if set to 0: GPIO interrupt disable if set to 1: rising edge 1583 trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ 1584 #define GPIO_PIN37_INT_TYPE 0x00000007 1585 #define GPIO_PIN37_INT_TYPE_M ((GPIO_PIN37_INT_TYPE_V)<<(GPIO_PIN37_INT_TYPE_S)) 1586 #define GPIO_PIN37_INT_TYPE_V 0x7 1587 #define GPIO_PIN37_INT_TYPE_S 7 1588 /* GPIO_PIN37_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ 1589 /*description: if set to 0: normal output if set to 1: open drain*/ 1590 #define GPIO_PIN37_PAD_DRIVER (BIT(2)) 1591 #define GPIO_PIN37_PAD_DRIVER_M (BIT(2)) 1592 #define GPIO_PIN37_PAD_DRIVER_V 0x1 1593 #define GPIO_PIN37_PAD_DRIVER_S 2 1594 1595 #define GPIO_PIN38_REG (DR_REG_GPIO_BASE + 0x0120) 1596 /* GPIO_PIN38_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ 1597 /*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt 1598 enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ 1599 #define GPIO_PIN38_INT_ENA 0x0000001F 1600 #define GPIO_PIN38_INT_ENA_M ((GPIO_PIN38_INT_ENA_V)<<(GPIO_PIN38_INT_ENA_S)) 1601 #define GPIO_PIN38_INT_ENA_V 0x1F 1602 #define GPIO_PIN38_INT_ENA_S 13 1603 /* GPIO_PIN38_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ 1604 /*description: NA*/ 1605 #define GPIO_PIN38_CONFIG 0x00000003 1606 #define GPIO_PIN38_CONFIG_M ((GPIO_PIN38_CONFIG_V)<<(GPIO_PIN38_CONFIG_S)) 1607 #define GPIO_PIN38_CONFIG_V 0x3 1608 #define GPIO_PIN38_CONFIG_S 11 1609 /* GPIO_PIN38_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ 1610 /*description: GPIO wake up enable only available in light sleep*/ 1611 #define GPIO_PIN38_WAKEUP_ENABLE (BIT(10)) 1612 #define GPIO_PIN38_WAKEUP_ENABLE_M (BIT(10)) 1613 #define GPIO_PIN38_WAKEUP_ENABLE_V 0x1 1614 #define GPIO_PIN38_WAKEUP_ENABLE_S 10 1615 /* GPIO_PIN38_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ 1616 /*description: if set to 0: GPIO interrupt disable if set to 1: rising edge 1617 trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ 1618 #define GPIO_PIN38_INT_TYPE 0x00000007 1619 #define GPIO_PIN38_INT_TYPE_M ((GPIO_PIN38_INT_TYPE_V)<<(GPIO_PIN38_INT_TYPE_S)) 1620 #define GPIO_PIN38_INT_TYPE_V 0x7 1621 #define GPIO_PIN38_INT_TYPE_S 7 1622 /* GPIO_PIN38_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ 1623 /*description: if set to 0: normal output if set to 1: open drain*/ 1624 #define GPIO_PIN38_PAD_DRIVER (BIT(2)) 1625 #define GPIO_PIN38_PAD_DRIVER_M (BIT(2)) 1626 #define GPIO_PIN38_PAD_DRIVER_V 0x1 1627 #define GPIO_PIN38_PAD_DRIVER_S 2 1628 1629 #define GPIO_PIN39_REG (DR_REG_GPIO_BASE + 0x0124) 1630 /* GPIO_PIN39_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ 1631 /*description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt 1632 enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ 1633 #define GPIO_PIN39_INT_ENA 0x0000001F 1634 #define GPIO_PIN39_INT_ENA_M ((GPIO_PIN39_INT_ENA_V)<<(GPIO_PIN39_INT_ENA_S)) 1635 #define GPIO_PIN39_INT_ENA_V 0x1F 1636 #define GPIO_PIN39_INT_ENA_S 13 1637 /* GPIO_PIN39_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ 1638 /*description: NA*/ 1639 #define GPIO_PIN39_CONFIG 0x00000003 1640 #define GPIO_PIN39_CONFIG_M ((GPIO_PIN39_CONFIG_V)<<(GPIO_PIN39_CONFIG_S)) 1641 #define GPIO_PIN39_CONFIG_V 0x3 1642 #define GPIO_PIN39_CONFIG_S 11 1643 /* GPIO_PIN39_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ 1644 /*description: GPIO wake up enable only available in light sleep*/ 1645 #define GPIO_PIN39_WAKEUP_ENABLE (BIT(10)) 1646 #define GPIO_PIN39_WAKEUP_ENABLE_M (BIT(10)) 1647 #define GPIO_PIN39_WAKEUP_ENABLE_V 0x1 1648 #define GPIO_PIN39_WAKEUP_ENABLE_S 10 1649 /* GPIO_PIN39_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ 1650 /*description: if set to 0: GPIO interrupt disable if set to 1: rising edge 1651 trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ 1652 #define GPIO_PIN39_INT_TYPE 0x00000007 1653 #define GPIO_PIN39_INT_TYPE_M ((GPIO_PIN39_INT_TYPE_V)<<(GPIO_PIN39_INT_TYPE_S)) 1654 #define GPIO_PIN39_INT_TYPE_V 0x7 1655 #define GPIO_PIN39_INT_TYPE_S 7 1656 /* GPIO_PIN39_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ 1657 /*description: if set to 0: normal output if set to 1: open drain*/ 1658 #define GPIO_PIN39_PAD_DRIVER (BIT(2)) 1659 #define GPIO_PIN39_PAD_DRIVER_M (BIT(2)) 1660 #define GPIO_PIN39_PAD_DRIVER_V 0x1 1661 #define GPIO_PIN39_PAD_DRIVER_S 2 1662 1663 #define GPIO_cali_conf_REG (DR_REG_GPIO_BASE + 0x0128) 1664 /* GPIO_CALI_START : R/W ;bitpos:[31] ;default: x ; */ 1665 /*description: */ 1666 #define GPIO_CALI_START (BIT(31)) 1667 #define GPIO_CALI_START_M (BIT(31)) 1668 #define GPIO_CALI_START_V 0x1 1669 #define GPIO_CALI_START_S 31 1670 /* GPIO_CALI_RTC_MAX : R/W ;bitpos:[9:0] ;default: x ; */ 1671 /*description: */ 1672 #define GPIO_CALI_RTC_MAX 0x000003FF 1673 #define GPIO_CALI_RTC_MAX_M ((GPIO_CALI_RTC_MAX_V)<<(GPIO_CALI_RTC_MAX_S)) 1674 #define GPIO_CALI_RTC_MAX_V 0x3FF 1675 #define GPIO_CALI_RTC_MAX_S 0 1676 1677 #define GPIO_cali_data_REG (DR_REG_GPIO_BASE + 0x012c) 1678 /* GPIO_CALI_RDY_SYNC2 : RO ;bitpos:[31] ;default: ; */ 1679 /*description: */ 1680 #define GPIO_CALI_RDY_SYNC2 (BIT(31)) 1681 #define GPIO_CALI_RDY_SYNC2_M (BIT(31)) 1682 #define GPIO_CALI_RDY_SYNC2_V 0x1 1683 #define GPIO_CALI_RDY_SYNC2_S 31 1684 /* GPIO_CALI_RDY_REAL : RO ;bitpos:[30] ;default: ; */ 1685 /*description: */ 1686 #define GPIO_CALI_RDY_REAL (BIT(30)) 1687 #define GPIO_CALI_RDY_REAL_M (BIT(30)) 1688 #define GPIO_CALI_RDY_REAL_V 0x1 1689 #define GPIO_CALI_RDY_REAL_S 30 1690 /* GPIO_CALI_VALUE_SYNC2 : RO ;bitpos:[19:0] ;default: ; */ 1691 /*description: */ 1692 #define GPIO_CALI_VALUE_SYNC2 0x000FFFFF 1693 #define GPIO_CALI_VALUE_SYNC2_M ((GPIO_CALI_VALUE_SYNC2_V)<<(GPIO_CALI_VALUE_SYNC2_S)) 1694 #define GPIO_CALI_VALUE_SYNC2_V 0xFFFFF 1695 #define GPIO_CALI_VALUE_SYNC2_S 0 1696 1697 #define GPIO_FUNC0_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0130) 1698 /* GPIO_SIG0_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 1699 /*description: if the slow signal bypass the io matrix or not if you want setting 1700 the value to 1*/ 1701 #define GPIO_SIG0_IN_SEL (BIT(7)) 1702 #define GPIO_SIG0_IN_SEL_M (BIT(7)) 1703 #define GPIO_SIG0_IN_SEL_V 0x1 1704 #define GPIO_SIG0_IN_SEL_S 7 1705 /* GPIO_FUNC0_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 1706 /*description: revert the value of the input if you want to revert please set the value to 1*/ 1707 #define GPIO_FUNC0_IN_INV_SEL (BIT(6)) 1708 #define GPIO_FUNC0_IN_INV_SEL_M (BIT(6)) 1709 #define GPIO_FUNC0_IN_INV_SEL_V 0x1 1710 #define GPIO_FUNC0_IN_INV_SEL_S 6 1711 /* GPIO_FUNC0_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 1712 /*description: select one of the 256 inputs*/ 1713 #define GPIO_FUNC0_IN_SEL 0x0000003F 1714 #define GPIO_FUNC0_IN_SEL_M ((GPIO_FUNC0_IN_SEL_V)<<(GPIO_FUNC0_IN_SEL_S)) 1715 #define GPIO_FUNC0_IN_SEL_V 0x3F 1716 #define GPIO_FUNC0_IN_SEL_S 0 1717 1718 #define GPIO_FUNC1_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0134) 1719 /* GPIO_SIG1_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 1720 /*description: if the slow signal bypass the io matrix or not if you want setting 1721 the value to 1*/ 1722 #define GPIO_SIG1_IN_SEL (BIT(7)) 1723 #define GPIO_SIG1_IN_SEL_M (BIT(7)) 1724 #define GPIO_SIG1_IN_SEL_V 0x1 1725 #define GPIO_SIG1_IN_SEL_S 7 1726 /* GPIO_FUNC1_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 1727 /*description: revert the value of the input if you want to revert please set the value to 1*/ 1728 #define GPIO_FUNC1_IN_INV_SEL (BIT(6)) 1729 #define GPIO_FUNC1_IN_INV_SEL_M (BIT(6)) 1730 #define GPIO_FUNC1_IN_INV_SEL_V 0x1 1731 #define GPIO_FUNC1_IN_INV_SEL_S 6 1732 /* GPIO_FUNC1_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 1733 /*description: select one of the 256 inputs*/ 1734 #define GPIO_FUNC1_IN_SEL 0x0000003F 1735 #define GPIO_FUNC1_IN_SEL_M ((GPIO_FUNC1_IN_SEL_V)<<(GPIO_FUNC1_IN_SEL_S)) 1736 #define GPIO_FUNC1_IN_SEL_V 0x3F 1737 #define GPIO_FUNC1_IN_SEL_S 0 1738 1739 #define GPIO_FUNC2_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0138) 1740 /* GPIO_SIG2_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 1741 /*description: if the slow signal bypass the io matrix or not if you want setting 1742 the value to 1*/ 1743 #define GPIO_SIG2_IN_SEL (BIT(7)) 1744 #define GPIO_SIG2_IN_SEL_M (BIT(7)) 1745 #define GPIO_SIG2_IN_SEL_V 0x1 1746 #define GPIO_SIG2_IN_SEL_S 7 1747 /* GPIO_FUNC2_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 1748 /*description: revert the value of the input if you want to revert please set the value to 1*/ 1749 #define GPIO_FUNC2_IN_INV_SEL (BIT(6)) 1750 #define GPIO_FUNC2_IN_INV_SEL_M (BIT(6)) 1751 #define GPIO_FUNC2_IN_INV_SEL_V 0x1 1752 #define GPIO_FUNC2_IN_INV_SEL_S 6 1753 /* GPIO_FUNC2_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 1754 /*description: select one of the 256 inputs*/ 1755 #define GPIO_FUNC2_IN_SEL 0x0000003F 1756 #define GPIO_FUNC2_IN_SEL_M ((GPIO_FUNC2_IN_SEL_V)<<(GPIO_FUNC2_IN_SEL_S)) 1757 #define GPIO_FUNC2_IN_SEL_V 0x3F 1758 #define GPIO_FUNC2_IN_SEL_S 0 1759 1760 #define GPIO_FUNC3_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x013c) 1761 /* GPIO_SIG3_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 1762 /*description: if the slow signal bypass the io matrix or not if you want setting 1763 the value to 1*/ 1764 #define GPIO_SIG3_IN_SEL (BIT(7)) 1765 #define GPIO_SIG3_IN_SEL_M (BIT(7)) 1766 #define GPIO_SIG3_IN_SEL_V 0x1 1767 #define GPIO_SIG3_IN_SEL_S 7 1768 /* GPIO_FUNC3_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 1769 /*description: revert the value of the input if you want to revert please set the value to 1*/ 1770 #define GPIO_FUNC3_IN_INV_SEL (BIT(6)) 1771 #define GPIO_FUNC3_IN_INV_SEL_M (BIT(6)) 1772 #define GPIO_FUNC3_IN_INV_SEL_V 0x1 1773 #define GPIO_FUNC3_IN_INV_SEL_S 6 1774 /* GPIO_FUNC3_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 1775 /*description: select one of the 256 inputs*/ 1776 #define GPIO_FUNC3_IN_SEL 0x0000003F 1777 #define GPIO_FUNC3_IN_SEL_M ((GPIO_FUNC3_IN_SEL_V)<<(GPIO_FUNC3_IN_SEL_S)) 1778 #define GPIO_FUNC3_IN_SEL_V 0x3F 1779 #define GPIO_FUNC3_IN_SEL_S 0 1780 1781 #define GPIO_FUNC4_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0140) 1782 /* GPIO_SIG4_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 1783 /*description: if the slow signal bypass the io matrix or not if you want setting 1784 the value to 1*/ 1785 #define GPIO_SIG4_IN_SEL (BIT(7)) 1786 #define GPIO_SIG4_IN_SEL_M (BIT(7)) 1787 #define GPIO_SIG4_IN_SEL_V 0x1 1788 #define GPIO_SIG4_IN_SEL_S 7 1789 /* GPIO_FUNC4_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 1790 /*description: revert the value of the input if you want to revert please set the value to 1*/ 1791 #define GPIO_FUNC4_IN_INV_SEL (BIT(6)) 1792 #define GPIO_FUNC4_IN_INV_SEL_M (BIT(6)) 1793 #define GPIO_FUNC4_IN_INV_SEL_V 0x1 1794 #define GPIO_FUNC4_IN_INV_SEL_S 6 1795 /* GPIO_FUNC4_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 1796 /*description: select one of the 256 inputs*/ 1797 #define GPIO_FUNC4_IN_SEL 0x0000003F 1798 #define GPIO_FUNC4_IN_SEL_M ((GPIO_FUNC4_IN_SEL_V)<<(GPIO_FUNC4_IN_SEL_S)) 1799 #define GPIO_FUNC4_IN_SEL_V 0x3F 1800 #define GPIO_FUNC4_IN_SEL_S 0 1801 1802 #define GPIO_FUNC5_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0144) 1803 /* GPIO_SIG5_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 1804 /*description: if the slow signal bypass the io matrix or not if you want setting 1805 the value to 1*/ 1806 #define GPIO_SIG5_IN_SEL (BIT(7)) 1807 #define GPIO_SIG5_IN_SEL_M (BIT(7)) 1808 #define GPIO_SIG5_IN_SEL_V 0x1 1809 #define GPIO_SIG5_IN_SEL_S 7 1810 /* GPIO_FUNC5_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 1811 /*description: revert the value of the input if you want to revert please set the value to 1*/ 1812 #define GPIO_FUNC5_IN_INV_SEL (BIT(6)) 1813 #define GPIO_FUNC5_IN_INV_SEL_M (BIT(6)) 1814 #define GPIO_FUNC5_IN_INV_SEL_V 0x1 1815 #define GPIO_FUNC5_IN_INV_SEL_S 6 1816 /* GPIO_FUNC5_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 1817 /*description: select one of the 256 inputs*/ 1818 #define GPIO_FUNC5_IN_SEL 0x0000003F 1819 #define GPIO_FUNC5_IN_SEL_M ((GPIO_FUNC5_IN_SEL_V)<<(GPIO_FUNC5_IN_SEL_S)) 1820 #define GPIO_FUNC5_IN_SEL_V 0x3F 1821 #define GPIO_FUNC5_IN_SEL_S 0 1822 1823 #define GPIO_FUNC6_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0148) 1824 /* GPIO_SIG6_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 1825 /*description: if the slow signal bypass the io matrix or not if you want setting 1826 the value to 1*/ 1827 #define GPIO_SIG6_IN_SEL (BIT(7)) 1828 #define GPIO_SIG6_IN_SEL_M (BIT(7)) 1829 #define GPIO_SIG6_IN_SEL_V 0x1 1830 #define GPIO_SIG6_IN_SEL_S 7 1831 /* GPIO_FUNC6_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 1832 /*description: revert the value of the input if you want to revert please set the value to 1*/ 1833 #define GPIO_FUNC6_IN_INV_SEL (BIT(6)) 1834 #define GPIO_FUNC6_IN_INV_SEL_M (BIT(6)) 1835 #define GPIO_FUNC6_IN_INV_SEL_V 0x1 1836 #define GPIO_FUNC6_IN_INV_SEL_S 6 1837 /* GPIO_FUNC6_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 1838 /*description: select one of the 256 inputs*/ 1839 #define GPIO_FUNC6_IN_SEL 0x0000003F 1840 #define GPIO_FUNC6_IN_SEL_M ((GPIO_FUNC6_IN_SEL_V)<<(GPIO_FUNC6_IN_SEL_S)) 1841 #define GPIO_FUNC6_IN_SEL_V 0x3F 1842 #define GPIO_FUNC6_IN_SEL_S 0 1843 1844 #define GPIO_FUNC7_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x014c) 1845 /* GPIO_SIG7_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 1846 /*description: if the slow signal bypass the io matrix or not if you want setting 1847 the value to 1*/ 1848 #define GPIO_SIG7_IN_SEL (BIT(7)) 1849 #define GPIO_SIG7_IN_SEL_M (BIT(7)) 1850 #define GPIO_SIG7_IN_SEL_V 0x1 1851 #define GPIO_SIG7_IN_SEL_S 7 1852 /* GPIO_FUNC7_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 1853 /*description: revert the value of the input if you want to revert please set the value to 1*/ 1854 #define GPIO_FUNC7_IN_INV_SEL (BIT(6)) 1855 #define GPIO_FUNC7_IN_INV_SEL_M (BIT(6)) 1856 #define GPIO_FUNC7_IN_INV_SEL_V 0x1 1857 #define GPIO_FUNC7_IN_INV_SEL_S 6 1858 /* GPIO_FUNC7_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 1859 /*description: select one of the 256 inputs*/ 1860 #define GPIO_FUNC7_IN_SEL 0x0000003F 1861 #define GPIO_FUNC7_IN_SEL_M ((GPIO_FUNC7_IN_SEL_V)<<(GPIO_FUNC7_IN_SEL_S)) 1862 #define GPIO_FUNC7_IN_SEL_V 0x3F 1863 #define GPIO_FUNC7_IN_SEL_S 0 1864 1865 #define GPIO_FUNC8_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0150) 1866 /* GPIO_SIG8_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 1867 /*description: if the slow signal bypass the io matrix or not if you want setting 1868 the value to 1*/ 1869 #define GPIO_SIG8_IN_SEL (BIT(7)) 1870 #define GPIO_SIG8_IN_SEL_M (BIT(7)) 1871 #define GPIO_SIG8_IN_SEL_V 0x1 1872 #define GPIO_SIG8_IN_SEL_S 7 1873 /* GPIO_FUNC8_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 1874 /*description: revert the value of the input if you want to revert please set the value to 1*/ 1875 #define GPIO_FUNC8_IN_INV_SEL (BIT(6)) 1876 #define GPIO_FUNC8_IN_INV_SEL_M (BIT(6)) 1877 #define GPIO_FUNC8_IN_INV_SEL_V 0x1 1878 #define GPIO_FUNC8_IN_INV_SEL_S 6 1879 /* GPIO_FUNC8_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 1880 /*description: select one of the 256 inputs*/ 1881 #define GPIO_FUNC8_IN_SEL 0x0000003F 1882 #define GPIO_FUNC8_IN_SEL_M ((GPIO_FUNC8_IN_SEL_V)<<(GPIO_FUNC8_IN_SEL_S)) 1883 #define GPIO_FUNC8_IN_SEL_V 0x3F 1884 #define GPIO_FUNC8_IN_SEL_S 0 1885 1886 #define GPIO_FUNC9_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0154) 1887 /* GPIO_SIG9_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 1888 /*description: if the slow signal bypass the io matrix or not if you want setting 1889 the value to 1*/ 1890 #define GPIO_SIG9_IN_SEL (BIT(7)) 1891 #define GPIO_SIG9_IN_SEL_M (BIT(7)) 1892 #define GPIO_SIG9_IN_SEL_V 0x1 1893 #define GPIO_SIG9_IN_SEL_S 7 1894 /* GPIO_FUNC9_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 1895 /*description: revert the value of the input if you want to revert please set the value to 1*/ 1896 #define GPIO_FUNC9_IN_INV_SEL (BIT(6)) 1897 #define GPIO_FUNC9_IN_INV_SEL_M (BIT(6)) 1898 #define GPIO_FUNC9_IN_INV_SEL_V 0x1 1899 #define GPIO_FUNC9_IN_INV_SEL_S 6 1900 /* GPIO_FUNC9_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 1901 /*description: select one of the 256 inputs*/ 1902 #define GPIO_FUNC9_IN_SEL 0x0000003F 1903 #define GPIO_FUNC9_IN_SEL_M ((GPIO_FUNC9_IN_SEL_V)<<(GPIO_FUNC9_IN_SEL_S)) 1904 #define GPIO_FUNC9_IN_SEL_V 0x3F 1905 #define GPIO_FUNC9_IN_SEL_S 0 1906 1907 #define GPIO_FUNC10_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0158) 1908 /* GPIO_SIG10_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 1909 /*description: if the slow signal bypass the io matrix or not if you want setting 1910 the value to 1*/ 1911 #define GPIO_SIG10_IN_SEL (BIT(7)) 1912 #define GPIO_SIG10_IN_SEL_M (BIT(7)) 1913 #define GPIO_SIG10_IN_SEL_V 0x1 1914 #define GPIO_SIG10_IN_SEL_S 7 1915 /* GPIO_FUNC10_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 1916 /*description: revert the value of the input if you want to revert please set the value to 1*/ 1917 #define GPIO_FUNC10_IN_INV_SEL (BIT(6)) 1918 #define GPIO_FUNC10_IN_INV_SEL_M (BIT(6)) 1919 #define GPIO_FUNC10_IN_INV_SEL_V 0x1 1920 #define GPIO_FUNC10_IN_INV_SEL_S 6 1921 /* GPIO_FUNC10_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 1922 /*description: select one of the 256 inputs*/ 1923 #define GPIO_FUNC10_IN_SEL 0x0000003F 1924 #define GPIO_FUNC10_IN_SEL_M ((GPIO_FUNC10_IN_SEL_V)<<(GPIO_FUNC10_IN_SEL_S)) 1925 #define GPIO_FUNC10_IN_SEL_V 0x3F 1926 #define GPIO_FUNC10_IN_SEL_S 0 1927 1928 #define GPIO_FUNC11_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x015c) 1929 /* GPIO_SIG11_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 1930 /*description: if the slow signal bypass the io matrix or not if you want setting 1931 the value to 1*/ 1932 #define GPIO_SIG11_IN_SEL (BIT(7)) 1933 #define GPIO_SIG11_IN_SEL_M (BIT(7)) 1934 #define GPIO_SIG11_IN_SEL_V 0x1 1935 #define GPIO_SIG11_IN_SEL_S 7 1936 /* GPIO_FUNC11_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 1937 /*description: revert the value of the input if you want to revert please set the value to 1*/ 1938 #define GPIO_FUNC11_IN_INV_SEL (BIT(6)) 1939 #define GPIO_FUNC11_IN_INV_SEL_M (BIT(6)) 1940 #define GPIO_FUNC11_IN_INV_SEL_V 0x1 1941 #define GPIO_FUNC11_IN_INV_SEL_S 6 1942 /* GPIO_FUNC11_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 1943 /*description: select one of the 256 inputs*/ 1944 #define GPIO_FUNC11_IN_SEL 0x0000003F 1945 #define GPIO_FUNC11_IN_SEL_M ((GPIO_FUNC11_IN_SEL_V)<<(GPIO_FUNC11_IN_SEL_S)) 1946 #define GPIO_FUNC11_IN_SEL_V 0x3F 1947 #define GPIO_FUNC11_IN_SEL_S 0 1948 1949 #define GPIO_FUNC12_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0160) 1950 /* GPIO_SIG12_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 1951 /*description: if the slow signal bypass the io matrix or not if you want setting 1952 the value to 1*/ 1953 #define GPIO_SIG12_IN_SEL (BIT(7)) 1954 #define GPIO_SIG12_IN_SEL_M (BIT(7)) 1955 #define GPIO_SIG12_IN_SEL_V 0x1 1956 #define GPIO_SIG12_IN_SEL_S 7 1957 /* GPIO_FUNC12_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 1958 /*description: revert the value of the input if you want to revert please set the value to 1*/ 1959 #define GPIO_FUNC12_IN_INV_SEL (BIT(6)) 1960 #define GPIO_FUNC12_IN_INV_SEL_M (BIT(6)) 1961 #define GPIO_FUNC12_IN_INV_SEL_V 0x1 1962 #define GPIO_FUNC12_IN_INV_SEL_S 6 1963 /* GPIO_FUNC12_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 1964 /*description: select one of the 256 inputs*/ 1965 #define GPIO_FUNC12_IN_SEL 0x0000003F 1966 #define GPIO_FUNC12_IN_SEL_M ((GPIO_FUNC12_IN_SEL_V)<<(GPIO_FUNC12_IN_SEL_S)) 1967 #define GPIO_FUNC12_IN_SEL_V 0x3F 1968 #define GPIO_FUNC12_IN_SEL_S 0 1969 1970 #define GPIO_FUNC13_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0164) 1971 /* GPIO_SIG13_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 1972 /*description: if the slow signal bypass the io matrix or not if you want setting 1973 the value to 1*/ 1974 #define GPIO_SIG13_IN_SEL (BIT(7)) 1975 #define GPIO_SIG13_IN_SEL_M (BIT(7)) 1976 #define GPIO_SIG13_IN_SEL_V 0x1 1977 #define GPIO_SIG13_IN_SEL_S 7 1978 /* GPIO_FUNC13_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 1979 /*description: revert the value of the input if you want to revert please set the value to 1*/ 1980 #define GPIO_FUNC13_IN_INV_SEL (BIT(6)) 1981 #define GPIO_FUNC13_IN_INV_SEL_M (BIT(6)) 1982 #define GPIO_FUNC13_IN_INV_SEL_V 0x1 1983 #define GPIO_FUNC13_IN_INV_SEL_S 6 1984 /* GPIO_FUNC13_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 1985 /*description: select one of the 256 inputs*/ 1986 #define GPIO_FUNC13_IN_SEL 0x0000003F 1987 #define GPIO_FUNC13_IN_SEL_M ((GPIO_FUNC13_IN_SEL_V)<<(GPIO_FUNC13_IN_SEL_S)) 1988 #define GPIO_FUNC13_IN_SEL_V 0x3F 1989 #define GPIO_FUNC13_IN_SEL_S 0 1990 1991 #define GPIO_FUNC14_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0168) 1992 /* GPIO_SIG14_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 1993 /*description: if the slow signal bypass the io matrix or not if you want setting 1994 the value to 1*/ 1995 #define GPIO_SIG14_IN_SEL (BIT(7)) 1996 #define GPIO_SIG14_IN_SEL_M (BIT(7)) 1997 #define GPIO_SIG14_IN_SEL_V 0x1 1998 #define GPIO_SIG14_IN_SEL_S 7 1999 /* GPIO_FUNC14_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 2000 /*description: revert the value of the input if you want to revert please set the value to 1*/ 2001 #define GPIO_FUNC14_IN_INV_SEL (BIT(6)) 2002 #define GPIO_FUNC14_IN_INV_SEL_M (BIT(6)) 2003 #define GPIO_FUNC14_IN_INV_SEL_V 0x1 2004 #define GPIO_FUNC14_IN_INV_SEL_S 6 2005 /* GPIO_FUNC14_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 2006 /*description: select one of the 256 inputs*/ 2007 #define GPIO_FUNC14_IN_SEL 0x0000003F 2008 #define GPIO_FUNC14_IN_SEL_M ((GPIO_FUNC14_IN_SEL_V)<<(GPIO_FUNC14_IN_SEL_S)) 2009 #define GPIO_FUNC14_IN_SEL_V 0x3F 2010 #define GPIO_FUNC14_IN_SEL_S 0 2011 2012 #define GPIO_FUNC15_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x016c) 2013 /* GPIO_SIG15_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 2014 /*description: if the slow signal bypass the io matrix or not if you want setting 2015 the value to 1*/ 2016 #define GPIO_SIG15_IN_SEL (BIT(7)) 2017 #define GPIO_SIG15_IN_SEL_M (BIT(7)) 2018 #define GPIO_SIG15_IN_SEL_V 0x1 2019 #define GPIO_SIG15_IN_SEL_S 7 2020 /* GPIO_FUNC15_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 2021 /*description: revert the value of the input if you want to revert please set the value to 1*/ 2022 #define GPIO_FUNC15_IN_INV_SEL (BIT(6)) 2023 #define GPIO_FUNC15_IN_INV_SEL_M (BIT(6)) 2024 #define GPIO_FUNC15_IN_INV_SEL_V 0x1 2025 #define GPIO_FUNC15_IN_INV_SEL_S 6 2026 /* GPIO_FUNC15_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 2027 /*description: select one of the 256 inputs*/ 2028 #define GPIO_FUNC15_IN_SEL 0x0000003F 2029 #define GPIO_FUNC15_IN_SEL_M ((GPIO_FUNC15_IN_SEL_V)<<(GPIO_FUNC15_IN_SEL_S)) 2030 #define GPIO_FUNC15_IN_SEL_V 0x3F 2031 #define GPIO_FUNC15_IN_SEL_S 0 2032 2033 #define GPIO_FUNC16_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0170) 2034 /* GPIO_SIG16_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 2035 /*description: if the slow signal bypass the io matrix or not if you want setting 2036 the value to 1*/ 2037 #define GPIO_SIG16_IN_SEL (BIT(7)) 2038 #define GPIO_SIG16_IN_SEL_M (BIT(7)) 2039 #define GPIO_SIG16_IN_SEL_V 0x1 2040 #define GPIO_SIG16_IN_SEL_S 7 2041 /* GPIO_FUNC16_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 2042 /*description: revert the value of the input if you want to revert please set the value to 1*/ 2043 #define GPIO_FUNC16_IN_INV_SEL (BIT(6)) 2044 #define GPIO_FUNC16_IN_INV_SEL_M (BIT(6)) 2045 #define GPIO_FUNC16_IN_INV_SEL_V 0x1 2046 #define GPIO_FUNC16_IN_INV_SEL_S 6 2047 /* GPIO_FUNC16_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 2048 /*description: select one of the 256 inputs*/ 2049 #define GPIO_FUNC16_IN_SEL 0x0000003F 2050 #define GPIO_FUNC16_IN_SEL_M ((GPIO_FUNC16_IN_SEL_V)<<(GPIO_FUNC16_IN_SEL_S)) 2051 #define GPIO_FUNC16_IN_SEL_V 0x3F 2052 #define GPIO_FUNC16_IN_SEL_S 0 2053 2054 #define GPIO_FUNC17_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0174) 2055 /* GPIO_SIG17_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 2056 /*description: if the slow signal bypass the io matrix or not if you want setting 2057 the value to 1*/ 2058 #define GPIO_SIG17_IN_SEL (BIT(7)) 2059 #define GPIO_SIG17_IN_SEL_M (BIT(7)) 2060 #define GPIO_SIG17_IN_SEL_V 0x1 2061 #define GPIO_SIG17_IN_SEL_S 7 2062 /* GPIO_FUNC17_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 2063 /*description: revert the value of the input if you want to revert please set the value to 1*/ 2064 #define GPIO_FUNC17_IN_INV_SEL (BIT(6)) 2065 #define GPIO_FUNC17_IN_INV_SEL_M (BIT(6)) 2066 #define GPIO_FUNC17_IN_INV_SEL_V 0x1 2067 #define GPIO_FUNC17_IN_INV_SEL_S 6 2068 /* GPIO_FUNC17_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 2069 /*description: select one of the 256 inputs*/ 2070 #define GPIO_FUNC17_IN_SEL 0x0000003F 2071 #define GPIO_FUNC17_IN_SEL_M ((GPIO_FUNC17_IN_SEL_V)<<(GPIO_FUNC17_IN_SEL_S)) 2072 #define GPIO_FUNC17_IN_SEL_V 0x3F 2073 #define GPIO_FUNC17_IN_SEL_S 0 2074 2075 #define GPIO_FUNC18_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0178) 2076 /* GPIO_SIG18_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 2077 /*description: if the slow signal bypass the io matrix or not if you want setting 2078 the value to 1*/ 2079 #define GPIO_SIG18_IN_SEL (BIT(7)) 2080 #define GPIO_SIG18_IN_SEL_M (BIT(7)) 2081 #define GPIO_SIG18_IN_SEL_V 0x1 2082 #define GPIO_SIG18_IN_SEL_S 7 2083 /* GPIO_FUNC18_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 2084 /*description: revert the value of the input if you want to revert please set the value to 1*/ 2085 #define GPIO_FUNC18_IN_INV_SEL (BIT(6)) 2086 #define GPIO_FUNC18_IN_INV_SEL_M (BIT(6)) 2087 #define GPIO_FUNC18_IN_INV_SEL_V 0x1 2088 #define GPIO_FUNC18_IN_INV_SEL_S 6 2089 /* GPIO_FUNC18_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 2090 /*description: select one of the 256 inputs*/ 2091 #define GPIO_FUNC18_IN_SEL 0x0000003F 2092 #define GPIO_FUNC18_IN_SEL_M ((GPIO_FUNC18_IN_SEL_V)<<(GPIO_FUNC18_IN_SEL_S)) 2093 #define GPIO_FUNC18_IN_SEL_V 0x3F 2094 #define GPIO_FUNC18_IN_SEL_S 0 2095 2096 #define GPIO_FUNC19_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x017c) 2097 /* GPIO_SIG19_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 2098 /*description: if the slow signal bypass the io matrix or not if you want setting 2099 the value to 1*/ 2100 #define GPIO_SIG19_IN_SEL (BIT(7)) 2101 #define GPIO_SIG19_IN_SEL_M (BIT(7)) 2102 #define GPIO_SIG19_IN_SEL_V 0x1 2103 #define GPIO_SIG19_IN_SEL_S 7 2104 /* GPIO_FUNC19_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 2105 /*description: revert the value of the input if you want to revert please set the value to 1*/ 2106 #define GPIO_FUNC19_IN_INV_SEL (BIT(6)) 2107 #define GPIO_FUNC19_IN_INV_SEL_M (BIT(6)) 2108 #define GPIO_FUNC19_IN_INV_SEL_V 0x1 2109 #define GPIO_FUNC19_IN_INV_SEL_S 6 2110 /* GPIO_FUNC19_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 2111 /*description: select one of the 256 inputs*/ 2112 #define GPIO_FUNC19_IN_SEL 0x0000003F 2113 #define GPIO_FUNC19_IN_SEL_M ((GPIO_FUNC19_IN_SEL_V)<<(GPIO_FUNC19_IN_SEL_S)) 2114 #define GPIO_FUNC19_IN_SEL_V 0x3F 2115 #define GPIO_FUNC19_IN_SEL_S 0 2116 2117 #define GPIO_FUNC20_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0180) 2118 /* GPIO_SIG20_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 2119 /*description: if the slow signal bypass the io matrix or not if you want setting 2120 the value to 1*/ 2121 #define GPIO_SIG20_IN_SEL (BIT(7)) 2122 #define GPIO_SIG20_IN_SEL_M (BIT(7)) 2123 #define GPIO_SIG20_IN_SEL_V 0x1 2124 #define GPIO_SIG20_IN_SEL_S 7 2125 /* GPIO_FUNC20_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 2126 /*description: revert the value of the input if you want to revert please set the value to 1*/ 2127 #define GPIO_FUNC20_IN_INV_SEL (BIT(6)) 2128 #define GPIO_FUNC20_IN_INV_SEL_M (BIT(6)) 2129 #define GPIO_FUNC20_IN_INV_SEL_V 0x1 2130 #define GPIO_FUNC20_IN_INV_SEL_S 6 2131 /* GPIO_FUNC20_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 2132 /*description: select one of the 256 inputs*/ 2133 #define GPIO_FUNC20_IN_SEL 0x0000003F 2134 #define GPIO_FUNC20_IN_SEL_M ((GPIO_FUNC20_IN_SEL_V)<<(GPIO_FUNC20_IN_SEL_S)) 2135 #define GPIO_FUNC20_IN_SEL_V 0x3F 2136 #define GPIO_FUNC20_IN_SEL_S 0 2137 2138 #define GPIO_FUNC21_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0184) 2139 /* GPIO_SIG21_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 2140 /*description: if the slow signal bypass the io matrix or not if you want setting 2141 the value to 1*/ 2142 #define GPIO_SIG21_IN_SEL (BIT(7)) 2143 #define GPIO_SIG21_IN_SEL_M (BIT(7)) 2144 #define GPIO_SIG21_IN_SEL_V 0x1 2145 #define GPIO_SIG21_IN_SEL_S 7 2146 /* GPIO_FUNC21_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 2147 /*description: revert the value of the input if you want to revert please set the value to 1*/ 2148 #define GPIO_FUNC21_IN_INV_SEL (BIT(6)) 2149 #define GPIO_FUNC21_IN_INV_SEL_M (BIT(6)) 2150 #define GPIO_FUNC21_IN_INV_SEL_V 0x1 2151 #define GPIO_FUNC21_IN_INV_SEL_S 6 2152 /* GPIO_FUNC21_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 2153 /*description: select one of the 256 inputs*/ 2154 #define GPIO_FUNC21_IN_SEL 0x0000003F 2155 #define GPIO_FUNC21_IN_SEL_M ((GPIO_FUNC21_IN_SEL_V)<<(GPIO_FUNC21_IN_SEL_S)) 2156 #define GPIO_FUNC21_IN_SEL_V 0x3F 2157 #define GPIO_FUNC21_IN_SEL_S 0 2158 2159 #define GPIO_FUNC22_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0188) 2160 /* GPIO_SIG22_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 2161 /*description: if the slow signal bypass the io matrix or not if you want setting 2162 the value to 1*/ 2163 #define GPIO_SIG22_IN_SEL (BIT(7)) 2164 #define GPIO_SIG22_IN_SEL_M (BIT(7)) 2165 #define GPIO_SIG22_IN_SEL_V 0x1 2166 #define GPIO_SIG22_IN_SEL_S 7 2167 /* GPIO_FUNC22_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 2168 /*description: revert the value of the input if you want to revert please set the value to 1*/ 2169 #define GPIO_FUNC22_IN_INV_SEL (BIT(6)) 2170 #define GPIO_FUNC22_IN_INV_SEL_M (BIT(6)) 2171 #define GPIO_FUNC22_IN_INV_SEL_V 0x1 2172 #define GPIO_FUNC22_IN_INV_SEL_S 6 2173 /* GPIO_FUNC22_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 2174 /*description: select one of the 256 inputs*/ 2175 #define GPIO_FUNC22_IN_SEL 0x0000003F 2176 #define GPIO_FUNC22_IN_SEL_M ((GPIO_FUNC22_IN_SEL_V)<<(GPIO_FUNC22_IN_SEL_S)) 2177 #define GPIO_FUNC22_IN_SEL_V 0x3F 2178 #define GPIO_FUNC22_IN_SEL_S 0 2179 2180 #define GPIO_FUNC23_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x018c) 2181 /* GPIO_SIG23_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 2182 /*description: if the slow signal bypass the io matrix or not if you want setting 2183 the value to 1*/ 2184 #define GPIO_SIG23_IN_SEL (BIT(7)) 2185 #define GPIO_SIG23_IN_SEL_M (BIT(7)) 2186 #define GPIO_SIG23_IN_SEL_V 0x1 2187 #define GPIO_SIG23_IN_SEL_S 7 2188 /* GPIO_FUNC23_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 2189 /*description: revert the value of the input if you want to revert please set the value to 1*/ 2190 #define GPIO_FUNC23_IN_INV_SEL (BIT(6)) 2191 #define GPIO_FUNC23_IN_INV_SEL_M (BIT(6)) 2192 #define GPIO_FUNC23_IN_INV_SEL_V 0x1 2193 #define GPIO_FUNC23_IN_INV_SEL_S 6 2194 /* GPIO_FUNC23_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 2195 /*description: select one of the 256 inputs*/ 2196 #define GPIO_FUNC23_IN_SEL 0x0000003F 2197 #define GPIO_FUNC23_IN_SEL_M ((GPIO_FUNC23_IN_SEL_V)<<(GPIO_FUNC23_IN_SEL_S)) 2198 #define GPIO_FUNC23_IN_SEL_V 0x3F 2199 #define GPIO_FUNC23_IN_SEL_S 0 2200 2201 #define GPIO_FUNC24_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0190) 2202 /* GPIO_SIG24_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 2203 /*description: if the slow signal bypass the io matrix or not if you want setting 2204 the value to 1*/ 2205 #define GPIO_SIG24_IN_SEL (BIT(7)) 2206 #define GPIO_SIG24_IN_SEL_M (BIT(7)) 2207 #define GPIO_SIG24_IN_SEL_V 0x1 2208 #define GPIO_SIG24_IN_SEL_S 7 2209 /* GPIO_FUNC24_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 2210 /*description: revert the value of the input if you want to revert please set the value to 1*/ 2211 #define GPIO_FUNC24_IN_INV_SEL (BIT(6)) 2212 #define GPIO_FUNC24_IN_INV_SEL_M (BIT(6)) 2213 #define GPIO_FUNC24_IN_INV_SEL_V 0x1 2214 #define GPIO_FUNC24_IN_INV_SEL_S 6 2215 /* GPIO_FUNC24_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 2216 /*description: select one of the 256 inputs*/ 2217 #define GPIO_FUNC24_IN_SEL 0x0000003F 2218 #define GPIO_FUNC24_IN_SEL_M ((GPIO_FUNC24_IN_SEL_V)<<(GPIO_FUNC24_IN_SEL_S)) 2219 #define GPIO_FUNC24_IN_SEL_V 0x3F 2220 #define GPIO_FUNC24_IN_SEL_S 0 2221 2222 #define GPIO_FUNC25_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0194) 2223 /* GPIO_SIG25_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 2224 /*description: if the slow signal bypass the io matrix or not if you want setting 2225 the value to 1*/ 2226 #define GPIO_SIG25_IN_SEL (BIT(7)) 2227 #define GPIO_SIG25_IN_SEL_M (BIT(7)) 2228 #define GPIO_SIG25_IN_SEL_V 0x1 2229 #define GPIO_SIG25_IN_SEL_S 7 2230 /* GPIO_FUNC25_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 2231 /*description: revert the value of the input if you want to revert please set the value to 1*/ 2232 #define GPIO_FUNC25_IN_INV_SEL (BIT(6)) 2233 #define GPIO_FUNC25_IN_INV_SEL_M (BIT(6)) 2234 #define GPIO_FUNC25_IN_INV_SEL_V 0x1 2235 #define GPIO_FUNC25_IN_INV_SEL_S 6 2236 /* GPIO_FUNC25_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 2237 /*description: select one of the 256 inputs*/ 2238 #define GPIO_FUNC25_IN_SEL 0x0000003F 2239 #define GPIO_FUNC25_IN_SEL_M ((GPIO_FUNC25_IN_SEL_V)<<(GPIO_FUNC25_IN_SEL_S)) 2240 #define GPIO_FUNC25_IN_SEL_V 0x3F 2241 #define GPIO_FUNC25_IN_SEL_S 0 2242 2243 #define GPIO_FUNC26_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0198) 2244 /* GPIO_SIG26_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 2245 /*description: if the slow signal bypass the io matrix or not if you want setting 2246 the value to 1*/ 2247 #define GPIO_SIG26_IN_SEL (BIT(7)) 2248 #define GPIO_SIG26_IN_SEL_M (BIT(7)) 2249 #define GPIO_SIG26_IN_SEL_V 0x1 2250 #define GPIO_SIG26_IN_SEL_S 7 2251 /* GPIO_FUNC26_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 2252 /*description: revert the value of the input if you want to revert please set the value to 1*/ 2253 #define GPIO_FUNC26_IN_INV_SEL (BIT(6)) 2254 #define GPIO_FUNC26_IN_INV_SEL_M (BIT(6)) 2255 #define GPIO_FUNC26_IN_INV_SEL_V 0x1 2256 #define GPIO_FUNC26_IN_INV_SEL_S 6 2257 /* GPIO_FUNC26_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 2258 /*description: select one of the 256 inputs*/ 2259 #define GPIO_FUNC26_IN_SEL 0x0000003F 2260 #define GPIO_FUNC26_IN_SEL_M ((GPIO_FUNC26_IN_SEL_V)<<(GPIO_FUNC26_IN_SEL_S)) 2261 #define GPIO_FUNC26_IN_SEL_V 0x3F 2262 #define GPIO_FUNC26_IN_SEL_S 0 2263 2264 #define GPIO_FUNC27_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x019c) 2265 /* GPIO_SIG27_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 2266 /*description: if the slow signal bypass the io matrix or not if you want setting 2267 the value to 1*/ 2268 #define GPIO_SIG27_IN_SEL (BIT(7)) 2269 #define GPIO_SIG27_IN_SEL_M (BIT(7)) 2270 #define GPIO_SIG27_IN_SEL_V 0x1 2271 #define GPIO_SIG27_IN_SEL_S 7 2272 /* GPIO_FUNC27_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 2273 /*description: revert the value of the input if you want to revert please set the value to 1*/ 2274 #define GPIO_FUNC27_IN_INV_SEL (BIT(6)) 2275 #define GPIO_FUNC27_IN_INV_SEL_M (BIT(6)) 2276 #define GPIO_FUNC27_IN_INV_SEL_V 0x1 2277 #define GPIO_FUNC27_IN_INV_SEL_S 6 2278 /* GPIO_FUNC27_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 2279 /*description: select one of the 256 inputs*/ 2280 #define GPIO_FUNC27_IN_SEL 0x0000003F 2281 #define GPIO_FUNC27_IN_SEL_M ((GPIO_FUNC27_IN_SEL_V)<<(GPIO_FUNC27_IN_SEL_S)) 2282 #define GPIO_FUNC27_IN_SEL_V 0x3F 2283 #define GPIO_FUNC27_IN_SEL_S 0 2284 2285 #define GPIO_FUNC28_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01a0) 2286 /* GPIO_SIG28_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 2287 /*description: if the slow signal bypass the io matrix or not if you want setting 2288 the value to 1*/ 2289 #define GPIO_SIG28_IN_SEL (BIT(7)) 2290 #define GPIO_SIG28_IN_SEL_M (BIT(7)) 2291 #define GPIO_SIG28_IN_SEL_V 0x1 2292 #define GPIO_SIG28_IN_SEL_S 7 2293 /* GPIO_FUNC28_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 2294 /*description: revert the value of the input if you want to revert please set the value to 1*/ 2295 #define GPIO_FUNC28_IN_INV_SEL (BIT(6)) 2296 #define GPIO_FUNC28_IN_INV_SEL_M (BIT(6)) 2297 #define GPIO_FUNC28_IN_INV_SEL_V 0x1 2298 #define GPIO_FUNC28_IN_INV_SEL_S 6 2299 /* GPIO_FUNC28_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 2300 /*description: select one of the 256 inputs*/ 2301 #define GPIO_FUNC28_IN_SEL 0x0000003F 2302 #define GPIO_FUNC28_IN_SEL_M ((GPIO_FUNC28_IN_SEL_V)<<(GPIO_FUNC28_IN_SEL_S)) 2303 #define GPIO_FUNC28_IN_SEL_V 0x3F 2304 #define GPIO_FUNC28_IN_SEL_S 0 2305 2306 #define GPIO_FUNC29_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01a4) 2307 /* GPIO_SIG29_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 2308 /*description: if the slow signal bypass the io matrix or not if you want setting 2309 the value to 1*/ 2310 #define GPIO_SIG29_IN_SEL (BIT(7)) 2311 #define GPIO_SIG29_IN_SEL_M (BIT(7)) 2312 #define GPIO_SIG29_IN_SEL_V 0x1 2313 #define GPIO_SIG29_IN_SEL_S 7 2314 /* GPIO_FUNC29_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 2315 /*description: revert the value of the input if you want to revert please set the value to 1*/ 2316 #define GPIO_FUNC29_IN_INV_SEL (BIT(6)) 2317 #define GPIO_FUNC29_IN_INV_SEL_M (BIT(6)) 2318 #define GPIO_FUNC29_IN_INV_SEL_V 0x1 2319 #define GPIO_FUNC29_IN_INV_SEL_S 6 2320 /* GPIO_FUNC29_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 2321 /*description: select one of the 256 inputs*/ 2322 #define GPIO_FUNC29_IN_SEL 0x0000003F 2323 #define GPIO_FUNC29_IN_SEL_M ((GPIO_FUNC29_IN_SEL_V)<<(GPIO_FUNC29_IN_SEL_S)) 2324 #define GPIO_FUNC29_IN_SEL_V 0x3F 2325 #define GPIO_FUNC29_IN_SEL_S 0 2326 2327 #define GPIO_FUNC30_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01a8) 2328 /* GPIO_SIG30_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 2329 /*description: if the slow signal bypass the io matrix or not if you want setting 2330 the value to 1*/ 2331 #define GPIO_SIG30_IN_SEL (BIT(7)) 2332 #define GPIO_SIG30_IN_SEL_M (BIT(7)) 2333 #define GPIO_SIG30_IN_SEL_V 0x1 2334 #define GPIO_SIG30_IN_SEL_S 7 2335 /* GPIO_FUNC30_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 2336 /*description: revert the value of the input if you want to revert please set the value to 1*/ 2337 #define GPIO_FUNC30_IN_INV_SEL (BIT(6)) 2338 #define GPIO_FUNC30_IN_INV_SEL_M (BIT(6)) 2339 #define GPIO_FUNC30_IN_INV_SEL_V 0x1 2340 #define GPIO_FUNC30_IN_INV_SEL_S 6 2341 /* GPIO_FUNC30_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 2342 /*description: select one of the 256 inputs*/ 2343 #define GPIO_FUNC30_IN_SEL 0x0000003F 2344 #define GPIO_FUNC30_IN_SEL_M ((GPIO_FUNC30_IN_SEL_V)<<(GPIO_FUNC30_IN_SEL_S)) 2345 #define GPIO_FUNC30_IN_SEL_V 0x3F 2346 #define GPIO_FUNC30_IN_SEL_S 0 2347 2348 #define GPIO_FUNC31_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01ac) 2349 /* GPIO_SIG31_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 2350 /*description: if the slow signal bypass the io matrix or not if you want setting 2351 the value to 1*/ 2352 #define GPIO_SIG31_IN_SEL (BIT(7)) 2353 #define GPIO_SIG31_IN_SEL_M (BIT(7)) 2354 #define GPIO_SIG31_IN_SEL_V 0x1 2355 #define GPIO_SIG31_IN_SEL_S 7 2356 /* GPIO_FUNC31_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 2357 /*description: revert the value of the input if you want to revert please set the value to 1*/ 2358 #define GPIO_FUNC31_IN_INV_SEL (BIT(6)) 2359 #define GPIO_FUNC31_IN_INV_SEL_M (BIT(6)) 2360 #define GPIO_FUNC31_IN_INV_SEL_V 0x1 2361 #define GPIO_FUNC31_IN_INV_SEL_S 6 2362 /* GPIO_FUNC31_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 2363 /*description: select one of the 256 inputs*/ 2364 #define GPIO_FUNC31_IN_SEL 0x0000003F 2365 #define GPIO_FUNC31_IN_SEL_M ((GPIO_FUNC31_IN_SEL_V)<<(GPIO_FUNC31_IN_SEL_S)) 2366 #define GPIO_FUNC31_IN_SEL_V 0x3F 2367 #define GPIO_FUNC31_IN_SEL_S 0 2368 2369 #define GPIO_FUNC32_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01b0) 2370 /* GPIO_SIG32_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 2371 /*description: if the slow signal bypass the io matrix or not if you want setting 2372 the value to 1*/ 2373 #define GPIO_SIG32_IN_SEL (BIT(7)) 2374 #define GPIO_SIG32_IN_SEL_M (BIT(7)) 2375 #define GPIO_SIG32_IN_SEL_V 0x1 2376 #define GPIO_SIG32_IN_SEL_S 7 2377 /* GPIO_FUNC32_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 2378 /*description: revert the value of the input if you want to revert please set the value to 1*/ 2379 #define GPIO_FUNC32_IN_INV_SEL (BIT(6)) 2380 #define GPIO_FUNC32_IN_INV_SEL_M (BIT(6)) 2381 #define GPIO_FUNC32_IN_INV_SEL_V 0x1 2382 #define GPIO_FUNC32_IN_INV_SEL_S 6 2383 /* GPIO_FUNC32_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 2384 /*description: select one of the 256 inputs*/ 2385 #define GPIO_FUNC32_IN_SEL 0x0000003F 2386 #define GPIO_FUNC32_IN_SEL_M ((GPIO_FUNC32_IN_SEL_V)<<(GPIO_FUNC32_IN_SEL_S)) 2387 #define GPIO_FUNC32_IN_SEL_V 0x3F 2388 #define GPIO_FUNC32_IN_SEL_S 0 2389 2390 #define GPIO_FUNC33_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01b4) 2391 /* GPIO_SIG33_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 2392 /*description: if the slow signal bypass the io matrix or not if you want setting 2393 the value to 1*/ 2394 #define GPIO_SIG33_IN_SEL (BIT(7)) 2395 #define GPIO_SIG33_IN_SEL_M (BIT(7)) 2396 #define GPIO_SIG33_IN_SEL_V 0x1 2397 #define GPIO_SIG33_IN_SEL_S 7 2398 /* GPIO_FUNC33_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 2399 /*description: revert the value of the input if you want to revert please set the value to 1*/ 2400 #define GPIO_FUNC33_IN_INV_SEL (BIT(6)) 2401 #define GPIO_FUNC33_IN_INV_SEL_M (BIT(6)) 2402 #define GPIO_FUNC33_IN_INV_SEL_V 0x1 2403 #define GPIO_FUNC33_IN_INV_SEL_S 6 2404 /* GPIO_FUNC33_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 2405 /*description: select one of the 256 inputs*/ 2406 #define GPIO_FUNC33_IN_SEL 0x0000003F 2407 #define GPIO_FUNC33_IN_SEL_M ((GPIO_FUNC33_IN_SEL_V)<<(GPIO_FUNC33_IN_SEL_S)) 2408 #define GPIO_FUNC33_IN_SEL_V 0x3F 2409 #define GPIO_FUNC33_IN_SEL_S 0 2410 2411 #define GPIO_FUNC34_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01b8) 2412 /* GPIO_SIG34_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 2413 /*description: if the slow signal bypass the io matrix or not if you want setting 2414 the value to 1*/ 2415 #define GPIO_SIG34_IN_SEL (BIT(7)) 2416 #define GPIO_SIG34_IN_SEL_M (BIT(7)) 2417 #define GPIO_SIG34_IN_SEL_V 0x1 2418 #define GPIO_SIG34_IN_SEL_S 7 2419 /* GPIO_FUNC34_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 2420 /*description: revert the value of the input if you want to revert please set the value to 1*/ 2421 #define GPIO_FUNC34_IN_INV_SEL (BIT(6)) 2422 #define GPIO_FUNC34_IN_INV_SEL_M (BIT(6)) 2423 #define GPIO_FUNC34_IN_INV_SEL_V 0x1 2424 #define GPIO_FUNC34_IN_INV_SEL_S 6 2425 /* GPIO_FUNC34_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 2426 /*description: select one of the 256 inputs*/ 2427 #define GPIO_FUNC34_IN_SEL 0x0000003F 2428 #define GPIO_FUNC34_IN_SEL_M ((GPIO_FUNC34_IN_SEL_V)<<(GPIO_FUNC34_IN_SEL_S)) 2429 #define GPIO_FUNC34_IN_SEL_V 0x3F 2430 #define GPIO_FUNC34_IN_SEL_S 0 2431 2432 #define GPIO_FUNC35_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01bc) 2433 /* GPIO_SIG35_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 2434 /*description: if the slow signal bypass the io matrix or not if you want setting 2435 the value to 1*/ 2436 #define GPIO_SIG35_IN_SEL (BIT(7)) 2437 #define GPIO_SIG35_IN_SEL_M (BIT(7)) 2438 #define GPIO_SIG35_IN_SEL_V 0x1 2439 #define GPIO_SIG35_IN_SEL_S 7 2440 /* GPIO_FUNC35_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 2441 /*description: revert the value of the input if you want to revert please set the value to 1*/ 2442 #define GPIO_FUNC35_IN_INV_SEL (BIT(6)) 2443 #define GPIO_FUNC35_IN_INV_SEL_M (BIT(6)) 2444 #define GPIO_FUNC35_IN_INV_SEL_V 0x1 2445 #define GPIO_FUNC35_IN_INV_SEL_S 6 2446 /* GPIO_FUNC35_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 2447 /*description: select one of the 256 inputs*/ 2448 #define GPIO_FUNC35_IN_SEL 0x0000003F 2449 #define GPIO_FUNC35_IN_SEL_M ((GPIO_FUNC35_IN_SEL_V)<<(GPIO_FUNC35_IN_SEL_S)) 2450 #define GPIO_FUNC35_IN_SEL_V 0x3F 2451 #define GPIO_FUNC35_IN_SEL_S 0 2452 2453 #define GPIO_FUNC36_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01c0) 2454 /* GPIO_SIG36_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 2455 /*description: if the slow signal bypass the io matrix or not if you want setting 2456 the value to 1*/ 2457 #define GPIO_SIG36_IN_SEL (BIT(7)) 2458 #define GPIO_SIG36_IN_SEL_M (BIT(7)) 2459 #define GPIO_SIG36_IN_SEL_V 0x1 2460 #define GPIO_SIG36_IN_SEL_S 7 2461 /* GPIO_FUNC36_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 2462 /*description: revert the value of the input if you want to revert please set the value to 1*/ 2463 #define GPIO_FUNC36_IN_INV_SEL (BIT(6)) 2464 #define GPIO_FUNC36_IN_INV_SEL_M (BIT(6)) 2465 #define GPIO_FUNC36_IN_INV_SEL_V 0x1 2466 #define GPIO_FUNC36_IN_INV_SEL_S 6 2467 /* GPIO_FUNC36_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 2468 /*description: select one of the 256 inputs*/ 2469 #define GPIO_FUNC36_IN_SEL 0x0000003F 2470 #define GPIO_FUNC36_IN_SEL_M ((GPIO_FUNC36_IN_SEL_V)<<(GPIO_FUNC36_IN_SEL_S)) 2471 #define GPIO_FUNC36_IN_SEL_V 0x3F 2472 #define GPIO_FUNC36_IN_SEL_S 0 2473 2474 #define GPIO_FUNC37_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01c4) 2475 /* GPIO_SIG37_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 2476 /*description: if the slow signal bypass the io matrix or not if you want setting 2477 the value to 1*/ 2478 #define GPIO_SIG37_IN_SEL (BIT(7)) 2479 #define GPIO_SIG37_IN_SEL_M (BIT(7)) 2480 #define GPIO_SIG37_IN_SEL_V 0x1 2481 #define GPIO_SIG37_IN_SEL_S 7 2482 /* GPIO_FUNC37_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 2483 /*description: revert the value of the input if you want to revert please set the value to 1*/ 2484 #define GPIO_FUNC37_IN_INV_SEL (BIT(6)) 2485 #define GPIO_FUNC37_IN_INV_SEL_M (BIT(6)) 2486 #define GPIO_FUNC37_IN_INV_SEL_V 0x1 2487 #define GPIO_FUNC37_IN_INV_SEL_S 6 2488 /* GPIO_FUNC37_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 2489 /*description: select one of the 256 inputs*/ 2490 #define GPIO_FUNC37_IN_SEL 0x0000003F 2491 #define GPIO_FUNC37_IN_SEL_M ((GPIO_FUNC37_IN_SEL_V)<<(GPIO_FUNC37_IN_SEL_S)) 2492 #define GPIO_FUNC37_IN_SEL_V 0x3F 2493 #define GPIO_FUNC37_IN_SEL_S 0 2494 2495 #define GPIO_FUNC38_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01c8) 2496 /* GPIO_SIG38_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 2497 /*description: if the slow signal bypass the io matrix or not if you want setting 2498 the value to 1*/ 2499 #define GPIO_SIG38_IN_SEL (BIT(7)) 2500 #define GPIO_SIG38_IN_SEL_M (BIT(7)) 2501 #define GPIO_SIG38_IN_SEL_V 0x1 2502 #define GPIO_SIG38_IN_SEL_S 7 2503 /* GPIO_FUNC38_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 2504 /*description: revert the value of the input if you want to revert please set the value to 1*/ 2505 #define GPIO_FUNC38_IN_INV_SEL (BIT(6)) 2506 #define GPIO_FUNC38_IN_INV_SEL_M (BIT(6)) 2507 #define GPIO_FUNC38_IN_INV_SEL_V 0x1 2508 #define GPIO_FUNC38_IN_INV_SEL_S 6 2509 /* GPIO_FUNC38_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 2510 /*description: select one of the 256 inputs*/ 2511 #define GPIO_FUNC38_IN_SEL 0x0000003F 2512 #define GPIO_FUNC38_IN_SEL_M ((GPIO_FUNC38_IN_SEL_V)<<(GPIO_FUNC38_IN_SEL_S)) 2513 #define GPIO_FUNC38_IN_SEL_V 0x3F 2514 #define GPIO_FUNC38_IN_SEL_S 0 2515 2516 #define GPIO_FUNC39_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01cc) 2517 /* GPIO_SIG39_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 2518 /*description: if the slow signal bypass the io matrix or not if you want setting 2519 the value to 1*/ 2520 #define GPIO_SIG39_IN_SEL (BIT(7)) 2521 #define GPIO_SIG39_IN_SEL_M (BIT(7)) 2522 #define GPIO_SIG39_IN_SEL_V 0x1 2523 #define GPIO_SIG39_IN_SEL_S 7 2524 /* GPIO_FUNC39_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 2525 /*description: revert the value of the input if you want to revert please set the value to 1*/ 2526 #define GPIO_FUNC39_IN_INV_SEL (BIT(6)) 2527 #define GPIO_FUNC39_IN_INV_SEL_M (BIT(6)) 2528 #define GPIO_FUNC39_IN_INV_SEL_V 0x1 2529 #define GPIO_FUNC39_IN_INV_SEL_S 6 2530 /* GPIO_FUNC39_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 2531 /*description: select one of the 256 inputs*/ 2532 #define GPIO_FUNC39_IN_SEL 0x0000003F 2533 #define GPIO_FUNC39_IN_SEL_M ((GPIO_FUNC39_IN_SEL_V)<<(GPIO_FUNC39_IN_SEL_S)) 2534 #define GPIO_FUNC39_IN_SEL_V 0x3F 2535 #define GPIO_FUNC39_IN_SEL_S 0 2536 2537 #define GPIO_FUNC40_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01d0) 2538 /* GPIO_SIG40_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 2539 /*description: if the slow signal bypass the io matrix or not if you want setting 2540 the value to 1*/ 2541 #define GPIO_SIG40_IN_SEL (BIT(7)) 2542 #define GPIO_SIG40_IN_SEL_M (BIT(7)) 2543 #define GPIO_SIG40_IN_SEL_V 0x1 2544 #define GPIO_SIG40_IN_SEL_S 7 2545 /* GPIO_FUNC40_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 2546 /*description: revert the value of the input if you want to revert please set the value to 1*/ 2547 #define GPIO_FUNC40_IN_INV_SEL (BIT(6)) 2548 #define GPIO_FUNC40_IN_INV_SEL_M (BIT(6)) 2549 #define GPIO_FUNC40_IN_INV_SEL_V 0x1 2550 #define GPIO_FUNC40_IN_INV_SEL_S 6 2551 /* GPIO_FUNC40_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 2552 /*description: select one of the 256 inputs*/ 2553 #define GPIO_FUNC40_IN_SEL 0x0000003F 2554 #define GPIO_FUNC40_IN_SEL_M ((GPIO_FUNC40_IN_SEL_V)<<(GPIO_FUNC40_IN_SEL_S)) 2555 #define GPIO_FUNC40_IN_SEL_V 0x3F 2556 #define GPIO_FUNC40_IN_SEL_S 0 2557 2558 #define GPIO_FUNC41_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01d4) 2559 /* GPIO_SIG41_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 2560 /*description: if the slow signal bypass the io matrix or not if you want setting 2561 the value to 1*/ 2562 #define GPIO_SIG41_IN_SEL (BIT(7)) 2563 #define GPIO_SIG41_IN_SEL_M (BIT(7)) 2564 #define GPIO_SIG41_IN_SEL_V 0x1 2565 #define GPIO_SIG41_IN_SEL_S 7 2566 /* GPIO_FUNC41_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 2567 /*description: revert the value of the input if you want to revert please set the value to 1*/ 2568 #define GPIO_FUNC41_IN_INV_SEL (BIT(6)) 2569 #define GPIO_FUNC41_IN_INV_SEL_M (BIT(6)) 2570 #define GPIO_FUNC41_IN_INV_SEL_V 0x1 2571 #define GPIO_FUNC41_IN_INV_SEL_S 6 2572 /* GPIO_FUNC41_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 2573 /*description: select one of the 256 inputs*/ 2574 #define GPIO_FUNC41_IN_SEL 0x0000003F 2575 #define GPIO_FUNC41_IN_SEL_M ((GPIO_FUNC41_IN_SEL_V)<<(GPIO_FUNC41_IN_SEL_S)) 2576 #define GPIO_FUNC41_IN_SEL_V 0x3F 2577 #define GPIO_FUNC41_IN_SEL_S 0 2578 2579 #define GPIO_FUNC42_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01d8) 2580 /* GPIO_SIG42_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 2581 /*description: if the slow signal bypass the io matrix or not if you want setting 2582 the value to 1*/ 2583 #define GPIO_SIG42_IN_SEL (BIT(7)) 2584 #define GPIO_SIG42_IN_SEL_M (BIT(7)) 2585 #define GPIO_SIG42_IN_SEL_V 0x1 2586 #define GPIO_SIG42_IN_SEL_S 7 2587 /* GPIO_FUNC42_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 2588 /*description: revert the value of the input if you want to revert please set the value to 1*/ 2589 #define GPIO_FUNC42_IN_INV_SEL (BIT(6)) 2590 #define GPIO_FUNC42_IN_INV_SEL_M (BIT(6)) 2591 #define GPIO_FUNC42_IN_INV_SEL_V 0x1 2592 #define GPIO_FUNC42_IN_INV_SEL_S 6 2593 /* GPIO_FUNC42_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 2594 /*description: select one of the 256 inputs*/ 2595 #define GPIO_FUNC42_IN_SEL 0x0000003F 2596 #define GPIO_FUNC42_IN_SEL_M ((GPIO_FUNC42_IN_SEL_V)<<(GPIO_FUNC42_IN_SEL_S)) 2597 #define GPIO_FUNC42_IN_SEL_V 0x3F 2598 #define GPIO_FUNC42_IN_SEL_S 0 2599 2600 #define GPIO_FUNC43_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01dc) 2601 /* GPIO_SIG43_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 2602 /*description: if the slow signal bypass the io matrix or not if you want setting 2603 the value to 1*/ 2604 #define GPIO_SIG43_IN_SEL (BIT(7)) 2605 #define GPIO_SIG43_IN_SEL_M (BIT(7)) 2606 #define GPIO_SIG43_IN_SEL_V 0x1 2607 #define GPIO_SIG43_IN_SEL_S 7 2608 /* GPIO_FUNC43_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 2609 /*description: revert the value of the input if you want to revert please set the value to 1*/ 2610 #define GPIO_FUNC43_IN_INV_SEL (BIT(6)) 2611 #define GPIO_FUNC43_IN_INV_SEL_M (BIT(6)) 2612 #define GPIO_FUNC43_IN_INV_SEL_V 0x1 2613 #define GPIO_FUNC43_IN_INV_SEL_S 6 2614 /* GPIO_FUNC43_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 2615 /*description: select one of the 256 inputs*/ 2616 #define GPIO_FUNC43_IN_SEL 0x0000003F 2617 #define GPIO_FUNC43_IN_SEL_M ((GPIO_FUNC43_IN_SEL_V)<<(GPIO_FUNC43_IN_SEL_S)) 2618 #define GPIO_FUNC43_IN_SEL_V 0x3F 2619 #define GPIO_FUNC43_IN_SEL_S 0 2620 2621 #define GPIO_FUNC44_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01e0) 2622 /* GPIO_SIG44_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 2623 /*description: if the slow signal bypass the io matrix or not if you want setting 2624 the value to 1*/ 2625 #define GPIO_SIG44_IN_SEL (BIT(7)) 2626 #define GPIO_SIG44_IN_SEL_M (BIT(7)) 2627 #define GPIO_SIG44_IN_SEL_V 0x1 2628 #define GPIO_SIG44_IN_SEL_S 7 2629 /* GPIO_FUNC44_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 2630 /*description: revert the value of the input if you want to revert please set the value to 1*/ 2631 #define GPIO_FUNC44_IN_INV_SEL (BIT(6)) 2632 #define GPIO_FUNC44_IN_INV_SEL_M (BIT(6)) 2633 #define GPIO_FUNC44_IN_INV_SEL_V 0x1 2634 #define GPIO_FUNC44_IN_INV_SEL_S 6 2635 /* GPIO_FUNC44_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 2636 /*description: select one of the 256 inputs*/ 2637 #define GPIO_FUNC44_IN_SEL 0x0000003F 2638 #define GPIO_FUNC44_IN_SEL_M ((GPIO_FUNC44_IN_SEL_V)<<(GPIO_FUNC44_IN_SEL_S)) 2639 #define GPIO_FUNC44_IN_SEL_V 0x3F 2640 #define GPIO_FUNC44_IN_SEL_S 0 2641 2642 #define GPIO_FUNC45_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01e4) 2643 /* GPIO_SIG45_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 2644 /*description: if the slow signal bypass the io matrix or not if you want setting 2645 the value to 1*/ 2646 #define GPIO_SIG45_IN_SEL (BIT(7)) 2647 #define GPIO_SIG45_IN_SEL_M (BIT(7)) 2648 #define GPIO_SIG45_IN_SEL_V 0x1 2649 #define GPIO_SIG45_IN_SEL_S 7 2650 /* GPIO_FUNC45_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 2651 /*description: revert the value of the input if you want to revert please set the value to 1*/ 2652 #define GPIO_FUNC45_IN_INV_SEL (BIT(6)) 2653 #define GPIO_FUNC45_IN_INV_SEL_M (BIT(6)) 2654 #define GPIO_FUNC45_IN_INV_SEL_V 0x1 2655 #define GPIO_FUNC45_IN_INV_SEL_S 6 2656 /* GPIO_FUNC45_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 2657 /*description: select one of the 256 inputs*/ 2658 #define GPIO_FUNC45_IN_SEL 0x0000003F 2659 #define GPIO_FUNC45_IN_SEL_M ((GPIO_FUNC45_IN_SEL_V)<<(GPIO_FUNC45_IN_SEL_S)) 2660 #define GPIO_FUNC45_IN_SEL_V 0x3F 2661 #define GPIO_FUNC45_IN_SEL_S 0 2662 2663 #define GPIO_FUNC46_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01e8) 2664 /* GPIO_SIG46_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 2665 /*description: if the slow signal bypass the io matrix or not if you want setting 2666 the value to 1*/ 2667 #define GPIO_SIG46_IN_SEL (BIT(7)) 2668 #define GPIO_SIG46_IN_SEL_M (BIT(7)) 2669 #define GPIO_SIG46_IN_SEL_V 0x1 2670 #define GPIO_SIG46_IN_SEL_S 7 2671 /* GPIO_FUNC46_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 2672 /*description: revert the value of the input if you want to revert please set the value to 1*/ 2673 #define GPIO_FUNC46_IN_INV_SEL (BIT(6)) 2674 #define GPIO_FUNC46_IN_INV_SEL_M (BIT(6)) 2675 #define GPIO_FUNC46_IN_INV_SEL_V 0x1 2676 #define GPIO_FUNC46_IN_INV_SEL_S 6 2677 /* GPIO_FUNC46_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 2678 /*description: select one of the 256 inputs*/ 2679 #define GPIO_FUNC46_IN_SEL 0x0000003F 2680 #define GPIO_FUNC46_IN_SEL_M ((GPIO_FUNC46_IN_SEL_V)<<(GPIO_FUNC46_IN_SEL_S)) 2681 #define GPIO_FUNC46_IN_SEL_V 0x3F 2682 #define GPIO_FUNC46_IN_SEL_S 0 2683 2684 #define GPIO_FUNC47_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01ec) 2685 /* GPIO_SIG47_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 2686 /*description: if the slow signal bypass the io matrix or not if you want setting 2687 the value to 1*/ 2688 #define GPIO_SIG47_IN_SEL (BIT(7)) 2689 #define GPIO_SIG47_IN_SEL_M (BIT(7)) 2690 #define GPIO_SIG47_IN_SEL_V 0x1 2691 #define GPIO_SIG47_IN_SEL_S 7 2692 /* GPIO_FUNC47_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 2693 /*description: revert the value of the input if you want to revert please set the value to 1*/ 2694 #define GPIO_FUNC47_IN_INV_SEL (BIT(6)) 2695 #define GPIO_FUNC47_IN_INV_SEL_M (BIT(6)) 2696 #define GPIO_FUNC47_IN_INV_SEL_V 0x1 2697 #define GPIO_FUNC47_IN_INV_SEL_S 6 2698 /* GPIO_FUNC47_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 2699 /*description: select one of the 256 inputs*/ 2700 #define GPIO_FUNC47_IN_SEL 0x0000003F 2701 #define GPIO_FUNC47_IN_SEL_M ((GPIO_FUNC47_IN_SEL_V)<<(GPIO_FUNC47_IN_SEL_S)) 2702 #define GPIO_FUNC47_IN_SEL_V 0x3F 2703 #define GPIO_FUNC47_IN_SEL_S 0 2704 2705 #define GPIO_FUNC48_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01f0) 2706 /* GPIO_SIG48_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 2707 /*description: if the slow signal bypass the io matrix or not if you want setting 2708 the value to 1*/ 2709 #define GPIO_SIG48_IN_SEL (BIT(7)) 2710 #define GPIO_SIG48_IN_SEL_M (BIT(7)) 2711 #define GPIO_SIG48_IN_SEL_V 0x1 2712 #define GPIO_SIG48_IN_SEL_S 7 2713 /* GPIO_FUNC48_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 2714 /*description: revert the value of the input if you want to revert please set the value to 1*/ 2715 #define GPIO_FUNC48_IN_INV_SEL (BIT(6)) 2716 #define GPIO_FUNC48_IN_INV_SEL_M (BIT(6)) 2717 #define GPIO_FUNC48_IN_INV_SEL_V 0x1 2718 #define GPIO_FUNC48_IN_INV_SEL_S 6 2719 /* GPIO_FUNC48_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 2720 /*description: select one of the 256 inputs*/ 2721 #define GPIO_FUNC48_IN_SEL 0x0000003F 2722 #define GPIO_FUNC48_IN_SEL_M ((GPIO_FUNC48_IN_SEL_V)<<(GPIO_FUNC48_IN_SEL_S)) 2723 #define GPIO_FUNC48_IN_SEL_V 0x3F 2724 #define GPIO_FUNC48_IN_SEL_S 0 2725 2726 #define GPIO_FUNC49_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01f4) 2727 /* GPIO_SIG49_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 2728 /*description: if the slow signal bypass the io matrix or not if you want setting 2729 the value to 1*/ 2730 #define GPIO_SIG49_IN_SEL (BIT(7)) 2731 #define GPIO_SIG49_IN_SEL_M (BIT(7)) 2732 #define GPIO_SIG49_IN_SEL_V 0x1 2733 #define GPIO_SIG49_IN_SEL_S 7 2734 /* GPIO_FUNC49_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 2735 /*description: revert the value of the input if you want to revert please set the value to 1*/ 2736 #define GPIO_FUNC49_IN_INV_SEL (BIT(6)) 2737 #define GPIO_FUNC49_IN_INV_SEL_M (BIT(6)) 2738 #define GPIO_FUNC49_IN_INV_SEL_V 0x1 2739 #define GPIO_FUNC49_IN_INV_SEL_S 6 2740 /* GPIO_FUNC49_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 2741 /*description: select one of the 256 inputs*/ 2742 #define GPIO_FUNC49_IN_SEL 0x0000003F 2743 #define GPIO_FUNC49_IN_SEL_M ((GPIO_FUNC49_IN_SEL_V)<<(GPIO_FUNC49_IN_SEL_S)) 2744 #define GPIO_FUNC49_IN_SEL_V 0x3F 2745 #define GPIO_FUNC49_IN_SEL_S 0 2746 2747 #define GPIO_FUNC50_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01f8) 2748 /* GPIO_SIG50_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 2749 /*description: if the slow signal bypass the io matrix or not if you want setting 2750 the value to 1*/ 2751 #define GPIO_SIG50_IN_SEL (BIT(7)) 2752 #define GPIO_SIG50_IN_SEL_M (BIT(7)) 2753 #define GPIO_SIG50_IN_SEL_V 0x1 2754 #define GPIO_SIG50_IN_SEL_S 7 2755 /* GPIO_FUNC50_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 2756 /*description: revert the value of the input if you want to revert please set the value to 1*/ 2757 #define GPIO_FUNC50_IN_INV_SEL (BIT(6)) 2758 #define GPIO_FUNC50_IN_INV_SEL_M (BIT(6)) 2759 #define GPIO_FUNC50_IN_INV_SEL_V 0x1 2760 #define GPIO_FUNC50_IN_INV_SEL_S 6 2761 /* GPIO_FUNC50_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 2762 /*description: select one of the 256 inputs*/ 2763 #define GPIO_FUNC50_IN_SEL 0x0000003F 2764 #define GPIO_FUNC50_IN_SEL_M ((GPIO_FUNC50_IN_SEL_V)<<(GPIO_FUNC50_IN_SEL_S)) 2765 #define GPIO_FUNC50_IN_SEL_V 0x3F 2766 #define GPIO_FUNC50_IN_SEL_S 0 2767 2768 #define GPIO_FUNC51_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01fc) 2769 /* GPIO_SIG51_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 2770 /*description: if the slow signal bypass the io matrix or not if you want setting 2771 the value to 1*/ 2772 #define GPIO_SIG51_IN_SEL (BIT(7)) 2773 #define GPIO_SIG51_IN_SEL_M (BIT(7)) 2774 #define GPIO_SIG51_IN_SEL_V 0x1 2775 #define GPIO_SIG51_IN_SEL_S 7 2776 /* GPIO_FUNC51_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 2777 /*description: revert the value of the input if you want to revert please set the value to 1*/ 2778 #define GPIO_FUNC51_IN_INV_SEL (BIT(6)) 2779 #define GPIO_FUNC51_IN_INV_SEL_M (BIT(6)) 2780 #define GPIO_FUNC51_IN_INV_SEL_V 0x1 2781 #define GPIO_FUNC51_IN_INV_SEL_S 6 2782 /* GPIO_FUNC51_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 2783 /*description: select one of the 256 inputs*/ 2784 #define GPIO_FUNC51_IN_SEL 0x0000003F 2785 #define GPIO_FUNC51_IN_SEL_M ((GPIO_FUNC51_IN_SEL_V)<<(GPIO_FUNC51_IN_SEL_S)) 2786 #define GPIO_FUNC51_IN_SEL_V 0x3F 2787 #define GPIO_FUNC51_IN_SEL_S 0 2788 2789 #define GPIO_FUNC52_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0200) 2790 /* GPIO_SIG52_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 2791 /*description: if the slow signal bypass the io matrix or not if you want setting 2792 the value to 1*/ 2793 #define GPIO_SIG52_IN_SEL (BIT(7)) 2794 #define GPIO_SIG52_IN_SEL_M (BIT(7)) 2795 #define GPIO_SIG52_IN_SEL_V 0x1 2796 #define GPIO_SIG52_IN_SEL_S 7 2797 /* GPIO_FUNC52_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 2798 /*description: revert the value of the input if you want to revert please set the value to 1*/ 2799 #define GPIO_FUNC52_IN_INV_SEL (BIT(6)) 2800 #define GPIO_FUNC52_IN_INV_SEL_M (BIT(6)) 2801 #define GPIO_FUNC52_IN_INV_SEL_V 0x1 2802 #define GPIO_FUNC52_IN_INV_SEL_S 6 2803 /* GPIO_FUNC52_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 2804 /*description: select one of the 256 inputs*/ 2805 #define GPIO_FUNC52_IN_SEL 0x0000003F 2806 #define GPIO_FUNC52_IN_SEL_M ((GPIO_FUNC52_IN_SEL_V)<<(GPIO_FUNC52_IN_SEL_S)) 2807 #define GPIO_FUNC52_IN_SEL_V 0x3F 2808 #define GPIO_FUNC52_IN_SEL_S 0 2809 2810 #define GPIO_FUNC53_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0204) 2811 /* GPIO_SIG53_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 2812 /*description: if the slow signal bypass the io matrix or not if you want setting 2813 the value to 1*/ 2814 #define GPIO_SIG53_IN_SEL (BIT(7)) 2815 #define GPIO_SIG53_IN_SEL_M (BIT(7)) 2816 #define GPIO_SIG53_IN_SEL_V 0x1 2817 #define GPIO_SIG53_IN_SEL_S 7 2818 /* GPIO_FUNC53_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 2819 /*description: revert the value of the input if you want to revert please set the value to 1*/ 2820 #define GPIO_FUNC53_IN_INV_SEL (BIT(6)) 2821 #define GPIO_FUNC53_IN_INV_SEL_M (BIT(6)) 2822 #define GPIO_FUNC53_IN_INV_SEL_V 0x1 2823 #define GPIO_FUNC53_IN_INV_SEL_S 6 2824 /* GPIO_FUNC53_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 2825 /*description: select one of the 256 inputs*/ 2826 #define GPIO_FUNC53_IN_SEL 0x0000003F 2827 #define GPIO_FUNC53_IN_SEL_M ((GPIO_FUNC53_IN_SEL_V)<<(GPIO_FUNC53_IN_SEL_S)) 2828 #define GPIO_FUNC53_IN_SEL_V 0x3F 2829 #define GPIO_FUNC53_IN_SEL_S 0 2830 2831 #define GPIO_FUNC54_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0208) 2832 /* GPIO_SIG54_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 2833 /*description: if the slow signal bypass the io matrix or not if you want setting 2834 the value to 1*/ 2835 #define GPIO_SIG54_IN_SEL (BIT(7)) 2836 #define GPIO_SIG54_IN_SEL_M (BIT(7)) 2837 #define GPIO_SIG54_IN_SEL_V 0x1 2838 #define GPIO_SIG54_IN_SEL_S 7 2839 /* GPIO_FUNC54_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 2840 /*description: revert the value of the input if you want to revert please set the value to 1*/ 2841 #define GPIO_FUNC54_IN_INV_SEL (BIT(6)) 2842 #define GPIO_FUNC54_IN_INV_SEL_M (BIT(6)) 2843 #define GPIO_FUNC54_IN_INV_SEL_V 0x1 2844 #define GPIO_FUNC54_IN_INV_SEL_S 6 2845 /* GPIO_FUNC54_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 2846 /*description: select one of the 256 inputs*/ 2847 #define GPIO_FUNC54_IN_SEL 0x0000003F 2848 #define GPIO_FUNC54_IN_SEL_M ((GPIO_FUNC54_IN_SEL_V)<<(GPIO_FUNC54_IN_SEL_S)) 2849 #define GPIO_FUNC54_IN_SEL_V 0x3F 2850 #define GPIO_FUNC54_IN_SEL_S 0 2851 2852 #define GPIO_FUNC55_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x020c) 2853 /* GPIO_SIG55_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 2854 /*description: if the slow signal bypass the io matrix or not if you want setting 2855 the value to 1*/ 2856 #define GPIO_SIG55_IN_SEL (BIT(7)) 2857 #define GPIO_SIG55_IN_SEL_M (BIT(7)) 2858 #define GPIO_SIG55_IN_SEL_V 0x1 2859 #define GPIO_SIG55_IN_SEL_S 7 2860 /* GPIO_FUNC55_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 2861 /*description: revert the value of the input if you want to revert please set the value to 1*/ 2862 #define GPIO_FUNC55_IN_INV_SEL (BIT(6)) 2863 #define GPIO_FUNC55_IN_INV_SEL_M (BIT(6)) 2864 #define GPIO_FUNC55_IN_INV_SEL_V 0x1 2865 #define GPIO_FUNC55_IN_INV_SEL_S 6 2866 /* GPIO_FUNC55_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 2867 /*description: select one of the 256 inputs*/ 2868 #define GPIO_FUNC55_IN_SEL 0x0000003F 2869 #define GPIO_FUNC55_IN_SEL_M ((GPIO_FUNC55_IN_SEL_V)<<(GPIO_FUNC55_IN_SEL_S)) 2870 #define GPIO_FUNC55_IN_SEL_V 0x3F 2871 #define GPIO_FUNC55_IN_SEL_S 0 2872 2873 #define GPIO_FUNC56_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0210) 2874 /* GPIO_SIG56_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 2875 /*description: if the slow signal bypass the io matrix or not if you want setting 2876 the value to 1*/ 2877 #define GPIO_SIG56_IN_SEL (BIT(7)) 2878 #define GPIO_SIG56_IN_SEL_M (BIT(7)) 2879 #define GPIO_SIG56_IN_SEL_V 0x1 2880 #define GPIO_SIG56_IN_SEL_S 7 2881 /* GPIO_FUNC56_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 2882 /*description: revert the value of the input if you want to revert please set the value to 1*/ 2883 #define GPIO_FUNC56_IN_INV_SEL (BIT(6)) 2884 #define GPIO_FUNC56_IN_INV_SEL_M (BIT(6)) 2885 #define GPIO_FUNC56_IN_INV_SEL_V 0x1 2886 #define GPIO_FUNC56_IN_INV_SEL_S 6 2887 /* GPIO_FUNC56_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 2888 /*description: select one of the 256 inputs*/ 2889 #define GPIO_FUNC56_IN_SEL 0x0000003F 2890 #define GPIO_FUNC56_IN_SEL_M ((GPIO_FUNC56_IN_SEL_V)<<(GPIO_FUNC56_IN_SEL_S)) 2891 #define GPIO_FUNC56_IN_SEL_V 0x3F 2892 #define GPIO_FUNC56_IN_SEL_S 0 2893 2894 #define GPIO_FUNC57_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0214) 2895 /* GPIO_SIG57_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 2896 /*description: if the slow signal bypass the io matrix or not if you want setting 2897 the value to 1*/ 2898 #define GPIO_SIG57_IN_SEL (BIT(7)) 2899 #define GPIO_SIG57_IN_SEL_M (BIT(7)) 2900 #define GPIO_SIG57_IN_SEL_V 0x1 2901 #define GPIO_SIG57_IN_SEL_S 7 2902 /* GPIO_FUNC57_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 2903 /*description: revert the value of the input if you want to revert please set the value to 1*/ 2904 #define GPIO_FUNC57_IN_INV_SEL (BIT(6)) 2905 #define GPIO_FUNC57_IN_INV_SEL_M (BIT(6)) 2906 #define GPIO_FUNC57_IN_INV_SEL_V 0x1 2907 #define GPIO_FUNC57_IN_INV_SEL_S 6 2908 /* GPIO_FUNC57_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 2909 /*description: select one of the 256 inputs*/ 2910 #define GPIO_FUNC57_IN_SEL 0x0000003F 2911 #define GPIO_FUNC57_IN_SEL_M ((GPIO_FUNC57_IN_SEL_V)<<(GPIO_FUNC57_IN_SEL_S)) 2912 #define GPIO_FUNC57_IN_SEL_V 0x3F 2913 #define GPIO_FUNC57_IN_SEL_S 0 2914 2915 #define GPIO_FUNC58_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0218) 2916 /* GPIO_SIG58_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 2917 /*description: if the slow signal bypass the io matrix or not if you want setting 2918 the value to 1*/ 2919 #define GPIO_SIG58_IN_SEL (BIT(7)) 2920 #define GPIO_SIG58_IN_SEL_M (BIT(7)) 2921 #define GPIO_SIG58_IN_SEL_V 0x1 2922 #define GPIO_SIG58_IN_SEL_S 7 2923 /* GPIO_FUNC58_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 2924 /*description: revert the value of the input if you want to revert please set the value to 1*/ 2925 #define GPIO_FUNC58_IN_INV_SEL (BIT(6)) 2926 #define GPIO_FUNC58_IN_INV_SEL_M (BIT(6)) 2927 #define GPIO_FUNC58_IN_INV_SEL_V 0x1 2928 #define GPIO_FUNC58_IN_INV_SEL_S 6 2929 /* GPIO_FUNC58_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 2930 /*description: select one of the 256 inputs*/ 2931 #define GPIO_FUNC58_IN_SEL 0x0000003F 2932 #define GPIO_FUNC58_IN_SEL_M ((GPIO_FUNC58_IN_SEL_V)<<(GPIO_FUNC58_IN_SEL_S)) 2933 #define GPIO_FUNC58_IN_SEL_V 0x3F 2934 #define GPIO_FUNC58_IN_SEL_S 0 2935 2936 #define GPIO_FUNC59_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x021c) 2937 /* GPIO_SIG59_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 2938 /*description: if the slow signal bypass the io matrix or not if you want setting 2939 the value to 1*/ 2940 #define GPIO_SIG59_IN_SEL (BIT(7)) 2941 #define GPIO_SIG59_IN_SEL_M (BIT(7)) 2942 #define GPIO_SIG59_IN_SEL_V 0x1 2943 #define GPIO_SIG59_IN_SEL_S 7 2944 /* GPIO_FUNC59_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 2945 /*description: revert the value of the input if you want to revert please set the value to 1*/ 2946 #define GPIO_FUNC59_IN_INV_SEL (BIT(6)) 2947 #define GPIO_FUNC59_IN_INV_SEL_M (BIT(6)) 2948 #define GPIO_FUNC59_IN_INV_SEL_V 0x1 2949 #define GPIO_FUNC59_IN_INV_SEL_S 6 2950 /* GPIO_FUNC59_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 2951 /*description: select one of the 256 inputs*/ 2952 #define GPIO_FUNC59_IN_SEL 0x0000003F 2953 #define GPIO_FUNC59_IN_SEL_M ((GPIO_FUNC59_IN_SEL_V)<<(GPIO_FUNC59_IN_SEL_S)) 2954 #define GPIO_FUNC59_IN_SEL_V 0x3F 2955 #define GPIO_FUNC59_IN_SEL_S 0 2956 2957 #define GPIO_FUNC60_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0220) 2958 /* GPIO_SIG60_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 2959 /*description: if the slow signal bypass the io matrix or not if you want setting 2960 the value to 1*/ 2961 #define GPIO_SIG60_IN_SEL (BIT(7)) 2962 #define GPIO_SIG60_IN_SEL_M (BIT(7)) 2963 #define GPIO_SIG60_IN_SEL_V 0x1 2964 #define GPIO_SIG60_IN_SEL_S 7 2965 /* GPIO_FUNC60_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 2966 /*description: revert the value of the input if you want to revert please set the value to 1*/ 2967 #define GPIO_FUNC60_IN_INV_SEL (BIT(6)) 2968 #define GPIO_FUNC60_IN_INV_SEL_M (BIT(6)) 2969 #define GPIO_FUNC60_IN_INV_SEL_V 0x1 2970 #define GPIO_FUNC60_IN_INV_SEL_S 6 2971 /* GPIO_FUNC60_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 2972 /*description: select one of the 256 inputs*/ 2973 #define GPIO_FUNC60_IN_SEL 0x0000003F 2974 #define GPIO_FUNC60_IN_SEL_M ((GPIO_FUNC60_IN_SEL_V)<<(GPIO_FUNC60_IN_SEL_S)) 2975 #define GPIO_FUNC60_IN_SEL_V 0x3F 2976 #define GPIO_FUNC60_IN_SEL_S 0 2977 2978 #define GPIO_FUNC61_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0224) 2979 /* GPIO_SIG61_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 2980 /*description: if the slow signal bypass the io matrix or not if you want setting 2981 the value to 1*/ 2982 #define GPIO_SIG61_IN_SEL (BIT(7)) 2983 #define GPIO_SIG61_IN_SEL_M (BIT(7)) 2984 #define GPIO_SIG61_IN_SEL_V 0x1 2985 #define GPIO_SIG61_IN_SEL_S 7 2986 /* GPIO_FUNC61_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 2987 /*description: revert the value of the input if you want to revert please set the value to 1*/ 2988 #define GPIO_FUNC61_IN_INV_SEL (BIT(6)) 2989 #define GPIO_FUNC61_IN_INV_SEL_M (BIT(6)) 2990 #define GPIO_FUNC61_IN_INV_SEL_V 0x1 2991 #define GPIO_FUNC61_IN_INV_SEL_S 6 2992 /* GPIO_FUNC61_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 2993 /*description: select one of the 256 inputs*/ 2994 #define GPIO_FUNC61_IN_SEL 0x0000003F 2995 #define GPIO_FUNC61_IN_SEL_M ((GPIO_FUNC61_IN_SEL_V)<<(GPIO_FUNC61_IN_SEL_S)) 2996 #define GPIO_FUNC61_IN_SEL_V 0x3F 2997 #define GPIO_FUNC61_IN_SEL_S 0 2998 2999 #define GPIO_FUNC62_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0228) 3000 /* GPIO_SIG62_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 3001 /*description: if the slow signal bypass the io matrix or not if you want setting 3002 the value to 1*/ 3003 #define GPIO_SIG62_IN_SEL (BIT(7)) 3004 #define GPIO_SIG62_IN_SEL_M (BIT(7)) 3005 #define GPIO_SIG62_IN_SEL_V 0x1 3006 #define GPIO_SIG62_IN_SEL_S 7 3007 /* GPIO_FUNC62_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 3008 /*description: revert the value of the input if you want to revert please set the value to 1*/ 3009 #define GPIO_FUNC62_IN_INV_SEL (BIT(6)) 3010 #define GPIO_FUNC62_IN_INV_SEL_M (BIT(6)) 3011 #define GPIO_FUNC62_IN_INV_SEL_V 0x1 3012 #define GPIO_FUNC62_IN_INV_SEL_S 6 3013 /* GPIO_FUNC62_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 3014 /*description: select one of the 256 inputs*/ 3015 #define GPIO_FUNC62_IN_SEL 0x0000003F 3016 #define GPIO_FUNC62_IN_SEL_M ((GPIO_FUNC62_IN_SEL_V)<<(GPIO_FUNC62_IN_SEL_S)) 3017 #define GPIO_FUNC62_IN_SEL_V 0x3F 3018 #define GPIO_FUNC62_IN_SEL_S 0 3019 3020 #define GPIO_FUNC63_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x022c) 3021 /* GPIO_SIG63_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 3022 /*description: if the slow signal bypass the io matrix or not if you want setting 3023 the value to 1*/ 3024 #define GPIO_SIG63_IN_SEL (BIT(7)) 3025 #define GPIO_SIG63_IN_SEL_M (BIT(7)) 3026 #define GPIO_SIG63_IN_SEL_V 0x1 3027 #define GPIO_SIG63_IN_SEL_S 7 3028 /* GPIO_FUNC63_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 3029 /*description: revert the value of the input if you want to revert please set the value to 1*/ 3030 #define GPIO_FUNC63_IN_INV_SEL (BIT(6)) 3031 #define GPIO_FUNC63_IN_INV_SEL_M (BIT(6)) 3032 #define GPIO_FUNC63_IN_INV_SEL_V 0x1 3033 #define GPIO_FUNC63_IN_INV_SEL_S 6 3034 /* GPIO_FUNC63_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 3035 /*description: select one of the 256 inputs*/ 3036 #define GPIO_FUNC63_IN_SEL 0x0000003F 3037 #define GPIO_FUNC63_IN_SEL_M ((GPIO_FUNC63_IN_SEL_V)<<(GPIO_FUNC63_IN_SEL_S)) 3038 #define GPIO_FUNC63_IN_SEL_V 0x3F 3039 #define GPIO_FUNC63_IN_SEL_S 0 3040 3041 #define GPIO_FUNC64_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0230) 3042 /* GPIO_SIG64_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 3043 /*description: if the slow signal bypass the io matrix or not if you want setting 3044 the value to 1*/ 3045 #define GPIO_SIG64_IN_SEL (BIT(7)) 3046 #define GPIO_SIG64_IN_SEL_M (BIT(7)) 3047 #define GPIO_SIG64_IN_SEL_V 0x1 3048 #define GPIO_SIG64_IN_SEL_S 7 3049 /* GPIO_FUNC64_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 3050 /*description: revert the value of the input if you want to revert please set the value to 1*/ 3051 #define GPIO_FUNC64_IN_INV_SEL (BIT(6)) 3052 #define GPIO_FUNC64_IN_INV_SEL_M (BIT(6)) 3053 #define GPIO_FUNC64_IN_INV_SEL_V 0x1 3054 #define GPIO_FUNC64_IN_INV_SEL_S 6 3055 /* GPIO_FUNC64_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 3056 /*description: select one of the 256 inputs*/ 3057 #define GPIO_FUNC64_IN_SEL 0x0000003F 3058 #define GPIO_FUNC64_IN_SEL_M ((GPIO_FUNC64_IN_SEL_V)<<(GPIO_FUNC64_IN_SEL_S)) 3059 #define GPIO_FUNC64_IN_SEL_V 0x3F 3060 #define GPIO_FUNC64_IN_SEL_S 0 3061 3062 #define GPIO_FUNC65_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0234) 3063 /* GPIO_SIG65_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 3064 /*description: if the slow signal bypass the io matrix or not if you want setting 3065 the value to 1*/ 3066 #define GPIO_SIG65_IN_SEL (BIT(7)) 3067 #define GPIO_SIG65_IN_SEL_M (BIT(7)) 3068 #define GPIO_SIG65_IN_SEL_V 0x1 3069 #define GPIO_SIG65_IN_SEL_S 7 3070 /* GPIO_FUNC65_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 3071 /*description: revert the value of the input if you want to revert please set the value to 1*/ 3072 #define GPIO_FUNC65_IN_INV_SEL (BIT(6)) 3073 #define GPIO_FUNC65_IN_INV_SEL_M (BIT(6)) 3074 #define GPIO_FUNC65_IN_INV_SEL_V 0x1 3075 #define GPIO_FUNC65_IN_INV_SEL_S 6 3076 /* GPIO_FUNC65_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 3077 /*description: select one of the 256 inputs*/ 3078 #define GPIO_FUNC65_IN_SEL 0x0000003F 3079 #define GPIO_FUNC65_IN_SEL_M ((GPIO_FUNC65_IN_SEL_V)<<(GPIO_FUNC65_IN_SEL_S)) 3080 #define GPIO_FUNC65_IN_SEL_V 0x3F 3081 #define GPIO_FUNC65_IN_SEL_S 0 3082 3083 #define GPIO_FUNC66_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0238) 3084 /* GPIO_SIG66_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 3085 /*description: if the slow signal bypass the io matrix or not if you want setting 3086 the value to 1*/ 3087 #define GPIO_SIG66_IN_SEL (BIT(7)) 3088 #define GPIO_SIG66_IN_SEL_M (BIT(7)) 3089 #define GPIO_SIG66_IN_SEL_V 0x1 3090 #define GPIO_SIG66_IN_SEL_S 7 3091 /* GPIO_FUNC66_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 3092 /*description: revert the value of the input if you want to revert please set the value to 1*/ 3093 #define GPIO_FUNC66_IN_INV_SEL (BIT(6)) 3094 #define GPIO_FUNC66_IN_INV_SEL_M (BIT(6)) 3095 #define GPIO_FUNC66_IN_INV_SEL_V 0x1 3096 #define GPIO_FUNC66_IN_INV_SEL_S 6 3097 /* GPIO_FUNC66_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 3098 /*description: select one of the 256 inputs*/ 3099 #define GPIO_FUNC66_IN_SEL 0x0000003F 3100 #define GPIO_FUNC66_IN_SEL_M ((GPIO_FUNC66_IN_SEL_V)<<(GPIO_FUNC66_IN_SEL_S)) 3101 #define GPIO_FUNC66_IN_SEL_V 0x3F 3102 #define GPIO_FUNC66_IN_SEL_S 0 3103 3104 #define GPIO_FUNC67_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x023c) 3105 /* GPIO_SIG67_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 3106 /*description: if the slow signal bypass the io matrix or not if you want setting 3107 the value to 1*/ 3108 #define GPIO_SIG67_IN_SEL (BIT(7)) 3109 #define GPIO_SIG67_IN_SEL_M (BIT(7)) 3110 #define GPIO_SIG67_IN_SEL_V 0x1 3111 #define GPIO_SIG67_IN_SEL_S 7 3112 /* GPIO_FUNC67_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 3113 /*description: revert the value of the input if you want to revert please set the value to 1*/ 3114 #define GPIO_FUNC67_IN_INV_SEL (BIT(6)) 3115 #define GPIO_FUNC67_IN_INV_SEL_M (BIT(6)) 3116 #define GPIO_FUNC67_IN_INV_SEL_V 0x1 3117 #define GPIO_FUNC67_IN_INV_SEL_S 6 3118 /* GPIO_FUNC67_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 3119 /*description: select one of the 256 inputs*/ 3120 #define GPIO_FUNC67_IN_SEL 0x0000003F 3121 #define GPIO_FUNC67_IN_SEL_M ((GPIO_FUNC67_IN_SEL_V)<<(GPIO_FUNC67_IN_SEL_S)) 3122 #define GPIO_FUNC67_IN_SEL_V 0x3F 3123 #define GPIO_FUNC67_IN_SEL_S 0 3124 3125 #define GPIO_FUNC68_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0240) 3126 /* GPIO_SIG68_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 3127 /*description: if the slow signal bypass the io matrix or not if you want setting 3128 the value to 1*/ 3129 #define GPIO_SIG68_IN_SEL (BIT(7)) 3130 #define GPIO_SIG68_IN_SEL_M (BIT(7)) 3131 #define GPIO_SIG68_IN_SEL_V 0x1 3132 #define GPIO_SIG68_IN_SEL_S 7 3133 /* GPIO_FUNC68_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 3134 /*description: revert the value of the input if you want to revert please set the value to 1*/ 3135 #define GPIO_FUNC68_IN_INV_SEL (BIT(6)) 3136 #define GPIO_FUNC68_IN_INV_SEL_M (BIT(6)) 3137 #define GPIO_FUNC68_IN_INV_SEL_V 0x1 3138 #define GPIO_FUNC68_IN_INV_SEL_S 6 3139 /* GPIO_FUNC68_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 3140 /*description: select one of the 256 inputs*/ 3141 #define GPIO_FUNC68_IN_SEL 0x0000003F 3142 #define GPIO_FUNC68_IN_SEL_M ((GPIO_FUNC68_IN_SEL_V)<<(GPIO_FUNC68_IN_SEL_S)) 3143 #define GPIO_FUNC68_IN_SEL_V 0x3F 3144 #define GPIO_FUNC68_IN_SEL_S 0 3145 3146 #define GPIO_FUNC69_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0244) 3147 /* GPIO_SIG69_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 3148 /*description: if the slow signal bypass the io matrix or not if you want setting 3149 the value to 1*/ 3150 #define GPIO_SIG69_IN_SEL (BIT(7)) 3151 #define GPIO_SIG69_IN_SEL_M (BIT(7)) 3152 #define GPIO_SIG69_IN_SEL_V 0x1 3153 #define GPIO_SIG69_IN_SEL_S 7 3154 /* GPIO_FUNC69_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 3155 /*description: revert the value of the input if you want to revert please set the value to 1*/ 3156 #define GPIO_FUNC69_IN_INV_SEL (BIT(6)) 3157 #define GPIO_FUNC69_IN_INV_SEL_M (BIT(6)) 3158 #define GPIO_FUNC69_IN_INV_SEL_V 0x1 3159 #define GPIO_FUNC69_IN_INV_SEL_S 6 3160 /* GPIO_FUNC69_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 3161 /*description: select one of the 256 inputs*/ 3162 #define GPIO_FUNC69_IN_SEL 0x0000003F 3163 #define GPIO_FUNC69_IN_SEL_M ((GPIO_FUNC69_IN_SEL_V)<<(GPIO_FUNC69_IN_SEL_S)) 3164 #define GPIO_FUNC69_IN_SEL_V 0x3F 3165 #define GPIO_FUNC69_IN_SEL_S 0 3166 3167 #define GPIO_FUNC70_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0248) 3168 /* GPIO_SIG70_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 3169 /*description: if the slow signal bypass the io matrix or not if you want setting 3170 the value to 1*/ 3171 #define GPIO_SIG70_IN_SEL (BIT(7)) 3172 #define GPIO_SIG70_IN_SEL_M (BIT(7)) 3173 #define GPIO_SIG70_IN_SEL_V 0x1 3174 #define GPIO_SIG70_IN_SEL_S 7 3175 /* GPIO_FUNC70_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 3176 /*description: revert the value of the input if you want to revert please set the value to 1*/ 3177 #define GPIO_FUNC70_IN_INV_SEL (BIT(6)) 3178 #define GPIO_FUNC70_IN_INV_SEL_M (BIT(6)) 3179 #define GPIO_FUNC70_IN_INV_SEL_V 0x1 3180 #define GPIO_FUNC70_IN_INV_SEL_S 6 3181 /* GPIO_FUNC70_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 3182 /*description: select one of the 256 inputs*/ 3183 #define GPIO_FUNC70_IN_SEL 0x0000003F 3184 #define GPIO_FUNC70_IN_SEL_M ((GPIO_FUNC70_IN_SEL_V)<<(GPIO_FUNC70_IN_SEL_S)) 3185 #define GPIO_FUNC70_IN_SEL_V 0x3F 3186 #define GPIO_FUNC70_IN_SEL_S 0 3187 3188 #define GPIO_FUNC71_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x024c) 3189 /* GPIO_SIG71_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 3190 /*description: if the slow signal bypass the io matrix or not if you want setting 3191 the value to 1*/ 3192 #define GPIO_SIG71_IN_SEL (BIT(7)) 3193 #define GPIO_SIG71_IN_SEL_M (BIT(7)) 3194 #define GPIO_SIG71_IN_SEL_V 0x1 3195 #define GPIO_SIG71_IN_SEL_S 7 3196 /* GPIO_FUNC71_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 3197 /*description: revert the value of the input if you want to revert please set the value to 1*/ 3198 #define GPIO_FUNC71_IN_INV_SEL (BIT(6)) 3199 #define GPIO_FUNC71_IN_INV_SEL_M (BIT(6)) 3200 #define GPIO_FUNC71_IN_INV_SEL_V 0x1 3201 #define GPIO_FUNC71_IN_INV_SEL_S 6 3202 /* GPIO_FUNC71_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 3203 /*description: select one of the 256 inputs*/ 3204 #define GPIO_FUNC71_IN_SEL 0x0000003F 3205 #define GPIO_FUNC71_IN_SEL_M ((GPIO_FUNC71_IN_SEL_V)<<(GPIO_FUNC71_IN_SEL_S)) 3206 #define GPIO_FUNC71_IN_SEL_V 0x3F 3207 #define GPIO_FUNC71_IN_SEL_S 0 3208 3209 #define GPIO_FUNC72_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0250) 3210 /* GPIO_SIG72_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 3211 /*description: if the slow signal bypass the io matrix or not if you want setting 3212 the value to 1*/ 3213 #define GPIO_SIG72_IN_SEL (BIT(7)) 3214 #define GPIO_SIG72_IN_SEL_M (BIT(7)) 3215 #define GPIO_SIG72_IN_SEL_V 0x1 3216 #define GPIO_SIG72_IN_SEL_S 7 3217 /* GPIO_FUNC72_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 3218 /*description: revert the value of the input if you want to revert please set the value to 1*/ 3219 #define GPIO_FUNC72_IN_INV_SEL (BIT(6)) 3220 #define GPIO_FUNC72_IN_INV_SEL_M (BIT(6)) 3221 #define GPIO_FUNC72_IN_INV_SEL_V 0x1 3222 #define GPIO_FUNC72_IN_INV_SEL_S 6 3223 /* GPIO_FUNC72_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 3224 /*description: select one of the 256 inputs*/ 3225 #define GPIO_FUNC72_IN_SEL 0x0000003F 3226 #define GPIO_FUNC72_IN_SEL_M ((GPIO_FUNC72_IN_SEL_V)<<(GPIO_FUNC72_IN_SEL_S)) 3227 #define GPIO_FUNC72_IN_SEL_V 0x3F 3228 #define GPIO_FUNC72_IN_SEL_S 0 3229 3230 #define GPIO_FUNC73_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0254) 3231 /* GPIO_SIG73_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 3232 /*description: if the slow signal bypass the io matrix or not if you want setting 3233 the value to 1*/ 3234 #define GPIO_SIG73_IN_SEL (BIT(7)) 3235 #define GPIO_SIG73_IN_SEL_M (BIT(7)) 3236 #define GPIO_SIG73_IN_SEL_V 0x1 3237 #define GPIO_SIG73_IN_SEL_S 7 3238 /* GPIO_FUNC73_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 3239 /*description: revert the value of the input if you want to revert please set the value to 1*/ 3240 #define GPIO_FUNC73_IN_INV_SEL (BIT(6)) 3241 #define GPIO_FUNC73_IN_INV_SEL_M (BIT(6)) 3242 #define GPIO_FUNC73_IN_INV_SEL_V 0x1 3243 #define GPIO_FUNC73_IN_INV_SEL_S 6 3244 /* GPIO_FUNC73_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 3245 /*description: select one of the 256 inputs*/ 3246 #define GPIO_FUNC73_IN_SEL 0x0000003F 3247 #define GPIO_FUNC73_IN_SEL_M ((GPIO_FUNC73_IN_SEL_V)<<(GPIO_FUNC73_IN_SEL_S)) 3248 #define GPIO_FUNC73_IN_SEL_V 0x3F 3249 #define GPIO_FUNC73_IN_SEL_S 0 3250 3251 #define GPIO_FUNC74_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0258) 3252 /* GPIO_SIG74_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 3253 /*description: if the slow signal bypass the io matrix or not if you want setting 3254 the value to 1*/ 3255 #define GPIO_SIG74_IN_SEL (BIT(7)) 3256 #define GPIO_SIG74_IN_SEL_M (BIT(7)) 3257 #define GPIO_SIG74_IN_SEL_V 0x1 3258 #define GPIO_SIG74_IN_SEL_S 7 3259 /* GPIO_FUNC74_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 3260 /*description: revert the value of the input if you want to revert please set the value to 1*/ 3261 #define GPIO_FUNC74_IN_INV_SEL (BIT(6)) 3262 #define GPIO_FUNC74_IN_INV_SEL_M (BIT(6)) 3263 #define GPIO_FUNC74_IN_INV_SEL_V 0x1 3264 #define GPIO_FUNC74_IN_INV_SEL_S 6 3265 /* GPIO_FUNC74_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 3266 /*description: select one of the 256 inputs*/ 3267 #define GPIO_FUNC74_IN_SEL 0x0000003F 3268 #define GPIO_FUNC74_IN_SEL_M ((GPIO_FUNC74_IN_SEL_V)<<(GPIO_FUNC74_IN_SEL_S)) 3269 #define GPIO_FUNC74_IN_SEL_V 0x3F 3270 #define GPIO_FUNC74_IN_SEL_S 0 3271 3272 #define GPIO_FUNC75_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x025c) 3273 /* GPIO_SIG75_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 3274 /*description: if the slow signal bypass the io matrix or not if you want setting 3275 the value to 1*/ 3276 #define GPIO_SIG75_IN_SEL (BIT(7)) 3277 #define GPIO_SIG75_IN_SEL_M (BIT(7)) 3278 #define GPIO_SIG75_IN_SEL_V 0x1 3279 #define GPIO_SIG75_IN_SEL_S 7 3280 /* GPIO_FUNC75_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 3281 /*description: revert the value of the input if you want to revert please set the value to 1*/ 3282 #define GPIO_FUNC75_IN_INV_SEL (BIT(6)) 3283 #define GPIO_FUNC75_IN_INV_SEL_M (BIT(6)) 3284 #define GPIO_FUNC75_IN_INV_SEL_V 0x1 3285 #define GPIO_FUNC75_IN_INV_SEL_S 6 3286 /* GPIO_FUNC75_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 3287 /*description: select one of the 256 inputs*/ 3288 #define GPIO_FUNC75_IN_SEL 0x0000003F 3289 #define GPIO_FUNC75_IN_SEL_M ((GPIO_FUNC75_IN_SEL_V)<<(GPIO_FUNC75_IN_SEL_S)) 3290 #define GPIO_FUNC75_IN_SEL_V 0x3F 3291 #define GPIO_FUNC75_IN_SEL_S 0 3292 3293 #define GPIO_FUNC76_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0260) 3294 /* GPIO_SIG76_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 3295 /*description: if the slow signal bypass the io matrix or not if you want setting 3296 the value to 1*/ 3297 #define GPIO_SIG76_IN_SEL (BIT(7)) 3298 #define GPIO_SIG76_IN_SEL_M (BIT(7)) 3299 #define GPIO_SIG76_IN_SEL_V 0x1 3300 #define GPIO_SIG76_IN_SEL_S 7 3301 /* GPIO_FUNC76_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 3302 /*description: revert the value of the input if you want to revert please set the value to 1*/ 3303 #define GPIO_FUNC76_IN_INV_SEL (BIT(6)) 3304 #define GPIO_FUNC76_IN_INV_SEL_M (BIT(6)) 3305 #define GPIO_FUNC76_IN_INV_SEL_V 0x1 3306 #define GPIO_FUNC76_IN_INV_SEL_S 6 3307 /* GPIO_FUNC76_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 3308 /*description: select one of the 256 inputs*/ 3309 #define GPIO_FUNC76_IN_SEL 0x0000003F 3310 #define GPIO_FUNC76_IN_SEL_M ((GPIO_FUNC76_IN_SEL_V)<<(GPIO_FUNC76_IN_SEL_S)) 3311 #define GPIO_FUNC76_IN_SEL_V 0x3F 3312 #define GPIO_FUNC76_IN_SEL_S 0 3313 3314 #define GPIO_FUNC77_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0264) 3315 /* GPIO_SIG77_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 3316 /*description: if the slow signal bypass the io matrix or not if you want setting 3317 the value to 1*/ 3318 #define GPIO_SIG77_IN_SEL (BIT(7)) 3319 #define GPIO_SIG77_IN_SEL_M (BIT(7)) 3320 #define GPIO_SIG77_IN_SEL_V 0x1 3321 #define GPIO_SIG77_IN_SEL_S 7 3322 /* GPIO_FUNC77_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 3323 /*description: revert the value of the input if you want to revert please set the value to 1*/ 3324 #define GPIO_FUNC77_IN_INV_SEL (BIT(6)) 3325 #define GPIO_FUNC77_IN_INV_SEL_M (BIT(6)) 3326 #define GPIO_FUNC77_IN_INV_SEL_V 0x1 3327 #define GPIO_FUNC77_IN_INV_SEL_S 6 3328 /* GPIO_FUNC77_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 3329 /*description: select one of the 256 inputs*/ 3330 #define GPIO_FUNC77_IN_SEL 0x0000003F 3331 #define GPIO_FUNC77_IN_SEL_M ((GPIO_FUNC77_IN_SEL_V)<<(GPIO_FUNC77_IN_SEL_S)) 3332 #define GPIO_FUNC77_IN_SEL_V 0x3F 3333 #define GPIO_FUNC77_IN_SEL_S 0 3334 3335 #define GPIO_FUNC78_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0268) 3336 /* GPIO_SIG78_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 3337 /*description: if the slow signal bypass the io matrix or not if you want setting 3338 the value to 1*/ 3339 #define GPIO_SIG78_IN_SEL (BIT(7)) 3340 #define GPIO_SIG78_IN_SEL_M (BIT(7)) 3341 #define GPIO_SIG78_IN_SEL_V 0x1 3342 #define GPIO_SIG78_IN_SEL_S 7 3343 /* GPIO_FUNC78_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 3344 /*description: revert the value of the input if you want to revert please set the value to 1*/ 3345 #define GPIO_FUNC78_IN_INV_SEL (BIT(6)) 3346 #define GPIO_FUNC78_IN_INV_SEL_M (BIT(6)) 3347 #define GPIO_FUNC78_IN_INV_SEL_V 0x1 3348 #define GPIO_FUNC78_IN_INV_SEL_S 6 3349 /* GPIO_FUNC78_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 3350 /*description: select one of the 256 inputs*/ 3351 #define GPIO_FUNC78_IN_SEL 0x0000003F 3352 #define GPIO_FUNC78_IN_SEL_M ((GPIO_FUNC78_IN_SEL_V)<<(GPIO_FUNC78_IN_SEL_S)) 3353 #define GPIO_FUNC78_IN_SEL_V 0x3F 3354 #define GPIO_FUNC78_IN_SEL_S 0 3355 3356 #define GPIO_FUNC79_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x026c) 3357 /* GPIO_SIG79_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 3358 /*description: if the slow signal bypass the io matrix or not if you want setting 3359 the value to 1*/ 3360 #define GPIO_SIG79_IN_SEL (BIT(7)) 3361 #define GPIO_SIG79_IN_SEL_M (BIT(7)) 3362 #define GPIO_SIG79_IN_SEL_V 0x1 3363 #define GPIO_SIG79_IN_SEL_S 7 3364 /* GPIO_FUNC79_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 3365 /*description: revert the value of the input if you want to revert please set the value to 1*/ 3366 #define GPIO_FUNC79_IN_INV_SEL (BIT(6)) 3367 #define GPIO_FUNC79_IN_INV_SEL_M (BIT(6)) 3368 #define GPIO_FUNC79_IN_INV_SEL_V 0x1 3369 #define GPIO_FUNC79_IN_INV_SEL_S 6 3370 /* GPIO_FUNC79_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 3371 /*description: select one of the 256 inputs*/ 3372 #define GPIO_FUNC79_IN_SEL 0x0000003F 3373 #define GPIO_FUNC79_IN_SEL_M ((GPIO_FUNC79_IN_SEL_V)<<(GPIO_FUNC79_IN_SEL_S)) 3374 #define GPIO_FUNC79_IN_SEL_V 0x3F 3375 #define GPIO_FUNC79_IN_SEL_S 0 3376 3377 #define GPIO_FUNC80_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0270) 3378 /* GPIO_SIG80_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 3379 /*description: if the slow signal bypass the io matrix or not if you want setting 3380 the value to 1*/ 3381 #define GPIO_SIG80_IN_SEL (BIT(7)) 3382 #define GPIO_SIG80_IN_SEL_M (BIT(7)) 3383 #define GPIO_SIG80_IN_SEL_V 0x1 3384 #define GPIO_SIG80_IN_SEL_S 7 3385 /* GPIO_FUNC80_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 3386 /*description: revert the value of the input if you want to revert please set the value to 1*/ 3387 #define GPIO_FUNC80_IN_INV_SEL (BIT(6)) 3388 #define GPIO_FUNC80_IN_INV_SEL_M (BIT(6)) 3389 #define GPIO_FUNC80_IN_INV_SEL_V 0x1 3390 #define GPIO_FUNC80_IN_INV_SEL_S 6 3391 /* GPIO_FUNC80_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 3392 /*description: select one of the 256 inputs*/ 3393 #define GPIO_FUNC80_IN_SEL 0x0000003F 3394 #define GPIO_FUNC80_IN_SEL_M ((GPIO_FUNC80_IN_SEL_V)<<(GPIO_FUNC80_IN_SEL_S)) 3395 #define GPIO_FUNC80_IN_SEL_V 0x3F 3396 #define GPIO_FUNC80_IN_SEL_S 0 3397 3398 #define GPIO_FUNC81_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0274) 3399 /* GPIO_SIG81_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 3400 /*description: if the slow signal bypass the io matrix or not if you want setting 3401 the value to 1*/ 3402 #define GPIO_SIG81_IN_SEL (BIT(7)) 3403 #define GPIO_SIG81_IN_SEL_M (BIT(7)) 3404 #define GPIO_SIG81_IN_SEL_V 0x1 3405 #define GPIO_SIG81_IN_SEL_S 7 3406 /* GPIO_FUNC81_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 3407 /*description: revert the value of the input if you want to revert please set the value to 1*/ 3408 #define GPIO_FUNC81_IN_INV_SEL (BIT(6)) 3409 #define GPIO_FUNC81_IN_INV_SEL_M (BIT(6)) 3410 #define GPIO_FUNC81_IN_INV_SEL_V 0x1 3411 #define GPIO_FUNC81_IN_INV_SEL_S 6 3412 /* GPIO_FUNC81_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 3413 /*description: select one of the 256 inputs*/ 3414 #define GPIO_FUNC81_IN_SEL 0x0000003F 3415 #define GPIO_FUNC81_IN_SEL_M ((GPIO_FUNC81_IN_SEL_V)<<(GPIO_FUNC81_IN_SEL_S)) 3416 #define GPIO_FUNC81_IN_SEL_V 0x3F 3417 #define GPIO_FUNC81_IN_SEL_S 0 3418 3419 #define GPIO_FUNC82_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0278) 3420 /* GPIO_SIG82_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 3421 /*description: if the slow signal bypass the io matrix or not if you want setting 3422 the value to 1*/ 3423 #define GPIO_SIG82_IN_SEL (BIT(7)) 3424 #define GPIO_SIG82_IN_SEL_M (BIT(7)) 3425 #define GPIO_SIG82_IN_SEL_V 0x1 3426 #define GPIO_SIG82_IN_SEL_S 7 3427 /* GPIO_FUNC82_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 3428 /*description: revert the value of the input if you want to revert please set the value to 1*/ 3429 #define GPIO_FUNC82_IN_INV_SEL (BIT(6)) 3430 #define GPIO_FUNC82_IN_INV_SEL_M (BIT(6)) 3431 #define GPIO_FUNC82_IN_INV_SEL_V 0x1 3432 #define GPIO_FUNC82_IN_INV_SEL_S 6 3433 /* GPIO_FUNC82_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 3434 /*description: select one of the 256 inputs*/ 3435 #define GPIO_FUNC82_IN_SEL 0x0000003F 3436 #define GPIO_FUNC82_IN_SEL_M ((GPIO_FUNC82_IN_SEL_V)<<(GPIO_FUNC82_IN_SEL_S)) 3437 #define GPIO_FUNC82_IN_SEL_V 0x3F 3438 #define GPIO_FUNC82_IN_SEL_S 0 3439 3440 #define GPIO_FUNC83_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x027c) 3441 /* GPIO_SIG83_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 3442 /*description: if the slow signal bypass the io matrix or not if you want setting 3443 the value to 1*/ 3444 #define GPIO_SIG83_IN_SEL (BIT(7)) 3445 #define GPIO_SIG83_IN_SEL_M (BIT(7)) 3446 #define GPIO_SIG83_IN_SEL_V 0x1 3447 #define GPIO_SIG83_IN_SEL_S 7 3448 /* GPIO_FUNC83_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 3449 /*description: revert the value of the input if you want to revert please set the value to 1*/ 3450 #define GPIO_FUNC83_IN_INV_SEL (BIT(6)) 3451 #define GPIO_FUNC83_IN_INV_SEL_M (BIT(6)) 3452 #define GPIO_FUNC83_IN_INV_SEL_V 0x1 3453 #define GPIO_FUNC83_IN_INV_SEL_S 6 3454 /* GPIO_FUNC83_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 3455 /*description: select one of the 256 inputs*/ 3456 #define GPIO_FUNC83_IN_SEL 0x0000003F 3457 #define GPIO_FUNC83_IN_SEL_M ((GPIO_FUNC83_IN_SEL_V)<<(GPIO_FUNC83_IN_SEL_S)) 3458 #define GPIO_FUNC83_IN_SEL_V 0x3F 3459 #define GPIO_FUNC83_IN_SEL_S 0 3460 3461 #define GPIO_FUNC84_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0280) 3462 /* GPIO_SIG84_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 3463 /*description: if the slow signal bypass the io matrix or not if you want setting 3464 the value to 1*/ 3465 #define GPIO_SIG84_IN_SEL (BIT(7)) 3466 #define GPIO_SIG84_IN_SEL_M (BIT(7)) 3467 #define GPIO_SIG84_IN_SEL_V 0x1 3468 #define GPIO_SIG84_IN_SEL_S 7 3469 /* GPIO_FUNC84_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 3470 /*description: revert the value of the input if you want to revert please set the value to 1*/ 3471 #define GPIO_FUNC84_IN_INV_SEL (BIT(6)) 3472 #define GPIO_FUNC84_IN_INV_SEL_M (BIT(6)) 3473 #define GPIO_FUNC84_IN_INV_SEL_V 0x1 3474 #define GPIO_FUNC84_IN_INV_SEL_S 6 3475 /* GPIO_FUNC84_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 3476 /*description: select one of the 256 inputs*/ 3477 #define GPIO_FUNC84_IN_SEL 0x0000003F 3478 #define GPIO_FUNC84_IN_SEL_M ((GPIO_FUNC84_IN_SEL_V)<<(GPIO_FUNC84_IN_SEL_S)) 3479 #define GPIO_FUNC84_IN_SEL_V 0x3F 3480 #define GPIO_FUNC84_IN_SEL_S 0 3481 3482 #define GPIO_FUNC85_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0284) 3483 /* GPIO_SIG85_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 3484 /*description: if the slow signal bypass the io matrix or not if you want setting 3485 the value to 1*/ 3486 #define GPIO_SIG85_IN_SEL (BIT(7)) 3487 #define GPIO_SIG85_IN_SEL_M (BIT(7)) 3488 #define GPIO_SIG85_IN_SEL_V 0x1 3489 #define GPIO_SIG85_IN_SEL_S 7 3490 /* GPIO_FUNC85_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 3491 /*description: revert the value of the input if you want to revert please set the value to 1*/ 3492 #define GPIO_FUNC85_IN_INV_SEL (BIT(6)) 3493 #define GPIO_FUNC85_IN_INV_SEL_M (BIT(6)) 3494 #define GPIO_FUNC85_IN_INV_SEL_V 0x1 3495 #define GPIO_FUNC85_IN_INV_SEL_S 6 3496 /* GPIO_FUNC85_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 3497 /*description: select one of the 256 inputs*/ 3498 #define GPIO_FUNC85_IN_SEL 0x0000003F 3499 #define GPIO_FUNC85_IN_SEL_M ((GPIO_FUNC85_IN_SEL_V)<<(GPIO_FUNC85_IN_SEL_S)) 3500 #define GPIO_FUNC85_IN_SEL_V 0x3F 3501 #define GPIO_FUNC85_IN_SEL_S 0 3502 3503 #define GPIO_FUNC86_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0288) 3504 /* GPIO_SIG86_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 3505 /*description: if the slow signal bypass the io matrix or not if you want setting 3506 the value to 1*/ 3507 #define GPIO_SIG86_IN_SEL (BIT(7)) 3508 #define GPIO_SIG86_IN_SEL_M (BIT(7)) 3509 #define GPIO_SIG86_IN_SEL_V 0x1 3510 #define GPIO_SIG86_IN_SEL_S 7 3511 /* GPIO_FUNC86_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 3512 /*description: revert the value of the input if you want to revert please set the value to 1*/ 3513 #define GPIO_FUNC86_IN_INV_SEL (BIT(6)) 3514 #define GPIO_FUNC86_IN_INV_SEL_M (BIT(6)) 3515 #define GPIO_FUNC86_IN_INV_SEL_V 0x1 3516 #define GPIO_FUNC86_IN_INV_SEL_S 6 3517 /* GPIO_FUNC86_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 3518 /*description: select one of the 256 inputs*/ 3519 #define GPIO_FUNC86_IN_SEL 0x0000003F 3520 #define GPIO_FUNC86_IN_SEL_M ((GPIO_FUNC86_IN_SEL_V)<<(GPIO_FUNC86_IN_SEL_S)) 3521 #define GPIO_FUNC86_IN_SEL_V 0x3F 3522 #define GPIO_FUNC86_IN_SEL_S 0 3523 3524 #define GPIO_FUNC87_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x028c) 3525 /* GPIO_SIG87_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 3526 /*description: if the slow signal bypass the io matrix or not if you want setting 3527 the value to 1*/ 3528 #define GPIO_SIG87_IN_SEL (BIT(7)) 3529 #define GPIO_SIG87_IN_SEL_M (BIT(7)) 3530 #define GPIO_SIG87_IN_SEL_V 0x1 3531 #define GPIO_SIG87_IN_SEL_S 7 3532 /* GPIO_FUNC87_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 3533 /*description: revert the value of the input if you want to revert please set the value to 1*/ 3534 #define GPIO_FUNC87_IN_INV_SEL (BIT(6)) 3535 #define GPIO_FUNC87_IN_INV_SEL_M (BIT(6)) 3536 #define GPIO_FUNC87_IN_INV_SEL_V 0x1 3537 #define GPIO_FUNC87_IN_INV_SEL_S 6 3538 /* GPIO_FUNC87_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 3539 /*description: select one of the 256 inputs*/ 3540 #define GPIO_FUNC87_IN_SEL 0x0000003F 3541 #define GPIO_FUNC87_IN_SEL_M ((GPIO_FUNC87_IN_SEL_V)<<(GPIO_FUNC87_IN_SEL_S)) 3542 #define GPIO_FUNC87_IN_SEL_V 0x3F 3543 #define GPIO_FUNC87_IN_SEL_S 0 3544 3545 #define GPIO_FUNC88_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0290) 3546 /* GPIO_SIG88_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 3547 /*description: if the slow signal bypass the io matrix or not if you want setting 3548 the value to 1*/ 3549 #define GPIO_SIG88_IN_SEL (BIT(7)) 3550 #define GPIO_SIG88_IN_SEL_M (BIT(7)) 3551 #define GPIO_SIG88_IN_SEL_V 0x1 3552 #define GPIO_SIG88_IN_SEL_S 7 3553 /* GPIO_FUNC88_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 3554 /*description: revert the value of the input if you want to revert please set the value to 1*/ 3555 #define GPIO_FUNC88_IN_INV_SEL (BIT(6)) 3556 #define GPIO_FUNC88_IN_INV_SEL_M (BIT(6)) 3557 #define GPIO_FUNC88_IN_INV_SEL_V 0x1 3558 #define GPIO_FUNC88_IN_INV_SEL_S 6 3559 /* GPIO_FUNC88_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 3560 /*description: select one of the 256 inputs*/ 3561 #define GPIO_FUNC88_IN_SEL 0x0000003F 3562 #define GPIO_FUNC88_IN_SEL_M ((GPIO_FUNC88_IN_SEL_V)<<(GPIO_FUNC88_IN_SEL_S)) 3563 #define GPIO_FUNC88_IN_SEL_V 0x3F 3564 #define GPIO_FUNC88_IN_SEL_S 0 3565 3566 #define GPIO_FUNC89_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0294) 3567 /* GPIO_SIG89_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 3568 /*description: if the slow signal bypass the io matrix or not if you want setting 3569 the value to 1*/ 3570 #define GPIO_SIG89_IN_SEL (BIT(7)) 3571 #define GPIO_SIG89_IN_SEL_M (BIT(7)) 3572 #define GPIO_SIG89_IN_SEL_V 0x1 3573 #define GPIO_SIG89_IN_SEL_S 7 3574 /* GPIO_FUNC89_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 3575 /*description: revert the value of the input if you want to revert please set the value to 1*/ 3576 #define GPIO_FUNC89_IN_INV_SEL (BIT(6)) 3577 #define GPIO_FUNC89_IN_INV_SEL_M (BIT(6)) 3578 #define GPIO_FUNC89_IN_INV_SEL_V 0x1 3579 #define GPIO_FUNC89_IN_INV_SEL_S 6 3580 /* GPIO_FUNC89_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 3581 /*description: select one of the 256 inputs*/ 3582 #define GPIO_FUNC89_IN_SEL 0x0000003F 3583 #define GPIO_FUNC89_IN_SEL_M ((GPIO_FUNC89_IN_SEL_V)<<(GPIO_FUNC89_IN_SEL_S)) 3584 #define GPIO_FUNC89_IN_SEL_V 0x3F 3585 #define GPIO_FUNC89_IN_SEL_S 0 3586 3587 #define GPIO_FUNC90_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0298) 3588 /* GPIO_SIG90_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 3589 /*description: if the slow signal bypass the io matrix or not if you want setting 3590 the value to 1*/ 3591 #define GPIO_SIG90_IN_SEL (BIT(7)) 3592 #define GPIO_SIG90_IN_SEL_M (BIT(7)) 3593 #define GPIO_SIG90_IN_SEL_V 0x1 3594 #define GPIO_SIG90_IN_SEL_S 7 3595 /* GPIO_FUNC90_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 3596 /*description: revert the value of the input if you want to revert please set the value to 1*/ 3597 #define GPIO_FUNC90_IN_INV_SEL (BIT(6)) 3598 #define GPIO_FUNC90_IN_INV_SEL_M (BIT(6)) 3599 #define GPIO_FUNC90_IN_INV_SEL_V 0x1 3600 #define GPIO_FUNC90_IN_INV_SEL_S 6 3601 /* GPIO_FUNC90_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 3602 /*description: select one of the 256 inputs*/ 3603 #define GPIO_FUNC90_IN_SEL 0x0000003F 3604 #define GPIO_FUNC90_IN_SEL_M ((GPIO_FUNC90_IN_SEL_V)<<(GPIO_FUNC90_IN_SEL_S)) 3605 #define GPIO_FUNC90_IN_SEL_V 0x3F 3606 #define GPIO_FUNC90_IN_SEL_S 0 3607 3608 #define GPIO_FUNC91_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x029c) 3609 /* GPIO_SIG91_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 3610 /*description: if the slow signal bypass the io matrix or not if you want setting 3611 the value to 1*/ 3612 #define GPIO_SIG91_IN_SEL (BIT(7)) 3613 #define GPIO_SIG91_IN_SEL_M (BIT(7)) 3614 #define GPIO_SIG91_IN_SEL_V 0x1 3615 #define GPIO_SIG91_IN_SEL_S 7 3616 /* GPIO_FUNC91_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 3617 /*description: revert the value of the input if you want to revert please set the value to 1*/ 3618 #define GPIO_FUNC91_IN_INV_SEL (BIT(6)) 3619 #define GPIO_FUNC91_IN_INV_SEL_M (BIT(6)) 3620 #define GPIO_FUNC91_IN_INV_SEL_V 0x1 3621 #define GPIO_FUNC91_IN_INV_SEL_S 6 3622 /* GPIO_FUNC91_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 3623 /*description: select one of the 256 inputs*/ 3624 #define GPIO_FUNC91_IN_SEL 0x0000003F 3625 #define GPIO_FUNC91_IN_SEL_M ((GPIO_FUNC91_IN_SEL_V)<<(GPIO_FUNC91_IN_SEL_S)) 3626 #define GPIO_FUNC91_IN_SEL_V 0x3F 3627 #define GPIO_FUNC91_IN_SEL_S 0 3628 3629 #define GPIO_FUNC92_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02a0) 3630 /* GPIO_SIG92_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 3631 /*description: if the slow signal bypass the io matrix or not if you want setting 3632 the value to 1*/ 3633 #define GPIO_SIG92_IN_SEL (BIT(7)) 3634 #define GPIO_SIG92_IN_SEL_M (BIT(7)) 3635 #define GPIO_SIG92_IN_SEL_V 0x1 3636 #define GPIO_SIG92_IN_SEL_S 7 3637 /* GPIO_FUNC92_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 3638 /*description: revert the value of the input if you want to revert please set the value to 1*/ 3639 #define GPIO_FUNC92_IN_INV_SEL (BIT(6)) 3640 #define GPIO_FUNC92_IN_INV_SEL_M (BIT(6)) 3641 #define GPIO_FUNC92_IN_INV_SEL_V 0x1 3642 #define GPIO_FUNC92_IN_INV_SEL_S 6 3643 /* GPIO_FUNC92_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 3644 /*description: select one of the 256 inputs*/ 3645 #define GPIO_FUNC92_IN_SEL 0x0000003F 3646 #define GPIO_FUNC92_IN_SEL_M ((GPIO_FUNC92_IN_SEL_V)<<(GPIO_FUNC92_IN_SEL_S)) 3647 #define GPIO_FUNC92_IN_SEL_V 0x3F 3648 #define GPIO_FUNC92_IN_SEL_S 0 3649 3650 #define GPIO_FUNC93_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02a4) 3651 /* GPIO_SIG93_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 3652 /*description: if the slow signal bypass the io matrix or not if you want setting 3653 the value to 1*/ 3654 #define GPIO_SIG93_IN_SEL (BIT(7)) 3655 #define GPIO_SIG93_IN_SEL_M (BIT(7)) 3656 #define GPIO_SIG93_IN_SEL_V 0x1 3657 #define GPIO_SIG93_IN_SEL_S 7 3658 /* GPIO_FUNC93_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 3659 /*description: revert the value of the input if you want to revert please set the value to 1*/ 3660 #define GPIO_FUNC93_IN_INV_SEL (BIT(6)) 3661 #define GPIO_FUNC93_IN_INV_SEL_M (BIT(6)) 3662 #define GPIO_FUNC93_IN_INV_SEL_V 0x1 3663 #define GPIO_FUNC93_IN_INV_SEL_S 6 3664 /* GPIO_FUNC93_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 3665 /*description: select one of the 256 inputs*/ 3666 #define GPIO_FUNC93_IN_SEL 0x0000003F 3667 #define GPIO_FUNC93_IN_SEL_M ((GPIO_FUNC93_IN_SEL_V)<<(GPIO_FUNC93_IN_SEL_S)) 3668 #define GPIO_FUNC93_IN_SEL_V 0x3F 3669 #define GPIO_FUNC93_IN_SEL_S 0 3670 3671 #define GPIO_FUNC94_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02a8) 3672 /* GPIO_SIG94_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 3673 /*description: if the slow signal bypass the io matrix or not if you want setting 3674 the value to 1*/ 3675 #define GPIO_SIG94_IN_SEL (BIT(7)) 3676 #define GPIO_SIG94_IN_SEL_M (BIT(7)) 3677 #define GPIO_SIG94_IN_SEL_V 0x1 3678 #define GPIO_SIG94_IN_SEL_S 7 3679 /* GPIO_FUNC94_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 3680 /*description: revert the value of the input if you want to revert please set the value to 1*/ 3681 #define GPIO_FUNC94_IN_INV_SEL (BIT(6)) 3682 #define GPIO_FUNC94_IN_INV_SEL_M (BIT(6)) 3683 #define GPIO_FUNC94_IN_INV_SEL_V 0x1 3684 #define GPIO_FUNC94_IN_INV_SEL_S 6 3685 /* GPIO_FUNC94_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 3686 /*description: select one of the 256 inputs*/ 3687 #define GPIO_FUNC94_IN_SEL 0x0000003F 3688 #define GPIO_FUNC94_IN_SEL_M ((GPIO_FUNC94_IN_SEL_V)<<(GPIO_FUNC94_IN_SEL_S)) 3689 #define GPIO_FUNC94_IN_SEL_V 0x3F 3690 #define GPIO_FUNC94_IN_SEL_S 0 3691 3692 #define GPIO_FUNC95_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02ac) 3693 /* GPIO_SIG95_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 3694 /*description: if the slow signal bypass the io matrix or not if you want setting 3695 the value to 1*/ 3696 #define GPIO_SIG95_IN_SEL (BIT(7)) 3697 #define GPIO_SIG95_IN_SEL_M (BIT(7)) 3698 #define GPIO_SIG95_IN_SEL_V 0x1 3699 #define GPIO_SIG95_IN_SEL_S 7 3700 /* GPIO_FUNC95_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 3701 /*description: revert the value of the input if you want to revert please set the value to 1*/ 3702 #define GPIO_FUNC95_IN_INV_SEL (BIT(6)) 3703 #define GPIO_FUNC95_IN_INV_SEL_M (BIT(6)) 3704 #define GPIO_FUNC95_IN_INV_SEL_V 0x1 3705 #define GPIO_FUNC95_IN_INV_SEL_S 6 3706 /* GPIO_FUNC95_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 3707 /*description: select one of the 256 inputs*/ 3708 #define GPIO_FUNC95_IN_SEL 0x0000003F 3709 #define GPIO_FUNC95_IN_SEL_M ((GPIO_FUNC95_IN_SEL_V)<<(GPIO_FUNC95_IN_SEL_S)) 3710 #define GPIO_FUNC95_IN_SEL_V 0x3F 3711 #define GPIO_FUNC95_IN_SEL_S 0 3712 3713 #define GPIO_FUNC96_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02b0) 3714 /* GPIO_SIG96_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 3715 /*description: if the slow signal bypass the io matrix or not if you want setting 3716 the value to 1*/ 3717 #define GPIO_SIG96_IN_SEL (BIT(7)) 3718 #define GPIO_SIG96_IN_SEL_M (BIT(7)) 3719 #define GPIO_SIG96_IN_SEL_V 0x1 3720 #define GPIO_SIG96_IN_SEL_S 7 3721 /* GPIO_FUNC96_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 3722 /*description: revert the value of the input if you want to revert please set the value to 1*/ 3723 #define GPIO_FUNC96_IN_INV_SEL (BIT(6)) 3724 #define GPIO_FUNC96_IN_INV_SEL_M (BIT(6)) 3725 #define GPIO_FUNC96_IN_INV_SEL_V 0x1 3726 #define GPIO_FUNC96_IN_INV_SEL_S 6 3727 /* GPIO_FUNC96_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 3728 /*description: select one of the 256 inputs*/ 3729 #define GPIO_FUNC96_IN_SEL 0x0000003F 3730 #define GPIO_FUNC96_IN_SEL_M ((GPIO_FUNC96_IN_SEL_V)<<(GPIO_FUNC96_IN_SEL_S)) 3731 #define GPIO_FUNC96_IN_SEL_V 0x3F 3732 #define GPIO_FUNC96_IN_SEL_S 0 3733 3734 #define GPIO_FUNC97_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02b4) 3735 /* GPIO_SIG97_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 3736 /*description: if the slow signal bypass the io matrix or not if you want setting 3737 the value to 1*/ 3738 #define GPIO_SIG97_IN_SEL (BIT(7)) 3739 #define GPIO_SIG97_IN_SEL_M (BIT(7)) 3740 #define GPIO_SIG97_IN_SEL_V 0x1 3741 #define GPIO_SIG97_IN_SEL_S 7 3742 /* GPIO_FUNC97_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 3743 /*description: revert the value of the input if you want to revert please set the value to 1*/ 3744 #define GPIO_FUNC97_IN_INV_SEL (BIT(6)) 3745 #define GPIO_FUNC97_IN_INV_SEL_M (BIT(6)) 3746 #define GPIO_FUNC97_IN_INV_SEL_V 0x1 3747 #define GPIO_FUNC97_IN_INV_SEL_S 6 3748 /* GPIO_FUNC97_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 3749 /*description: select one of the 256 inputs*/ 3750 #define GPIO_FUNC97_IN_SEL 0x0000003F 3751 #define GPIO_FUNC97_IN_SEL_M ((GPIO_FUNC97_IN_SEL_V)<<(GPIO_FUNC97_IN_SEL_S)) 3752 #define GPIO_FUNC97_IN_SEL_V 0x3F 3753 #define GPIO_FUNC97_IN_SEL_S 0 3754 3755 #define GPIO_FUNC98_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02b8) 3756 /* GPIO_SIG98_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 3757 /*description: if the slow signal bypass the io matrix or not if you want setting 3758 the value to 1*/ 3759 #define GPIO_SIG98_IN_SEL (BIT(7)) 3760 #define GPIO_SIG98_IN_SEL_M (BIT(7)) 3761 #define GPIO_SIG98_IN_SEL_V 0x1 3762 #define GPIO_SIG98_IN_SEL_S 7 3763 /* GPIO_FUNC98_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 3764 /*description: revert the value of the input if you want to revert please set the value to 1*/ 3765 #define GPIO_FUNC98_IN_INV_SEL (BIT(6)) 3766 #define GPIO_FUNC98_IN_INV_SEL_M (BIT(6)) 3767 #define GPIO_FUNC98_IN_INV_SEL_V 0x1 3768 #define GPIO_FUNC98_IN_INV_SEL_S 6 3769 /* GPIO_FUNC98_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 3770 /*description: select one of the 256 inputs*/ 3771 #define GPIO_FUNC98_IN_SEL 0x0000003F 3772 #define GPIO_FUNC98_IN_SEL_M ((GPIO_FUNC98_IN_SEL_V)<<(GPIO_FUNC98_IN_SEL_S)) 3773 #define GPIO_FUNC98_IN_SEL_V 0x3F 3774 #define GPIO_FUNC98_IN_SEL_S 0 3775 3776 #define GPIO_FUNC99_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02bc) 3777 /* GPIO_SIG99_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 3778 /*description: if the slow signal bypass the io matrix or not if you want setting 3779 the value to 1*/ 3780 #define GPIO_SIG99_IN_SEL (BIT(7)) 3781 #define GPIO_SIG99_IN_SEL_M (BIT(7)) 3782 #define GPIO_SIG99_IN_SEL_V 0x1 3783 #define GPIO_SIG99_IN_SEL_S 7 3784 /* GPIO_FUNC99_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 3785 /*description: revert the value of the input if you want to revert please set the value to 1*/ 3786 #define GPIO_FUNC99_IN_INV_SEL (BIT(6)) 3787 #define GPIO_FUNC99_IN_INV_SEL_M (BIT(6)) 3788 #define GPIO_FUNC99_IN_INV_SEL_V 0x1 3789 #define GPIO_FUNC99_IN_INV_SEL_S 6 3790 /* GPIO_FUNC99_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 3791 /*description: select one of the 256 inputs*/ 3792 #define GPIO_FUNC99_IN_SEL 0x0000003F 3793 #define GPIO_FUNC99_IN_SEL_M ((GPIO_FUNC99_IN_SEL_V)<<(GPIO_FUNC99_IN_SEL_S)) 3794 #define GPIO_FUNC99_IN_SEL_V 0x3F 3795 #define GPIO_FUNC99_IN_SEL_S 0 3796 3797 #define GPIO_FUNC100_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02c0) 3798 /* GPIO_SIG100_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 3799 /*description: if the slow signal bypass the io matrix or not if you want setting 3800 the value to 1*/ 3801 #define GPIO_SIG100_IN_SEL (BIT(7)) 3802 #define GPIO_SIG100_IN_SEL_M (BIT(7)) 3803 #define GPIO_SIG100_IN_SEL_V 0x1 3804 #define GPIO_SIG100_IN_SEL_S 7 3805 /* GPIO_FUNC100_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 3806 /*description: revert the value of the input if you want to revert please set the value to 1*/ 3807 #define GPIO_FUNC100_IN_INV_SEL (BIT(6)) 3808 #define GPIO_FUNC100_IN_INV_SEL_M (BIT(6)) 3809 #define GPIO_FUNC100_IN_INV_SEL_V 0x1 3810 #define GPIO_FUNC100_IN_INV_SEL_S 6 3811 /* GPIO_FUNC100_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 3812 /*description: select one of the 256 inputs*/ 3813 #define GPIO_FUNC100_IN_SEL 0x0000003F 3814 #define GPIO_FUNC100_IN_SEL_M ((GPIO_FUNC100_IN_SEL_V)<<(GPIO_FUNC100_IN_SEL_S)) 3815 #define GPIO_FUNC100_IN_SEL_V 0x3F 3816 #define GPIO_FUNC100_IN_SEL_S 0 3817 3818 #define GPIO_FUNC101_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02c4) 3819 /* GPIO_SIG101_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 3820 /*description: if the slow signal bypass the io matrix or not if you want setting 3821 the value to 1*/ 3822 #define GPIO_SIG101_IN_SEL (BIT(7)) 3823 #define GPIO_SIG101_IN_SEL_M (BIT(7)) 3824 #define GPIO_SIG101_IN_SEL_V 0x1 3825 #define GPIO_SIG101_IN_SEL_S 7 3826 /* GPIO_FUNC101_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 3827 /*description: revert the value of the input if you want to revert please set the value to 1*/ 3828 #define GPIO_FUNC101_IN_INV_SEL (BIT(6)) 3829 #define GPIO_FUNC101_IN_INV_SEL_M (BIT(6)) 3830 #define GPIO_FUNC101_IN_INV_SEL_V 0x1 3831 #define GPIO_FUNC101_IN_INV_SEL_S 6 3832 /* GPIO_FUNC101_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 3833 /*description: select one of the 256 inputs*/ 3834 #define GPIO_FUNC101_IN_SEL 0x0000003F 3835 #define GPIO_FUNC101_IN_SEL_M ((GPIO_FUNC101_IN_SEL_V)<<(GPIO_FUNC101_IN_SEL_S)) 3836 #define GPIO_FUNC101_IN_SEL_V 0x3F 3837 #define GPIO_FUNC101_IN_SEL_S 0 3838 3839 #define GPIO_FUNC102_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02c8) 3840 /* GPIO_SIG102_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 3841 /*description: if the slow signal bypass the io matrix or not if you want setting 3842 the value to 1*/ 3843 #define GPIO_SIG102_IN_SEL (BIT(7)) 3844 #define GPIO_SIG102_IN_SEL_M (BIT(7)) 3845 #define GPIO_SIG102_IN_SEL_V 0x1 3846 #define GPIO_SIG102_IN_SEL_S 7 3847 /* GPIO_FUNC102_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 3848 /*description: revert the value of the input if you want to revert please set the value to 1*/ 3849 #define GPIO_FUNC102_IN_INV_SEL (BIT(6)) 3850 #define GPIO_FUNC102_IN_INV_SEL_M (BIT(6)) 3851 #define GPIO_FUNC102_IN_INV_SEL_V 0x1 3852 #define GPIO_FUNC102_IN_INV_SEL_S 6 3853 /* GPIO_FUNC102_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 3854 /*description: select one of the 256 inputs*/ 3855 #define GPIO_FUNC102_IN_SEL 0x0000003F 3856 #define GPIO_FUNC102_IN_SEL_M ((GPIO_FUNC102_IN_SEL_V)<<(GPIO_FUNC102_IN_SEL_S)) 3857 #define GPIO_FUNC102_IN_SEL_V 0x3F 3858 #define GPIO_FUNC102_IN_SEL_S 0 3859 3860 #define GPIO_FUNC103_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02cc) 3861 /* GPIO_SIG103_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 3862 /*description: if the slow signal bypass the io matrix or not if you want setting 3863 the value to 1*/ 3864 #define GPIO_SIG103_IN_SEL (BIT(7)) 3865 #define GPIO_SIG103_IN_SEL_M (BIT(7)) 3866 #define GPIO_SIG103_IN_SEL_V 0x1 3867 #define GPIO_SIG103_IN_SEL_S 7 3868 /* GPIO_FUNC103_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 3869 /*description: revert the value of the input if you want to revert please set the value to 1*/ 3870 #define GPIO_FUNC103_IN_INV_SEL (BIT(6)) 3871 #define GPIO_FUNC103_IN_INV_SEL_M (BIT(6)) 3872 #define GPIO_FUNC103_IN_INV_SEL_V 0x1 3873 #define GPIO_FUNC103_IN_INV_SEL_S 6 3874 /* GPIO_FUNC103_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 3875 /*description: select one of the 256 inputs*/ 3876 #define GPIO_FUNC103_IN_SEL 0x0000003F 3877 #define GPIO_FUNC103_IN_SEL_M ((GPIO_FUNC103_IN_SEL_V)<<(GPIO_FUNC103_IN_SEL_S)) 3878 #define GPIO_FUNC103_IN_SEL_V 0x3F 3879 #define GPIO_FUNC103_IN_SEL_S 0 3880 3881 #define GPIO_FUNC104_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02d0) 3882 /* GPIO_SIG104_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 3883 /*description: if the slow signal bypass the io matrix or not if you want setting 3884 the value to 1*/ 3885 #define GPIO_SIG104_IN_SEL (BIT(7)) 3886 #define GPIO_SIG104_IN_SEL_M (BIT(7)) 3887 #define GPIO_SIG104_IN_SEL_V 0x1 3888 #define GPIO_SIG104_IN_SEL_S 7 3889 /* GPIO_FUNC104_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 3890 /*description: revert the value of the input if you want to revert please set the value to 1*/ 3891 #define GPIO_FUNC104_IN_INV_SEL (BIT(6)) 3892 #define GPIO_FUNC104_IN_INV_SEL_M (BIT(6)) 3893 #define GPIO_FUNC104_IN_INV_SEL_V 0x1 3894 #define GPIO_FUNC104_IN_INV_SEL_S 6 3895 /* GPIO_FUNC104_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 3896 /*description: select one of the 256 inputs*/ 3897 #define GPIO_FUNC104_IN_SEL 0x0000003F 3898 #define GPIO_FUNC104_IN_SEL_M ((GPIO_FUNC104_IN_SEL_V)<<(GPIO_FUNC104_IN_SEL_S)) 3899 #define GPIO_FUNC104_IN_SEL_V 0x3F 3900 #define GPIO_FUNC104_IN_SEL_S 0 3901 3902 #define GPIO_FUNC105_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02d4) 3903 /* GPIO_SIG105_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 3904 /*description: if the slow signal bypass the io matrix or not if you want setting 3905 the value to 1*/ 3906 #define GPIO_SIG105_IN_SEL (BIT(7)) 3907 #define GPIO_SIG105_IN_SEL_M (BIT(7)) 3908 #define GPIO_SIG105_IN_SEL_V 0x1 3909 #define GPIO_SIG105_IN_SEL_S 7 3910 /* GPIO_FUNC105_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 3911 /*description: revert the value of the input if you want to revert please set the value to 1*/ 3912 #define GPIO_FUNC105_IN_INV_SEL (BIT(6)) 3913 #define GPIO_FUNC105_IN_INV_SEL_M (BIT(6)) 3914 #define GPIO_FUNC105_IN_INV_SEL_V 0x1 3915 #define GPIO_FUNC105_IN_INV_SEL_S 6 3916 /* GPIO_FUNC105_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 3917 /*description: select one of the 256 inputs*/ 3918 #define GPIO_FUNC105_IN_SEL 0x0000003F 3919 #define GPIO_FUNC105_IN_SEL_M ((GPIO_FUNC105_IN_SEL_V)<<(GPIO_FUNC105_IN_SEL_S)) 3920 #define GPIO_FUNC105_IN_SEL_V 0x3F 3921 #define GPIO_FUNC105_IN_SEL_S 0 3922 3923 #define GPIO_FUNC106_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02d8) 3924 /* GPIO_SIG106_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 3925 /*description: if the slow signal bypass the io matrix or not if you want setting 3926 the value to 1*/ 3927 #define GPIO_SIG106_IN_SEL (BIT(7)) 3928 #define GPIO_SIG106_IN_SEL_M (BIT(7)) 3929 #define GPIO_SIG106_IN_SEL_V 0x1 3930 #define GPIO_SIG106_IN_SEL_S 7 3931 /* GPIO_FUNC106_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 3932 /*description: revert the value of the input if you want to revert please set the value to 1*/ 3933 #define GPIO_FUNC106_IN_INV_SEL (BIT(6)) 3934 #define GPIO_FUNC106_IN_INV_SEL_M (BIT(6)) 3935 #define GPIO_FUNC106_IN_INV_SEL_V 0x1 3936 #define GPIO_FUNC106_IN_INV_SEL_S 6 3937 /* GPIO_FUNC106_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 3938 /*description: select one of the 256 inputs*/ 3939 #define GPIO_FUNC106_IN_SEL 0x0000003F 3940 #define GPIO_FUNC106_IN_SEL_M ((GPIO_FUNC106_IN_SEL_V)<<(GPIO_FUNC106_IN_SEL_S)) 3941 #define GPIO_FUNC106_IN_SEL_V 0x3F 3942 #define GPIO_FUNC106_IN_SEL_S 0 3943 3944 #define GPIO_FUNC107_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02dc) 3945 /* GPIO_SIG107_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 3946 /*description: if the slow signal bypass the io matrix or not if you want setting 3947 the value to 1*/ 3948 #define GPIO_SIG107_IN_SEL (BIT(7)) 3949 #define GPIO_SIG107_IN_SEL_M (BIT(7)) 3950 #define GPIO_SIG107_IN_SEL_V 0x1 3951 #define GPIO_SIG107_IN_SEL_S 7 3952 /* GPIO_FUNC107_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 3953 /*description: revert the value of the input if you want to revert please set the value to 1*/ 3954 #define GPIO_FUNC107_IN_INV_SEL (BIT(6)) 3955 #define GPIO_FUNC107_IN_INV_SEL_M (BIT(6)) 3956 #define GPIO_FUNC107_IN_INV_SEL_V 0x1 3957 #define GPIO_FUNC107_IN_INV_SEL_S 6 3958 /* GPIO_FUNC107_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 3959 /*description: select one of the 256 inputs*/ 3960 #define GPIO_FUNC107_IN_SEL 0x0000003F 3961 #define GPIO_FUNC107_IN_SEL_M ((GPIO_FUNC107_IN_SEL_V)<<(GPIO_FUNC107_IN_SEL_S)) 3962 #define GPIO_FUNC107_IN_SEL_V 0x3F 3963 #define GPIO_FUNC107_IN_SEL_S 0 3964 3965 #define GPIO_FUNC108_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02e0) 3966 /* GPIO_SIG108_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 3967 /*description: if the slow signal bypass the io matrix or not if you want setting 3968 the value to 1*/ 3969 #define GPIO_SIG108_IN_SEL (BIT(7)) 3970 #define GPIO_SIG108_IN_SEL_M (BIT(7)) 3971 #define GPIO_SIG108_IN_SEL_V 0x1 3972 #define GPIO_SIG108_IN_SEL_S 7 3973 /* GPIO_FUNC108_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 3974 /*description: revert the value of the input if you want to revert please set the value to 1*/ 3975 #define GPIO_FUNC108_IN_INV_SEL (BIT(6)) 3976 #define GPIO_FUNC108_IN_INV_SEL_M (BIT(6)) 3977 #define GPIO_FUNC108_IN_INV_SEL_V 0x1 3978 #define GPIO_FUNC108_IN_INV_SEL_S 6 3979 /* GPIO_FUNC108_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 3980 /*description: select one of the 256 inputs*/ 3981 #define GPIO_FUNC108_IN_SEL 0x0000003F 3982 #define GPIO_FUNC108_IN_SEL_M ((GPIO_FUNC108_IN_SEL_V)<<(GPIO_FUNC108_IN_SEL_S)) 3983 #define GPIO_FUNC108_IN_SEL_V 0x3F 3984 #define GPIO_FUNC108_IN_SEL_S 0 3985 3986 #define GPIO_FUNC109_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02e4) 3987 /* GPIO_SIG109_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 3988 /*description: if the slow signal bypass the io matrix or not if you want setting 3989 the value to 1*/ 3990 #define GPIO_SIG109_IN_SEL (BIT(7)) 3991 #define GPIO_SIG109_IN_SEL_M (BIT(7)) 3992 #define GPIO_SIG109_IN_SEL_V 0x1 3993 #define GPIO_SIG109_IN_SEL_S 7 3994 /* GPIO_FUNC109_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 3995 /*description: revert the value of the input if you want to revert please set the value to 1*/ 3996 #define GPIO_FUNC109_IN_INV_SEL (BIT(6)) 3997 #define GPIO_FUNC109_IN_INV_SEL_M (BIT(6)) 3998 #define GPIO_FUNC109_IN_INV_SEL_V 0x1 3999 #define GPIO_FUNC109_IN_INV_SEL_S 6 4000 /* GPIO_FUNC109_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 4001 /*description: select one of the 256 inputs*/ 4002 #define GPIO_FUNC109_IN_SEL 0x0000003F 4003 #define GPIO_FUNC109_IN_SEL_M ((GPIO_FUNC109_IN_SEL_V)<<(GPIO_FUNC109_IN_SEL_S)) 4004 #define GPIO_FUNC109_IN_SEL_V 0x3F 4005 #define GPIO_FUNC109_IN_SEL_S 0 4006 4007 #define GPIO_FUNC110_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02e8) 4008 /* GPIO_SIG110_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 4009 /*description: if the slow signal bypass the io matrix or not if you want setting 4010 the value to 1*/ 4011 #define GPIO_SIG110_IN_SEL (BIT(7)) 4012 #define GPIO_SIG110_IN_SEL_M (BIT(7)) 4013 #define GPIO_SIG110_IN_SEL_V 0x1 4014 #define GPIO_SIG110_IN_SEL_S 7 4015 /* GPIO_FUNC110_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 4016 /*description: revert the value of the input if you want to revert please set the value to 1*/ 4017 #define GPIO_FUNC110_IN_INV_SEL (BIT(6)) 4018 #define GPIO_FUNC110_IN_INV_SEL_M (BIT(6)) 4019 #define GPIO_FUNC110_IN_INV_SEL_V 0x1 4020 #define GPIO_FUNC110_IN_INV_SEL_S 6 4021 /* GPIO_FUNC110_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 4022 /*description: select one of the 256 inputs*/ 4023 #define GPIO_FUNC110_IN_SEL 0x0000003F 4024 #define GPIO_FUNC110_IN_SEL_M ((GPIO_FUNC110_IN_SEL_V)<<(GPIO_FUNC110_IN_SEL_S)) 4025 #define GPIO_FUNC110_IN_SEL_V 0x3F 4026 #define GPIO_FUNC110_IN_SEL_S 0 4027 4028 #define GPIO_FUNC111_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02ec) 4029 /* GPIO_SIG111_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 4030 /*description: if the slow signal bypass the io matrix or not if you want setting 4031 the value to 1*/ 4032 #define GPIO_SIG111_IN_SEL (BIT(7)) 4033 #define GPIO_SIG111_IN_SEL_M (BIT(7)) 4034 #define GPIO_SIG111_IN_SEL_V 0x1 4035 #define GPIO_SIG111_IN_SEL_S 7 4036 /* GPIO_FUNC111_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 4037 /*description: revert the value of the input if you want to revert please set the value to 1*/ 4038 #define GPIO_FUNC111_IN_INV_SEL (BIT(6)) 4039 #define GPIO_FUNC111_IN_INV_SEL_M (BIT(6)) 4040 #define GPIO_FUNC111_IN_INV_SEL_V 0x1 4041 #define GPIO_FUNC111_IN_INV_SEL_S 6 4042 /* GPIO_FUNC111_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 4043 /*description: select one of the 256 inputs*/ 4044 #define GPIO_FUNC111_IN_SEL 0x0000003F 4045 #define GPIO_FUNC111_IN_SEL_M ((GPIO_FUNC111_IN_SEL_V)<<(GPIO_FUNC111_IN_SEL_S)) 4046 #define GPIO_FUNC111_IN_SEL_V 0x3F 4047 #define GPIO_FUNC111_IN_SEL_S 0 4048 4049 #define GPIO_FUNC112_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02f0) 4050 /* GPIO_SIG112_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 4051 /*description: if the slow signal bypass the io matrix or not if you want setting 4052 the value to 1*/ 4053 #define GPIO_SIG112_IN_SEL (BIT(7)) 4054 #define GPIO_SIG112_IN_SEL_M (BIT(7)) 4055 #define GPIO_SIG112_IN_SEL_V 0x1 4056 #define GPIO_SIG112_IN_SEL_S 7 4057 /* GPIO_FUNC112_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 4058 /*description: revert the value of the input if you want to revert please set the value to 1*/ 4059 #define GPIO_FUNC112_IN_INV_SEL (BIT(6)) 4060 #define GPIO_FUNC112_IN_INV_SEL_M (BIT(6)) 4061 #define GPIO_FUNC112_IN_INV_SEL_V 0x1 4062 #define GPIO_FUNC112_IN_INV_SEL_S 6 4063 /* GPIO_FUNC112_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 4064 /*description: select one of the 256 inputs*/ 4065 #define GPIO_FUNC112_IN_SEL 0x0000003F 4066 #define GPIO_FUNC112_IN_SEL_M ((GPIO_FUNC112_IN_SEL_V)<<(GPIO_FUNC112_IN_SEL_S)) 4067 #define GPIO_FUNC112_IN_SEL_V 0x3F 4068 #define GPIO_FUNC112_IN_SEL_S 0 4069 4070 #define GPIO_FUNC113_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02f4) 4071 /* GPIO_SIG113_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 4072 /*description: if the slow signal bypass the io matrix or not if you want setting 4073 the value to 1*/ 4074 #define GPIO_SIG113_IN_SEL (BIT(7)) 4075 #define GPIO_SIG113_IN_SEL_M (BIT(7)) 4076 #define GPIO_SIG113_IN_SEL_V 0x1 4077 #define GPIO_SIG113_IN_SEL_S 7 4078 /* GPIO_FUNC113_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 4079 /*description: revert the value of the input if you want to revert please set the value to 1*/ 4080 #define GPIO_FUNC113_IN_INV_SEL (BIT(6)) 4081 #define GPIO_FUNC113_IN_INV_SEL_M (BIT(6)) 4082 #define GPIO_FUNC113_IN_INV_SEL_V 0x1 4083 #define GPIO_FUNC113_IN_INV_SEL_S 6 4084 /* GPIO_FUNC113_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 4085 /*description: select one of the 256 inputs*/ 4086 #define GPIO_FUNC113_IN_SEL 0x0000003F 4087 #define GPIO_FUNC113_IN_SEL_M ((GPIO_FUNC113_IN_SEL_V)<<(GPIO_FUNC113_IN_SEL_S)) 4088 #define GPIO_FUNC113_IN_SEL_V 0x3F 4089 #define GPIO_FUNC113_IN_SEL_S 0 4090 4091 #define GPIO_FUNC114_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02f8) 4092 /* GPIO_SIG114_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 4093 /*description: if the slow signal bypass the io matrix or not if you want setting 4094 the value to 1*/ 4095 #define GPIO_SIG114_IN_SEL (BIT(7)) 4096 #define GPIO_SIG114_IN_SEL_M (BIT(7)) 4097 #define GPIO_SIG114_IN_SEL_V 0x1 4098 #define GPIO_SIG114_IN_SEL_S 7 4099 /* GPIO_FUNC114_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 4100 /*description: revert the value of the input if you want to revert please set the value to 1*/ 4101 #define GPIO_FUNC114_IN_INV_SEL (BIT(6)) 4102 #define GPIO_FUNC114_IN_INV_SEL_M (BIT(6)) 4103 #define GPIO_FUNC114_IN_INV_SEL_V 0x1 4104 #define GPIO_FUNC114_IN_INV_SEL_S 6 4105 /* GPIO_FUNC114_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 4106 /*description: select one of the 256 inputs*/ 4107 #define GPIO_FUNC114_IN_SEL 0x0000003F 4108 #define GPIO_FUNC114_IN_SEL_M ((GPIO_FUNC114_IN_SEL_V)<<(GPIO_FUNC114_IN_SEL_S)) 4109 #define GPIO_FUNC114_IN_SEL_V 0x3F 4110 #define GPIO_FUNC114_IN_SEL_S 0 4111 4112 #define GPIO_FUNC115_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02fc) 4113 /* GPIO_SIG115_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 4114 /*description: if the slow signal bypass the io matrix or not if you want setting 4115 the value to 1*/ 4116 #define GPIO_SIG115_IN_SEL (BIT(7)) 4117 #define GPIO_SIG115_IN_SEL_M (BIT(7)) 4118 #define GPIO_SIG115_IN_SEL_V 0x1 4119 #define GPIO_SIG115_IN_SEL_S 7 4120 /* GPIO_FUNC115_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 4121 /*description: revert the value of the input if you want to revert please set the value to 1*/ 4122 #define GPIO_FUNC115_IN_INV_SEL (BIT(6)) 4123 #define GPIO_FUNC115_IN_INV_SEL_M (BIT(6)) 4124 #define GPIO_FUNC115_IN_INV_SEL_V 0x1 4125 #define GPIO_FUNC115_IN_INV_SEL_S 6 4126 /* GPIO_FUNC115_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 4127 /*description: select one of the 256 inputs*/ 4128 #define GPIO_FUNC115_IN_SEL 0x0000003F 4129 #define GPIO_FUNC115_IN_SEL_M ((GPIO_FUNC115_IN_SEL_V)<<(GPIO_FUNC115_IN_SEL_S)) 4130 #define GPIO_FUNC115_IN_SEL_V 0x3F 4131 #define GPIO_FUNC115_IN_SEL_S 0 4132 4133 #define GPIO_FUNC116_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0300) 4134 /* GPIO_SIG116_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 4135 /*description: if the slow signal bypass the io matrix or not if you want setting 4136 the value to 1*/ 4137 #define GPIO_SIG116_IN_SEL (BIT(7)) 4138 #define GPIO_SIG116_IN_SEL_M (BIT(7)) 4139 #define GPIO_SIG116_IN_SEL_V 0x1 4140 #define GPIO_SIG116_IN_SEL_S 7 4141 /* GPIO_FUNC116_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 4142 /*description: revert the value of the input if you want to revert please set the value to 1*/ 4143 #define GPIO_FUNC116_IN_INV_SEL (BIT(6)) 4144 #define GPIO_FUNC116_IN_INV_SEL_M (BIT(6)) 4145 #define GPIO_FUNC116_IN_INV_SEL_V 0x1 4146 #define GPIO_FUNC116_IN_INV_SEL_S 6 4147 /* GPIO_FUNC116_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 4148 /*description: select one of the 256 inputs*/ 4149 #define GPIO_FUNC116_IN_SEL 0x0000003F 4150 #define GPIO_FUNC116_IN_SEL_M ((GPIO_FUNC116_IN_SEL_V)<<(GPIO_FUNC116_IN_SEL_S)) 4151 #define GPIO_FUNC116_IN_SEL_V 0x3F 4152 #define GPIO_FUNC116_IN_SEL_S 0 4153 4154 #define GPIO_FUNC117_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0304) 4155 /* GPIO_SIG117_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 4156 /*description: if the slow signal bypass the io matrix or not if you want setting 4157 the value to 1*/ 4158 #define GPIO_SIG117_IN_SEL (BIT(7)) 4159 #define GPIO_SIG117_IN_SEL_M (BIT(7)) 4160 #define GPIO_SIG117_IN_SEL_V 0x1 4161 #define GPIO_SIG117_IN_SEL_S 7 4162 /* GPIO_FUNC117_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 4163 /*description: revert the value of the input if you want to revert please set the value to 1*/ 4164 #define GPIO_FUNC117_IN_INV_SEL (BIT(6)) 4165 #define GPIO_FUNC117_IN_INV_SEL_M (BIT(6)) 4166 #define GPIO_FUNC117_IN_INV_SEL_V 0x1 4167 #define GPIO_FUNC117_IN_INV_SEL_S 6 4168 /* GPIO_FUNC117_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 4169 /*description: select one of the 256 inputs*/ 4170 #define GPIO_FUNC117_IN_SEL 0x0000003F 4171 #define GPIO_FUNC117_IN_SEL_M ((GPIO_FUNC117_IN_SEL_V)<<(GPIO_FUNC117_IN_SEL_S)) 4172 #define GPIO_FUNC117_IN_SEL_V 0x3F 4173 #define GPIO_FUNC117_IN_SEL_S 0 4174 4175 #define GPIO_FUNC118_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0308) 4176 /* GPIO_SIG118_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 4177 /*description: if the slow signal bypass the io matrix or not if you want setting 4178 the value to 1*/ 4179 #define GPIO_SIG118_IN_SEL (BIT(7)) 4180 #define GPIO_SIG118_IN_SEL_M (BIT(7)) 4181 #define GPIO_SIG118_IN_SEL_V 0x1 4182 #define GPIO_SIG118_IN_SEL_S 7 4183 /* GPIO_FUNC118_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 4184 /*description: revert the value of the input if you want to revert please set the value to 1*/ 4185 #define GPIO_FUNC118_IN_INV_SEL (BIT(6)) 4186 #define GPIO_FUNC118_IN_INV_SEL_M (BIT(6)) 4187 #define GPIO_FUNC118_IN_INV_SEL_V 0x1 4188 #define GPIO_FUNC118_IN_INV_SEL_S 6 4189 /* GPIO_FUNC118_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 4190 /*description: select one of the 256 inputs*/ 4191 #define GPIO_FUNC118_IN_SEL 0x0000003F 4192 #define GPIO_FUNC118_IN_SEL_M ((GPIO_FUNC118_IN_SEL_V)<<(GPIO_FUNC118_IN_SEL_S)) 4193 #define GPIO_FUNC118_IN_SEL_V 0x3F 4194 #define GPIO_FUNC118_IN_SEL_S 0 4195 4196 #define GPIO_FUNC119_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x030c) 4197 /* GPIO_SIG119_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 4198 /*description: if the slow signal bypass the io matrix or not if you want setting 4199 the value to 1*/ 4200 #define GPIO_SIG119_IN_SEL (BIT(7)) 4201 #define GPIO_SIG119_IN_SEL_M (BIT(7)) 4202 #define GPIO_SIG119_IN_SEL_V 0x1 4203 #define GPIO_SIG119_IN_SEL_S 7 4204 /* GPIO_FUNC119_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 4205 /*description: revert the value of the input if you want to revert please set the value to 1*/ 4206 #define GPIO_FUNC119_IN_INV_SEL (BIT(6)) 4207 #define GPIO_FUNC119_IN_INV_SEL_M (BIT(6)) 4208 #define GPIO_FUNC119_IN_INV_SEL_V 0x1 4209 #define GPIO_FUNC119_IN_INV_SEL_S 6 4210 /* GPIO_FUNC119_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 4211 /*description: select one of the 256 inputs*/ 4212 #define GPIO_FUNC119_IN_SEL 0x0000003F 4213 #define GPIO_FUNC119_IN_SEL_M ((GPIO_FUNC119_IN_SEL_V)<<(GPIO_FUNC119_IN_SEL_S)) 4214 #define GPIO_FUNC119_IN_SEL_V 0x3F 4215 #define GPIO_FUNC119_IN_SEL_S 0 4216 4217 #define GPIO_FUNC120_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0310) 4218 /* GPIO_SIG120_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 4219 /*description: if the slow signal bypass the io matrix or not if you want setting 4220 the value to 1*/ 4221 #define GPIO_SIG120_IN_SEL (BIT(7)) 4222 #define GPIO_SIG120_IN_SEL_M (BIT(7)) 4223 #define GPIO_SIG120_IN_SEL_V 0x1 4224 #define GPIO_SIG120_IN_SEL_S 7 4225 /* GPIO_FUNC120_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 4226 /*description: revert the value of the input if you want to revert please set the value to 1*/ 4227 #define GPIO_FUNC120_IN_INV_SEL (BIT(6)) 4228 #define GPIO_FUNC120_IN_INV_SEL_M (BIT(6)) 4229 #define GPIO_FUNC120_IN_INV_SEL_V 0x1 4230 #define GPIO_FUNC120_IN_INV_SEL_S 6 4231 /* GPIO_FUNC120_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 4232 /*description: select one of the 256 inputs*/ 4233 #define GPIO_FUNC120_IN_SEL 0x0000003F 4234 #define GPIO_FUNC120_IN_SEL_M ((GPIO_FUNC120_IN_SEL_V)<<(GPIO_FUNC120_IN_SEL_S)) 4235 #define GPIO_FUNC120_IN_SEL_V 0x3F 4236 #define GPIO_FUNC120_IN_SEL_S 0 4237 4238 #define GPIO_FUNC121_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0314) 4239 /* GPIO_SIG121_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 4240 /*description: if the slow signal bypass the io matrix or not if you want setting 4241 the value to 1*/ 4242 #define GPIO_SIG121_IN_SEL (BIT(7)) 4243 #define GPIO_SIG121_IN_SEL_M (BIT(7)) 4244 #define GPIO_SIG121_IN_SEL_V 0x1 4245 #define GPIO_SIG121_IN_SEL_S 7 4246 /* GPIO_FUNC121_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 4247 /*description: revert the value of the input if you want to revert please set the value to 1*/ 4248 #define GPIO_FUNC121_IN_INV_SEL (BIT(6)) 4249 #define GPIO_FUNC121_IN_INV_SEL_M (BIT(6)) 4250 #define GPIO_FUNC121_IN_INV_SEL_V 0x1 4251 #define GPIO_FUNC121_IN_INV_SEL_S 6 4252 /* GPIO_FUNC121_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 4253 /*description: select one of the 256 inputs*/ 4254 #define GPIO_FUNC121_IN_SEL 0x0000003F 4255 #define GPIO_FUNC121_IN_SEL_M ((GPIO_FUNC121_IN_SEL_V)<<(GPIO_FUNC121_IN_SEL_S)) 4256 #define GPIO_FUNC121_IN_SEL_V 0x3F 4257 #define GPIO_FUNC121_IN_SEL_S 0 4258 4259 #define GPIO_FUNC122_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0318) 4260 /* GPIO_SIG122_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 4261 /*description: if the slow signal bypass the io matrix or not if you want setting 4262 the value to 1*/ 4263 #define GPIO_SIG122_IN_SEL (BIT(7)) 4264 #define GPIO_SIG122_IN_SEL_M (BIT(7)) 4265 #define GPIO_SIG122_IN_SEL_V 0x1 4266 #define GPIO_SIG122_IN_SEL_S 7 4267 /* GPIO_FUNC122_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 4268 /*description: revert the value of the input if you want to revert please set the value to 1*/ 4269 #define GPIO_FUNC122_IN_INV_SEL (BIT(6)) 4270 #define GPIO_FUNC122_IN_INV_SEL_M (BIT(6)) 4271 #define GPIO_FUNC122_IN_INV_SEL_V 0x1 4272 #define GPIO_FUNC122_IN_INV_SEL_S 6 4273 /* GPIO_FUNC122_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 4274 /*description: select one of the 256 inputs*/ 4275 #define GPIO_FUNC122_IN_SEL 0x0000003F 4276 #define GPIO_FUNC122_IN_SEL_M ((GPIO_FUNC122_IN_SEL_V)<<(GPIO_FUNC122_IN_SEL_S)) 4277 #define GPIO_FUNC122_IN_SEL_V 0x3F 4278 #define GPIO_FUNC122_IN_SEL_S 0 4279 4280 #define GPIO_FUNC123_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x031c) 4281 /* GPIO_SIG123_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 4282 /*description: if the slow signal bypass the io matrix or not if you want setting 4283 the value to 1*/ 4284 #define GPIO_SIG123_IN_SEL (BIT(7)) 4285 #define GPIO_SIG123_IN_SEL_M (BIT(7)) 4286 #define GPIO_SIG123_IN_SEL_V 0x1 4287 #define GPIO_SIG123_IN_SEL_S 7 4288 /* GPIO_FUNC123_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 4289 /*description: revert the value of the input if you want to revert please set the value to 1*/ 4290 #define GPIO_FUNC123_IN_INV_SEL (BIT(6)) 4291 #define GPIO_FUNC123_IN_INV_SEL_M (BIT(6)) 4292 #define GPIO_FUNC123_IN_INV_SEL_V 0x1 4293 #define GPIO_FUNC123_IN_INV_SEL_S 6 4294 /* GPIO_FUNC123_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 4295 /*description: select one of the 256 inputs*/ 4296 #define GPIO_FUNC123_IN_SEL 0x0000003F 4297 #define GPIO_FUNC123_IN_SEL_M ((GPIO_FUNC123_IN_SEL_V)<<(GPIO_FUNC123_IN_SEL_S)) 4298 #define GPIO_FUNC123_IN_SEL_V 0x3F 4299 #define GPIO_FUNC123_IN_SEL_S 0 4300 4301 #define GPIO_FUNC124_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0320) 4302 /* GPIO_SIG124_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 4303 /*description: if the slow signal bypass the io matrix or not if you want setting 4304 the value to 1*/ 4305 #define GPIO_SIG124_IN_SEL (BIT(7)) 4306 #define GPIO_SIG124_IN_SEL_M (BIT(7)) 4307 #define GPIO_SIG124_IN_SEL_V 0x1 4308 #define GPIO_SIG124_IN_SEL_S 7 4309 /* GPIO_FUNC124_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 4310 /*description: revert the value of the input if you want to revert please set the value to 1*/ 4311 #define GPIO_FUNC124_IN_INV_SEL (BIT(6)) 4312 #define GPIO_FUNC124_IN_INV_SEL_M (BIT(6)) 4313 #define GPIO_FUNC124_IN_INV_SEL_V 0x1 4314 #define GPIO_FUNC124_IN_INV_SEL_S 6 4315 /* GPIO_FUNC124_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 4316 /*description: select one of the 256 inputs*/ 4317 #define GPIO_FUNC124_IN_SEL 0x0000003F 4318 #define GPIO_FUNC124_IN_SEL_M ((GPIO_FUNC124_IN_SEL_V)<<(GPIO_FUNC124_IN_SEL_S)) 4319 #define GPIO_FUNC124_IN_SEL_V 0x3F 4320 #define GPIO_FUNC124_IN_SEL_S 0 4321 4322 #define GPIO_FUNC125_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0324) 4323 /* GPIO_SIG125_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 4324 /*description: if the slow signal bypass the io matrix or not if you want setting 4325 the value to 1*/ 4326 #define GPIO_SIG125_IN_SEL (BIT(7)) 4327 #define GPIO_SIG125_IN_SEL_M (BIT(7)) 4328 #define GPIO_SIG125_IN_SEL_V 0x1 4329 #define GPIO_SIG125_IN_SEL_S 7 4330 /* GPIO_FUNC125_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 4331 /*description: revert the value of the input if you want to revert please set the value to 1*/ 4332 #define GPIO_FUNC125_IN_INV_SEL (BIT(6)) 4333 #define GPIO_FUNC125_IN_INV_SEL_M (BIT(6)) 4334 #define GPIO_FUNC125_IN_INV_SEL_V 0x1 4335 #define GPIO_FUNC125_IN_INV_SEL_S 6 4336 /* GPIO_FUNC125_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 4337 /*description: select one of the 256 inputs*/ 4338 #define GPIO_FUNC125_IN_SEL 0x0000003F 4339 #define GPIO_FUNC125_IN_SEL_M ((GPIO_FUNC125_IN_SEL_V)<<(GPIO_FUNC125_IN_SEL_S)) 4340 #define GPIO_FUNC125_IN_SEL_V 0x3F 4341 #define GPIO_FUNC125_IN_SEL_S 0 4342 4343 #define GPIO_FUNC126_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0328) 4344 /* GPIO_SIG126_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 4345 /*description: if the slow signal bypass the io matrix or not if you want setting 4346 the value to 1*/ 4347 #define GPIO_SIG126_IN_SEL (BIT(7)) 4348 #define GPIO_SIG126_IN_SEL_M (BIT(7)) 4349 #define GPIO_SIG126_IN_SEL_V 0x1 4350 #define GPIO_SIG126_IN_SEL_S 7 4351 /* GPIO_FUNC126_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 4352 /*description: revert the value of the input if you want to revert please set the value to 1*/ 4353 #define GPIO_FUNC126_IN_INV_SEL (BIT(6)) 4354 #define GPIO_FUNC126_IN_INV_SEL_M (BIT(6)) 4355 #define GPIO_FUNC126_IN_INV_SEL_V 0x1 4356 #define GPIO_FUNC126_IN_INV_SEL_S 6 4357 /* GPIO_FUNC126_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 4358 /*description: select one of the 256 inputs*/ 4359 #define GPIO_FUNC126_IN_SEL 0x0000003F 4360 #define GPIO_FUNC126_IN_SEL_M ((GPIO_FUNC126_IN_SEL_V)<<(GPIO_FUNC126_IN_SEL_S)) 4361 #define GPIO_FUNC126_IN_SEL_V 0x3F 4362 #define GPIO_FUNC126_IN_SEL_S 0 4363 4364 #define GPIO_FUNC127_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x032c) 4365 /* GPIO_SIG127_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 4366 /*description: if the slow signal bypass the io matrix or not if you want setting 4367 the value to 1*/ 4368 #define GPIO_SIG127_IN_SEL (BIT(7)) 4369 #define GPIO_SIG127_IN_SEL_M (BIT(7)) 4370 #define GPIO_SIG127_IN_SEL_V 0x1 4371 #define GPIO_SIG127_IN_SEL_S 7 4372 /* GPIO_FUNC127_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 4373 /*description: revert the value of the input if you want to revert please set the value to 1*/ 4374 #define GPIO_FUNC127_IN_INV_SEL (BIT(6)) 4375 #define GPIO_FUNC127_IN_INV_SEL_M (BIT(6)) 4376 #define GPIO_FUNC127_IN_INV_SEL_V 0x1 4377 #define GPIO_FUNC127_IN_INV_SEL_S 6 4378 /* GPIO_FUNC127_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 4379 /*description: select one of the 256 inputs*/ 4380 #define GPIO_FUNC127_IN_SEL 0x0000003F 4381 #define GPIO_FUNC127_IN_SEL_M ((GPIO_FUNC127_IN_SEL_V)<<(GPIO_FUNC127_IN_SEL_S)) 4382 #define GPIO_FUNC127_IN_SEL_V 0x3F 4383 #define GPIO_FUNC127_IN_SEL_S 0 4384 4385 #define GPIO_FUNC128_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0330) 4386 /* GPIO_SIG128_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 4387 /*description: if the slow signal bypass the io matrix or not if you want setting 4388 the value to 1*/ 4389 #define GPIO_SIG128_IN_SEL (BIT(7)) 4390 #define GPIO_SIG128_IN_SEL_M (BIT(7)) 4391 #define GPIO_SIG128_IN_SEL_V 0x1 4392 #define GPIO_SIG128_IN_SEL_S 7 4393 /* GPIO_FUNC128_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 4394 /*description: revert the value of the input if you want to revert please set the value to 1*/ 4395 #define GPIO_FUNC128_IN_INV_SEL (BIT(6)) 4396 #define GPIO_FUNC128_IN_INV_SEL_M (BIT(6)) 4397 #define GPIO_FUNC128_IN_INV_SEL_V 0x1 4398 #define GPIO_FUNC128_IN_INV_SEL_S 6 4399 /* GPIO_FUNC128_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 4400 /*description: select one of the 256 inputs*/ 4401 #define GPIO_FUNC128_IN_SEL 0x0000003F 4402 #define GPIO_FUNC128_IN_SEL_M ((GPIO_FUNC128_IN_SEL_V)<<(GPIO_FUNC128_IN_SEL_S)) 4403 #define GPIO_FUNC128_IN_SEL_V 0x3F 4404 #define GPIO_FUNC128_IN_SEL_S 0 4405 4406 #define GPIO_FUNC129_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0334) 4407 /* GPIO_SIG129_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 4408 /*description: if the slow signal bypass the io matrix or not if you want setting 4409 the value to 1*/ 4410 #define GPIO_SIG129_IN_SEL (BIT(7)) 4411 #define GPIO_SIG129_IN_SEL_M (BIT(7)) 4412 #define GPIO_SIG129_IN_SEL_V 0x1 4413 #define GPIO_SIG129_IN_SEL_S 7 4414 /* GPIO_FUNC129_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 4415 /*description: revert the value of the input if you want to revert please set the value to 1*/ 4416 #define GPIO_FUNC129_IN_INV_SEL (BIT(6)) 4417 #define GPIO_FUNC129_IN_INV_SEL_M (BIT(6)) 4418 #define GPIO_FUNC129_IN_INV_SEL_V 0x1 4419 #define GPIO_FUNC129_IN_INV_SEL_S 6 4420 /* GPIO_FUNC129_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 4421 /*description: select one of the 256 inputs*/ 4422 #define GPIO_FUNC129_IN_SEL 0x0000003F 4423 #define GPIO_FUNC129_IN_SEL_M ((GPIO_FUNC129_IN_SEL_V)<<(GPIO_FUNC129_IN_SEL_S)) 4424 #define GPIO_FUNC129_IN_SEL_V 0x3F 4425 #define GPIO_FUNC129_IN_SEL_S 0 4426 4427 #define GPIO_FUNC130_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0338) 4428 /* GPIO_SIG130_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 4429 /*description: if the slow signal bypass the io matrix or not if you want setting 4430 the value to 1*/ 4431 #define GPIO_SIG130_IN_SEL (BIT(7)) 4432 #define GPIO_SIG130_IN_SEL_M (BIT(7)) 4433 #define GPIO_SIG130_IN_SEL_V 0x1 4434 #define GPIO_SIG130_IN_SEL_S 7 4435 /* GPIO_FUNC130_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 4436 /*description: revert the value of the input if you want to revert please set the value to 1*/ 4437 #define GPIO_FUNC130_IN_INV_SEL (BIT(6)) 4438 #define GPIO_FUNC130_IN_INV_SEL_M (BIT(6)) 4439 #define GPIO_FUNC130_IN_INV_SEL_V 0x1 4440 #define GPIO_FUNC130_IN_INV_SEL_S 6 4441 /* GPIO_FUNC130_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 4442 /*description: select one of the 256 inputs*/ 4443 #define GPIO_FUNC130_IN_SEL 0x0000003F 4444 #define GPIO_FUNC130_IN_SEL_M ((GPIO_FUNC130_IN_SEL_V)<<(GPIO_FUNC130_IN_SEL_S)) 4445 #define GPIO_FUNC130_IN_SEL_V 0x3F 4446 #define GPIO_FUNC130_IN_SEL_S 0 4447 4448 #define GPIO_FUNC131_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x033c) 4449 /* GPIO_SIG131_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 4450 /*description: if the slow signal bypass the io matrix or not if you want setting 4451 the value to 1*/ 4452 #define GPIO_SIG131_IN_SEL (BIT(7)) 4453 #define GPIO_SIG131_IN_SEL_M (BIT(7)) 4454 #define GPIO_SIG131_IN_SEL_V 0x1 4455 #define GPIO_SIG131_IN_SEL_S 7 4456 /* GPIO_FUNC131_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 4457 /*description: revert the value of the input if you want to revert please set the value to 1*/ 4458 #define GPIO_FUNC131_IN_INV_SEL (BIT(6)) 4459 #define GPIO_FUNC131_IN_INV_SEL_M (BIT(6)) 4460 #define GPIO_FUNC131_IN_INV_SEL_V 0x1 4461 #define GPIO_FUNC131_IN_INV_SEL_S 6 4462 /* GPIO_FUNC131_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 4463 /*description: select one of the 256 inputs*/ 4464 #define GPIO_FUNC131_IN_SEL 0x0000003F 4465 #define GPIO_FUNC131_IN_SEL_M ((GPIO_FUNC131_IN_SEL_V)<<(GPIO_FUNC131_IN_SEL_S)) 4466 #define GPIO_FUNC131_IN_SEL_V 0x3F 4467 #define GPIO_FUNC131_IN_SEL_S 0 4468 4469 #define GPIO_FUNC132_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0340) 4470 /* GPIO_SIG132_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 4471 /*description: if the slow signal bypass the io matrix or not if you want setting 4472 the value to 1*/ 4473 #define GPIO_SIG132_IN_SEL (BIT(7)) 4474 #define GPIO_SIG132_IN_SEL_M (BIT(7)) 4475 #define GPIO_SIG132_IN_SEL_V 0x1 4476 #define GPIO_SIG132_IN_SEL_S 7 4477 /* GPIO_FUNC132_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 4478 /*description: revert the value of the input if you want to revert please set the value to 1*/ 4479 #define GPIO_FUNC132_IN_INV_SEL (BIT(6)) 4480 #define GPIO_FUNC132_IN_INV_SEL_M (BIT(6)) 4481 #define GPIO_FUNC132_IN_INV_SEL_V 0x1 4482 #define GPIO_FUNC132_IN_INV_SEL_S 6 4483 /* GPIO_FUNC132_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 4484 /*description: select one of the 256 inputs*/ 4485 #define GPIO_FUNC132_IN_SEL 0x0000003F 4486 #define GPIO_FUNC132_IN_SEL_M ((GPIO_FUNC132_IN_SEL_V)<<(GPIO_FUNC132_IN_SEL_S)) 4487 #define GPIO_FUNC132_IN_SEL_V 0x3F 4488 #define GPIO_FUNC132_IN_SEL_S 0 4489 4490 #define GPIO_FUNC133_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0344) 4491 /* GPIO_SIG133_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 4492 /*description: if the slow signal bypass the io matrix or not if you want setting 4493 the value to 1*/ 4494 #define GPIO_SIG133_IN_SEL (BIT(7)) 4495 #define GPIO_SIG133_IN_SEL_M (BIT(7)) 4496 #define GPIO_SIG133_IN_SEL_V 0x1 4497 #define GPIO_SIG133_IN_SEL_S 7 4498 /* GPIO_FUNC133_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 4499 /*description: revert the value of the input if you want to revert please set the value to 1*/ 4500 #define GPIO_FUNC133_IN_INV_SEL (BIT(6)) 4501 #define GPIO_FUNC133_IN_INV_SEL_M (BIT(6)) 4502 #define GPIO_FUNC133_IN_INV_SEL_V 0x1 4503 #define GPIO_FUNC133_IN_INV_SEL_S 6 4504 /* GPIO_FUNC133_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 4505 /*description: select one of the 256 inputs*/ 4506 #define GPIO_FUNC133_IN_SEL 0x0000003F 4507 #define GPIO_FUNC133_IN_SEL_M ((GPIO_FUNC133_IN_SEL_V)<<(GPIO_FUNC133_IN_SEL_S)) 4508 #define GPIO_FUNC133_IN_SEL_V 0x3F 4509 #define GPIO_FUNC133_IN_SEL_S 0 4510 4511 #define GPIO_FUNC134_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0348) 4512 /* GPIO_SIG134_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 4513 /*description: if the slow signal bypass the io matrix or not if you want setting 4514 the value to 1*/ 4515 #define GPIO_SIG134_IN_SEL (BIT(7)) 4516 #define GPIO_SIG134_IN_SEL_M (BIT(7)) 4517 #define GPIO_SIG134_IN_SEL_V 0x1 4518 #define GPIO_SIG134_IN_SEL_S 7 4519 /* GPIO_FUNC134_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 4520 /*description: revert the value of the input if you want to revert please set the value to 1*/ 4521 #define GPIO_FUNC134_IN_INV_SEL (BIT(6)) 4522 #define GPIO_FUNC134_IN_INV_SEL_M (BIT(6)) 4523 #define GPIO_FUNC134_IN_INV_SEL_V 0x1 4524 #define GPIO_FUNC134_IN_INV_SEL_S 6 4525 /* GPIO_FUNC134_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 4526 /*description: select one of the 256 inputs*/ 4527 #define GPIO_FUNC134_IN_SEL 0x0000003F 4528 #define GPIO_FUNC134_IN_SEL_M ((GPIO_FUNC134_IN_SEL_V)<<(GPIO_FUNC134_IN_SEL_S)) 4529 #define GPIO_FUNC134_IN_SEL_V 0x3F 4530 #define GPIO_FUNC134_IN_SEL_S 0 4531 4532 #define GPIO_FUNC135_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x034c) 4533 /* GPIO_SIG135_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 4534 /*description: if the slow signal bypass the io matrix or not if you want setting 4535 the value to 1*/ 4536 #define GPIO_SIG135_IN_SEL (BIT(7)) 4537 #define GPIO_SIG135_IN_SEL_M (BIT(7)) 4538 #define GPIO_SIG135_IN_SEL_V 0x1 4539 #define GPIO_SIG135_IN_SEL_S 7 4540 /* GPIO_FUNC135_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 4541 /*description: revert the value of the input if you want to revert please set the value to 1*/ 4542 #define GPIO_FUNC135_IN_INV_SEL (BIT(6)) 4543 #define GPIO_FUNC135_IN_INV_SEL_M (BIT(6)) 4544 #define GPIO_FUNC135_IN_INV_SEL_V 0x1 4545 #define GPIO_FUNC135_IN_INV_SEL_S 6 4546 /* GPIO_FUNC135_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 4547 /*description: select one of the 256 inputs*/ 4548 #define GPIO_FUNC135_IN_SEL 0x0000003F 4549 #define GPIO_FUNC135_IN_SEL_M ((GPIO_FUNC135_IN_SEL_V)<<(GPIO_FUNC135_IN_SEL_S)) 4550 #define GPIO_FUNC135_IN_SEL_V 0x3F 4551 #define GPIO_FUNC135_IN_SEL_S 0 4552 4553 #define GPIO_FUNC136_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0350) 4554 /* GPIO_SIG136_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 4555 /*description: if the slow signal bypass the io matrix or not if you want setting 4556 the value to 1*/ 4557 #define GPIO_SIG136_IN_SEL (BIT(7)) 4558 #define GPIO_SIG136_IN_SEL_M (BIT(7)) 4559 #define GPIO_SIG136_IN_SEL_V 0x1 4560 #define GPIO_SIG136_IN_SEL_S 7 4561 /* GPIO_FUNC136_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 4562 /*description: revert the value of the input if you want to revert please set the value to 1*/ 4563 #define GPIO_FUNC136_IN_INV_SEL (BIT(6)) 4564 #define GPIO_FUNC136_IN_INV_SEL_M (BIT(6)) 4565 #define GPIO_FUNC136_IN_INV_SEL_V 0x1 4566 #define GPIO_FUNC136_IN_INV_SEL_S 6 4567 /* GPIO_FUNC136_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 4568 /*description: select one of the 256 inputs*/ 4569 #define GPIO_FUNC136_IN_SEL 0x0000003F 4570 #define GPIO_FUNC136_IN_SEL_M ((GPIO_FUNC136_IN_SEL_V)<<(GPIO_FUNC136_IN_SEL_S)) 4571 #define GPIO_FUNC136_IN_SEL_V 0x3F 4572 #define GPIO_FUNC136_IN_SEL_S 0 4573 4574 #define GPIO_FUNC137_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0354) 4575 /* GPIO_SIG137_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 4576 /*description: if the slow signal bypass the io matrix or not if you want setting 4577 the value to 1*/ 4578 #define GPIO_SIG137_IN_SEL (BIT(7)) 4579 #define GPIO_SIG137_IN_SEL_M (BIT(7)) 4580 #define GPIO_SIG137_IN_SEL_V 0x1 4581 #define GPIO_SIG137_IN_SEL_S 7 4582 /* GPIO_FUNC137_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 4583 /*description: revert the value of the input if you want to revert please set the value to 1*/ 4584 #define GPIO_FUNC137_IN_INV_SEL (BIT(6)) 4585 #define GPIO_FUNC137_IN_INV_SEL_M (BIT(6)) 4586 #define GPIO_FUNC137_IN_INV_SEL_V 0x1 4587 #define GPIO_FUNC137_IN_INV_SEL_S 6 4588 /* GPIO_FUNC137_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 4589 /*description: select one of the 256 inputs*/ 4590 #define GPIO_FUNC137_IN_SEL 0x0000003F 4591 #define GPIO_FUNC137_IN_SEL_M ((GPIO_FUNC137_IN_SEL_V)<<(GPIO_FUNC137_IN_SEL_S)) 4592 #define GPIO_FUNC137_IN_SEL_V 0x3F 4593 #define GPIO_FUNC137_IN_SEL_S 0 4594 4595 #define GPIO_FUNC138_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0358) 4596 /* GPIO_SIG138_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 4597 /*description: if the slow signal bypass the io matrix or not if you want setting 4598 the value to 1*/ 4599 #define GPIO_SIG138_IN_SEL (BIT(7)) 4600 #define GPIO_SIG138_IN_SEL_M (BIT(7)) 4601 #define GPIO_SIG138_IN_SEL_V 0x1 4602 #define GPIO_SIG138_IN_SEL_S 7 4603 /* GPIO_FUNC138_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 4604 /*description: revert the value of the input if you want to revert please set the value to 1*/ 4605 #define GPIO_FUNC138_IN_INV_SEL (BIT(6)) 4606 #define GPIO_FUNC138_IN_INV_SEL_M (BIT(6)) 4607 #define GPIO_FUNC138_IN_INV_SEL_V 0x1 4608 #define GPIO_FUNC138_IN_INV_SEL_S 6 4609 /* GPIO_FUNC138_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 4610 /*description: select one of the 256 inputs*/ 4611 #define GPIO_FUNC138_IN_SEL 0x0000003F 4612 #define GPIO_FUNC138_IN_SEL_M ((GPIO_FUNC138_IN_SEL_V)<<(GPIO_FUNC138_IN_SEL_S)) 4613 #define GPIO_FUNC138_IN_SEL_V 0x3F 4614 #define GPIO_FUNC138_IN_SEL_S 0 4615 4616 #define GPIO_FUNC139_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x035c) 4617 /* GPIO_SIG139_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 4618 /*description: if the slow signal bypass the io matrix or not if you want setting 4619 the value to 1*/ 4620 #define GPIO_SIG139_IN_SEL (BIT(7)) 4621 #define GPIO_SIG139_IN_SEL_M (BIT(7)) 4622 #define GPIO_SIG139_IN_SEL_V 0x1 4623 #define GPIO_SIG139_IN_SEL_S 7 4624 /* GPIO_FUNC139_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 4625 /*description: revert the value of the input if you want to revert please set the value to 1*/ 4626 #define GPIO_FUNC139_IN_INV_SEL (BIT(6)) 4627 #define GPIO_FUNC139_IN_INV_SEL_M (BIT(6)) 4628 #define GPIO_FUNC139_IN_INV_SEL_V 0x1 4629 #define GPIO_FUNC139_IN_INV_SEL_S 6 4630 /* GPIO_FUNC139_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 4631 /*description: select one of the 256 inputs*/ 4632 #define GPIO_FUNC139_IN_SEL 0x0000003F 4633 #define GPIO_FUNC139_IN_SEL_M ((GPIO_FUNC139_IN_SEL_V)<<(GPIO_FUNC139_IN_SEL_S)) 4634 #define GPIO_FUNC139_IN_SEL_V 0x3F 4635 #define GPIO_FUNC139_IN_SEL_S 0 4636 4637 #define GPIO_FUNC140_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0360) 4638 /* GPIO_SIG140_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 4639 /*description: if the slow signal bypass the io matrix or not if you want setting 4640 the value to 1*/ 4641 #define GPIO_SIG140_IN_SEL (BIT(7)) 4642 #define GPIO_SIG140_IN_SEL_M (BIT(7)) 4643 #define GPIO_SIG140_IN_SEL_V 0x1 4644 #define GPIO_SIG140_IN_SEL_S 7 4645 /* GPIO_FUNC140_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 4646 /*description: revert the value of the input if you want to revert please set the value to 1*/ 4647 #define GPIO_FUNC140_IN_INV_SEL (BIT(6)) 4648 #define GPIO_FUNC140_IN_INV_SEL_M (BIT(6)) 4649 #define GPIO_FUNC140_IN_INV_SEL_V 0x1 4650 #define GPIO_FUNC140_IN_INV_SEL_S 6 4651 /* GPIO_FUNC140_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 4652 /*description: select one of the 256 inputs*/ 4653 #define GPIO_FUNC140_IN_SEL 0x0000003F 4654 #define GPIO_FUNC140_IN_SEL_M ((GPIO_FUNC140_IN_SEL_V)<<(GPIO_FUNC140_IN_SEL_S)) 4655 #define GPIO_FUNC140_IN_SEL_V 0x3F 4656 #define GPIO_FUNC140_IN_SEL_S 0 4657 4658 #define GPIO_FUNC141_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0364) 4659 /* GPIO_SIG141_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 4660 /*description: if the slow signal bypass the io matrix or not if you want setting 4661 the value to 1*/ 4662 #define GPIO_SIG141_IN_SEL (BIT(7)) 4663 #define GPIO_SIG141_IN_SEL_M (BIT(7)) 4664 #define GPIO_SIG141_IN_SEL_V 0x1 4665 #define GPIO_SIG141_IN_SEL_S 7 4666 /* GPIO_FUNC141_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 4667 /*description: revert the value of the input if you want to revert please set the value to 1*/ 4668 #define GPIO_FUNC141_IN_INV_SEL (BIT(6)) 4669 #define GPIO_FUNC141_IN_INV_SEL_M (BIT(6)) 4670 #define GPIO_FUNC141_IN_INV_SEL_V 0x1 4671 #define GPIO_FUNC141_IN_INV_SEL_S 6 4672 /* GPIO_FUNC141_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 4673 /*description: select one of the 256 inputs*/ 4674 #define GPIO_FUNC141_IN_SEL 0x0000003F 4675 #define GPIO_FUNC141_IN_SEL_M ((GPIO_FUNC141_IN_SEL_V)<<(GPIO_FUNC141_IN_SEL_S)) 4676 #define GPIO_FUNC141_IN_SEL_V 0x3F 4677 #define GPIO_FUNC141_IN_SEL_S 0 4678 4679 #define GPIO_FUNC142_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0368) 4680 /* GPIO_SIG142_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 4681 /*description: if the slow signal bypass the io matrix or not if you want setting 4682 the value to 1*/ 4683 #define GPIO_SIG142_IN_SEL (BIT(7)) 4684 #define GPIO_SIG142_IN_SEL_M (BIT(7)) 4685 #define GPIO_SIG142_IN_SEL_V 0x1 4686 #define GPIO_SIG142_IN_SEL_S 7 4687 /* GPIO_FUNC142_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 4688 /*description: revert the value of the input if you want to revert please set the value to 1*/ 4689 #define GPIO_FUNC142_IN_INV_SEL (BIT(6)) 4690 #define GPIO_FUNC142_IN_INV_SEL_M (BIT(6)) 4691 #define GPIO_FUNC142_IN_INV_SEL_V 0x1 4692 #define GPIO_FUNC142_IN_INV_SEL_S 6 4693 /* GPIO_FUNC142_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 4694 /*description: select one of the 256 inputs*/ 4695 #define GPIO_FUNC142_IN_SEL 0x0000003F 4696 #define GPIO_FUNC142_IN_SEL_M ((GPIO_FUNC142_IN_SEL_V)<<(GPIO_FUNC142_IN_SEL_S)) 4697 #define GPIO_FUNC142_IN_SEL_V 0x3F 4698 #define GPIO_FUNC142_IN_SEL_S 0 4699 4700 #define GPIO_FUNC143_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x036c) 4701 /* GPIO_SIG143_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 4702 /*description: if the slow signal bypass the io matrix or not if you want setting 4703 the value to 1*/ 4704 #define GPIO_SIG143_IN_SEL (BIT(7)) 4705 #define GPIO_SIG143_IN_SEL_M (BIT(7)) 4706 #define GPIO_SIG143_IN_SEL_V 0x1 4707 #define GPIO_SIG143_IN_SEL_S 7 4708 /* GPIO_FUNC143_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 4709 /*description: revert the value of the input if you want to revert please set the value to 1*/ 4710 #define GPIO_FUNC143_IN_INV_SEL (BIT(6)) 4711 #define GPIO_FUNC143_IN_INV_SEL_M (BIT(6)) 4712 #define GPIO_FUNC143_IN_INV_SEL_V 0x1 4713 #define GPIO_FUNC143_IN_INV_SEL_S 6 4714 /* GPIO_FUNC143_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 4715 /*description: select one of the 256 inputs*/ 4716 #define GPIO_FUNC143_IN_SEL 0x0000003F 4717 #define GPIO_FUNC143_IN_SEL_M ((GPIO_FUNC143_IN_SEL_V)<<(GPIO_FUNC143_IN_SEL_S)) 4718 #define GPIO_FUNC143_IN_SEL_V 0x3F 4719 #define GPIO_FUNC143_IN_SEL_S 0 4720 4721 #define GPIO_FUNC144_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0370) 4722 /* GPIO_SIG144_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 4723 /*description: if the slow signal bypass the io matrix or not if you want setting 4724 the value to 1*/ 4725 #define GPIO_SIG144_IN_SEL (BIT(7)) 4726 #define GPIO_SIG144_IN_SEL_M (BIT(7)) 4727 #define GPIO_SIG144_IN_SEL_V 0x1 4728 #define GPIO_SIG144_IN_SEL_S 7 4729 /* GPIO_FUNC144_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 4730 /*description: revert the value of the input if you want to revert please set the value to 1*/ 4731 #define GPIO_FUNC144_IN_INV_SEL (BIT(6)) 4732 #define GPIO_FUNC144_IN_INV_SEL_M (BIT(6)) 4733 #define GPIO_FUNC144_IN_INV_SEL_V 0x1 4734 #define GPIO_FUNC144_IN_INV_SEL_S 6 4735 /* GPIO_FUNC144_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 4736 /*description: select one of the 256 inputs*/ 4737 #define GPIO_FUNC144_IN_SEL 0x0000003F 4738 #define GPIO_FUNC144_IN_SEL_M ((GPIO_FUNC144_IN_SEL_V)<<(GPIO_FUNC144_IN_SEL_S)) 4739 #define GPIO_FUNC144_IN_SEL_V 0x3F 4740 #define GPIO_FUNC144_IN_SEL_S 0 4741 4742 #define GPIO_FUNC145_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0374) 4743 /* GPIO_SIG145_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 4744 /*description: if the slow signal bypass the io matrix or not if you want setting 4745 the value to 1*/ 4746 #define GPIO_SIG145_IN_SEL (BIT(7)) 4747 #define GPIO_SIG145_IN_SEL_M (BIT(7)) 4748 #define GPIO_SIG145_IN_SEL_V 0x1 4749 #define GPIO_SIG145_IN_SEL_S 7 4750 /* GPIO_FUNC145_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 4751 /*description: revert the value of the input if you want to revert please set the value to 1*/ 4752 #define GPIO_FUNC145_IN_INV_SEL (BIT(6)) 4753 #define GPIO_FUNC145_IN_INV_SEL_M (BIT(6)) 4754 #define GPIO_FUNC145_IN_INV_SEL_V 0x1 4755 #define GPIO_FUNC145_IN_INV_SEL_S 6 4756 /* GPIO_FUNC145_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 4757 /*description: select one of the 256 inputs*/ 4758 #define GPIO_FUNC145_IN_SEL 0x0000003F 4759 #define GPIO_FUNC145_IN_SEL_M ((GPIO_FUNC145_IN_SEL_V)<<(GPIO_FUNC145_IN_SEL_S)) 4760 #define GPIO_FUNC145_IN_SEL_V 0x3F 4761 #define GPIO_FUNC145_IN_SEL_S 0 4762 4763 #define GPIO_FUNC146_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0378) 4764 /* GPIO_SIG146_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 4765 /*description: if the slow signal bypass the io matrix or not if you want setting 4766 the value to 1*/ 4767 #define GPIO_SIG146_IN_SEL (BIT(7)) 4768 #define GPIO_SIG146_IN_SEL_M (BIT(7)) 4769 #define GPIO_SIG146_IN_SEL_V 0x1 4770 #define GPIO_SIG146_IN_SEL_S 7 4771 /* GPIO_FUNC146_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 4772 /*description: revert the value of the input if you want to revert please set the value to 1*/ 4773 #define GPIO_FUNC146_IN_INV_SEL (BIT(6)) 4774 #define GPIO_FUNC146_IN_INV_SEL_M (BIT(6)) 4775 #define GPIO_FUNC146_IN_INV_SEL_V 0x1 4776 #define GPIO_FUNC146_IN_INV_SEL_S 6 4777 /* GPIO_FUNC146_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 4778 /*description: select one of the 256 inputs*/ 4779 #define GPIO_FUNC146_IN_SEL 0x0000003F 4780 #define GPIO_FUNC146_IN_SEL_M ((GPIO_FUNC146_IN_SEL_V)<<(GPIO_FUNC146_IN_SEL_S)) 4781 #define GPIO_FUNC146_IN_SEL_V 0x3F 4782 #define GPIO_FUNC146_IN_SEL_S 0 4783 4784 #define GPIO_FUNC147_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x037c) 4785 /* GPIO_SIG147_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 4786 /*description: if the slow signal bypass the io matrix or not if you want setting 4787 the value to 1*/ 4788 #define GPIO_SIG147_IN_SEL (BIT(7)) 4789 #define GPIO_SIG147_IN_SEL_M (BIT(7)) 4790 #define GPIO_SIG147_IN_SEL_V 0x1 4791 #define GPIO_SIG147_IN_SEL_S 7 4792 /* GPIO_FUNC147_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 4793 /*description: revert the value of the input if you want to revert please set the value to 1*/ 4794 #define GPIO_FUNC147_IN_INV_SEL (BIT(6)) 4795 #define GPIO_FUNC147_IN_INV_SEL_M (BIT(6)) 4796 #define GPIO_FUNC147_IN_INV_SEL_V 0x1 4797 #define GPIO_FUNC147_IN_INV_SEL_S 6 4798 /* GPIO_FUNC147_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 4799 /*description: select one of the 256 inputs*/ 4800 #define GPIO_FUNC147_IN_SEL 0x0000003F 4801 #define GPIO_FUNC147_IN_SEL_M ((GPIO_FUNC147_IN_SEL_V)<<(GPIO_FUNC147_IN_SEL_S)) 4802 #define GPIO_FUNC147_IN_SEL_V 0x3F 4803 #define GPIO_FUNC147_IN_SEL_S 0 4804 4805 #define GPIO_FUNC148_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0380) 4806 /* GPIO_SIG148_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 4807 /*description: if the slow signal bypass the io matrix or not if you want setting 4808 the value to 1*/ 4809 #define GPIO_SIG148_IN_SEL (BIT(7)) 4810 #define GPIO_SIG148_IN_SEL_M (BIT(7)) 4811 #define GPIO_SIG148_IN_SEL_V 0x1 4812 #define GPIO_SIG148_IN_SEL_S 7 4813 /* GPIO_FUNC148_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 4814 /*description: revert the value of the input if you want to revert please set the value to 1*/ 4815 #define GPIO_FUNC148_IN_INV_SEL (BIT(6)) 4816 #define GPIO_FUNC148_IN_INV_SEL_M (BIT(6)) 4817 #define GPIO_FUNC148_IN_INV_SEL_V 0x1 4818 #define GPIO_FUNC148_IN_INV_SEL_S 6 4819 /* GPIO_FUNC148_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 4820 /*description: select one of the 256 inputs*/ 4821 #define GPIO_FUNC148_IN_SEL 0x0000003F 4822 #define GPIO_FUNC148_IN_SEL_M ((GPIO_FUNC148_IN_SEL_V)<<(GPIO_FUNC148_IN_SEL_S)) 4823 #define GPIO_FUNC148_IN_SEL_V 0x3F 4824 #define GPIO_FUNC148_IN_SEL_S 0 4825 4826 #define GPIO_FUNC149_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0384) 4827 /* GPIO_SIG149_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 4828 /*description: if the slow signal bypass the io matrix or not if you want setting 4829 the value to 1*/ 4830 #define GPIO_SIG149_IN_SEL (BIT(7)) 4831 #define GPIO_SIG149_IN_SEL_M (BIT(7)) 4832 #define GPIO_SIG149_IN_SEL_V 0x1 4833 #define GPIO_SIG149_IN_SEL_S 7 4834 /* GPIO_FUNC149_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 4835 /*description: revert the value of the input if you want to revert please set the value to 1*/ 4836 #define GPIO_FUNC149_IN_INV_SEL (BIT(6)) 4837 #define GPIO_FUNC149_IN_INV_SEL_M (BIT(6)) 4838 #define GPIO_FUNC149_IN_INV_SEL_V 0x1 4839 #define GPIO_FUNC149_IN_INV_SEL_S 6 4840 /* GPIO_FUNC149_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 4841 /*description: select one of the 256 inputs*/ 4842 #define GPIO_FUNC149_IN_SEL 0x0000003F 4843 #define GPIO_FUNC149_IN_SEL_M ((GPIO_FUNC149_IN_SEL_V)<<(GPIO_FUNC149_IN_SEL_S)) 4844 #define GPIO_FUNC149_IN_SEL_V 0x3F 4845 #define GPIO_FUNC149_IN_SEL_S 0 4846 4847 #define GPIO_FUNC150_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0388) 4848 /* GPIO_SIG150_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 4849 /*description: if the slow signal bypass the io matrix or not if you want setting 4850 the value to 1*/ 4851 #define GPIO_SIG150_IN_SEL (BIT(7)) 4852 #define GPIO_SIG150_IN_SEL_M (BIT(7)) 4853 #define GPIO_SIG150_IN_SEL_V 0x1 4854 #define GPIO_SIG150_IN_SEL_S 7 4855 /* GPIO_FUNC150_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 4856 /*description: revert the value of the input if you want to revert please set the value to 1*/ 4857 #define GPIO_FUNC150_IN_INV_SEL (BIT(6)) 4858 #define GPIO_FUNC150_IN_INV_SEL_M (BIT(6)) 4859 #define GPIO_FUNC150_IN_INV_SEL_V 0x1 4860 #define GPIO_FUNC150_IN_INV_SEL_S 6 4861 /* GPIO_FUNC150_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 4862 /*description: select one of the 256 inputs*/ 4863 #define GPIO_FUNC150_IN_SEL 0x0000003F 4864 #define GPIO_FUNC150_IN_SEL_M ((GPIO_FUNC150_IN_SEL_V)<<(GPIO_FUNC150_IN_SEL_S)) 4865 #define GPIO_FUNC150_IN_SEL_V 0x3F 4866 #define GPIO_FUNC150_IN_SEL_S 0 4867 4868 #define GPIO_FUNC151_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x038c) 4869 /* GPIO_SIG151_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 4870 /*description: if the slow signal bypass the io matrix or not if you want setting 4871 the value to 1*/ 4872 #define GPIO_SIG151_IN_SEL (BIT(7)) 4873 #define GPIO_SIG151_IN_SEL_M (BIT(7)) 4874 #define GPIO_SIG151_IN_SEL_V 0x1 4875 #define GPIO_SIG151_IN_SEL_S 7 4876 /* GPIO_FUNC151_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 4877 /*description: revert the value of the input if you want to revert please set the value to 1*/ 4878 #define GPIO_FUNC151_IN_INV_SEL (BIT(6)) 4879 #define GPIO_FUNC151_IN_INV_SEL_M (BIT(6)) 4880 #define GPIO_FUNC151_IN_INV_SEL_V 0x1 4881 #define GPIO_FUNC151_IN_INV_SEL_S 6 4882 /* GPIO_FUNC151_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 4883 /*description: select one of the 256 inputs*/ 4884 #define GPIO_FUNC151_IN_SEL 0x0000003F 4885 #define GPIO_FUNC151_IN_SEL_M ((GPIO_FUNC151_IN_SEL_V)<<(GPIO_FUNC151_IN_SEL_S)) 4886 #define GPIO_FUNC151_IN_SEL_V 0x3F 4887 #define GPIO_FUNC151_IN_SEL_S 0 4888 4889 #define GPIO_FUNC152_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0390) 4890 /* GPIO_SIG152_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 4891 /*description: if the slow signal bypass the io matrix or not if you want setting 4892 the value to 1*/ 4893 #define GPIO_SIG152_IN_SEL (BIT(7)) 4894 #define GPIO_SIG152_IN_SEL_M (BIT(7)) 4895 #define GPIO_SIG152_IN_SEL_V 0x1 4896 #define GPIO_SIG152_IN_SEL_S 7 4897 /* GPIO_FUNC152_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 4898 /*description: revert the value of the input if you want to revert please set the value to 1*/ 4899 #define GPIO_FUNC152_IN_INV_SEL (BIT(6)) 4900 #define GPIO_FUNC152_IN_INV_SEL_M (BIT(6)) 4901 #define GPIO_FUNC152_IN_INV_SEL_V 0x1 4902 #define GPIO_FUNC152_IN_INV_SEL_S 6 4903 /* GPIO_FUNC152_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 4904 /*description: select one of the 256 inputs*/ 4905 #define GPIO_FUNC152_IN_SEL 0x0000003F 4906 #define GPIO_FUNC152_IN_SEL_M ((GPIO_FUNC152_IN_SEL_V)<<(GPIO_FUNC152_IN_SEL_S)) 4907 #define GPIO_FUNC152_IN_SEL_V 0x3F 4908 #define GPIO_FUNC152_IN_SEL_S 0 4909 4910 #define GPIO_FUNC153_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0394) 4911 /* GPIO_SIG153_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 4912 /*description: if the slow signal bypass the io matrix or not if you want setting 4913 the value to 1*/ 4914 #define GPIO_SIG153_IN_SEL (BIT(7)) 4915 #define GPIO_SIG153_IN_SEL_M (BIT(7)) 4916 #define GPIO_SIG153_IN_SEL_V 0x1 4917 #define GPIO_SIG153_IN_SEL_S 7 4918 /* GPIO_FUNC153_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 4919 /*description: revert the value of the input if you want to revert please set the value to 1*/ 4920 #define GPIO_FUNC153_IN_INV_SEL (BIT(6)) 4921 #define GPIO_FUNC153_IN_INV_SEL_M (BIT(6)) 4922 #define GPIO_FUNC153_IN_INV_SEL_V 0x1 4923 #define GPIO_FUNC153_IN_INV_SEL_S 6 4924 /* GPIO_FUNC153_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 4925 /*description: select one of the 256 inputs*/ 4926 #define GPIO_FUNC153_IN_SEL 0x0000003F 4927 #define GPIO_FUNC153_IN_SEL_M ((GPIO_FUNC153_IN_SEL_V)<<(GPIO_FUNC153_IN_SEL_S)) 4928 #define GPIO_FUNC153_IN_SEL_V 0x3F 4929 #define GPIO_FUNC153_IN_SEL_S 0 4930 4931 #define GPIO_FUNC154_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0398) 4932 /* GPIO_SIG154_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 4933 /*description: if the slow signal bypass the io matrix or not if you want setting 4934 the value to 1*/ 4935 #define GPIO_SIG154_IN_SEL (BIT(7)) 4936 #define GPIO_SIG154_IN_SEL_M (BIT(7)) 4937 #define GPIO_SIG154_IN_SEL_V 0x1 4938 #define GPIO_SIG154_IN_SEL_S 7 4939 /* GPIO_FUNC154_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 4940 /*description: revert the value of the input if you want to revert please set the value to 1*/ 4941 #define GPIO_FUNC154_IN_INV_SEL (BIT(6)) 4942 #define GPIO_FUNC154_IN_INV_SEL_M (BIT(6)) 4943 #define GPIO_FUNC154_IN_INV_SEL_V 0x1 4944 #define GPIO_FUNC154_IN_INV_SEL_S 6 4945 /* GPIO_FUNC154_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 4946 /*description: select one of the 256 inputs*/ 4947 #define GPIO_FUNC154_IN_SEL 0x0000003F 4948 #define GPIO_FUNC154_IN_SEL_M ((GPIO_FUNC154_IN_SEL_V)<<(GPIO_FUNC154_IN_SEL_S)) 4949 #define GPIO_FUNC154_IN_SEL_V 0x3F 4950 #define GPIO_FUNC154_IN_SEL_S 0 4951 4952 #define GPIO_FUNC155_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x039c) 4953 /* GPIO_SIG155_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 4954 /*description: if the slow signal bypass the io matrix or not if you want setting 4955 the value to 1*/ 4956 #define GPIO_SIG155_IN_SEL (BIT(7)) 4957 #define GPIO_SIG155_IN_SEL_M (BIT(7)) 4958 #define GPIO_SIG155_IN_SEL_V 0x1 4959 #define GPIO_SIG155_IN_SEL_S 7 4960 /* GPIO_FUNC155_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 4961 /*description: revert the value of the input if you want to revert please set the value to 1*/ 4962 #define GPIO_FUNC155_IN_INV_SEL (BIT(6)) 4963 #define GPIO_FUNC155_IN_INV_SEL_M (BIT(6)) 4964 #define GPIO_FUNC155_IN_INV_SEL_V 0x1 4965 #define GPIO_FUNC155_IN_INV_SEL_S 6 4966 /* GPIO_FUNC155_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 4967 /*description: select one of the 256 inputs*/ 4968 #define GPIO_FUNC155_IN_SEL 0x0000003F 4969 #define GPIO_FUNC155_IN_SEL_M ((GPIO_FUNC155_IN_SEL_V)<<(GPIO_FUNC155_IN_SEL_S)) 4970 #define GPIO_FUNC155_IN_SEL_V 0x3F 4971 #define GPIO_FUNC155_IN_SEL_S 0 4972 4973 #define GPIO_FUNC156_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03a0) 4974 /* GPIO_SIG156_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 4975 /*description: if the slow signal bypass the io matrix or not if you want setting 4976 the value to 1*/ 4977 #define GPIO_SIG156_IN_SEL (BIT(7)) 4978 #define GPIO_SIG156_IN_SEL_M (BIT(7)) 4979 #define GPIO_SIG156_IN_SEL_V 0x1 4980 #define GPIO_SIG156_IN_SEL_S 7 4981 /* GPIO_FUNC156_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 4982 /*description: revert the value of the input if you want to revert please set the value to 1*/ 4983 #define GPIO_FUNC156_IN_INV_SEL (BIT(6)) 4984 #define GPIO_FUNC156_IN_INV_SEL_M (BIT(6)) 4985 #define GPIO_FUNC156_IN_INV_SEL_V 0x1 4986 #define GPIO_FUNC156_IN_INV_SEL_S 6 4987 /* GPIO_FUNC156_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 4988 /*description: select one of the 256 inputs*/ 4989 #define GPIO_FUNC156_IN_SEL 0x0000003F 4990 #define GPIO_FUNC156_IN_SEL_M ((GPIO_FUNC156_IN_SEL_V)<<(GPIO_FUNC156_IN_SEL_S)) 4991 #define GPIO_FUNC156_IN_SEL_V 0x3F 4992 #define GPIO_FUNC156_IN_SEL_S 0 4993 4994 #define GPIO_FUNC157_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03a4) 4995 /* GPIO_SIG157_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 4996 /*description: if the slow signal bypass the io matrix or not if you want setting 4997 the value to 1*/ 4998 #define GPIO_SIG157_IN_SEL (BIT(7)) 4999 #define GPIO_SIG157_IN_SEL_M (BIT(7)) 5000 #define GPIO_SIG157_IN_SEL_V 0x1 5001 #define GPIO_SIG157_IN_SEL_S 7 5002 /* GPIO_FUNC157_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 5003 /*description: revert the value of the input if you want to revert please set the value to 1*/ 5004 #define GPIO_FUNC157_IN_INV_SEL (BIT(6)) 5005 #define GPIO_FUNC157_IN_INV_SEL_M (BIT(6)) 5006 #define GPIO_FUNC157_IN_INV_SEL_V 0x1 5007 #define GPIO_FUNC157_IN_INV_SEL_S 6 5008 /* GPIO_FUNC157_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 5009 /*description: select one of the 256 inputs*/ 5010 #define GPIO_FUNC157_IN_SEL 0x0000003F 5011 #define GPIO_FUNC157_IN_SEL_M ((GPIO_FUNC157_IN_SEL_V)<<(GPIO_FUNC157_IN_SEL_S)) 5012 #define GPIO_FUNC157_IN_SEL_V 0x3F 5013 #define GPIO_FUNC157_IN_SEL_S 0 5014 5015 #define GPIO_FUNC158_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03a8) 5016 /* GPIO_SIG158_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 5017 /*description: if the slow signal bypass the io matrix or not if you want setting 5018 the value to 1*/ 5019 #define GPIO_SIG158_IN_SEL (BIT(7)) 5020 #define GPIO_SIG158_IN_SEL_M (BIT(7)) 5021 #define GPIO_SIG158_IN_SEL_V 0x1 5022 #define GPIO_SIG158_IN_SEL_S 7 5023 /* GPIO_FUNC158_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 5024 /*description: revert the value of the input if you want to revert please set the value to 1*/ 5025 #define GPIO_FUNC158_IN_INV_SEL (BIT(6)) 5026 #define GPIO_FUNC158_IN_INV_SEL_M (BIT(6)) 5027 #define GPIO_FUNC158_IN_INV_SEL_V 0x1 5028 #define GPIO_FUNC158_IN_INV_SEL_S 6 5029 /* GPIO_FUNC158_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 5030 /*description: select one of the 256 inputs*/ 5031 #define GPIO_FUNC158_IN_SEL 0x0000003F 5032 #define GPIO_FUNC158_IN_SEL_M ((GPIO_FUNC158_IN_SEL_V)<<(GPIO_FUNC158_IN_SEL_S)) 5033 #define GPIO_FUNC158_IN_SEL_V 0x3F 5034 #define GPIO_FUNC158_IN_SEL_S 0 5035 5036 #define GPIO_FUNC159_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03ac) 5037 /* GPIO_SIG159_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 5038 /*description: if the slow signal bypass the io matrix or not if you want setting 5039 the value to 1*/ 5040 #define GPIO_SIG159_IN_SEL (BIT(7)) 5041 #define GPIO_SIG159_IN_SEL_M (BIT(7)) 5042 #define GPIO_SIG159_IN_SEL_V 0x1 5043 #define GPIO_SIG159_IN_SEL_S 7 5044 /* GPIO_FUNC159_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 5045 /*description: revert the value of the input if you want to revert please set the value to 1*/ 5046 #define GPIO_FUNC159_IN_INV_SEL (BIT(6)) 5047 #define GPIO_FUNC159_IN_INV_SEL_M (BIT(6)) 5048 #define GPIO_FUNC159_IN_INV_SEL_V 0x1 5049 #define GPIO_FUNC159_IN_INV_SEL_S 6 5050 /* GPIO_FUNC159_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 5051 /*description: select one of the 256 inputs*/ 5052 #define GPIO_FUNC159_IN_SEL 0x0000003F 5053 #define GPIO_FUNC159_IN_SEL_M ((GPIO_FUNC159_IN_SEL_V)<<(GPIO_FUNC159_IN_SEL_S)) 5054 #define GPIO_FUNC159_IN_SEL_V 0x3F 5055 #define GPIO_FUNC159_IN_SEL_S 0 5056 5057 #define GPIO_FUNC160_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03b0) 5058 /* GPIO_SIG160_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 5059 /*description: if the slow signal bypass the io matrix or not if you want setting 5060 the value to 1*/ 5061 #define GPIO_SIG160_IN_SEL (BIT(7)) 5062 #define GPIO_SIG160_IN_SEL_M (BIT(7)) 5063 #define GPIO_SIG160_IN_SEL_V 0x1 5064 #define GPIO_SIG160_IN_SEL_S 7 5065 /* GPIO_FUNC160_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 5066 /*description: revert the value of the input if you want to revert please set the value to 1*/ 5067 #define GPIO_FUNC160_IN_INV_SEL (BIT(6)) 5068 #define GPIO_FUNC160_IN_INV_SEL_M (BIT(6)) 5069 #define GPIO_FUNC160_IN_INV_SEL_V 0x1 5070 #define GPIO_FUNC160_IN_INV_SEL_S 6 5071 /* GPIO_FUNC160_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 5072 /*description: select one of the 256 inputs*/ 5073 #define GPIO_FUNC160_IN_SEL 0x0000003F 5074 #define GPIO_FUNC160_IN_SEL_M ((GPIO_FUNC160_IN_SEL_V)<<(GPIO_FUNC160_IN_SEL_S)) 5075 #define GPIO_FUNC160_IN_SEL_V 0x3F 5076 #define GPIO_FUNC160_IN_SEL_S 0 5077 5078 #define GPIO_FUNC161_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03b4) 5079 /* GPIO_SIG161_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 5080 /*description: if the slow signal bypass the io matrix or not if you want setting 5081 the value to 1*/ 5082 #define GPIO_SIG161_IN_SEL (BIT(7)) 5083 #define GPIO_SIG161_IN_SEL_M (BIT(7)) 5084 #define GPIO_SIG161_IN_SEL_V 0x1 5085 #define GPIO_SIG161_IN_SEL_S 7 5086 /* GPIO_FUNC161_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 5087 /*description: revert the value of the input if you want to revert please set the value to 1*/ 5088 #define GPIO_FUNC161_IN_INV_SEL (BIT(6)) 5089 #define GPIO_FUNC161_IN_INV_SEL_M (BIT(6)) 5090 #define GPIO_FUNC161_IN_INV_SEL_V 0x1 5091 #define GPIO_FUNC161_IN_INV_SEL_S 6 5092 /* GPIO_FUNC161_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 5093 /*description: select one of the 256 inputs*/ 5094 #define GPIO_FUNC161_IN_SEL 0x0000003F 5095 #define GPIO_FUNC161_IN_SEL_M ((GPIO_FUNC161_IN_SEL_V)<<(GPIO_FUNC161_IN_SEL_S)) 5096 #define GPIO_FUNC161_IN_SEL_V 0x3F 5097 #define GPIO_FUNC161_IN_SEL_S 0 5098 5099 #define GPIO_FUNC162_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03b8) 5100 /* GPIO_SIG162_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 5101 /*description: if the slow signal bypass the io matrix or not if you want setting 5102 the value to 1*/ 5103 #define GPIO_SIG162_IN_SEL (BIT(7)) 5104 #define GPIO_SIG162_IN_SEL_M (BIT(7)) 5105 #define GPIO_SIG162_IN_SEL_V 0x1 5106 #define GPIO_SIG162_IN_SEL_S 7 5107 /* GPIO_FUNC162_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 5108 /*description: revert the value of the input if you want to revert please set the value to 1*/ 5109 #define GPIO_FUNC162_IN_INV_SEL (BIT(6)) 5110 #define GPIO_FUNC162_IN_INV_SEL_M (BIT(6)) 5111 #define GPIO_FUNC162_IN_INV_SEL_V 0x1 5112 #define GPIO_FUNC162_IN_INV_SEL_S 6 5113 /* GPIO_FUNC162_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 5114 /*description: select one of the 256 inputs*/ 5115 #define GPIO_FUNC162_IN_SEL 0x0000003F 5116 #define GPIO_FUNC162_IN_SEL_M ((GPIO_FUNC162_IN_SEL_V)<<(GPIO_FUNC162_IN_SEL_S)) 5117 #define GPIO_FUNC162_IN_SEL_V 0x3F 5118 #define GPIO_FUNC162_IN_SEL_S 0 5119 5120 #define GPIO_FUNC163_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03bc) 5121 /* GPIO_SIG163_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 5122 /*description: if the slow signal bypass the io matrix or not if you want setting 5123 the value to 1*/ 5124 #define GPIO_SIG163_IN_SEL (BIT(7)) 5125 #define GPIO_SIG163_IN_SEL_M (BIT(7)) 5126 #define GPIO_SIG163_IN_SEL_V 0x1 5127 #define GPIO_SIG163_IN_SEL_S 7 5128 /* GPIO_FUNC163_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 5129 /*description: revert the value of the input if you want to revert please set the value to 1*/ 5130 #define GPIO_FUNC163_IN_INV_SEL (BIT(6)) 5131 #define GPIO_FUNC163_IN_INV_SEL_M (BIT(6)) 5132 #define GPIO_FUNC163_IN_INV_SEL_V 0x1 5133 #define GPIO_FUNC163_IN_INV_SEL_S 6 5134 /* GPIO_FUNC163_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 5135 /*description: select one of the 256 inputs*/ 5136 #define GPIO_FUNC163_IN_SEL 0x0000003F 5137 #define GPIO_FUNC163_IN_SEL_M ((GPIO_FUNC163_IN_SEL_V)<<(GPIO_FUNC163_IN_SEL_S)) 5138 #define GPIO_FUNC163_IN_SEL_V 0x3F 5139 #define GPIO_FUNC163_IN_SEL_S 0 5140 5141 #define GPIO_FUNC164_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03c0) 5142 /* GPIO_SIG164_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 5143 /*description: if the slow signal bypass the io matrix or not if you want setting 5144 the value to 1*/ 5145 #define GPIO_SIG164_IN_SEL (BIT(7)) 5146 #define GPIO_SIG164_IN_SEL_M (BIT(7)) 5147 #define GPIO_SIG164_IN_SEL_V 0x1 5148 #define GPIO_SIG164_IN_SEL_S 7 5149 /* GPIO_FUNC164_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 5150 /*description: revert the value of the input if you want to revert please set the value to 1*/ 5151 #define GPIO_FUNC164_IN_INV_SEL (BIT(6)) 5152 #define GPIO_FUNC164_IN_INV_SEL_M (BIT(6)) 5153 #define GPIO_FUNC164_IN_INV_SEL_V 0x1 5154 #define GPIO_FUNC164_IN_INV_SEL_S 6 5155 /* GPIO_FUNC164_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 5156 /*description: select one of the 256 inputs*/ 5157 #define GPIO_FUNC164_IN_SEL 0x0000003F 5158 #define GPIO_FUNC164_IN_SEL_M ((GPIO_FUNC164_IN_SEL_V)<<(GPIO_FUNC164_IN_SEL_S)) 5159 #define GPIO_FUNC164_IN_SEL_V 0x3F 5160 #define GPIO_FUNC164_IN_SEL_S 0 5161 5162 #define GPIO_FUNC165_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03c4) 5163 /* GPIO_SIG165_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 5164 /*description: if the slow signal bypass the io matrix or not if you want setting 5165 the value to 1*/ 5166 #define GPIO_SIG165_IN_SEL (BIT(7)) 5167 #define GPIO_SIG165_IN_SEL_M (BIT(7)) 5168 #define GPIO_SIG165_IN_SEL_V 0x1 5169 #define GPIO_SIG165_IN_SEL_S 7 5170 /* GPIO_FUNC165_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 5171 /*description: revert the value of the input if you want to revert please set the value to 1*/ 5172 #define GPIO_FUNC165_IN_INV_SEL (BIT(6)) 5173 #define GPIO_FUNC165_IN_INV_SEL_M (BIT(6)) 5174 #define GPIO_FUNC165_IN_INV_SEL_V 0x1 5175 #define GPIO_FUNC165_IN_INV_SEL_S 6 5176 /* GPIO_FUNC165_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 5177 /*description: select one of the 256 inputs*/ 5178 #define GPIO_FUNC165_IN_SEL 0x0000003F 5179 #define GPIO_FUNC165_IN_SEL_M ((GPIO_FUNC165_IN_SEL_V)<<(GPIO_FUNC165_IN_SEL_S)) 5180 #define GPIO_FUNC165_IN_SEL_V 0x3F 5181 #define GPIO_FUNC165_IN_SEL_S 0 5182 5183 #define GPIO_FUNC166_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03c8) 5184 /* GPIO_SIG166_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 5185 /*description: if the slow signal bypass the io matrix or not if you want setting 5186 the value to 1*/ 5187 #define GPIO_SIG166_IN_SEL (BIT(7)) 5188 #define GPIO_SIG166_IN_SEL_M (BIT(7)) 5189 #define GPIO_SIG166_IN_SEL_V 0x1 5190 #define GPIO_SIG166_IN_SEL_S 7 5191 /* GPIO_FUNC166_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 5192 /*description: revert the value of the input if you want to revert please set the value to 1*/ 5193 #define GPIO_FUNC166_IN_INV_SEL (BIT(6)) 5194 #define GPIO_FUNC166_IN_INV_SEL_M (BIT(6)) 5195 #define GPIO_FUNC166_IN_INV_SEL_V 0x1 5196 #define GPIO_FUNC166_IN_INV_SEL_S 6 5197 /* GPIO_FUNC166_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 5198 /*description: select one of the 256 inputs*/ 5199 #define GPIO_FUNC166_IN_SEL 0x0000003F 5200 #define GPIO_FUNC166_IN_SEL_M ((GPIO_FUNC166_IN_SEL_V)<<(GPIO_FUNC166_IN_SEL_S)) 5201 #define GPIO_FUNC166_IN_SEL_V 0x3F 5202 #define GPIO_FUNC166_IN_SEL_S 0 5203 5204 #define GPIO_FUNC167_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03cc) 5205 /* GPIO_SIG167_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 5206 /*description: if the slow signal bypass the io matrix or not if you want setting 5207 the value to 1*/ 5208 #define GPIO_SIG167_IN_SEL (BIT(7)) 5209 #define GPIO_SIG167_IN_SEL_M (BIT(7)) 5210 #define GPIO_SIG167_IN_SEL_V 0x1 5211 #define GPIO_SIG167_IN_SEL_S 7 5212 /* GPIO_FUNC167_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 5213 /*description: revert the value of the input if you want to revert please set the value to 1*/ 5214 #define GPIO_FUNC167_IN_INV_SEL (BIT(6)) 5215 #define GPIO_FUNC167_IN_INV_SEL_M (BIT(6)) 5216 #define GPIO_FUNC167_IN_INV_SEL_V 0x1 5217 #define GPIO_FUNC167_IN_INV_SEL_S 6 5218 /* GPIO_FUNC167_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 5219 /*description: select one of the 256 inputs*/ 5220 #define GPIO_FUNC167_IN_SEL 0x0000003F 5221 #define GPIO_FUNC167_IN_SEL_M ((GPIO_FUNC167_IN_SEL_V)<<(GPIO_FUNC167_IN_SEL_S)) 5222 #define GPIO_FUNC167_IN_SEL_V 0x3F 5223 #define GPIO_FUNC167_IN_SEL_S 0 5224 5225 #define GPIO_FUNC168_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03d0) 5226 /* GPIO_SIG168_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 5227 /*description: if the slow signal bypass the io matrix or not if you want setting 5228 the value to 1*/ 5229 #define GPIO_SIG168_IN_SEL (BIT(7)) 5230 #define GPIO_SIG168_IN_SEL_M (BIT(7)) 5231 #define GPIO_SIG168_IN_SEL_V 0x1 5232 #define GPIO_SIG168_IN_SEL_S 7 5233 /* GPIO_FUNC168_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 5234 /*description: revert the value of the input if you want to revert please set the value to 1*/ 5235 #define GPIO_FUNC168_IN_INV_SEL (BIT(6)) 5236 #define GPIO_FUNC168_IN_INV_SEL_M (BIT(6)) 5237 #define GPIO_FUNC168_IN_INV_SEL_V 0x1 5238 #define GPIO_FUNC168_IN_INV_SEL_S 6 5239 /* GPIO_FUNC168_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 5240 /*description: select one of the 256 inputs*/ 5241 #define GPIO_FUNC168_IN_SEL 0x0000003F 5242 #define GPIO_FUNC168_IN_SEL_M ((GPIO_FUNC168_IN_SEL_V)<<(GPIO_FUNC168_IN_SEL_S)) 5243 #define GPIO_FUNC168_IN_SEL_V 0x3F 5244 #define GPIO_FUNC168_IN_SEL_S 0 5245 5246 #define GPIO_FUNC169_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03d4) 5247 /* GPIO_SIG169_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 5248 /*description: if the slow signal bypass the io matrix or not if you want setting 5249 the value to 1*/ 5250 #define GPIO_SIG169_IN_SEL (BIT(7)) 5251 #define GPIO_SIG169_IN_SEL_M (BIT(7)) 5252 #define GPIO_SIG169_IN_SEL_V 0x1 5253 #define GPIO_SIG169_IN_SEL_S 7 5254 /* GPIO_FUNC169_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 5255 /*description: revert the value of the input if you want to revert please set the value to 1*/ 5256 #define GPIO_FUNC169_IN_INV_SEL (BIT(6)) 5257 #define GPIO_FUNC169_IN_INV_SEL_M (BIT(6)) 5258 #define GPIO_FUNC169_IN_INV_SEL_V 0x1 5259 #define GPIO_FUNC169_IN_INV_SEL_S 6 5260 /* GPIO_FUNC169_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 5261 /*description: select one of the 256 inputs*/ 5262 #define GPIO_FUNC169_IN_SEL 0x0000003F 5263 #define GPIO_FUNC169_IN_SEL_M ((GPIO_FUNC169_IN_SEL_V)<<(GPIO_FUNC169_IN_SEL_S)) 5264 #define GPIO_FUNC169_IN_SEL_V 0x3F 5265 #define GPIO_FUNC169_IN_SEL_S 0 5266 5267 #define GPIO_FUNC170_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03d8) 5268 /* GPIO_SIG170_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 5269 /*description: if the slow signal bypass the io matrix or not if you want setting 5270 the value to 1*/ 5271 #define GPIO_SIG170_IN_SEL (BIT(7)) 5272 #define GPIO_SIG170_IN_SEL_M (BIT(7)) 5273 #define GPIO_SIG170_IN_SEL_V 0x1 5274 #define GPIO_SIG170_IN_SEL_S 7 5275 /* GPIO_FUNC170_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 5276 /*description: revert the value of the input if you want to revert please set the value to 1*/ 5277 #define GPIO_FUNC170_IN_INV_SEL (BIT(6)) 5278 #define GPIO_FUNC170_IN_INV_SEL_M (BIT(6)) 5279 #define GPIO_FUNC170_IN_INV_SEL_V 0x1 5280 #define GPIO_FUNC170_IN_INV_SEL_S 6 5281 /* GPIO_FUNC170_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 5282 /*description: select one of the 256 inputs*/ 5283 #define GPIO_FUNC170_IN_SEL 0x0000003F 5284 #define GPIO_FUNC170_IN_SEL_M ((GPIO_FUNC170_IN_SEL_V)<<(GPIO_FUNC170_IN_SEL_S)) 5285 #define GPIO_FUNC170_IN_SEL_V 0x3F 5286 #define GPIO_FUNC170_IN_SEL_S 0 5287 5288 #define GPIO_FUNC171_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03dc) 5289 /* GPIO_SIG171_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 5290 /*description: if the slow signal bypass the io matrix or not if you want setting 5291 the value to 1*/ 5292 #define GPIO_SIG171_IN_SEL (BIT(7)) 5293 #define GPIO_SIG171_IN_SEL_M (BIT(7)) 5294 #define GPIO_SIG171_IN_SEL_V 0x1 5295 #define GPIO_SIG171_IN_SEL_S 7 5296 /* GPIO_FUNC171_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 5297 /*description: revert the value of the input if you want to revert please set the value to 1*/ 5298 #define GPIO_FUNC171_IN_INV_SEL (BIT(6)) 5299 #define GPIO_FUNC171_IN_INV_SEL_M (BIT(6)) 5300 #define GPIO_FUNC171_IN_INV_SEL_V 0x1 5301 #define GPIO_FUNC171_IN_INV_SEL_S 6 5302 /* GPIO_FUNC171_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 5303 /*description: select one of the 256 inputs*/ 5304 #define GPIO_FUNC171_IN_SEL 0x0000003F 5305 #define GPIO_FUNC171_IN_SEL_M ((GPIO_FUNC171_IN_SEL_V)<<(GPIO_FUNC171_IN_SEL_S)) 5306 #define GPIO_FUNC171_IN_SEL_V 0x3F 5307 #define GPIO_FUNC171_IN_SEL_S 0 5308 5309 #define GPIO_FUNC172_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03e0) 5310 /* GPIO_SIG172_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 5311 /*description: if the slow signal bypass the io matrix or not if you want setting 5312 the value to 1*/ 5313 #define GPIO_SIG172_IN_SEL (BIT(7)) 5314 #define GPIO_SIG172_IN_SEL_M (BIT(7)) 5315 #define GPIO_SIG172_IN_SEL_V 0x1 5316 #define GPIO_SIG172_IN_SEL_S 7 5317 /* GPIO_FUNC172_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 5318 /*description: revert the value of the input if you want to revert please set the value to 1*/ 5319 #define GPIO_FUNC172_IN_INV_SEL (BIT(6)) 5320 #define GPIO_FUNC172_IN_INV_SEL_M (BIT(6)) 5321 #define GPIO_FUNC172_IN_INV_SEL_V 0x1 5322 #define GPIO_FUNC172_IN_INV_SEL_S 6 5323 /* GPIO_FUNC172_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 5324 /*description: select one of the 256 inputs*/ 5325 #define GPIO_FUNC172_IN_SEL 0x0000003F 5326 #define GPIO_FUNC172_IN_SEL_M ((GPIO_FUNC172_IN_SEL_V)<<(GPIO_FUNC172_IN_SEL_S)) 5327 #define GPIO_FUNC172_IN_SEL_V 0x3F 5328 #define GPIO_FUNC172_IN_SEL_S 0 5329 5330 #define GPIO_FUNC173_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03e4) 5331 /* GPIO_SIG173_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 5332 /*description: if the slow signal bypass the io matrix or not if you want setting 5333 the value to 1*/ 5334 #define GPIO_SIG173_IN_SEL (BIT(7)) 5335 #define GPIO_SIG173_IN_SEL_M (BIT(7)) 5336 #define GPIO_SIG173_IN_SEL_V 0x1 5337 #define GPIO_SIG173_IN_SEL_S 7 5338 /* GPIO_FUNC173_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 5339 /*description: revert the value of the input if you want to revert please set the value to 1*/ 5340 #define GPIO_FUNC173_IN_INV_SEL (BIT(6)) 5341 #define GPIO_FUNC173_IN_INV_SEL_M (BIT(6)) 5342 #define GPIO_FUNC173_IN_INV_SEL_V 0x1 5343 #define GPIO_FUNC173_IN_INV_SEL_S 6 5344 /* GPIO_FUNC173_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 5345 /*description: select one of the 256 inputs*/ 5346 #define GPIO_FUNC173_IN_SEL 0x0000003F 5347 #define GPIO_FUNC173_IN_SEL_M ((GPIO_FUNC173_IN_SEL_V)<<(GPIO_FUNC173_IN_SEL_S)) 5348 #define GPIO_FUNC173_IN_SEL_V 0x3F 5349 #define GPIO_FUNC173_IN_SEL_S 0 5350 5351 #define GPIO_FUNC174_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03e8) 5352 /* GPIO_SIG174_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 5353 /*description: if the slow signal bypass the io matrix or not if you want setting 5354 the value to 1*/ 5355 #define GPIO_SIG174_IN_SEL (BIT(7)) 5356 #define GPIO_SIG174_IN_SEL_M (BIT(7)) 5357 #define GPIO_SIG174_IN_SEL_V 0x1 5358 #define GPIO_SIG174_IN_SEL_S 7 5359 /* GPIO_FUNC174_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 5360 /*description: revert the value of the input if you want to revert please set the value to 1*/ 5361 #define GPIO_FUNC174_IN_INV_SEL (BIT(6)) 5362 #define GPIO_FUNC174_IN_INV_SEL_M (BIT(6)) 5363 #define GPIO_FUNC174_IN_INV_SEL_V 0x1 5364 #define GPIO_FUNC174_IN_INV_SEL_S 6 5365 /* GPIO_FUNC174_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 5366 /*description: select one of the 256 inputs*/ 5367 #define GPIO_FUNC174_IN_SEL 0x0000003F 5368 #define GPIO_FUNC174_IN_SEL_M ((GPIO_FUNC174_IN_SEL_V)<<(GPIO_FUNC174_IN_SEL_S)) 5369 #define GPIO_FUNC174_IN_SEL_V 0x3F 5370 #define GPIO_FUNC174_IN_SEL_S 0 5371 5372 #define GPIO_FUNC175_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03ec) 5373 /* GPIO_SIG175_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 5374 /*description: if the slow signal bypass the io matrix or not if you want setting 5375 the value to 1*/ 5376 #define GPIO_SIG175_IN_SEL (BIT(7)) 5377 #define GPIO_SIG175_IN_SEL_M (BIT(7)) 5378 #define GPIO_SIG175_IN_SEL_V 0x1 5379 #define GPIO_SIG175_IN_SEL_S 7 5380 /* GPIO_FUNC175_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 5381 /*description: revert the value of the input if you want to revert please set the value to 1*/ 5382 #define GPIO_FUNC175_IN_INV_SEL (BIT(6)) 5383 #define GPIO_FUNC175_IN_INV_SEL_M (BIT(6)) 5384 #define GPIO_FUNC175_IN_INV_SEL_V 0x1 5385 #define GPIO_FUNC175_IN_INV_SEL_S 6 5386 /* GPIO_FUNC175_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 5387 /*description: select one of the 256 inputs*/ 5388 #define GPIO_FUNC175_IN_SEL 0x0000003F 5389 #define GPIO_FUNC175_IN_SEL_M ((GPIO_FUNC175_IN_SEL_V)<<(GPIO_FUNC175_IN_SEL_S)) 5390 #define GPIO_FUNC175_IN_SEL_V 0x3F 5391 #define GPIO_FUNC175_IN_SEL_S 0 5392 5393 #define GPIO_FUNC176_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03f0) 5394 /* GPIO_SIG176_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 5395 /*description: if the slow signal bypass the io matrix or not if you want setting 5396 the value to 1*/ 5397 #define GPIO_SIG176_IN_SEL (BIT(7)) 5398 #define GPIO_SIG176_IN_SEL_M (BIT(7)) 5399 #define GPIO_SIG176_IN_SEL_V 0x1 5400 #define GPIO_SIG176_IN_SEL_S 7 5401 /* GPIO_FUNC176_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 5402 /*description: revert the value of the input if you want to revert please set the value to 1*/ 5403 #define GPIO_FUNC176_IN_INV_SEL (BIT(6)) 5404 #define GPIO_FUNC176_IN_INV_SEL_M (BIT(6)) 5405 #define GPIO_FUNC176_IN_INV_SEL_V 0x1 5406 #define GPIO_FUNC176_IN_INV_SEL_S 6 5407 /* GPIO_FUNC176_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 5408 /*description: select one of the 256 inputs*/ 5409 #define GPIO_FUNC176_IN_SEL 0x0000003F 5410 #define GPIO_FUNC176_IN_SEL_M ((GPIO_FUNC176_IN_SEL_V)<<(GPIO_FUNC176_IN_SEL_S)) 5411 #define GPIO_FUNC176_IN_SEL_V 0x3F 5412 #define GPIO_FUNC176_IN_SEL_S 0 5413 5414 #define GPIO_FUNC177_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03f4) 5415 /* GPIO_SIG177_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 5416 /*description: if the slow signal bypass the io matrix or not if you want setting 5417 the value to 1*/ 5418 #define GPIO_SIG177_IN_SEL (BIT(7)) 5419 #define GPIO_SIG177_IN_SEL_M (BIT(7)) 5420 #define GPIO_SIG177_IN_SEL_V 0x1 5421 #define GPIO_SIG177_IN_SEL_S 7 5422 /* GPIO_FUNC177_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 5423 /*description: revert the value of the input if you want to revert please set the value to 1*/ 5424 #define GPIO_FUNC177_IN_INV_SEL (BIT(6)) 5425 #define GPIO_FUNC177_IN_INV_SEL_M (BIT(6)) 5426 #define GPIO_FUNC177_IN_INV_SEL_V 0x1 5427 #define GPIO_FUNC177_IN_INV_SEL_S 6 5428 /* GPIO_FUNC177_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 5429 /*description: select one of the 256 inputs*/ 5430 #define GPIO_FUNC177_IN_SEL 0x0000003F 5431 #define GPIO_FUNC177_IN_SEL_M ((GPIO_FUNC177_IN_SEL_V)<<(GPIO_FUNC177_IN_SEL_S)) 5432 #define GPIO_FUNC177_IN_SEL_V 0x3F 5433 #define GPIO_FUNC177_IN_SEL_S 0 5434 5435 #define GPIO_FUNC178_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03f8) 5436 /* GPIO_SIG178_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 5437 /*description: if the slow signal bypass the io matrix or not if you want setting 5438 the value to 1*/ 5439 #define GPIO_SIG178_IN_SEL (BIT(7)) 5440 #define GPIO_SIG178_IN_SEL_M (BIT(7)) 5441 #define GPIO_SIG178_IN_SEL_V 0x1 5442 #define GPIO_SIG178_IN_SEL_S 7 5443 /* GPIO_FUNC178_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 5444 /*description: revert the value of the input if you want to revert please set the value to 1*/ 5445 #define GPIO_FUNC178_IN_INV_SEL (BIT(6)) 5446 #define GPIO_FUNC178_IN_INV_SEL_M (BIT(6)) 5447 #define GPIO_FUNC178_IN_INV_SEL_V 0x1 5448 #define GPIO_FUNC178_IN_INV_SEL_S 6 5449 /* GPIO_FUNC178_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 5450 /*description: select one of the 256 inputs*/ 5451 #define GPIO_FUNC178_IN_SEL 0x0000003F 5452 #define GPIO_FUNC178_IN_SEL_M ((GPIO_FUNC178_IN_SEL_V)<<(GPIO_FUNC178_IN_SEL_S)) 5453 #define GPIO_FUNC178_IN_SEL_V 0x3F 5454 #define GPIO_FUNC178_IN_SEL_S 0 5455 5456 #define GPIO_FUNC179_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03fc) 5457 /* GPIO_SIG179_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 5458 /*description: if the slow signal bypass the io matrix or not if you want setting 5459 the value to 1*/ 5460 #define GPIO_SIG179_IN_SEL (BIT(7)) 5461 #define GPIO_SIG179_IN_SEL_M (BIT(7)) 5462 #define GPIO_SIG179_IN_SEL_V 0x1 5463 #define GPIO_SIG179_IN_SEL_S 7 5464 /* GPIO_FUNC179_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 5465 /*description: revert the value of the input if you want to revert please set the value to 1*/ 5466 #define GPIO_FUNC179_IN_INV_SEL (BIT(6)) 5467 #define GPIO_FUNC179_IN_INV_SEL_M (BIT(6)) 5468 #define GPIO_FUNC179_IN_INV_SEL_V 0x1 5469 #define GPIO_FUNC179_IN_INV_SEL_S 6 5470 /* GPIO_FUNC179_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 5471 /*description: select one of the 256 inputs*/ 5472 #define GPIO_FUNC179_IN_SEL 0x0000003F 5473 #define GPIO_FUNC179_IN_SEL_M ((GPIO_FUNC179_IN_SEL_V)<<(GPIO_FUNC179_IN_SEL_S)) 5474 #define GPIO_FUNC179_IN_SEL_V 0x3F 5475 #define GPIO_FUNC179_IN_SEL_S 0 5476 5477 #define GPIO_FUNC180_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0400) 5478 /* GPIO_SIG180_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 5479 /*description: if the slow signal bypass the io matrix or not if you want setting 5480 the value to 1*/ 5481 #define GPIO_SIG180_IN_SEL (BIT(7)) 5482 #define GPIO_SIG180_IN_SEL_M (BIT(7)) 5483 #define GPIO_SIG180_IN_SEL_V 0x1 5484 #define GPIO_SIG180_IN_SEL_S 7 5485 /* GPIO_FUNC180_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 5486 /*description: revert the value of the input if you want to revert please set the value to 1*/ 5487 #define GPIO_FUNC180_IN_INV_SEL (BIT(6)) 5488 #define GPIO_FUNC180_IN_INV_SEL_M (BIT(6)) 5489 #define GPIO_FUNC180_IN_INV_SEL_V 0x1 5490 #define GPIO_FUNC180_IN_INV_SEL_S 6 5491 /* GPIO_FUNC180_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 5492 /*description: select one of the 256 inputs*/ 5493 #define GPIO_FUNC180_IN_SEL 0x0000003F 5494 #define GPIO_FUNC180_IN_SEL_M ((GPIO_FUNC180_IN_SEL_V)<<(GPIO_FUNC180_IN_SEL_S)) 5495 #define GPIO_FUNC180_IN_SEL_V 0x3F 5496 #define GPIO_FUNC180_IN_SEL_S 0 5497 5498 #define GPIO_FUNC181_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0404) 5499 /* GPIO_SIG181_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 5500 /*description: if the slow signal bypass the io matrix or not if you want setting 5501 the value to 1*/ 5502 #define GPIO_SIG181_IN_SEL (BIT(7)) 5503 #define GPIO_SIG181_IN_SEL_M (BIT(7)) 5504 #define GPIO_SIG181_IN_SEL_V 0x1 5505 #define GPIO_SIG181_IN_SEL_S 7 5506 /* GPIO_FUNC181_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 5507 /*description: revert the value of the input if you want to revert please set the value to 1*/ 5508 #define GPIO_FUNC181_IN_INV_SEL (BIT(6)) 5509 #define GPIO_FUNC181_IN_INV_SEL_M (BIT(6)) 5510 #define GPIO_FUNC181_IN_INV_SEL_V 0x1 5511 #define GPIO_FUNC181_IN_INV_SEL_S 6 5512 /* GPIO_FUNC181_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 5513 /*description: select one of the 256 inputs*/ 5514 #define GPIO_FUNC181_IN_SEL 0x0000003F 5515 #define GPIO_FUNC181_IN_SEL_M ((GPIO_FUNC181_IN_SEL_V)<<(GPIO_FUNC181_IN_SEL_S)) 5516 #define GPIO_FUNC181_IN_SEL_V 0x3F 5517 #define GPIO_FUNC181_IN_SEL_S 0 5518 5519 #define GPIO_FUNC182_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0408) 5520 /* GPIO_SIG182_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 5521 /*description: if the slow signal bypass the io matrix or not if you want setting 5522 the value to 1*/ 5523 #define GPIO_SIG182_IN_SEL (BIT(7)) 5524 #define GPIO_SIG182_IN_SEL_M (BIT(7)) 5525 #define GPIO_SIG182_IN_SEL_V 0x1 5526 #define GPIO_SIG182_IN_SEL_S 7 5527 /* GPIO_FUNC182_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 5528 /*description: revert the value of the input if you want to revert please set the value to 1*/ 5529 #define GPIO_FUNC182_IN_INV_SEL (BIT(6)) 5530 #define GPIO_FUNC182_IN_INV_SEL_M (BIT(6)) 5531 #define GPIO_FUNC182_IN_INV_SEL_V 0x1 5532 #define GPIO_FUNC182_IN_INV_SEL_S 6 5533 /* GPIO_FUNC182_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 5534 /*description: select one of the 256 inputs*/ 5535 #define GPIO_FUNC182_IN_SEL 0x0000003F 5536 #define GPIO_FUNC182_IN_SEL_M ((GPIO_FUNC182_IN_SEL_V)<<(GPIO_FUNC182_IN_SEL_S)) 5537 #define GPIO_FUNC182_IN_SEL_V 0x3F 5538 #define GPIO_FUNC182_IN_SEL_S 0 5539 5540 #define GPIO_FUNC183_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x040c) 5541 /* GPIO_SIG183_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 5542 /*description: if the slow signal bypass the io matrix or not if you want setting 5543 the value to 1*/ 5544 #define GPIO_SIG183_IN_SEL (BIT(7)) 5545 #define GPIO_SIG183_IN_SEL_M (BIT(7)) 5546 #define GPIO_SIG183_IN_SEL_V 0x1 5547 #define GPIO_SIG183_IN_SEL_S 7 5548 /* GPIO_FUNC183_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 5549 /*description: revert the value of the input if you want to revert please set the value to 1*/ 5550 #define GPIO_FUNC183_IN_INV_SEL (BIT(6)) 5551 #define GPIO_FUNC183_IN_INV_SEL_M (BIT(6)) 5552 #define GPIO_FUNC183_IN_INV_SEL_V 0x1 5553 #define GPIO_FUNC183_IN_INV_SEL_S 6 5554 /* GPIO_FUNC183_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 5555 /*description: select one of the 256 inputs*/ 5556 #define GPIO_FUNC183_IN_SEL 0x0000003F 5557 #define GPIO_FUNC183_IN_SEL_M ((GPIO_FUNC183_IN_SEL_V)<<(GPIO_FUNC183_IN_SEL_S)) 5558 #define GPIO_FUNC183_IN_SEL_V 0x3F 5559 #define GPIO_FUNC183_IN_SEL_S 0 5560 5561 #define GPIO_FUNC184_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0410) 5562 /* GPIO_SIG184_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 5563 /*description: if the slow signal bypass the io matrix or not if you want setting 5564 the value to 1*/ 5565 #define GPIO_SIG184_IN_SEL (BIT(7)) 5566 #define GPIO_SIG184_IN_SEL_M (BIT(7)) 5567 #define GPIO_SIG184_IN_SEL_V 0x1 5568 #define GPIO_SIG184_IN_SEL_S 7 5569 /* GPIO_FUNC184_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 5570 /*description: revert the value of the input if you want to revert please set the value to 1*/ 5571 #define GPIO_FUNC184_IN_INV_SEL (BIT(6)) 5572 #define GPIO_FUNC184_IN_INV_SEL_M (BIT(6)) 5573 #define GPIO_FUNC184_IN_INV_SEL_V 0x1 5574 #define GPIO_FUNC184_IN_INV_SEL_S 6 5575 /* GPIO_FUNC184_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 5576 /*description: select one of the 256 inputs*/ 5577 #define GPIO_FUNC184_IN_SEL 0x0000003F 5578 #define GPIO_FUNC184_IN_SEL_M ((GPIO_FUNC184_IN_SEL_V)<<(GPIO_FUNC184_IN_SEL_S)) 5579 #define GPIO_FUNC184_IN_SEL_V 0x3F 5580 #define GPIO_FUNC184_IN_SEL_S 0 5581 5582 #define GPIO_FUNC185_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0414) 5583 /* GPIO_SIG185_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 5584 /*description: if the slow signal bypass the io matrix or not if you want setting 5585 the value to 1*/ 5586 #define GPIO_SIG185_IN_SEL (BIT(7)) 5587 #define GPIO_SIG185_IN_SEL_M (BIT(7)) 5588 #define GPIO_SIG185_IN_SEL_V 0x1 5589 #define GPIO_SIG185_IN_SEL_S 7 5590 /* GPIO_FUNC185_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 5591 /*description: revert the value of the input if you want to revert please set the value to 1*/ 5592 #define GPIO_FUNC185_IN_INV_SEL (BIT(6)) 5593 #define GPIO_FUNC185_IN_INV_SEL_M (BIT(6)) 5594 #define GPIO_FUNC185_IN_INV_SEL_V 0x1 5595 #define GPIO_FUNC185_IN_INV_SEL_S 6 5596 /* GPIO_FUNC185_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 5597 /*description: select one of the 256 inputs*/ 5598 #define GPIO_FUNC185_IN_SEL 0x0000003F 5599 #define GPIO_FUNC185_IN_SEL_M ((GPIO_FUNC185_IN_SEL_V)<<(GPIO_FUNC185_IN_SEL_S)) 5600 #define GPIO_FUNC185_IN_SEL_V 0x3F 5601 #define GPIO_FUNC185_IN_SEL_S 0 5602 5603 #define GPIO_FUNC186_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0418) 5604 /* GPIO_SIG186_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 5605 /*description: if the slow signal bypass the io matrix or not if you want setting 5606 the value to 1*/ 5607 #define GPIO_SIG186_IN_SEL (BIT(7)) 5608 #define GPIO_SIG186_IN_SEL_M (BIT(7)) 5609 #define GPIO_SIG186_IN_SEL_V 0x1 5610 #define GPIO_SIG186_IN_SEL_S 7 5611 /* GPIO_FUNC186_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 5612 /*description: revert the value of the input if you want to revert please set the value to 1*/ 5613 #define GPIO_FUNC186_IN_INV_SEL (BIT(6)) 5614 #define GPIO_FUNC186_IN_INV_SEL_M (BIT(6)) 5615 #define GPIO_FUNC186_IN_INV_SEL_V 0x1 5616 #define GPIO_FUNC186_IN_INV_SEL_S 6 5617 /* GPIO_FUNC186_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 5618 /*description: select one of the 256 inputs*/ 5619 #define GPIO_FUNC186_IN_SEL 0x0000003F 5620 #define GPIO_FUNC186_IN_SEL_M ((GPIO_FUNC186_IN_SEL_V)<<(GPIO_FUNC186_IN_SEL_S)) 5621 #define GPIO_FUNC186_IN_SEL_V 0x3F 5622 #define GPIO_FUNC186_IN_SEL_S 0 5623 5624 #define GPIO_FUNC187_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x041c) 5625 /* GPIO_SIG187_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 5626 /*description: if the slow signal bypass the io matrix or not if you want setting 5627 the value to 1*/ 5628 #define GPIO_SIG187_IN_SEL (BIT(7)) 5629 #define GPIO_SIG187_IN_SEL_M (BIT(7)) 5630 #define GPIO_SIG187_IN_SEL_V 0x1 5631 #define GPIO_SIG187_IN_SEL_S 7 5632 /* GPIO_FUNC187_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 5633 /*description: revert the value of the input if you want to revert please set the value to 1*/ 5634 #define GPIO_FUNC187_IN_INV_SEL (BIT(6)) 5635 #define GPIO_FUNC187_IN_INV_SEL_M (BIT(6)) 5636 #define GPIO_FUNC187_IN_INV_SEL_V 0x1 5637 #define GPIO_FUNC187_IN_INV_SEL_S 6 5638 /* GPIO_FUNC187_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 5639 /*description: select one of the 256 inputs*/ 5640 #define GPIO_FUNC187_IN_SEL 0x0000003F 5641 #define GPIO_FUNC187_IN_SEL_M ((GPIO_FUNC187_IN_SEL_V)<<(GPIO_FUNC187_IN_SEL_S)) 5642 #define GPIO_FUNC187_IN_SEL_V 0x3F 5643 #define GPIO_FUNC187_IN_SEL_S 0 5644 5645 #define GPIO_FUNC188_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0420) 5646 /* GPIO_SIG188_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 5647 /*description: if the slow signal bypass the io matrix or not if you want setting 5648 the value to 1*/ 5649 #define GPIO_SIG188_IN_SEL (BIT(7)) 5650 #define GPIO_SIG188_IN_SEL_M (BIT(7)) 5651 #define GPIO_SIG188_IN_SEL_V 0x1 5652 #define GPIO_SIG188_IN_SEL_S 7 5653 /* GPIO_FUNC188_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 5654 /*description: revert the value of the input if you want to revert please set the value to 1*/ 5655 #define GPIO_FUNC188_IN_INV_SEL (BIT(6)) 5656 #define GPIO_FUNC188_IN_INV_SEL_M (BIT(6)) 5657 #define GPIO_FUNC188_IN_INV_SEL_V 0x1 5658 #define GPIO_FUNC188_IN_INV_SEL_S 6 5659 /* GPIO_FUNC188_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 5660 /*description: select one of the 256 inputs*/ 5661 #define GPIO_FUNC188_IN_SEL 0x0000003F 5662 #define GPIO_FUNC188_IN_SEL_M ((GPIO_FUNC188_IN_SEL_V)<<(GPIO_FUNC188_IN_SEL_S)) 5663 #define GPIO_FUNC188_IN_SEL_V 0x3F 5664 #define GPIO_FUNC188_IN_SEL_S 0 5665 5666 #define GPIO_FUNC189_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0424) 5667 /* GPIO_SIG189_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 5668 /*description: if the slow signal bypass the io matrix or not if you want setting 5669 the value to 1*/ 5670 #define GPIO_SIG189_IN_SEL (BIT(7)) 5671 #define GPIO_SIG189_IN_SEL_M (BIT(7)) 5672 #define GPIO_SIG189_IN_SEL_V 0x1 5673 #define GPIO_SIG189_IN_SEL_S 7 5674 /* GPIO_FUNC189_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 5675 /*description: revert the value of the input if you want to revert please set the value to 1*/ 5676 #define GPIO_FUNC189_IN_INV_SEL (BIT(6)) 5677 #define GPIO_FUNC189_IN_INV_SEL_M (BIT(6)) 5678 #define GPIO_FUNC189_IN_INV_SEL_V 0x1 5679 #define GPIO_FUNC189_IN_INV_SEL_S 6 5680 /* GPIO_FUNC189_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 5681 /*description: select one of the 256 inputs*/ 5682 #define GPIO_FUNC189_IN_SEL 0x0000003F 5683 #define GPIO_FUNC189_IN_SEL_M ((GPIO_FUNC189_IN_SEL_V)<<(GPIO_FUNC189_IN_SEL_S)) 5684 #define GPIO_FUNC189_IN_SEL_V 0x3F 5685 #define GPIO_FUNC189_IN_SEL_S 0 5686 5687 #define GPIO_FUNC190_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0428) 5688 /* GPIO_SIG190_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 5689 /*description: if the slow signal bypass the io matrix or not if you want setting 5690 the value to 1*/ 5691 #define GPIO_SIG190_IN_SEL (BIT(7)) 5692 #define GPIO_SIG190_IN_SEL_M (BIT(7)) 5693 #define GPIO_SIG190_IN_SEL_V 0x1 5694 #define GPIO_SIG190_IN_SEL_S 7 5695 /* GPIO_FUNC190_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 5696 /*description: revert the value of the input if you want to revert please set the value to 1*/ 5697 #define GPIO_FUNC190_IN_INV_SEL (BIT(6)) 5698 #define GPIO_FUNC190_IN_INV_SEL_M (BIT(6)) 5699 #define GPIO_FUNC190_IN_INV_SEL_V 0x1 5700 #define GPIO_FUNC190_IN_INV_SEL_S 6 5701 /* GPIO_FUNC190_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 5702 /*description: select one of the 256 inputs*/ 5703 #define GPIO_FUNC190_IN_SEL 0x0000003F 5704 #define GPIO_FUNC190_IN_SEL_M ((GPIO_FUNC190_IN_SEL_V)<<(GPIO_FUNC190_IN_SEL_S)) 5705 #define GPIO_FUNC190_IN_SEL_V 0x3F 5706 #define GPIO_FUNC190_IN_SEL_S 0 5707 5708 #define GPIO_FUNC191_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x042c) 5709 /* GPIO_SIG191_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 5710 /*description: if the slow signal bypass the io matrix or not if you want setting 5711 the value to 1*/ 5712 #define GPIO_SIG191_IN_SEL (BIT(7)) 5713 #define GPIO_SIG191_IN_SEL_M (BIT(7)) 5714 #define GPIO_SIG191_IN_SEL_V 0x1 5715 #define GPIO_SIG191_IN_SEL_S 7 5716 /* GPIO_FUNC191_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 5717 /*description: revert the value of the input if you want to revert please set the value to 1*/ 5718 #define GPIO_FUNC191_IN_INV_SEL (BIT(6)) 5719 #define GPIO_FUNC191_IN_INV_SEL_M (BIT(6)) 5720 #define GPIO_FUNC191_IN_INV_SEL_V 0x1 5721 #define GPIO_FUNC191_IN_INV_SEL_S 6 5722 /* GPIO_FUNC191_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 5723 /*description: select one of the 256 inputs*/ 5724 #define GPIO_FUNC191_IN_SEL 0x0000003F 5725 #define GPIO_FUNC191_IN_SEL_M ((GPIO_FUNC191_IN_SEL_V)<<(GPIO_FUNC191_IN_SEL_S)) 5726 #define GPIO_FUNC191_IN_SEL_V 0x3F 5727 #define GPIO_FUNC191_IN_SEL_S 0 5728 5729 #define GPIO_FUNC192_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0430) 5730 /* GPIO_SIG192_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 5731 /*description: if the slow signal bypass the io matrix or not if you want setting 5732 the value to 1*/ 5733 #define GPIO_SIG192_IN_SEL (BIT(7)) 5734 #define GPIO_SIG192_IN_SEL_M (BIT(7)) 5735 #define GPIO_SIG192_IN_SEL_V 0x1 5736 #define GPIO_SIG192_IN_SEL_S 7 5737 /* GPIO_FUNC192_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 5738 /*description: revert the value of the input if you want to revert please set the value to 1*/ 5739 #define GPIO_FUNC192_IN_INV_SEL (BIT(6)) 5740 #define GPIO_FUNC192_IN_INV_SEL_M (BIT(6)) 5741 #define GPIO_FUNC192_IN_INV_SEL_V 0x1 5742 #define GPIO_FUNC192_IN_INV_SEL_S 6 5743 /* GPIO_FUNC192_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 5744 /*description: select one of the 256 inputs*/ 5745 #define GPIO_FUNC192_IN_SEL 0x0000003F 5746 #define GPIO_FUNC192_IN_SEL_M ((GPIO_FUNC192_IN_SEL_V)<<(GPIO_FUNC192_IN_SEL_S)) 5747 #define GPIO_FUNC192_IN_SEL_V 0x3F 5748 #define GPIO_FUNC192_IN_SEL_S 0 5749 5750 #define GPIO_FUNC193_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0434) 5751 /* GPIO_SIG193_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 5752 /*description: if the slow signal bypass the io matrix or not if you want setting 5753 the value to 1*/ 5754 #define GPIO_SIG193_IN_SEL (BIT(7)) 5755 #define GPIO_SIG193_IN_SEL_M (BIT(7)) 5756 #define GPIO_SIG193_IN_SEL_V 0x1 5757 #define GPIO_SIG193_IN_SEL_S 7 5758 /* GPIO_FUNC193_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 5759 /*description: revert the value of the input if you want to revert please set the value to 1*/ 5760 #define GPIO_FUNC193_IN_INV_SEL (BIT(6)) 5761 #define GPIO_FUNC193_IN_INV_SEL_M (BIT(6)) 5762 #define GPIO_FUNC193_IN_INV_SEL_V 0x1 5763 #define GPIO_FUNC193_IN_INV_SEL_S 6 5764 /* GPIO_FUNC193_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 5765 /*description: select one of the 256 inputs*/ 5766 #define GPIO_FUNC193_IN_SEL 0x0000003F 5767 #define GPIO_FUNC193_IN_SEL_M ((GPIO_FUNC193_IN_SEL_V)<<(GPIO_FUNC193_IN_SEL_S)) 5768 #define GPIO_FUNC193_IN_SEL_V 0x3F 5769 #define GPIO_FUNC193_IN_SEL_S 0 5770 5771 #define GPIO_FUNC194_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0438) 5772 /* GPIO_SIG194_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 5773 /*description: if the slow signal bypass the io matrix or not if you want setting 5774 the value to 1*/ 5775 #define GPIO_SIG194_IN_SEL (BIT(7)) 5776 #define GPIO_SIG194_IN_SEL_M (BIT(7)) 5777 #define GPIO_SIG194_IN_SEL_V 0x1 5778 #define GPIO_SIG194_IN_SEL_S 7 5779 /* GPIO_FUNC194_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 5780 /*description: revert the value of the input if you want to revert please set the value to 1*/ 5781 #define GPIO_FUNC194_IN_INV_SEL (BIT(6)) 5782 #define GPIO_FUNC194_IN_INV_SEL_M (BIT(6)) 5783 #define GPIO_FUNC194_IN_INV_SEL_V 0x1 5784 #define GPIO_FUNC194_IN_INV_SEL_S 6 5785 /* GPIO_FUNC194_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 5786 /*description: select one of the 256 inputs*/ 5787 #define GPIO_FUNC194_IN_SEL 0x0000003F 5788 #define GPIO_FUNC194_IN_SEL_M ((GPIO_FUNC194_IN_SEL_V)<<(GPIO_FUNC194_IN_SEL_S)) 5789 #define GPIO_FUNC194_IN_SEL_V 0x3F 5790 #define GPIO_FUNC194_IN_SEL_S 0 5791 5792 #define GPIO_FUNC195_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x043c) 5793 /* GPIO_SIG195_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 5794 /*description: if the slow signal bypass the io matrix or not if you want setting 5795 the value to 1*/ 5796 #define GPIO_SIG195_IN_SEL (BIT(7)) 5797 #define GPIO_SIG195_IN_SEL_M (BIT(7)) 5798 #define GPIO_SIG195_IN_SEL_V 0x1 5799 #define GPIO_SIG195_IN_SEL_S 7 5800 /* GPIO_FUNC195_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 5801 /*description: revert the value of the input if you want to revert please set the value to 1*/ 5802 #define GPIO_FUNC195_IN_INV_SEL (BIT(6)) 5803 #define GPIO_FUNC195_IN_INV_SEL_M (BIT(6)) 5804 #define GPIO_FUNC195_IN_INV_SEL_V 0x1 5805 #define GPIO_FUNC195_IN_INV_SEL_S 6 5806 /* GPIO_FUNC195_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 5807 /*description: select one of the 256 inputs*/ 5808 #define GPIO_FUNC195_IN_SEL 0x0000003F 5809 #define GPIO_FUNC195_IN_SEL_M ((GPIO_FUNC195_IN_SEL_V)<<(GPIO_FUNC195_IN_SEL_S)) 5810 #define GPIO_FUNC195_IN_SEL_V 0x3F 5811 #define GPIO_FUNC195_IN_SEL_S 0 5812 5813 #define GPIO_FUNC196_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0440) 5814 /* GPIO_SIG196_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 5815 /*description: if the slow signal bypass the io matrix or not if you want setting 5816 the value to 1*/ 5817 #define GPIO_SIG196_IN_SEL (BIT(7)) 5818 #define GPIO_SIG196_IN_SEL_M (BIT(7)) 5819 #define GPIO_SIG196_IN_SEL_V 0x1 5820 #define GPIO_SIG196_IN_SEL_S 7 5821 /* GPIO_FUNC196_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 5822 /*description: revert the value of the input if you want to revert please set the value to 1*/ 5823 #define GPIO_FUNC196_IN_INV_SEL (BIT(6)) 5824 #define GPIO_FUNC196_IN_INV_SEL_M (BIT(6)) 5825 #define GPIO_FUNC196_IN_INV_SEL_V 0x1 5826 #define GPIO_FUNC196_IN_INV_SEL_S 6 5827 /* GPIO_FUNC196_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 5828 /*description: select one of the 256 inputs*/ 5829 #define GPIO_FUNC196_IN_SEL 0x0000003F 5830 #define GPIO_FUNC196_IN_SEL_M ((GPIO_FUNC196_IN_SEL_V)<<(GPIO_FUNC196_IN_SEL_S)) 5831 #define GPIO_FUNC196_IN_SEL_V 0x3F 5832 #define GPIO_FUNC196_IN_SEL_S 0 5833 5834 #define GPIO_FUNC197_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0444) 5835 /* GPIO_SIG197_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 5836 /*description: if the slow signal bypass the io matrix or not if you want setting 5837 the value to 1*/ 5838 #define GPIO_SIG197_IN_SEL (BIT(7)) 5839 #define GPIO_SIG197_IN_SEL_M (BIT(7)) 5840 #define GPIO_SIG197_IN_SEL_V 0x1 5841 #define GPIO_SIG197_IN_SEL_S 7 5842 /* GPIO_FUNC197_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 5843 /*description: revert the value of the input if you want to revert please set the value to 1*/ 5844 #define GPIO_FUNC197_IN_INV_SEL (BIT(6)) 5845 #define GPIO_FUNC197_IN_INV_SEL_M (BIT(6)) 5846 #define GPIO_FUNC197_IN_INV_SEL_V 0x1 5847 #define GPIO_FUNC197_IN_INV_SEL_S 6 5848 /* GPIO_FUNC197_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 5849 /*description: select one of the 256 inputs*/ 5850 #define GPIO_FUNC197_IN_SEL 0x0000003F 5851 #define GPIO_FUNC197_IN_SEL_M ((GPIO_FUNC197_IN_SEL_V)<<(GPIO_FUNC197_IN_SEL_S)) 5852 #define GPIO_FUNC197_IN_SEL_V 0x3F 5853 #define GPIO_FUNC197_IN_SEL_S 0 5854 5855 #define GPIO_FUNC198_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0448) 5856 /* GPIO_SIG198_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 5857 /*description: if the slow signal bypass the io matrix or not if you want setting 5858 the value to 1*/ 5859 #define GPIO_SIG198_IN_SEL (BIT(7)) 5860 #define GPIO_SIG198_IN_SEL_M (BIT(7)) 5861 #define GPIO_SIG198_IN_SEL_V 0x1 5862 #define GPIO_SIG198_IN_SEL_S 7 5863 /* GPIO_FUNC198_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 5864 /*description: revert the value of the input if you want to revert please set the value to 1*/ 5865 #define GPIO_FUNC198_IN_INV_SEL (BIT(6)) 5866 #define GPIO_FUNC198_IN_INV_SEL_M (BIT(6)) 5867 #define GPIO_FUNC198_IN_INV_SEL_V 0x1 5868 #define GPIO_FUNC198_IN_INV_SEL_S 6 5869 /* GPIO_FUNC198_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 5870 /*description: select one of the 256 inputs*/ 5871 #define GPIO_FUNC198_IN_SEL 0x0000003F 5872 #define GPIO_FUNC198_IN_SEL_M ((GPIO_FUNC198_IN_SEL_V)<<(GPIO_FUNC198_IN_SEL_S)) 5873 #define GPIO_FUNC198_IN_SEL_V 0x3F 5874 #define GPIO_FUNC198_IN_SEL_S 0 5875 5876 #define GPIO_FUNC199_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x044c) 5877 /* GPIO_SIG199_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 5878 /*description: if the slow signal bypass the io matrix or not if you want setting 5879 the value to 1*/ 5880 #define GPIO_SIG199_IN_SEL (BIT(7)) 5881 #define GPIO_SIG199_IN_SEL_M (BIT(7)) 5882 #define GPIO_SIG199_IN_SEL_V 0x1 5883 #define GPIO_SIG199_IN_SEL_S 7 5884 /* GPIO_FUNC199_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 5885 /*description: revert the value of the input if you want to revert please set the value to 1*/ 5886 #define GPIO_FUNC199_IN_INV_SEL (BIT(6)) 5887 #define GPIO_FUNC199_IN_INV_SEL_M (BIT(6)) 5888 #define GPIO_FUNC199_IN_INV_SEL_V 0x1 5889 #define GPIO_FUNC199_IN_INV_SEL_S 6 5890 /* GPIO_FUNC199_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 5891 /*description: select one of the 256 inputs*/ 5892 #define GPIO_FUNC199_IN_SEL 0x0000003F 5893 #define GPIO_FUNC199_IN_SEL_M ((GPIO_FUNC199_IN_SEL_V)<<(GPIO_FUNC199_IN_SEL_S)) 5894 #define GPIO_FUNC199_IN_SEL_V 0x3F 5895 #define GPIO_FUNC199_IN_SEL_S 0 5896 5897 #define GPIO_FUNC200_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0450) 5898 /* GPIO_SIG200_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 5899 /*description: if the slow signal bypass the io matrix or not if you want setting 5900 the value to 1*/ 5901 #define GPIO_SIG200_IN_SEL (BIT(7)) 5902 #define GPIO_SIG200_IN_SEL_M (BIT(7)) 5903 #define GPIO_SIG200_IN_SEL_V 0x1 5904 #define GPIO_SIG200_IN_SEL_S 7 5905 /* GPIO_FUNC200_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 5906 /*description: revert the value of the input if you want to revert please set the value to 1*/ 5907 #define GPIO_FUNC200_IN_INV_SEL (BIT(6)) 5908 #define GPIO_FUNC200_IN_INV_SEL_M (BIT(6)) 5909 #define GPIO_FUNC200_IN_INV_SEL_V 0x1 5910 #define GPIO_FUNC200_IN_INV_SEL_S 6 5911 /* GPIO_FUNC200_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 5912 /*description: select one of the 256 inputs*/ 5913 #define GPIO_FUNC200_IN_SEL 0x0000003F 5914 #define GPIO_FUNC200_IN_SEL_M ((GPIO_FUNC200_IN_SEL_V)<<(GPIO_FUNC200_IN_SEL_S)) 5915 #define GPIO_FUNC200_IN_SEL_V 0x3F 5916 #define GPIO_FUNC200_IN_SEL_S 0 5917 5918 #define GPIO_FUNC201_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0454) 5919 /* GPIO_SIG201_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 5920 /*description: if the slow signal bypass the io matrix or not if you want setting 5921 the value to 1*/ 5922 #define GPIO_SIG201_IN_SEL (BIT(7)) 5923 #define GPIO_SIG201_IN_SEL_M (BIT(7)) 5924 #define GPIO_SIG201_IN_SEL_V 0x1 5925 #define GPIO_SIG201_IN_SEL_S 7 5926 /* GPIO_FUNC201_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 5927 /*description: revert the value of the input if you want to revert please set the value to 1*/ 5928 #define GPIO_FUNC201_IN_INV_SEL (BIT(6)) 5929 #define GPIO_FUNC201_IN_INV_SEL_M (BIT(6)) 5930 #define GPIO_FUNC201_IN_INV_SEL_V 0x1 5931 #define GPIO_FUNC201_IN_INV_SEL_S 6 5932 /* GPIO_FUNC201_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 5933 /*description: select one of the 256 inputs*/ 5934 #define GPIO_FUNC201_IN_SEL 0x0000003F 5935 #define GPIO_FUNC201_IN_SEL_M ((GPIO_FUNC201_IN_SEL_V)<<(GPIO_FUNC201_IN_SEL_S)) 5936 #define GPIO_FUNC201_IN_SEL_V 0x3F 5937 #define GPIO_FUNC201_IN_SEL_S 0 5938 5939 #define GPIO_FUNC202_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0458) 5940 /* GPIO_SIG202_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 5941 /*description: if the slow signal bypass the io matrix or not if you want setting 5942 the value to 1*/ 5943 #define GPIO_SIG202_IN_SEL (BIT(7)) 5944 #define GPIO_SIG202_IN_SEL_M (BIT(7)) 5945 #define GPIO_SIG202_IN_SEL_V 0x1 5946 #define GPIO_SIG202_IN_SEL_S 7 5947 /* GPIO_FUNC202_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 5948 /*description: revert the value of the input if you want to revert please set the value to 1*/ 5949 #define GPIO_FUNC202_IN_INV_SEL (BIT(6)) 5950 #define GPIO_FUNC202_IN_INV_SEL_M (BIT(6)) 5951 #define GPIO_FUNC202_IN_INV_SEL_V 0x1 5952 #define GPIO_FUNC202_IN_INV_SEL_S 6 5953 /* GPIO_FUNC202_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 5954 /*description: select one of the 256 inputs*/ 5955 #define GPIO_FUNC202_IN_SEL 0x0000003F 5956 #define GPIO_FUNC202_IN_SEL_M ((GPIO_FUNC202_IN_SEL_V)<<(GPIO_FUNC202_IN_SEL_S)) 5957 #define GPIO_FUNC202_IN_SEL_V 0x3F 5958 #define GPIO_FUNC202_IN_SEL_S 0 5959 5960 #define GPIO_FUNC203_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x045c) 5961 /* GPIO_SIG203_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 5962 /*description: if the slow signal bypass the io matrix or not if you want setting 5963 the value to 1*/ 5964 #define GPIO_SIG203_IN_SEL (BIT(7)) 5965 #define GPIO_SIG203_IN_SEL_M (BIT(7)) 5966 #define GPIO_SIG203_IN_SEL_V 0x1 5967 #define GPIO_SIG203_IN_SEL_S 7 5968 /* GPIO_FUNC203_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 5969 /*description: revert the value of the input if you want to revert please set the value to 1*/ 5970 #define GPIO_FUNC203_IN_INV_SEL (BIT(6)) 5971 #define GPIO_FUNC203_IN_INV_SEL_M (BIT(6)) 5972 #define GPIO_FUNC203_IN_INV_SEL_V 0x1 5973 #define GPIO_FUNC203_IN_INV_SEL_S 6 5974 /* GPIO_FUNC203_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 5975 /*description: select one of the 256 inputs*/ 5976 #define GPIO_FUNC203_IN_SEL 0x0000003F 5977 #define GPIO_FUNC203_IN_SEL_M ((GPIO_FUNC203_IN_SEL_V)<<(GPIO_FUNC203_IN_SEL_S)) 5978 #define GPIO_FUNC203_IN_SEL_V 0x3F 5979 #define GPIO_FUNC203_IN_SEL_S 0 5980 5981 #define GPIO_FUNC204_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0460) 5982 /* GPIO_SIG204_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 5983 /*description: if the slow signal bypass the io matrix or not if you want setting 5984 the value to 1*/ 5985 #define GPIO_SIG204_IN_SEL (BIT(7)) 5986 #define GPIO_SIG204_IN_SEL_M (BIT(7)) 5987 #define GPIO_SIG204_IN_SEL_V 0x1 5988 #define GPIO_SIG204_IN_SEL_S 7 5989 /* GPIO_FUNC204_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 5990 /*description: revert the value of the input if you want to revert please set the value to 1*/ 5991 #define GPIO_FUNC204_IN_INV_SEL (BIT(6)) 5992 #define GPIO_FUNC204_IN_INV_SEL_M (BIT(6)) 5993 #define GPIO_FUNC204_IN_INV_SEL_V 0x1 5994 #define GPIO_FUNC204_IN_INV_SEL_S 6 5995 /* GPIO_FUNC204_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 5996 /*description: select one of the 256 inputs*/ 5997 #define GPIO_FUNC204_IN_SEL 0x0000003F 5998 #define GPIO_FUNC204_IN_SEL_M ((GPIO_FUNC204_IN_SEL_V)<<(GPIO_FUNC204_IN_SEL_S)) 5999 #define GPIO_FUNC204_IN_SEL_V 0x3F 6000 #define GPIO_FUNC204_IN_SEL_S 0 6001 6002 #define GPIO_FUNC205_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0464) 6003 /* GPIO_SIG205_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 6004 /*description: if the slow signal bypass the io matrix or not if you want setting 6005 the value to 1*/ 6006 #define GPIO_SIG205_IN_SEL (BIT(7)) 6007 #define GPIO_SIG205_IN_SEL_M (BIT(7)) 6008 #define GPIO_SIG205_IN_SEL_V 0x1 6009 #define GPIO_SIG205_IN_SEL_S 7 6010 /* GPIO_FUNC205_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 6011 /*description: revert the value of the input if you want to revert please set the value to 1*/ 6012 #define GPIO_FUNC205_IN_INV_SEL (BIT(6)) 6013 #define GPIO_FUNC205_IN_INV_SEL_M (BIT(6)) 6014 #define GPIO_FUNC205_IN_INV_SEL_V 0x1 6015 #define GPIO_FUNC205_IN_INV_SEL_S 6 6016 /* GPIO_FUNC205_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 6017 /*description: select one of the 256 inputs*/ 6018 #define GPIO_FUNC205_IN_SEL 0x0000003F 6019 #define GPIO_FUNC205_IN_SEL_M ((GPIO_FUNC205_IN_SEL_V)<<(GPIO_FUNC205_IN_SEL_S)) 6020 #define GPIO_FUNC205_IN_SEL_V 0x3F 6021 #define GPIO_FUNC205_IN_SEL_S 0 6022 6023 #define GPIO_FUNC206_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0468) 6024 /* GPIO_SIG206_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 6025 /*description: if the slow signal bypass the io matrix or not if you want setting 6026 the value to 1*/ 6027 #define GPIO_SIG206_IN_SEL (BIT(7)) 6028 #define GPIO_SIG206_IN_SEL_M (BIT(7)) 6029 #define GPIO_SIG206_IN_SEL_V 0x1 6030 #define GPIO_SIG206_IN_SEL_S 7 6031 /* GPIO_FUNC206_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 6032 /*description: revert the value of the input if you want to revert please set the value to 1*/ 6033 #define GPIO_FUNC206_IN_INV_SEL (BIT(6)) 6034 #define GPIO_FUNC206_IN_INV_SEL_M (BIT(6)) 6035 #define GPIO_FUNC206_IN_INV_SEL_V 0x1 6036 #define GPIO_FUNC206_IN_INV_SEL_S 6 6037 /* GPIO_FUNC206_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 6038 /*description: select one of the 256 inputs*/ 6039 #define GPIO_FUNC206_IN_SEL 0x0000003F 6040 #define GPIO_FUNC206_IN_SEL_M ((GPIO_FUNC206_IN_SEL_V)<<(GPIO_FUNC206_IN_SEL_S)) 6041 #define GPIO_FUNC206_IN_SEL_V 0x3F 6042 #define GPIO_FUNC206_IN_SEL_S 0 6043 6044 #define GPIO_FUNC207_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x046c) 6045 /* GPIO_SIG207_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 6046 /*description: if the slow signal bypass the io matrix or not if you want setting 6047 the value to 1*/ 6048 #define GPIO_SIG207_IN_SEL (BIT(7)) 6049 #define GPIO_SIG207_IN_SEL_M (BIT(7)) 6050 #define GPIO_SIG207_IN_SEL_V 0x1 6051 #define GPIO_SIG207_IN_SEL_S 7 6052 /* GPIO_FUNC207_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 6053 /*description: revert the value of the input if you want to revert please set the value to 1*/ 6054 #define GPIO_FUNC207_IN_INV_SEL (BIT(6)) 6055 #define GPIO_FUNC207_IN_INV_SEL_M (BIT(6)) 6056 #define GPIO_FUNC207_IN_INV_SEL_V 0x1 6057 #define GPIO_FUNC207_IN_INV_SEL_S 6 6058 /* GPIO_FUNC207_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 6059 /*description: select one of the 256 inputs*/ 6060 #define GPIO_FUNC207_IN_SEL 0x0000003F 6061 #define GPIO_FUNC207_IN_SEL_M ((GPIO_FUNC207_IN_SEL_V)<<(GPIO_FUNC207_IN_SEL_S)) 6062 #define GPIO_FUNC207_IN_SEL_V 0x3F 6063 #define GPIO_FUNC207_IN_SEL_S 0 6064 6065 #define GPIO_FUNC208_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0470) 6066 /* GPIO_SIG208_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 6067 /*description: if the slow signal bypass the io matrix or not if you want setting 6068 the value to 1*/ 6069 #define GPIO_SIG208_IN_SEL (BIT(7)) 6070 #define GPIO_SIG208_IN_SEL_M (BIT(7)) 6071 #define GPIO_SIG208_IN_SEL_V 0x1 6072 #define GPIO_SIG208_IN_SEL_S 7 6073 /* GPIO_FUNC208_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 6074 /*description: revert the value of the input if you want to revert please set the value to 1*/ 6075 #define GPIO_FUNC208_IN_INV_SEL (BIT(6)) 6076 #define GPIO_FUNC208_IN_INV_SEL_M (BIT(6)) 6077 #define GPIO_FUNC208_IN_INV_SEL_V 0x1 6078 #define GPIO_FUNC208_IN_INV_SEL_S 6 6079 /* GPIO_FUNC208_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 6080 /*description: select one of the 256 inputs*/ 6081 #define GPIO_FUNC208_IN_SEL 0x0000003F 6082 #define GPIO_FUNC208_IN_SEL_M ((GPIO_FUNC208_IN_SEL_V)<<(GPIO_FUNC208_IN_SEL_S)) 6083 #define GPIO_FUNC208_IN_SEL_V 0x3F 6084 #define GPIO_FUNC208_IN_SEL_S 0 6085 6086 #define GPIO_FUNC209_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0474) 6087 /* GPIO_SIG209_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 6088 /*description: if the slow signal bypass the io matrix or not if you want setting 6089 the value to 1*/ 6090 #define GPIO_SIG209_IN_SEL (BIT(7)) 6091 #define GPIO_SIG209_IN_SEL_M (BIT(7)) 6092 #define GPIO_SIG209_IN_SEL_V 0x1 6093 #define GPIO_SIG209_IN_SEL_S 7 6094 /* GPIO_FUNC209_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 6095 /*description: revert the value of the input if you want to revert please set the value to 1*/ 6096 #define GPIO_FUNC209_IN_INV_SEL (BIT(6)) 6097 #define GPIO_FUNC209_IN_INV_SEL_M (BIT(6)) 6098 #define GPIO_FUNC209_IN_INV_SEL_V 0x1 6099 #define GPIO_FUNC209_IN_INV_SEL_S 6 6100 /* GPIO_FUNC209_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 6101 /*description: select one of the 256 inputs*/ 6102 #define GPIO_FUNC209_IN_SEL 0x0000003F 6103 #define GPIO_FUNC209_IN_SEL_M ((GPIO_FUNC209_IN_SEL_V)<<(GPIO_FUNC209_IN_SEL_S)) 6104 #define GPIO_FUNC209_IN_SEL_V 0x3F 6105 #define GPIO_FUNC209_IN_SEL_S 0 6106 6107 #define GPIO_FUNC210_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0478) 6108 /* GPIO_SIG210_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 6109 /*description: if the slow signal bypass the io matrix or not if you want setting 6110 the value to 1*/ 6111 #define GPIO_SIG210_IN_SEL (BIT(7)) 6112 #define GPIO_SIG210_IN_SEL_M (BIT(7)) 6113 #define GPIO_SIG210_IN_SEL_V 0x1 6114 #define GPIO_SIG210_IN_SEL_S 7 6115 /* GPIO_FUNC210_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 6116 /*description: revert the value of the input if you want to revert please set the value to 1*/ 6117 #define GPIO_FUNC210_IN_INV_SEL (BIT(6)) 6118 #define GPIO_FUNC210_IN_INV_SEL_M (BIT(6)) 6119 #define GPIO_FUNC210_IN_INV_SEL_V 0x1 6120 #define GPIO_FUNC210_IN_INV_SEL_S 6 6121 /* GPIO_FUNC210_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 6122 /*description: select one of the 256 inputs*/ 6123 #define GPIO_FUNC210_IN_SEL 0x0000003F 6124 #define GPIO_FUNC210_IN_SEL_M ((GPIO_FUNC210_IN_SEL_V)<<(GPIO_FUNC210_IN_SEL_S)) 6125 #define GPIO_FUNC210_IN_SEL_V 0x3F 6126 #define GPIO_FUNC210_IN_SEL_S 0 6127 6128 #define GPIO_FUNC211_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x047c) 6129 /* GPIO_SIG211_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 6130 /*description: if the slow signal bypass the io matrix or not if you want setting 6131 the value to 1*/ 6132 #define GPIO_SIG211_IN_SEL (BIT(7)) 6133 #define GPIO_SIG211_IN_SEL_M (BIT(7)) 6134 #define GPIO_SIG211_IN_SEL_V 0x1 6135 #define GPIO_SIG211_IN_SEL_S 7 6136 /* GPIO_FUNC211_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 6137 /*description: revert the value of the input if you want to revert please set the value to 1*/ 6138 #define GPIO_FUNC211_IN_INV_SEL (BIT(6)) 6139 #define GPIO_FUNC211_IN_INV_SEL_M (BIT(6)) 6140 #define GPIO_FUNC211_IN_INV_SEL_V 0x1 6141 #define GPIO_FUNC211_IN_INV_SEL_S 6 6142 /* GPIO_FUNC211_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 6143 /*description: select one of the 256 inputs*/ 6144 #define GPIO_FUNC211_IN_SEL 0x0000003F 6145 #define GPIO_FUNC211_IN_SEL_M ((GPIO_FUNC211_IN_SEL_V)<<(GPIO_FUNC211_IN_SEL_S)) 6146 #define GPIO_FUNC211_IN_SEL_V 0x3F 6147 #define GPIO_FUNC211_IN_SEL_S 0 6148 6149 #define GPIO_FUNC212_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0480) 6150 /* GPIO_SIG212_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 6151 /*description: if the slow signal bypass the io matrix or not if you want setting 6152 the value to 1*/ 6153 #define GPIO_SIG212_IN_SEL (BIT(7)) 6154 #define GPIO_SIG212_IN_SEL_M (BIT(7)) 6155 #define GPIO_SIG212_IN_SEL_V 0x1 6156 #define GPIO_SIG212_IN_SEL_S 7 6157 /* GPIO_FUNC212_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 6158 /*description: revert the value of the input if you want to revert please set the value to 1*/ 6159 #define GPIO_FUNC212_IN_INV_SEL (BIT(6)) 6160 #define GPIO_FUNC212_IN_INV_SEL_M (BIT(6)) 6161 #define GPIO_FUNC212_IN_INV_SEL_V 0x1 6162 #define GPIO_FUNC212_IN_INV_SEL_S 6 6163 /* GPIO_FUNC212_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 6164 /*description: select one of the 256 inputs*/ 6165 #define GPIO_FUNC212_IN_SEL 0x0000003F 6166 #define GPIO_FUNC212_IN_SEL_M ((GPIO_FUNC212_IN_SEL_V)<<(GPIO_FUNC212_IN_SEL_S)) 6167 #define GPIO_FUNC212_IN_SEL_V 0x3F 6168 #define GPIO_FUNC212_IN_SEL_S 0 6169 6170 #define GPIO_FUNC213_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0484) 6171 /* GPIO_SIG213_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 6172 /*description: if the slow signal bypass the io matrix or not if you want setting 6173 the value to 1*/ 6174 #define GPIO_SIG213_IN_SEL (BIT(7)) 6175 #define GPIO_SIG213_IN_SEL_M (BIT(7)) 6176 #define GPIO_SIG213_IN_SEL_V 0x1 6177 #define GPIO_SIG213_IN_SEL_S 7 6178 /* GPIO_FUNC213_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 6179 /*description: revert the value of the input if you want to revert please set the value to 1*/ 6180 #define GPIO_FUNC213_IN_INV_SEL (BIT(6)) 6181 #define GPIO_FUNC213_IN_INV_SEL_M (BIT(6)) 6182 #define GPIO_FUNC213_IN_INV_SEL_V 0x1 6183 #define GPIO_FUNC213_IN_INV_SEL_S 6 6184 /* GPIO_FUNC213_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 6185 /*description: select one of the 256 inputs*/ 6186 #define GPIO_FUNC213_IN_SEL 0x0000003F 6187 #define GPIO_FUNC213_IN_SEL_M ((GPIO_FUNC213_IN_SEL_V)<<(GPIO_FUNC213_IN_SEL_S)) 6188 #define GPIO_FUNC213_IN_SEL_V 0x3F 6189 #define GPIO_FUNC213_IN_SEL_S 0 6190 6191 #define GPIO_FUNC214_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0488) 6192 /* GPIO_SIG214_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 6193 /*description: if the slow signal bypass the io matrix or not if you want setting 6194 the value to 1*/ 6195 #define GPIO_SIG214_IN_SEL (BIT(7)) 6196 #define GPIO_SIG214_IN_SEL_M (BIT(7)) 6197 #define GPIO_SIG214_IN_SEL_V 0x1 6198 #define GPIO_SIG214_IN_SEL_S 7 6199 /* GPIO_FUNC214_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 6200 /*description: revert the value of the input if you want to revert please set the value to 1*/ 6201 #define GPIO_FUNC214_IN_INV_SEL (BIT(6)) 6202 #define GPIO_FUNC214_IN_INV_SEL_M (BIT(6)) 6203 #define GPIO_FUNC214_IN_INV_SEL_V 0x1 6204 #define GPIO_FUNC214_IN_INV_SEL_S 6 6205 /* GPIO_FUNC214_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 6206 /*description: select one of the 256 inputs*/ 6207 #define GPIO_FUNC214_IN_SEL 0x0000003F 6208 #define GPIO_FUNC214_IN_SEL_M ((GPIO_FUNC214_IN_SEL_V)<<(GPIO_FUNC214_IN_SEL_S)) 6209 #define GPIO_FUNC214_IN_SEL_V 0x3F 6210 #define GPIO_FUNC214_IN_SEL_S 0 6211 6212 #define GPIO_FUNC215_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x048c) 6213 /* GPIO_SIG215_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 6214 /*description: if the slow signal bypass the io matrix or not if you want setting 6215 the value to 1*/ 6216 #define GPIO_SIG215_IN_SEL (BIT(7)) 6217 #define GPIO_SIG215_IN_SEL_M (BIT(7)) 6218 #define GPIO_SIG215_IN_SEL_V 0x1 6219 #define GPIO_SIG215_IN_SEL_S 7 6220 /* GPIO_FUNC215_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 6221 /*description: revert the value of the input if you want to revert please set the value to 1*/ 6222 #define GPIO_FUNC215_IN_INV_SEL (BIT(6)) 6223 #define GPIO_FUNC215_IN_INV_SEL_M (BIT(6)) 6224 #define GPIO_FUNC215_IN_INV_SEL_V 0x1 6225 #define GPIO_FUNC215_IN_INV_SEL_S 6 6226 /* GPIO_FUNC215_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 6227 /*description: select one of the 256 inputs*/ 6228 #define GPIO_FUNC215_IN_SEL 0x0000003F 6229 #define GPIO_FUNC215_IN_SEL_M ((GPIO_FUNC215_IN_SEL_V)<<(GPIO_FUNC215_IN_SEL_S)) 6230 #define GPIO_FUNC215_IN_SEL_V 0x3F 6231 #define GPIO_FUNC215_IN_SEL_S 0 6232 6233 #define GPIO_FUNC216_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0490) 6234 /* GPIO_SIG216_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 6235 /*description: if the slow signal bypass the io matrix or not if you want setting 6236 the value to 1*/ 6237 #define GPIO_SIG216_IN_SEL (BIT(7)) 6238 #define GPIO_SIG216_IN_SEL_M (BIT(7)) 6239 #define GPIO_SIG216_IN_SEL_V 0x1 6240 #define GPIO_SIG216_IN_SEL_S 7 6241 /* GPIO_FUNC216_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 6242 /*description: revert the value of the input if you want to revert please set the value to 1*/ 6243 #define GPIO_FUNC216_IN_INV_SEL (BIT(6)) 6244 #define GPIO_FUNC216_IN_INV_SEL_M (BIT(6)) 6245 #define GPIO_FUNC216_IN_INV_SEL_V 0x1 6246 #define GPIO_FUNC216_IN_INV_SEL_S 6 6247 /* GPIO_FUNC216_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 6248 /*description: select one of the 256 inputs*/ 6249 #define GPIO_FUNC216_IN_SEL 0x0000003F 6250 #define GPIO_FUNC216_IN_SEL_M ((GPIO_FUNC216_IN_SEL_V)<<(GPIO_FUNC216_IN_SEL_S)) 6251 #define GPIO_FUNC216_IN_SEL_V 0x3F 6252 #define GPIO_FUNC216_IN_SEL_S 0 6253 6254 #define GPIO_FUNC217_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0494) 6255 /* GPIO_SIG217_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 6256 /*description: if the slow signal bypass the io matrix or not if you want setting 6257 the value to 1*/ 6258 #define GPIO_SIG217_IN_SEL (BIT(7)) 6259 #define GPIO_SIG217_IN_SEL_M (BIT(7)) 6260 #define GPIO_SIG217_IN_SEL_V 0x1 6261 #define GPIO_SIG217_IN_SEL_S 7 6262 /* GPIO_FUNC217_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 6263 /*description: revert the value of the input if you want to revert please set the value to 1*/ 6264 #define GPIO_FUNC217_IN_INV_SEL (BIT(6)) 6265 #define GPIO_FUNC217_IN_INV_SEL_M (BIT(6)) 6266 #define GPIO_FUNC217_IN_INV_SEL_V 0x1 6267 #define GPIO_FUNC217_IN_INV_SEL_S 6 6268 /* GPIO_FUNC217_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 6269 /*description: select one of the 256 inputs*/ 6270 #define GPIO_FUNC217_IN_SEL 0x0000003F 6271 #define GPIO_FUNC217_IN_SEL_M ((GPIO_FUNC217_IN_SEL_V)<<(GPIO_FUNC217_IN_SEL_S)) 6272 #define GPIO_FUNC217_IN_SEL_V 0x3F 6273 #define GPIO_FUNC217_IN_SEL_S 0 6274 6275 #define GPIO_FUNC218_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0498) 6276 /* GPIO_SIG218_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 6277 /*description: if the slow signal bypass the io matrix or not if you want setting 6278 the value to 1*/ 6279 #define GPIO_SIG218_IN_SEL (BIT(7)) 6280 #define GPIO_SIG218_IN_SEL_M (BIT(7)) 6281 #define GPIO_SIG218_IN_SEL_V 0x1 6282 #define GPIO_SIG218_IN_SEL_S 7 6283 /* GPIO_FUNC218_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 6284 /*description: revert the value of the input if you want to revert please set the value to 1*/ 6285 #define GPIO_FUNC218_IN_INV_SEL (BIT(6)) 6286 #define GPIO_FUNC218_IN_INV_SEL_M (BIT(6)) 6287 #define GPIO_FUNC218_IN_INV_SEL_V 0x1 6288 #define GPIO_FUNC218_IN_INV_SEL_S 6 6289 /* GPIO_FUNC218_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 6290 /*description: select one of the 256 inputs*/ 6291 #define GPIO_FUNC218_IN_SEL 0x0000003F 6292 #define GPIO_FUNC218_IN_SEL_M ((GPIO_FUNC218_IN_SEL_V)<<(GPIO_FUNC218_IN_SEL_S)) 6293 #define GPIO_FUNC218_IN_SEL_V 0x3F 6294 #define GPIO_FUNC218_IN_SEL_S 0 6295 6296 #define GPIO_FUNC219_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x049c) 6297 /* GPIO_SIG219_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 6298 /*description: if the slow signal bypass the io matrix or not if you want setting 6299 the value to 1*/ 6300 #define GPIO_SIG219_IN_SEL (BIT(7)) 6301 #define GPIO_SIG219_IN_SEL_M (BIT(7)) 6302 #define GPIO_SIG219_IN_SEL_V 0x1 6303 #define GPIO_SIG219_IN_SEL_S 7 6304 /* GPIO_FUNC219_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 6305 /*description: revert the value of the input if you want to revert please set the value to 1*/ 6306 #define GPIO_FUNC219_IN_INV_SEL (BIT(6)) 6307 #define GPIO_FUNC219_IN_INV_SEL_M (BIT(6)) 6308 #define GPIO_FUNC219_IN_INV_SEL_V 0x1 6309 #define GPIO_FUNC219_IN_INV_SEL_S 6 6310 /* GPIO_FUNC219_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 6311 /*description: select one of the 256 inputs*/ 6312 #define GPIO_FUNC219_IN_SEL 0x0000003F 6313 #define GPIO_FUNC219_IN_SEL_M ((GPIO_FUNC219_IN_SEL_V)<<(GPIO_FUNC219_IN_SEL_S)) 6314 #define GPIO_FUNC219_IN_SEL_V 0x3F 6315 #define GPIO_FUNC219_IN_SEL_S 0 6316 6317 #define GPIO_FUNC220_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04a0) 6318 /* GPIO_SIG220_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 6319 /*description: if the slow signal bypass the io matrix or not if you want setting 6320 the value to 1*/ 6321 #define GPIO_SIG220_IN_SEL (BIT(7)) 6322 #define GPIO_SIG220_IN_SEL_M (BIT(7)) 6323 #define GPIO_SIG220_IN_SEL_V 0x1 6324 #define GPIO_SIG220_IN_SEL_S 7 6325 /* GPIO_FUNC220_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 6326 /*description: revert the value of the input if you want to revert please set the value to 1*/ 6327 #define GPIO_FUNC220_IN_INV_SEL (BIT(6)) 6328 #define GPIO_FUNC220_IN_INV_SEL_M (BIT(6)) 6329 #define GPIO_FUNC220_IN_INV_SEL_V 0x1 6330 #define GPIO_FUNC220_IN_INV_SEL_S 6 6331 /* GPIO_FUNC220_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 6332 /*description: select one of the 256 inputs*/ 6333 #define GPIO_FUNC220_IN_SEL 0x0000003F 6334 #define GPIO_FUNC220_IN_SEL_M ((GPIO_FUNC220_IN_SEL_V)<<(GPIO_FUNC220_IN_SEL_S)) 6335 #define GPIO_FUNC220_IN_SEL_V 0x3F 6336 #define GPIO_FUNC220_IN_SEL_S 0 6337 6338 #define GPIO_FUNC221_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04a4) 6339 /* GPIO_SIG221_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 6340 /*description: if the slow signal bypass the io matrix or not if you want setting 6341 the value to 1*/ 6342 #define GPIO_SIG221_IN_SEL (BIT(7)) 6343 #define GPIO_SIG221_IN_SEL_M (BIT(7)) 6344 #define GPIO_SIG221_IN_SEL_V 0x1 6345 #define GPIO_SIG221_IN_SEL_S 7 6346 /* GPIO_FUNC221_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 6347 /*description: revert the value of the input if you want to revert please set the value to 1*/ 6348 #define GPIO_FUNC221_IN_INV_SEL (BIT(6)) 6349 #define GPIO_FUNC221_IN_INV_SEL_M (BIT(6)) 6350 #define GPIO_FUNC221_IN_INV_SEL_V 0x1 6351 #define GPIO_FUNC221_IN_INV_SEL_S 6 6352 /* GPIO_FUNC221_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 6353 /*description: select one of the 256 inputs*/ 6354 #define GPIO_FUNC221_IN_SEL 0x0000003F 6355 #define GPIO_FUNC221_IN_SEL_M ((GPIO_FUNC221_IN_SEL_V)<<(GPIO_FUNC221_IN_SEL_S)) 6356 #define GPIO_FUNC221_IN_SEL_V 0x3F 6357 #define GPIO_FUNC221_IN_SEL_S 0 6358 6359 #define GPIO_FUNC222_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04a8) 6360 /* GPIO_SIG222_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 6361 /*description: if the slow signal bypass the io matrix or not if you want setting 6362 the value to 1*/ 6363 #define GPIO_SIG222_IN_SEL (BIT(7)) 6364 #define GPIO_SIG222_IN_SEL_M (BIT(7)) 6365 #define GPIO_SIG222_IN_SEL_V 0x1 6366 #define GPIO_SIG222_IN_SEL_S 7 6367 /* GPIO_FUNC222_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 6368 /*description: revert the value of the input if you want to revert please set the value to 1*/ 6369 #define GPIO_FUNC222_IN_INV_SEL (BIT(6)) 6370 #define GPIO_FUNC222_IN_INV_SEL_M (BIT(6)) 6371 #define GPIO_FUNC222_IN_INV_SEL_V 0x1 6372 #define GPIO_FUNC222_IN_INV_SEL_S 6 6373 /* GPIO_FUNC222_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 6374 /*description: select one of the 256 inputs*/ 6375 #define GPIO_FUNC222_IN_SEL 0x0000003F 6376 #define GPIO_FUNC222_IN_SEL_M ((GPIO_FUNC222_IN_SEL_V)<<(GPIO_FUNC222_IN_SEL_S)) 6377 #define GPIO_FUNC222_IN_SEL_V 0x3F 6378 #define GPIO_FUNC222_IN_SEL_S 0 6379 6380 #define GPIO_FUNC223_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04ac) 6381 /* GPIO_SIG223_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 6382 /*description: if the slow signal bypass the io matrix or not if you want setting 6383 the value to 1*/ 6384 #define GPIO_SIG223_IN_SEL (BIT(7)) 6385 #define GPIO_SIG223_IN_SEL_M (BIT(7)) 6386 #define GPIO_SIG223_IN_SEL_V 0x1 6387 #define GPIO_SIG223_IN_SEL_S 7 6388 /* GPIO_FUNC223_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 6389 /*description: revert the value of the input if you want to revert please set the value to 1*/ 6390 #define GPIO_FUNC223_IN_INV_SEL (BIT(6)) 6391 #define GPIO_FUNC223_IN_INV_SEL_M (BIT(6)) 6392 #define GPIO_FUNC223_IN_INV_SEL_V 0x1 6393 #define GPIO_FUNC223_IN_INV_SEL_S 6 6394 /* GPIO_FUNC223_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 6395 /*description: select one of the 256 inputs*/ 6396 #define GPIO_FUNC223_IN_SEL 0x0000003F 6397 #define GPIO_FUNC223_IN_SEL_M ((GPIO_FUNC223_IN_SEL_V)<<(GPIO_FUNC223_IN_SEL_S)) 6398 #define GPIO_FUNC223_IN_SEL_V 0x3F 6399 #define GPIO_FUNC223_IN_SEL_S 0 6400 6401 #define GPIO_FUNC224_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04b0) 6402 /* GPIO_SIG224_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 6403 /*description: if the slow signal bypass the io matrix or not if you want setting 6404 the value to 1*/ 6405 #define GPIO_SIG224_IN_SEL (BIT(7)) 6406 #define GPIO_SIG224_IN_SEL_M (BIT(7)) 6407 #define GPIO_SIG224_IN_SEL_V 0x1 6408 #define GPIO_SIG224_IN_SEL_S 7 6409 /* GPIO_FUNC224_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 6410 /*description: revert the value of the input if you want to revert please set the value to 1*/ 6411 #define GPIO_FUNC224_IN_INV_SEL (BIT(6)) 6412 #define GPIO_FUNC224_IN_INV_SEL_M (BIT(6)) 6413 #define GPIO_FUNC224_IN_INV_SEL_V 0x1 6414 #define GPIO_FUNC224_IN_INV_SEL_S 6 6415 /* GPIO_FUNC224_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 6416 /*description: select one of the 256 inputs*/ 6417 #define GPIO_FUNC224_IN_SEL 0x0000003F 6418 #define GPIO_FUNC224_IN_SEL_M ((GPIO_FUNC224_IN_SEL_V)<<(GPIO_FUNC224_IN_SEL_S)) 6419 #define GPIO_FUNC224_IN_SEL_V 0x3F 6420 #define GPIO_FUNC224_IN_SEL_S 0 6421 6422 #define GPIO_FUNC225_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04b4) 6423 /* GPIO_SIG225_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 6424 /*description: if the slow signal bypass the io matrix or not if you want setting 6425 the value to 1*/ 6426 #define GPIO_SIG225_IN_SEL (BIT(7)) 6427 #define GPIO_SIG225_IN_SEL_M (BIT(7)) 6428 #define GPIO_SIG225_IN_SEL_V 0x1 6429 #define GPIO_SIG225_IN_SEL_S 7 6430 /* GPIO_FUNC225_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 6431 /*description: revert the value of the input if you want to revert please set the value to 1*/ 6432 #define GPIO_FUNC225_IN_INV_SEL (BIT(6)) 6433 #define GPIO_FUNC225_IN_INV_SEL_M (BIT(6)) 6434 #define GPIO_FUNC225_IN_INV_SEL_V 0x1 6435 #define GPIO_FUNC225_IN_INV_SEL_S 6 6436 /* GPIO_FUNC225_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 6437 /*description: select one of the 256 inputs*/ 6438 #define GPIO_FUNC225_IN_SEL 0x0000003F 6439 #define GPIO_FUNC225_IN_SEL_M ((GPIO_FUNC225_IN_SEL_V)<<(GPIO_FUNC225_IN_SEL_S)) 6440 #define GPIO_FUNC225_IN_SEL_V 0x3F 6441 #define GPIO_FUNC225_IN_SEL_S 0 6442 6443 #define GPIO_FUNC226_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04b8) 6444 /* GPIO_SIG226_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 6445 /*description: if the slow signal bypass the io matrix or not if you want setting 6446 the value to 1*/ 6447 #define GPIO_SIG226_IN_SEL (BIT(7)) 6448 #define GPIO_SIG226_IN_SEL_M (BIT(7)) 6449 #define GPIO_SIG226_IN_SEL_V 0x1 6450 #define GPIO_SIG226_IN_SEL_S 7 6451 /* GPIO_FUNC226_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 6452 /*description: revert the value of the input if you want to revert please set the value to 1*/ 6453 #define GPIO_FUNC226_IN_INV_SEL (BIT(6)) 6454 #define GPIO_FUNC226_IN_INV_SEL_M (BIT(6)) 6455 #define GPIO_FUNC226_IN_INV_SEL_V 0x1 6456 #define GPIO_FUNC226_IN_INV_SEL_S 6 6457 /* GPIO_FUNC226_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 6458 /*description: select one of the 256 inputs*/ 6459 #define GPIO_FUNC226_IN_SEL 0x0000003F 6460 #define GPIO_FUNC226_IN_SEL_M ((GPIO_FUNC226_IN_SEL_V)<<(GPIO_FUNC226_IN_SEL_S)) 6461 #define GPIO_FUNC226_IN_SEL_V 0x3F 6462 #define GPIO_FUNC226_IN_SEL_S 0 6463 6464 #define GPIO_FUNC227_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04bc) 6465 /* GPIO_SIG227_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 6466 /*description: if the slow signal bypass the io matrix or not if you want setting 6467 the value to 1*/ 6468 #define GPIO_SIG227_IN_SEL (BIT(7)) 6469 #define GPIO_SIG227_IN_SEL_M (BIT(7)) 6470 #define GPIO_SIG227_IN_SEL_V 0x1 6471 #define GPIO_SIG227_IN_SEL_S 7 6472 /* GPIO_FUNC227_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 6473 /*description: revert the value of the input if you want to revert please set the value to 1*/ 6474 #define GPIO_FUNC227_IN_INV_SEL (BIT(6)) 6475 #define GPIO_FUNC227_IN_INV_SEL_M (BIT(6)) 6476 #define GPIO_FUNC227_IN_INV_SEL_V 0x1 6477 #define GPIO_FUNC227_IN_INV_SEL_S 6 6478 /* GPIO_FUNC227_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 6479 /*description: select one of the 256 inputs*/ 6480 #define GPIO_FUNC227_IN_SEL 0x0000003F 6481 #define GPIO_FUNC227_IN_SEL_M ((GPIO_FUNC227_IN_SEL_V)<<(GPIO_FUNC227_IN_SEL_S)) 6482 #define GPIO_FUNC227_IN_SEL_V 0x3F 6483 #define GPIO_FUNC227_IN_SEL_S 0 6484 6485 #define GPIO_FUNC228_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04c0) 6486 /* GPIO_SIG228_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 6487 /*description: if the slow signal bypass the io matrix or not if you want setting 6488 the value to 1*/ 6489 #define GPIO_SIG228_IN_SEL (BIT(7)) 6490 #define GPIO_SIG228_IN_SEL_M (BIT(7)) 6491 #define GPIO_SIG228_IN_SEL_V 0x1 6492 #define GPIO_SIG228_IN_SEL_S 7 6493 /* GPIO_FUNC228_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 6494 /*description: revert the value of the input if you want to revert please set the value to 1*/ 6495 #define GPIO_FUNC228_IN_INV_SEL (BIT(6)) 6496 #define GPIO_FUNC228_IN_INV_SEL_M (BIT(6)) 6497 #define GPIO_FUNC228_IN_INV_SEL_V 0x1 6498 #define GPIO_FUNC228_IN_INV_SEL_S 6 6499 /* GPIO_FUNC228_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 6500 /*description: select one of the 256 inputs*/ 6501 #define GPIO_FUNC228_IN_SEL 0x0000003F 6502 #define GPIO_FUNC228_IN_SEL_M ((GPIO_FUNC228_IN_SEL_V)<<(GPIO_FUNC228_IN_SEL_S)) 6503 #define GPIO_FUNC228_IN_SEL_V 0x3F 6504 #define GPIO_FUNC228_IN_SEL_S 0 6505 6506 #define GPIO_FUNC229_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04c4) 6507 /* GPIO_SIG229_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 6508 /*description: if the slow signal bypass the io matrix or not if you want setting 6509 the value to 1*/ 6510 #define GPIO_SIG229_IN_SEL (BIT(7)) 6511 #define GPIO_SIG229_IN_SEL_M (BIT(7)) 6512 #define GPIO_SIG229_IN_SEL_V 0x1 6513 #define GPIO_SIG229_IN_SEL_S 7 6514 /* GPIO_FUNC229_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 6515 /*description: revert the value of the input if you want to revert please set the value to 1*/ 6516 #define GPIO_FUNC229_IN_INV_SEL (BIT(6)) 6517 #define GPIO_FUNC229_IN_INV_SEL_M (BIT(6)) 6518 #define GPIO_FUNC229_IN_INV_SEL_V 0x1 6519 #define GPIO_FUNC229_IN_INV_SEL_S 6 6520 /* GPIO_FUNC229_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 6521 /*description: select one of the 256 inputs*/ 6522 #define GPIO_FUNC229_IN_SEL 0x0000003F 6523 #define GPIO_FUNC229_IN_SEL_M ((GPIO_FUNC229_IN_SEL_V)<<(GPIO_FUNC229_IN_SEL_S)) 6524 #define GPIO_FUNC229_IN_SEL_V 0x3F 6525 #define GPIO_FUNC229_IN_SEL_S 0 6526 6527 #define GPIO_FUNC230_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04c8) 6528 /* GPIO_SIG230_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 6529 /*description: if the slow signal bypass the io matrix or not if you want setting 6530 the value to 1*/ 6531 #define GPIO_SIG230_IN_SEL (BIT(7)) 6532 #define GPIO_SIG230_IN_SEL_M (BIT(7)) 6533 #define GPIO_SIG230_IN_SEL_V 0x1 6534 #define GPIO_SIG230_IN_SEL_S 7 6535 /* GPIO_FUNC230_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 6536 /*description: revert the value of the input if you want to revert please set the value to 1*/ 6537 #define GPIO_FUNC230_IN_INV_SEL (BIT(6)) 6538 #define GPIO_FUNC230_IN_INV_SEL_M (BIT(6)) 6539 #define GPIO_FUNC230_IN_INV_SEL_V 0x1 6540 #define GPIO_FUNC230_IN_INV_SEL_S 6 6541 /* GPIO_FUNC230_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 6542 /*description: select one of the 256 inputs*/ 6543 #define GPIO_FUNC230_IN_SEL 0x0000003F 6544 #define GPIO_FUNC230_IN_SEL_M ((GPIO_FUNC230_IN_SEL_V)<<(GPIO_FUNC230_IN_SEL_S)) 6545 #define GPIO_FUNC230_IN_SEL_V 0x3F 6546 #define GPIO_FUNC230_IN_SEL_S 0 6547 6548 #define GPIO_FUNC231_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04cc) 6549 /* GPIO_SIG231_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 6550 /*description: if the slow signal bypass the io matrix or not if you want setting 6551 the value to 1*/ 6552 #define GPIO_SIG231_IN_SEL (BIT(7)) 6553 #define GPIO_SIG231_IN_SEL_M (BIT(7)) 6554 #define GPIO_SIG231_IN_SEL_V 0x1 6555 #define GPIO_SIG231_IN_SEL_S 7 6556 /* GPIO_FUNC231_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 6557 /*description: revert the value of the input if you want to revert please set the value to 1*/ 6558 #define GPIO_FUNC231_IN_INV_SEL (BIT(6)) 6559 #define GPIO_FUNC231_IN_INV_SEL_M (BIT(6)) 6560 #define GPIO_FUNC231_IN_INV_SEL_V 0x1 6561 #define GPIO_FUNC231_IN_INV_SEL_S 6 6562 /* GPIO_FUNC231_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 6563 /*description: select one of the 256 inputs*/ 6564 #define GPIO_FUNC231_IN_SEL 0x0000003F 6565 #define GPIO_FUNC231_IN_SEL_M ((GPIO_FUNC231_IN_SEL_V)<<(GPIO_FUNC231_IN_SEL_S)) 6566 #define GPIO_FUNC231_IN_SEL_V 0x3F 6567 #define GPIO_FUNC231_IN_SEL_S 0 6568 6569 #define GPIO_FUNC232_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04d0) 6570 /* GPIO_SIG232_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 6571 /*description: if the slow signal bypass the io matrix or not if you want setting 6572 the value to 1*/ 6573 #define GPIO_SIG232_IN_SEL (BIT(7)) 6574 #define GPIO_SIG232_IN_SEL_M (BIT(7)) 6575 #define GPIO_SIG232_IN_SEL_V 0x1 6576 #define GPIO_SIG232_IN_SEL_S 7 6577 /* GPIO_FUNC232_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 6578 /*description: revert the value of the input if you want to revert please set the value to 1*/ 6579 #define GPIO_FUNC232_IN_INV_SEL (BIT(6)) 6580 #define GPIO_FUNC232_IN_INV_SEL_M (BIT(6)) 6581 #define GPIO_FUNC232_IN_INV_SEL_V 0x1 6582 #define GPIO_FUNC232_IN_INV_SEL_S 6 6583 /* GPIO_FUNC232_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 6584 /*description: select one of the 256 inputs*/ 6585 #define GPIO_FUNC232_IN_SEL 0x0000003F 6586 #define GPIO_FUNC232_IN_SEL_M ((GPIO_FUNC232_IN_SEL_V)<<(GPIO_FUNC232_IN_SEL_S)) 6587 #define GPIO_FUNC232_IN_SEL_V 0x3F 6588 #define GPIO_FUNC232_IN_SEL_S 0 6589 6590 #define GPIO_FUNC233_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04d4) 6591 /* GPIO_SIG233_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 6592 /*description: if the slow signal bypass the io matrix or not if you want setting 6593 the value to 1*/ 6594 #define GPIO_SIG233_IN_SEL (BIT(7)) 6595 #define GPIO_SIG233_IN_SEL_M (BIT(7)) 6596 #define GPIO_SIG233_IN_SEL_V 0x1 6597 #define GPIO_SIG233_IN_SEL_S 7 6598 /* GPIO_FUNC233_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 6599 /*description: revert the value of the input if you want to revert please set the value to 1*/ 6600 #define GPIO_FUNC233_IN_INV_SEL (BIT(6)) 6601 #define GPIO_FUNC233_IN_INV_SEL_M (BIT(6)) 6602 #define GPIO_FUNC233_IN_INV_SEL_V 0x1 6603 #define GPIO_FUNC233_IN_INV_SEL_S 6 6604 /* GPIO_FUNC233_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 6605 /*description: select one of the 256 inputs*/ 6606 #define GPIO_FUNC233_IN_SEL 0x0000003F 6607 #define GPIO_FUNC233_IN_SEL_M ((GPIO_FUNC233_IN_SEL_V)<<(GPIO_FUNC233_IN_SEL_S)) 6608 #define GPIO_FUNC233_IN_SEL_V 0x3F 6609 #define GPIO_FUNC233_IN_SEL_S 0 6610 6611 #define GPIO_FUNC234_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04d8) 6612 /* GPIO_SIG234_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 6613 /*description: if the slow signal bypass the io matrix or not if you want setting 6614 the value to 1*/ 6615 #define GPIO_SIG234_IN_SEL (BIT(7)) 6616 #define GPIO_SIG234_IN_SEL_M (BIT(7)) 6617 #define GPIO_SIG234_IN_SEL_V 0x1 6618 #define GPIO_SIG234_IN_SEL_S 7 6619 /* GPIO_FUNC234_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 6620 /*description: revert the value of the input if you want to revert please set the value to 1*/ 6621 #define GPIO_FUNC234_IN_INV_SEL (BIT(6)) 6622 #define GPIO_FUNC234_IN_INV_SEL_M (BIT(6)) 6623 #define GPIO_FUNC234_IN_INV_SEL_V 0x1 6624 #define GPIO_FUNC234_IN_INV_SEL_S 6 6625 /* GPIO_FUNC234_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 6626 /*description: select one of the 256 inputs*/ 6627 #define GPIO_FUNC234_IN_SEL 0x0000003F 6628 #define GPIO_FUNC234_IN_SEL_M ((GPIO_FUNC234_IN_SEL_V)<<(GPIO_FUNC234_IN_SEL_S)) 6629 #define GPIO_FUNC234_IN_SEL_V 0x3F 6630 #define GPIO_FUNC234_IN_SEL_S 0 6631 6632 #define GPIO_FUNC235_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04dc) 6633 /* GPIO_SIG235_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 6634 /*description: if the slow signal bypass the io matrix or not if you want setting 6635 the value to 1*/ 6636 #define GPIO_SIG235_IN_SEL (BIT(7)) 6637 #define GPIO_SIG235_IN_SEL_M (BIT(7)) 6638 #define GPIO_SIG235_IN_SEL_V 0x1 6639 #define GPIO_SIG235_IN_SEL_S 7 6640 /* GPIO_FUNC235_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 6641 /*description: revert the value of the input if you want to revert please set the value to 1*/ 6642 #define GPIO_FUNC235_IN_INV_SEL (BIT(6)) 6643 #define GPIO_FUNC235_IN_INV_SEL_M (BIT(6)) 6644 #define GPIO_FUNC235_IN_INV_SEL_V 0x1 6645 #define GPIO_FUNC235_IN_INV_SEL_S 6 6646 /* GPIO_FUNC235_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 6647 /*description: select one of the 256 inputs*/ 6648 #define GPIO_FUNC235_IN_SEL 0x0000003F 6649 #define GPIO_FUNC235_IN_SEL_M ((GPIO_FUNC235_IN_SEL_V)<<(GPIO_FUNC235_IN_SEL_S)) 6650 #define GPIO_FUNC235_IN_SEL_V 0x3F 6651 #define GPIO_FUNC235_IN_SEL_S 0 6652 6653 #define GPIO_FUNC236_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04e0) 6654 /* GPIO_SIG236_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 6655 /*description: if the slow signal bypass the io matrix or not if you want setting 6656 the value to 1*/ 6657 #define GPIO_SIG236_IN_SEL (BIT(7)) 6658 #define GPIO_SIG236_IN_SEL_M (BIT(7)) 6659 #define GPIO_SIG236_IN_SEL_V 0x1 6660 #define GPIO_SIG236_IN_SEL_S 7 6661 /* GPIO_FUNC236_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 6662 /*description: revert the value of the input if you want to revert please set the value to 1*/ 6663 #define GPIO_FUNC236_IN_INV_SEL (BIT(6)) 6664 #define GPIO_FUNC236_IN_INV_SEL_M (BIT(6)) 6665 #define GPIO_FUNC236_IN_INV_SEL_V 0x1 6666 #define GPIO_FUNC236_IN_INV_SEL_S 6 6667 /* GPIO_FUNC236_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 6668 /*description: select one of the 256 inputs*/ 6669 #define GPIO_FUNC236_IN_SEL 0x0000003F 6670 #define GPIO_FUNC236_IN_SEL_M ((GPIO_FUNC236_IN_SEL_V)<<(GPIO_FUNC236_IN_SEL_S)) 6671 #define GPIO_FUNC236_IN_SEL_V 0x3F 6672 #define GPIO_FUNC236_IN_SEL_S 0 6673 6674 #define GPIO_FUNC237_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04e4) 6675 /* GPIO_SIG237_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 6676 /*description: if the slow signal bypass the io matrix or not if you want setting 6677 the value to 1*/ 6678 #define GPIO_SIG237_IN_SEL (BIT(7)) 6679 #define GPIO_SIG237_IN_SEL_M (BIT(7)) 6680 #define GPIO_SIG237_IN_SEL_V 0x1 6681 #define GPIO_SIG237_IN_SEL_S 7 6682 /* GPIO_FUNC237_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 6683 /*description: revert the value of the input if you want to revert please set the value to 1*/ 6684 #define GPIO_FUNC237_IN_INV_SEL (BIT(6)) 6685 #define GPIO_FUNC237_IN_INV_SEL_M (BIT(6)) 6686 #define GPIO_FUNC237_IN_INV_SEL_V 0x1 6687 #define GPIO_FUNC237_IN_INV_SEL_S 6 6688 /* GPIO_FUNC237_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 6689 /*description: select one of the 256 inputs*/ 6690 #define GPIO_FUNC237_IN_SEL 0x0000003F 6691 #define GPIO_FUNC237_IN_SEL_M ((GPIO_FUNC237_IN_SEL_V)<<(GPIO_FUNC237_IN_SEL_S)) 6692 #define GPIO_FUNC237_IN_SEL_V 0x3F 6693 #define GPIO_FUNC237_IN_SEL_S 0 6694 6695 #define GPIO_FUNC238_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04e8) 6696 /* GPIO_SIG238_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 6697 /*description: if the slow signal bypass the io matrix or not if you want setting 6698 the value to 1*/ 6699 #define GPIO_SIG238_IN_SEL (BIT(7)) 6700 #define GPIO_SIG238_IN_SEL_M (BIT(7)) 6701 #define GPIO_SIG238_IN_SEL_V 0x1 6702 #define GPIO_SIG238_IN_SEL_S 7 6703 /* GPIO_FUNC238_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 6704 /*description: revert the value of the input if you want to revert please set the value to 1*/ 6705 #define GPIO_FUNC238_IN_INV_SEL (BIT(6)) 6706 #define GPIO_FUNC238_IN_INV_SEL_M (BIT(6)) 6707 #define GPIO_FUNC238_IN_INV_SEL_V 0x1 6708 #define GPIO_FUNC238_IN_INV_SEL_S 6 6709 /* GPIO_FUNC238_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 6710 /*description: select one of the 256 inputs*/ 6711 #define GPIO_FUNC238_IN_SEL 0x0000003F 6712 #define GPIO_FUNC238_IN_SEL_M ((GPIO_FUNC238_IN_SEL_V)<<(GPIO_FUNC238_IN_SEL_S)) 6713 #define GPIO_FUNC238_IN_SEL_V 0x3F 6714 #define GPIO_FUNC238_IN_SEL_S 0 6715 6716 #define GPIO_FUNC239_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04ec) 6717 /* GPIO_SIG239_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 6718 /*description: if the slow signal bypass the io matrix or not if you want setting 6719 the value to 1*/ 6720 #define GPIO_SIG239_IN_SEL (BIT(7)) 6721 #define GPIO_SIG239_IN_SEL_M (BIT(7)) 6722 #define GPIO_SIG239_IN_SEL_V 0x1 6723 #define GPIO_SIG239_IN_SEL_S 7 6724 /* GPIO_FUNC239_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 6725 /*description: revert the value of the input if you want to revert please set the value to 1*/ 6726 #define GPIO_FUNC239_IN_INV_SEL (BIT(6)) 6727 #define GPIO_FUNC239_IN_INV_SEL_M (BIT(6)) 6728 #define GPIO_FUNC239_IN_INV_SEL_V 0x1 6729 #define GPIO_FUNC239_IN_INV_SEL_S 6 6730 /* GPIO_FUNC239_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 6731 /*description: select one of the 256 inputs*/ 6732 #define GPIO_FUNC239_IN_SEL 0x0000003F 6733 #define GPIO_FUNC239_IN_SEL_M ((GPIO_FUNC239_IN_SEL_V)<<(GPIO_FUNC239_IN_SEL_S)) 6734 #define GPIO_FUNC239_IN_SEL_V 0x3F 6735 #define GPIO_FUNC239_IN_SEL_S 0 6736 6737 #define GPIO_FUNC240_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04f0) 6738 /* GPIO_SIG240_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 6739 /*description: if the slow signal bypass the io matrix or not if you want setting 6740 the value to 1*/ 6741 #define GPIO_SIG240_IN_SEL (BIT(7)) 6742 #define GPIO_SIG240_IN_SEL_M (BIT(7)) 6743 #define GPIO_SIG240_IN_SEL_V 0x1 6744 #define GPIO_SIG240_IN_SEL_S 7 6745 /* GPIO_FUNC240_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 6746 /*description: revert the value of the input if you want to revert please set the value to 1*/ 6747 #define GPIO_FUNC240_IN_INV_SEL (BIT(6)) 6748 #define GPIO_FUNC240_IN_INV_SEL_M (BIT(6)) 6749 #define GPIO_FUNC240_IN_INV_SEL_V 0x1 6750 #define GPIO_FUNC240_IN_INV_SEL_S 6 6751 /* GPIO_FUNC240_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 6752 /*description: select one of the 256 inputs*/ 6753 #define GPIO_FUNC240_IN_SEL 0x0000003F 6754 #define GPIO_FUNC240_IN_SEL_M ((GPIO_FUNC240_IN_SEL_V)<<(GPIO_FUNC240_IN_SEL_S)) 6755 #define GPIO_FUNC240_IN_SEL_V 0x3F 6756 #define GPIO_FUNC240_IN_SEL_S 0 6757 6758 #define GPIO_FUNC241_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04f4) 6759 /* GPIO_SIG241_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 6760 /*description: if the slow signal bypass the io matrix or not if you want setting 6761 the value to 1*/ 6762 #define GPIO_SIG241_IN_SEL (BIT(7)) 6763 #define GPIO_SIG241_IN_SEL_M (BIT(7)) 6764 #define GPIO_SIG241_IN_SEL_V 0x1 6765 #define GPIO_SIG241_IN_SEL_S 7 6766 /* GPIO_FUNC241_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 6767 /*description: revert the value of the input if you want to revert please set the value to 1*/ 6768 #define GPIO_FUNC241_IN_INV_SEL (BIT(6)) 6769 #define GPIO_FUNC241_IN_INV_SEL_M (BIT(6)) 6770 #define GPIO_FUNC241_IN_INV_SEL_V 0x1 6771 #define GPIO_FUNC241_IN_INV_SEL_S 6 6772 /* GPIO_FUNC241_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 6773 /*description: select one of the 256 inputs*/ 6774 #define GPIO_FUNC241_IN_SEL 0x0000003F 6775 #define GPIO_FUNC241_IN_SEL_M ((GPIO_FUNC241_IN_SEL_V)<<(GPIO_FUNC241_IN_SEL_S)) 6776 #define GPIO_FUNC241_IN_SEL_V 0x3F 6777 #define GPIO_FUNC241_IN_SEL_S 0 6778 6779 #define GPIO_FUNC242_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04f8) 6780 /* GPIO_SIG242_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 6781 /*description: if the slow signal bypass the io matrix or not if you want setting 6782 the value to 1*/ 6783 #define GPIO_SIG242_IN_SEL (BIT(7)) 6784 #define GPIO_SIG242_IN_SEL_M (BIT(7)) 6785 #define GPIO_SIG242_IN_SEL_V 0x1 6786 #define GPIO_SIG242_IN_SEL_S 7 6787 /* GPIO_FUNC242_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 6788 /*description: revert the value of the input if you want to revert please set the value to 1*/ 6789 #define GPIO_FUNC242_IN_INV_SEL (BIT(6)) 6790 #define GPIO_FUNC242_IN_INV_SEL_M (BIT(6)) 6791 #define GPIO_FUNC242_IN_INV_SEL_V 0x1 6792 #define GPIO_FUNC242_IN_INV_SEL_S 6 6793 /* GPIO_FUNC242_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 6794 /*description: select one of the 256 inputs*/ 6795 #define GPIO_FUNC242_IN_SEL 0x0000003F 6796 #define GPIO_FUNC242_IN_SEL_M ((GPIO_FUNC242_IN_SEL_V)<<(GPIO_FUNC242_IN_SEL_S)) 6797 #define GPIO_FUNC242_IN_SEL_V 0x3F 6798 #define GPIO_FUNC242_IN_SEL_S 0 6799 6800 #define GPIO_FUNC243_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04fc) 6801 /* GPIO_SIG243_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 6802 /*description: if the slow signal bypass the io matrix or not if you want setting 6803 the value to 1*/ 6804 #define GPIO_SIG243_IN_SEL (BIT(7)) 6805 #define GPIO_SIG243_IN_SEL_M (BIT(7)) 6806 #define GPIO_SIG243_IN_SEL_V 0x1 6807 #define GPIO_SIG243_IN_SEL_S 7 6808 /* GPIO_FUNC243_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 6809 /*description: revert the value of the input if you want to revert please set the value to 1*/ 6810 #define GPIO_FUNC243_IN_INV_SEL (BIT(6)) 6811 #define GPIO_FUNC243_IN_INV_SEL_M (BIT(6)) 6812 #define GPIO_FUNC243_IN_INV_SEL_V 0x1 6813 #define GPIO_FUNC243_IN_INV_SEL_S 6 6814 /* GPIO_FUNC243_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 6815 /*description: select one of the 256 inputs*/ 6816 #define GPIO_FUNC243_IN_SEL 0x0000003F 6817 #define GPIO_FUNC243_IN_SEL_M ((GPIO_FUNC243_IN_SEL_V)<<(GPIO_FUNC243_IN_SEL_S)) 6818 #define GPIO_FUNC243_IN_SEL_V 0x3F 6819 #define GPIO_FUNC243_IN_SEL_S 0 6820 6821 #define GPIO_FUNC244_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0500) 6822 /* GPIO_SIG244_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 6823 /*description: if the slow signal bypass the io matrix or not if you want setting 6824 the value to 1*/ 6825 #define GPIO_SIG244_IN_SEL (BIT(7)) 6826 #define GPIO_SIG244_IN_SEL_M (BIT(7)) 6827 #define GPIO_SIG244_IN_SEL_V 0x1 6828 #define GPIO_SIG244_IN_SEL_S 7 6829 /* GPIO_FUNC244_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 6830 /*description: revert the value of the input if you want to revert please set the value to 1*/ 6831 #define GPIO_FUNC244_IN_INV_SEL (BIT(6)) 6832 #define GPIO_FUNC244_IN_INV_SEL_M (BIT(6)) 6833 #define GPIO_FUNC244_IN_INV_SEL_V 0x1 6834 #define GPIO_FUNC244_IN_INV_SEL_S 6 6835 /* GPIO_FUNC244_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 6836 /*description: select one of the 256 inputs*/ 6837 #define GPIO_FUNC244_IN_SEL 0x0000003F 6838 #define GPIO_FUNC244_IN_SEL_M ((GPIO_FUNC244_IN_SEL_V)<<(GPIO_FUNC244_IN_SEL_S)) 6839 #define GPIO_FUNC244_IN_SEL_V 0x3F 6840 #define GPIO_FUNC244_IN_SEL_S 0 6841 6842 #define GPIO_FUNC245_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0504) 6843 /* GPIO_SIG245_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 6844 /*description: if the slow signal bypass the io matrix or not if you want setting 6845 the value to 1*/ 6846 #define GPIO_SIG245_IN_SEL (BIT(7)) 6847 #define GPIO_SIG245_IN_SEL_M (BIT(7)) 6848 #define GPIO_SIG245_IN_SEL_V 0x1 6849 #define GPIO_SIG245_IN_SEL_S 7 6850 /* GPIO_FUNC245_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 6851 /*description: revert the value of the input if you want to revert please set the value to 1*/ 6852 #define GPIO_FUNC245_IN_INV_SEL (BIT(6)) 6853 #define GPIO_FUNC245_IN_INV_SEL_M (BIT(6)) 6854 #define GPIO_FUNC245_IN_INV_SEL_V 0x1 6855 #define GPIO_FUNC245_IN_INV_SEL_S 6 6856 /* GPIO_FUNC245_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 6857 /*description: select one of the 256 inputs*/ 6858 #define GPIO_FUNC245_IN_SEL 0x0000003F 6859 #define GPIO_FUNC245_IN_SEL_M ((GPIO_FUNC245_IN_SEL_V)<<(GPIO_FUNC245_IN_SEL_S)) 6860 #define GPIO_FUNC245_IN_SEL_V 0x3F 6861 #define GPIO_FUNC245_IN_SEL_S 0 6862 6863 #define GPIO_FUNC246_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0508) 6864 /* GPIO_SIG246_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 6865 /*description: if the slow signal bypass the io matrix or not if you want setting 6866 the value to 1*/ 6867 #define GPIO_SIG246_IN_SEL (BIT(7)) 6868 #define GPIO_SIG246_IN_SEL_M (BIT(7)) 6869 #define GPIO_SIG246_IN_SEL_V 0x1 6870 #define GPIO_SIG246_IN_SEL_S 7 6871 /* GPIO_FUNC246_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 6872 /*description: revert the value of the input if you want to revert please set the value to 1*/ 6873 #define GPIO_FUNC246_IN_INV_SEL (BIT(6)) 6874 #define GPIO_FUNC246_IN_INV_SEL_M (BIT(6)) 6875 #define GPIO_FUNC246_IN_INV_SEL_V 0x1 6876 #define GPIO_FUNC246_IN_INV_SEL_S 6 6877 /* GPIO_FUNC246_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 6878 /*description: select one of the 256 inputs*/ 6879 #define GPIO_FUNC246_IN_SEL 0x0000003F 6880 #define GPIO_FUNC246_IN_SEL_M ((GPIO_FUNC246_IN_SEL_V)<<(GPIO_FUNC246_IN_SEL_S)) 6881 #define GPIO_FUNC246_IN_SEL_V 0x3F 6882 #define GPIO_FUNC246_IN_SEL_S 0 6883 6884 #define GPIO_FUNC247_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x050c) 6885 /* GPIO_SIG247_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 6886 /*description: if the slow signal bypass the io matrix or not if you want setting 6887 the value to 1*/ 6888 #define GPIO_SIG247_IN_SEL (BIT(7)) 6889 #define GPIO_SIG247_IN_SEL_M (BIT(7)) 6890 #define GPIO_SIG247_IN_SEL_V 0x1 6891 #define GPIO_SIG247_IN_SEL_S 7 6892 /* GPIO_FUNC247_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 6893 /*description: revert the value of the input if you want to revert please set the value to 1*/ 6894 #define GPIO_FUNC247_IN_INV_SEL (BIT(6)) 6895 #define GPIO_FUNC247_IN_INV_SEL_M (BIT(6)) 6896 #define GPIO_FUNC247_IN_INV_SEL_V 0x1 6897 #define GPIO_FUNC247_IN_INV_SEL_S 6 6898 /* GPIO_FUNC247_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 6899 /*description: select one of the 256 inputs*/ 6900 #define GPIO_FUNC247_IN_SEL 0x0000003F 6901 #define GPIO_FUNC247_IN_SEL_M ((GPIO_FUNC247_IN_SEL_V)<<(GPIO_FUNC247_IN_SEL_S)) 6902 #define GPIO_FUNC247_IN_SEL_V 0x3F 6903 #define GPIO_FUNC247_IN_SEL_S 0 6904 6905 #define GPIO_FUNC248_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0510) 6906 /* GPIO_SIG248_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 6907 /*description: if the slow signal bypass the io matrix or not if you want setting 6908 the value to 1*/ 6909 #define GPIO_SIG248_IN_SEL (BIT(7)) 6910 #define GPIO_SIG248_IN_SEL_M (BIT(7)) 6911 #define GPIO_SIG248_IN_SEL_V 0x1 6912 #define GPIO_SIG248_IN_SEL_S 7 6913 /* GPIO_FUNC248_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 6914 /*description: revert the value of the input if you want to revert please set the value to 1*/ 6915 #define GPIO_FUNC248_IN_INV_SEL (BIT(6)) 6916 #define GPIO_FUNC248_IN_INV_SEL_M (BIT(6)) 6917 #define GPIO_FUNC248_IN_INV_SEL_V 0x1 6918 #define GPIO_FUNC248_IN_INV_SEL_S 6 6919 /* GPIO_FUNC248_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 6920 /*description: select one of the 256 inputs*/ 6921 #define GPIO_FUNC248_IN_SEL 0x0000003F 6922 #define GPIO_FUNC248_IN_SEL_M ((GPIO_FUNC248_IN_SEL_V)<<(GPIO_FUNC248_IN_SEL_S)) 6923 #define GPIO_FUNC248_IN_SEL_V 0x3F 6924 #define GPIO_FUNC248_IN_SEL_S 0 6925 6926 #define GPIO_FUNC249_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0514) 6927 /* GPIO_SIG249_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 6928 /*description: if the slow signal bypass the io matrix or not if you want setting 6929 the value to 1*/ 6930 #define GPIO_SIG249_IN_SEL (BIT(7)) 6931 #define GPIO_SIG249_IN_SEL_M (BIT(7)) 6932 #define GPIO_SIG249_IN_SEL_V 0x1 6933 #define GPIO_SIG249_IN_SEL_S 7 6934 /* GPIO_FUNC249_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 6935 /*description: revert the value of the input if you want to revert please set the value to 1*/ 6936 #define GPIO_FUNC249_IN_INV_SEL (BIT(6)) 6937 #define GPIO_FUNC249_IN_INV_SEL_M (BIT(6)) 6938 #define GPIO_FUNC249_IN_INV_SEL_V 0x1 6939 #define GPIO_FUNC249_IN_INV_SEL_S 6 6940 /* GPIO_FUNC249_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 6941 /*description: select one of the 256 inputs*/ 6942 #define GPIO_FUNC249_IN_SEL 0x0000003F 6943 #define GPIO_FUNC249_IN_SEL_M ((GPIO_FUNC249_IN_SEL_V)<<(GPIO_FUNC249_IN_SEL_S)) 6944 #define GPIO_FUNC249_IN_SEL_V 0x3F 6945 #define GPIO_FUNC249_IN_SEL_S 0 6946 6947 #define GPIO_FUNC250_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0518) 6948 /* GPIO_SIG250_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 6949 /*description: if the slow signal bypass the io matrix or not if you want setting 6950 the value to 1*/ 6951 #define GPIO_SIG250_IN_SEL (BIT(7)) 6952 #define GPIO_SIG250_IN_SEL_M (BIT(7)) 6953 #define GPIO_SIG250_IN_SEL_V 0x1 6954 #define GPIO_SIG250_IN_SEL_S 7 6955 /* GPIO_FUNC250_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 6956 /*description: revert the value of the input if you want to revert please set the value to 1*/ 6957 #define GPIO_FUNC250_IN_INV_SEL (BIT(6)) 6958 #define GPIO_FUNC250_IN_INV_SEL_M (BIT(6)) 6959 #define GPIO_FUNC250_IN_INV_SEL_V 0x1 6960 #define GPIO_FUNC250_IN_INV_SEL_S 6 6961 /* GPIO_FUNC250_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 6962 /*description: select one of the 256 inputs*/ 6963 #define GPIO_FUNC250_IN_SEL 0x0000003F 6964 #define GPIO_FUNC250_IN_SEL_M ((GPIO_FUNC250_IN_SEL_V)<<(GPIO_FUNC250_IN_SEL_S)) 6965 #define GPIO_FUNC250_IN_SEL_V 0x3F 6966 #define GPIO_FUNC250_IN_SEL_S 0 6967 6968 #define GPIO_FUNC251_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x051c) 6969 /* GPIO_SIG251_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 6970 /*description: if the slow signal bypass the io matrix or not if you want setting 6971 the value to 1*/ 6972 #define GPIO_SIG251_IN_SEL (BIT(7)) 6973 #define GPIO_SIG251_IN_SEL_M (BIT(7)) 6974 #define GPIO_SIG251_IN_SEL_V 0x1 6975 #define GPIO_SIG251_IN_SEL_S 7 6976 /* GPIO_FUNC251_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 6977 /*description: revert the value of the input if you want to revert please set the value to 1*/ 6978 #define GPIO_FUNC251_IN_INV_SEL (BIT(6)) 6979 #define GPIO_FUNC251_IN_INV_SEL_M (BIT(6)) 6980 #define GPIO_FUNC251_IN_INV_SEL_V 0x1 6981 #define GPIO_FUNC251_IN_INV_SEL_S 6 6982 /* GPIO_FUNC251_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 6983 /*description: select one of the 256 inputs*/ 6984 #define GPIO_FUNC251_IN_SEL 0x0000003F 6985 #define GPIO_FUNC251_IN_SEL_M ((GPIO_FUNC251_IN_SEL_V)<<(GPIO_FUNC251_IN_SEL_S)) 6986 #define GPIO_FUNC251_IN_SEL_V 0x3F 6987 #define GPIO_FUNC251_IN_SEL_S 0 6988 6989 #define GPIO_FUNC252_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0520) 6990 /* GPIO_SIG252_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 6991 /*description: if the slow signal bypass the io matrix or not if you want setting 6992 the value to 1*/ 6993 #define GPIO_SIG252_IN_SEL (BIT(7)) 6994 #define GPIO_SIG252_IN_SEL_M (BIT(7)) 6995 #define GPIO_SIG252_IN_SEL_V 0x1 6996 #define GPIO_SIG252_IN_SEL_S 7 6997 /* GPIO_FUNC252_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 6998 /*description: revert the value of the input if you want to revert please set the value to 1*/ 6999 #define GPIO_FUNC252_IN_INV_SEL (BIT(6)) 7000 #define GPIO_FUNC252_IN_INV_SEL_M (BIT(6)) 7001 #define GPIO_FUNC252_IN_INV_SEL_V 0x1 7002 #define GPIO_FUNC252_IN_INV_SEL_S 6 7003 /* GPIO_FUNC252_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 7004 /*description: select one of the 256 inputs*/ 7005 #define GPIO_FUNC252_IN_SEL 0x0000003F 7006 #define GPIO_FUNC252_IN_SEL_M ((GPIO_FUNC252_IN_SEL_V)<<(GPIO_FUNC252_IN_SEL_S)) 7007 #define GPIO_FUNC252_IN_SEL_V 0x3F 7008 #define GPIO_FUNC252_IN_SEL_S 0 7009 7010 #define GPIO_FUNC253_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0524) 7011 /* GPIO_SIG253_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 7012 /*description: if the slow signal bypass the io matrix or not if you want setting 7013 the value to 1*/ 7014 #define GPIO_SIG253_IN_SEL (BIT(7)) 7015 #define GPIO_SIG253_IN_SEL_M (BIT(7)) 7016 #define GPIO_SIG253_IN_SEL_V 0x1 7017 #define GPIO_SIG253_IN_SEL_S 7 7018 /* GPIO_FUNC253_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 7019 /*description: revert the value of the input if you want to revert please set the value to 1*/ 7020 #define GPIO_FUNC253_IN_INV_SEL (BIT(6)) 7021 #define GPIO_FUNC253_IN_INV_SEL_M (BIT(6)) 7022 #define GPIO_FUNC253_IN_INV_SEL_V 0x1 7023 #define GPIO_FUNC253_IN_INV_SEL_S 6 7024 /* GPIO_FUNC253_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 7025 /*description: select one of the 256 inputs*/ 7026 #define GPIO_FUNC253_IN_SEL 0x0000003F 7027 #define GPIO_FUNC253_IN_SEL_M ((GPIO_FUNC253_IN_SEL_V)<<(GPIO_FUNC253_IN_SEL_S)) 7028 #define GPIO_FUNC253_IN_SEL_V 0x3F 7029 #define GPIO_FUNC253_IN_SEL_S 0 7030 7031 #define GPIO_FUNC254_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0528) 7032 /* GPIO_SIG254_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 7033 /*description: if the slow signal bypass the io matrix or not if you want setting 7034 the value to 1*/ 7035 #define GPIO_SIG254_IN_SEL (BIT(7)) 7036 #define GPIO_SIG254_IN_SEL_M (BIT(7)) 7037 #define GPIO_SIG254_IN_SEL_V 0x1 7038 #define GPIO_SIG254_IN_SEL_S 7 7039 /* GPIO_FUNC254_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 7040 /*description: revert the value of the input if you want to revert please set the value to 1*/ 7041 #define GPIO_FUNC254_IN_INV_SEL (BIT(6)) 7042 #define GPIO_FUNC254_IN_INV_SEL_M (BIT(6)) 7043 #define GPIO_FUNC254_IN_INV_SEL_V 0x1 7044 #define GPIO_FUNC254_IN_INV_SEL_S 6 7045 /* GPIO_FUNC254_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 7046 /*description: select one of the 256 inputs*/ 7047 #define GPIO_FUNC254_IN_SEL 0x0000003F 7048 #define GPIO_FUNC254_IN_SEL_M ((GPIO_FUNC254_IN_SEL_V)<<(GPIO_FUNC254_IN_SEL_S)) 7049 #define GPIO_FUNC254_IN_SEL_V 0x3F 7050 #define GPIO_FUNC254_IN_SEL_S 0 7051 7052 #define GPIO_FUNC255_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x052c) 7053 /* GPIO_SIG255_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ 7054 /*description: if the slow signal bypass the io matrix or not if you want setting 7055 the value to 1*/ 7056 #define GPIO_SIG255_IN_SEL (BIT(7)) 7057 #define GPIO_SIG255_IN_SEL_M (BIT(7)) 7058 #define GPIO_SIG255_IN_SEL_V 0x1 7059 #define GPIO_SIG255_IN_SEL_S 7 7060 /* GPIO_FUNC255_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ 7061 /*description: revert the value of the input if you want to revert please set the value to 1*/ 7062 #define GPIO_FUNC255_IN_INV_SEL (BIT(6)) 7063 #define GPIO_FUNC255_IN_INV_SEL_M (BIT(6)) 7064 #define GPIO_FUNC255_IN_INV_SEL_V 0x1 7065 #define GPIO_FUNC255_IN_INV_SEL_S 6 7066 /* GPIO_FUNC255_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ 7067 /*description: select one of the 256 inputs*/ 7068 #define GPIO_FUNC255_IN_SEL 0x0000003F 7069 #define GPIO_FUNC255_IN_SEL_M ((GPIO_FUNC255_IN_SEL_V)<<(GPIO_FUNC255_IN_SEL_S)) 7070 #define GPIO_FUNC255_IN_SEL_V 0x3F 7071 #define GPIO_FUNC255_IN_SEL_S 0 7072 7073 #define GPIO_FUNC0_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0530) 7074 /* GPIO_FUNC0_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ 7075 /*description: invert the output enable value if you want to revert the output 7076 enable value setting the value to 1*/ 7077 #define GPIO_FUNC0_OEN_INV_SEL (BIT(11)) 7078 #define GPIO_FUNC0_OEN_INV_SEL_M (BIT(11)) 7079 #define GPIO_FUNC0_OEN_INV_SEL_V 0x1 7080 #define GPIO_FUNC0_OEN_INV_SEL_S 11 7081 /* GPIO_FUNC0_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ 7082 /*description: weather using the logical oen signal or not using the value setting 7083 by the register*/ 7084 #define GPIO_FUNC0_OEN_SEL (BIT(10)) 7085 #define GPIO_FUNC0_OEN_SEL_M (BIT(10)) 7086 #define GPIO_FUNC0_OEN_SEL_V 0x1 7087 #define GPIO_FUNC0_OEN_SEL_S 10 7088 /* GPIO_FUNC0_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ 7089 /*description: invert the output value if you want to revert the output value 7090 setting the value to 1*/ 7091 #define GPIO_FUNC0_OUT_INV_SEL (BIT(9)) 7092 #define GPIO_FUNC0_OUT_INV_SEL_M (BIT(9)) 7093 #define GPIO_FUNC0_OUT_INV_SEL_V 0x1 7094 #define GPIO_FUNC0_OUT_INV_SEL_S 9 7095 /* GPIO_FUNC0_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ 7096 /*description: select one of the 256 output to 40 GPIO*/ 7097 #define GPIO_FUNC0_OUT_SEL 0x000001FF 7098 #define GPIO_FUNC0_OUT_SEL_M ((GPIO_FUNC0_OUT_SEL_V)<<(GPIO_FUNC0_OUT_SEL_S)) 7099 #define GPIO_FUNC0_OUT_SEL_V 0x1FF 7100 #define GPIO_FUNC0_OUT_SEL_S 0 7101 7102 #define GPIO_FUNC1_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0534) 7103 /* GPIO_FUNC1_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ 7104 /*description: invert the output enable value if you want to revert the output 7105 enable value setting the value to 1*/ 7106 #define GPIO_FUNC1_OEN_INV_SEL (BIT(11)) 7107 #define GPIO_FUNC1_OEN_INV_SEL_M (BIT(11)) 7108 #define GPIO_FUNC1_OEN_INV_SEL_V 0x1 7109 #define GPIO_FUNC1_OEN_INV_SEL_S 11 7110 /* GPIO_FUNC1_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ 7111 /*description: weather using the logical oen signal or not using the value setting 7112 by the register*/ 7113 #define GPIO_FUNC1_OEN_SEL (BIT(10)) 7114 #define GPIO_FUNC1_OEN_SEL_M (BIT(10)) 7115 #define GPIO_FUNC1_OEN_SEL_V 0x1 7116 #define GPIO_FUNC1_OEN_SEL_S 10 7117 /* GPIO_FUNC1_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ 7118 /*description: invert the output value if you want to revert the output value 7119 setting the value to 1*/ 7120 #define GPIO_FUNC1_OUT_INV_SEL (BIT(9)) 7121 #define GPIO_FUNC1_OUT_INV_SEL_M (BIT(9)) 7122 #define GPIO_FUNC1_OUT_INV_SEL_V 0x1 7123 #define GPIO_FUNC1_OUT_INV_SEL_S 9 7124 /* GPIO_FUNC1_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ 7125 /*description: select one of the 256 output to 40 GPIO*/ 7126 #define GPIO_FUNC1_OUT_SEL 0x000001FF 7127 #define GPIO_FUNC1_OUT_SEL_M ((GPIO_FUNC1_OUT_SEL_V)<<(GPIO_FUNC1_OUT_SEL_S)) 7128 #define GPIO_FUNC1_OUT_SEL_V 0x1FF 7129 #define GPIO_FUNC1_OUT_SEL_S 0 7130 7131 #define GPIO_FUNC2_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0538) 7132 /* GPIO_FUNC2_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ 7133 /*description: invert the output enable value if you want to revert the output 7134 enable value setting the value to 1*/ 7135 #define GPIO_FUNC2_OEN_INV_SEL (BIT(11)) 7136 #define GPIO_FUNC2_OEN_INV_SEL_M (BIT(11)) 7137 #define GPIO_FUNC2_OEN_INV_SEL_V 0x1 7138 #define GPIO_FUNC2_OEN_INV_SEL_S 11 7139 /* GPIO_FUNC2_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ 7140 /*description: weather using the logical oen signal or not using the value setting 7141 by the register*/ 7142 #define GPIO_FUNC2_OEN_SEL (BIT(10)) 7143 #define GPIO_FUNC2_OEN_SEL_M (BIT(10)) 7144 #define GPIO_FUNC2_OEN_SEL_V 0x1 7145 #define GPIO_FUNC2_OEN_SEL_S 10 7146 /* GPIO_FUNC2_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ 7147 /*description: invert the output value if you want to revert the output value 7148 setting the value to 1*/ 7149 #define GPIO_FUNC2_OUT_INV_SEL (BIT(9)) 7150 #define GPIO_FUNC2_OUT_INV_SEL_M (BIT(9)) 7151 #define GPIO_FUNC2_OUT_INV_SEL_V 0x1 7152 #define GPIO_FUNC2_OUT_INV_SEL_S 9 7153 /* GPIO_FUNC2_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ 7154 /*description: select one of the 256 output to 40 GPIO*/ 7155 #define GPIO_FUNC2_OUT_SEL 0x000001FF 7156 #define GPIO_FUNC2_OUT_SEL_M ((GPIO_FUNC2_OUT_SEL_V)<<(GPIO_FUNC2_OUT_SEL_S)) 7157 #define GPIO_FUNC2_OUT_SEL_V 0x1FF 7158 #define GPIO_FUNC2_OUT_SEL_S 0 7159 7160 #define GPIO_FUNC3_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x053c) 7161 /* GPIO_FUNC3_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ 7162 /*description: invert the output enable value if you want to revert the output 7163 enable value setting the value to 1*/ 7164 #define GPIO_FUNC3_OEN_INV_SEL (BIT(11)) 7165 #define GPIO_FUNC3_OEN_INV_SEL_M (BIT(11)) 7166 #define GPIO_FUNC3_OEN_INV_SEL_V 0x1 7167 #define GPIO_FUNC3_OEN_INV_SEL_S 11 7168 /* GPIO_FUNC3_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ 7169 /*description: weather using the logical oen signal or not using the value setting 7170 by the register*/ 7171 #define GPIO_FUNC3_OEN_SEL (BIT(10)) 7172 #define GPIO_FUNC3_OEN_SEL_M (BIT(10)) 7173 #define GPIO_FUNC3_OEN_SEL_V 0x1 7174 #define GPIO_FUNC3_OEN_SEL_S 10 7175 /* GPIO_FUNC3_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ 7176 /*description: invert the output value if you want to revert the output value 7177 setting the value to 1*/ 7178 #define GPIO_FUNC3_OUT_INV_SEL (BIT(9)) 7179 #define GPIO_FUNC3_OUT_INV_SEL_M (BIT(9)) 7180 #define GPIO_FUNC3_OUT_INV_SEL_V 0x1 7181 #define GPIO_FUNC3_OUT_INV_SEL_S 9 7182 /* GPIO_FUNC3_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ 7183 /*description: select one of the 256 output to 40 GPIO*/ 7184 #define GPIO_FUNC3_OUT_SEL 0x000001FF 7185 #define GPIO_FUNC3_OUT_SEL_M ((GPIO_FUNC3_OUT_SEL_V)<<(GPIO_FUNC3_OUT_SEL_S)) 7186 #define GPIO_FUNC3_OUT_SEL_V 0x1FF 7187 #define GPIO_FUNC3_OUT_SEL_S 0 7188 7189 #define GPIO_FUNC4_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0540) 7190 /* GPIO_FUNC4_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ 7191 /*description: invert the output enable value if you want to revert the output 7192 enable value setting the value to 1*/ 7193 #define GPIO_FUNC4_OEN_INV_SEL (BIT(11)) 7194 #define GPIO_FUNC4_OEN_INV_SEL_M (BIT(11)) 7195 #define GPIO_FUNC4_OEN_INV_SEL_V 0x1 7196 #define GPIO_FUNC4_OEN_INV_SEL_S 11 7197 /* GPIO_FUNC4_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ 7198 /*description: weather using the logical oen signal or not using the value setting 7199 by the register*/ 7200 #define GPIO_FUNC4_OEN_SEL (BIT(10)) 7201 #define GPIO_FUNC4_OEN_SEL_M (BIT(10)) 7202 #define GPIO_FUNC4_OEN_SEL_V 0x1 7203 #define GPIO_FUNC4_OEN_SEL_S 10 7204 /* GPIO_FUNC4_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ 7205 /*description: invert the output value if you want to revert the output value 7206 setting the value to 1*/ 7207 #define GPIO_FUNC4_OUT_INV_SEL (BIT(9)) 7208 #define GPIO_FUNC4_OUT_INV_SEL_M (BIT(9)) 7209 #define GPIO_FUNC4_OUT_INV_SEL_V 0x1 7210 #define GPIO_FUNC4_OUT_INV_SEL_S 9 7211 /* GPIO_FUNC4_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ 7212 /*description: select one of the 256 output to 40 GPIO*/ 7213 #define GPIO_FUNC4_OUT_SEL 0x000001FF 7214 #define GPIO_FUNC4_OUT_SEL_M ((GPIO_FUNC4_OUT_SEL_V)<<(GPIO_FUNC4_OUT_SEL_S)) 7215 #define GPIO_FUNC4_OUT_SEL_V 0x1FF 7216 #define GPIO_FUNC4_OUT_SEL_S 0 7217 7218 #define GPIO_FUNC5_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0544) 7219 /* GPIO_FUNC5_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ 7220 /*description: invert the output enable value if you want to revert the output 7221 enable value setting the value to 1*/ 7222 #define GPIO_FUNC5_OEN_INV_SEL (BIT(11)) 7223 #define GPIO_FUNC5_OEN_INV_SEL_M (BIT(11)) 7224 #define GPIO_FUNC5_OEN_INV_SEL_V 0x1 7225 #define GPIO_FUNC5_OEN_INV_SEL_S 11 7226 /* GPIO_FUNC5_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ 7227 /*description: weather using the logical oen signal or not using the value setting 7228 by the register*/ 7229 #define GPIO_FUNC5_OEN_SEL (BIT(10)) 7230 #define GPIO_FUNC5_OEN_SEL_M (BIT(10)) 7231 #define GPIO_FUNC5_OEN_SEL_V 0x1 7232 #define GPIO_FUNC5_OEN_SEL_S 10 7233 /* GPIO_FUNC5_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ 7234 /*description: invert the output value if you want to revert the output value 7235 setting the value to 1*/ 7236 #define GPIO_FUNC5_OUT_INV_SEL (BIT(9)) 7237 #define GPIO_FUNC5_OUT_INV_SEL_M (BIT(9)) 7238 #define GPIO_FUNC5_OUT_INV_SEL_V 0x1 7239 #define GPIO_FUNC5_OUT_INV_SEL_S 9 7240 /* GPIO_FUNC5_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ 7241 /*description: select one of the 256 output to 40 GPIO*/ 7242 #define GPIO_FUNC5_OUT_SEL 0x000001FF 7243 #define GPIO_FUNC5_OUT_SEL_M ((GPIO_FUNC5_OUT_SEL_V)<<(GPIO_FUNC5_OUT_SEL_S)) 7244 #define GPIO_FUNC5_OUT_SEL_V 0x1FF 7245 #define GPIO_FUNC5_OUT_SEL_S 0 7246 7247 #define GPIO_FUNC6_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0548) 7248 /* GPIO_FUNC6_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ 7249 /*description: invert the output enable value if you want to revert the output 7250 enable value setting the value to 1*/ 7251 #define GPIO_FUNC6_OEN_INV_SEL (BIT(11)) 7252 #define GPIO_FUNC6_OEN_INV_SEL_M (BIT(11)) 7253 #define GPIO_FUNC6_OEN_INV_SEL_V 0x1 7254 #define GPIO_FUNC6_OEN_INV_SEL_S 11 7255 /* GPIO_FUNC6_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ 7256 /*description: weather using the logical oen signal or not using the value setting 7257 by the register*/ 7258 #define GPIO_FUNC6_OEN_SEL (BIT(10)) 7259 #define GPIO_FUNC6_OEN_SEL_M (BIT(10)) 7260 #define GPIO_FUNC6_OEN_SEL_V 0x1 7261 #define GPIO_FUNC6_OEN_SEL_S 10 7262 /* GPIO_FUNC6_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ 7263 /*description: invert the output value if you want to revert the output value 7264 setting the value to 1*/ 7265 #define GPIO_FUNC6_OUT_INV_SEL (BIT(9)) 7266 #define GPIO_FUNC6_OUT_INV_SEL_M (BIT(9)) 7267 #define GPIO_FUNC6_OUT_INV_SEL_V 0x1 7268 #define GPIO_FUNC6_OUT_INV_SEL_S 9 7269 /* GPIO_FUNC6_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ 7270 /*description: select one of the 256 output to 40 GPIO*/ 7271 #define GPIO_FUNC6_OUT_SEL 0x000001FF 7272 #define GPIO_FUNC6_OUT_SEL_M ((GPIO_FUNC6_OUT_SEL_V)<<(GPIO_FUNC6_OUT_SEL_S)) 7273 #define GPIO_FUNC6_OUT_SEL_V 0x1FF 7274 #define GPIO_FUNC6_OUT_SEL_S 0 7275 7276 #define GPIO_FUNC7_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x054c) 7277 /* GPIO_FUNC7_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ 7278 /*description: invert the output enable value if you want to revert the output 7279 enable value setting the value to 1*/ 7280 #define GPIO_FUNC7_OEN_INV_SEL (BIT(11)) 7281 #define GPIO_FUNC7_OEN_INV_SEL_M (BIT(11)) 7282 #define GPIO_FUNC7_OEN_INV_SEL_V 0x1 7283 #define GPIO_FUNC7_OEN_INV_SEL_S 11 7284 /* GPIO_FUNC7_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ 7285 /*description: weather using the logical oen signal or not using the value setting 7286 by the register*/ 7287 #define GPIO_FUNC7_OEN_SEL (BIT(10)) 7288 #define GPIO_FUNC7_OEN_SEL_M (BIT(10)) 7289 #define GPIO_FUNC7_OEN_SEL_V 0x1 7290 #define GPIO_FUNC7_OEN_SEL_S 10 7291 /* GPIO_FUNC7_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ 7292 /*description: invert the output value if you want to revert the output value 7293 setting the value to 1*/ 7294 #define GPIO_FUNC7_OUT_INV_SEL (BIT(9)) 7295 #define GPIO_FUNC7_OUT_INV_SEL_M (BIT(9)) 7296 #define GPIO_FUNC7_OUT_INV_SEL_V 0x1 7297 #define GPIO_FUNC7_OUT_INV_SEL_S 9 7298 /* GPIO_FUNC7_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ 7299 /*description: select one of the 256 output to 40 GPIO*/ 7300 #define GPIO_FUNC7_OUT_SEL 0x000001FF 7301 #define GPIO_FUNC7_OUT_SEL_M ((GPIO_FUNC7_OUT_SEL_V)<<(GPIO_FUNC7_OUT_SEL_S)) 7302 #define GPIO_FUNC7_OUT_SEL_V 0x1FF 7303 #define GPIO_FUNC7_OUT_SEL_S 0 7304 7305 #define GPIO_FUNC8_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0550) 7306 /* GPIO_FUNC8_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ 7307 /*description: invert the output enable value if you want to revert the output 7308 enable value setting the value to 1*/ 7309 #define GPIO_FUNC8_OEN_INV_SEL (BIT(11)) 7310 #define GPIO_FUNC8_OEN_INV_SEL_M (BIT(11)) 7311 #define GPIO_FUNC8_OEN_INV_SEL_V 0x1 7312 #define GPIO_FUNC8_OEN_INV_SEL_S 11 7313 /* GPIO_FUNC8_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ 7314 /*description: weather using the logical oen signal or not using the value setting 7315 by the register*/ 7316 #define GPIO_FUNC8_OEN_SEL (BIT(10)) 7317 #define GPIO_FUNC8_OEN_SEL_M (BIT(10)) 7318 #define GPIO_FUNC8_OEN_SEL_V 0x1 7319 #define GPIO_FUNC8_OEN_SEL_S 10 7320 /* GPIO_FUNC8_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ 7321 /*description: invert the output value if you want to revert the output value 7322 setting the value to 1*/ 7323 #define GPIO_FUNC8_OUT_INV_SEL (BIT(9)) 7324 #define GPIO_FUNC8_OUT_INV_SEL_M (BIT(9)) 7325 #define GPIO_FUNC8_OUT_INV_SEL_V 0x1 7326 #define GPIO_FUNC8_OUT_INV_SEL_S 9 7327 /* GPIO_FUNC8_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ 7328 /*description: select one of the 256 output to 40 GPIO*/ 7329 #define GPIO_FUNC8_OUT_SEL 0x000001FF 7330 #define GPIO_FUNC8_OUT_SEL_M ((GPIO_FUNC8_OUT_SEL_V)<<(GPIO_FUNC8_OUT_SEL_S)) 7331 #define GPIO_FUNC8_OUT_SEL_V 0x1FF 7332 #define GPIO_FUNC8_OUT_SEL_S 0 7333 7334 #define GPIO_FUNC9_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0554) 7335 /* GPIO_FUNC9_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ 7336 /*description: invert the output enable value if you want to revert the output 7337 enable value setting the value to 1*/ 7338 #define GPIO_FUNC9_OEN_INV_SEL (BIT(11)) 7339 #define GPIO_FUNC9_OEN_INV_SEL_M (BIT(11)) 7340 #define GPIO_FUNC9_OEN_INV_SEL_V 0x1 7341 #define GPIO_FUNC9_OEN_INV_SEL_S 11 7342 /* GPIO_FUNC9_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ 7343 /*description: weather using the logical oen signal or not using the value setting 7344 by the register*/ 7345 #define GPIO_FUNC9_OEN_SEL (BIT(10)) 7346 #define GPIO_FUNC9_OEN_SEL_M (BIT(10)) 7347 #define GPIO_FUNC9_OEN_SEL_V 0x1 7348 #define GPIO_FUNC9_OEN_SEL_S 10 7349 /* GPIO_FUNC9_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ 7350 /*description: invert the output value if you want to revert the output value 7351 setting the value to 1*/ 7352 #define GPIO_FUNC9_OUT_INV_SEL (BIT(9)) 7353 #define GPIO_FUNC9_OUT_INV_SEL_M (BIT(9)) 7354 #define GPIO_FUNC9_OUT_INV_SEL_V 0x1 7355 #define GPIO_FUNC9_OUT_INV_SEL_S 9 7356 /* GPIO_FUNC9_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ 7357 /*description: select one of the 256 output to 40 GPIO*/ 7358 #define GPIO_FUNC9_OUT_SEL 0x000001FF 7359 #define GPIO_FUNC9_OUT_SEL_M ((GPIO_FUNC9_OUT_SEL_V)<<(GPIO_FUNC9_OUT_SEL_S)) 7360 #define GPIO_FUNC9_OUT_SEL_V 0x1FF 7361 #define GPIO_FUNC9_OUT_SEL_S 0 7362 7363 #define GPIO_FUNC10_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0558) 7364 /* GPIO_FUNC10_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ 7365 /*description: invert the output enable value if you want to revert the output 7366 enable value setting the value to 1*/ 7367 #define GPIO_FUNC10_OEN_INV_SEL (BIT(11)) 7368 #define GPIO_FUNC10_OEN_INV_SEL_M (BIT(11)) 7369 #define GPIO_FUNC10_OEN_INV_SEL_V 0x1 7370 #define GPIO_FUNC10_OEN_INV_SEL_S 11 7371 /* GPIO_FUNC10_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ 7372 /*description: weather using the logical oen signal or not using the value setting 7373 by the register*/ 7374 #define GPIO_FUNC10_OEN_SEL (BIT(10)) 7375 #define GPIO_FUNC10_OEN_SEL_M (BIT(10)) 7376 #define GPIO_FUNC10_OEN_SEL_V 0x1 7377 #define GPIO_FUNC10_OEN_SEL_S 10 7378 /* GPIO_FUNC10_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ 7379 /*description: invert the output value if you want to revert the output value 7380 setting the value to 1*/ 7381 #define GPIO_FUNC10_OUT_INV_SEL (BIT(9)) 7382 #define GPIO_FUNC10_OUT_INV_SEL_M (BIT(9)) 7383 #define GPIO_FUNC10_OUT_INV_SEL_V 0x1 7384 #define GPIO_FUNC10_OUT_INV_SEL_S 9 7385 /* GPIO_FUNC10_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ 7386 /*description: select one of the 256 output to 40 GPIO*/ 7387 #define GPIO_FUNC10_OUT_SEL 0x000001FF 7388 #define GPIO_FUNC10_OUT_SEL_M ((GPIO_FUNC10_OUT_SEL_V)<<(GPIO_FUNC10_OUT_SEL_S)) 7389 #define GPIO_FUNC10_OUT_SEL_V 0x1FF 7390 #define GPIO_FUNC10_OUT_SEL_S 0 7391 7392 #define GPIO_FUNC11_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x055c) 7393 /* GPIO_FUNC11_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ 7394 /*description: invert the output enable value if you want to revert the output 7395 enable value setting the value to 1*/ 7396 #define GPIO_FUNC11_OEN_INV_SEL (BIT(11)) 7397 #define GPIO_FUNC11_OEN_INV_SEL_M (BIT(11)) 7398 #define GPIO_FUNC11_OEN_INV_SEL_V 0x1 7399 #define GPIO_FUNC11_OEN_INV_SEL_S 11 7400 /* GPIO_FUNC11_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ 7401 /*description: weather using the logical oen signal or not using the value setting 7402 by the register*/ 7403 #define GPIO_FUNC11_OEN_SEL (BIT(10)) 7404 #define GPIO_FUNC11_OEN_SEL_M (BIT(10)) 7405 #define GPIO_FUNC11_OEN_SEL_V 0x1 7406 #define GPIO_FUNC11_OEN_SEL_S 10 7407 /* GPIO_FUNC11_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ 7408 /*description: invert the output value if you want to revert the output value 7409 setting the value to 1*/ 7410 #define GPIO_FUNC11_OUT_INV_SEL (BIT(9)) 7411 #define GPIO_FUNC11_OUT_INV_SEL_M (BIT(9)) 7412 #define GPIO_FUNC11_OUT_INV_SEL_V 0x1 7413 #define GPIO_FUNC11_OUT_INV_SEL_S 9 7414 /* GPIO_FUNC11_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ 7415 /*description: select one of the 256 output to 40 GPIO*/ 7416 #define GPIO_FUNC11_OUT_SEL 0x000001FF 7417 #define GPIO_FUNC11_OUT_SEL_M ((GPIO_FUNC11_OUT_SEL_V)<<(GPIO_FUNC11_OUT_SEL_S)) 7418 #define GPIO_FUNC11_OUT_SEL_V 0x1FF 7419 #define GPIO_FUNC11_OUT_SEL_S 0 7420 7421 #define GPIO_FUNC12_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0560) 7422 /* GPIO_FUNC12_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ 7423 /*description: invert the output enable value if you want to revert the output 7424 enable value setting the value to 1*/ 7425 #define GPIO_FUNC12_OEN_INV_SEL (BIT(11)) 7426 #define GPIO_FUNC12_OEN_INV_SEL_M (BIT(11)) 7427 #define GPIO_FUNC12_OEN_INV_SEL_V 0x1 7428 #define GPIO_FUNC12_OEN_INV_SEL_S 11 7429 /* GPIO_FUNC12_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ 7430 /*description: weather using the logical oen signal or not using the value setting 7431 by the register*/ 7432 #define GPIO_FUNC12_OEN_SEL (BIT(10)) 7433 #define GPIO_FUNC12_OEN_SEL_M (BIT(10)) 7434 #define GPIO_FUNC12_OEN_SEL_V 0x1 7435 #define GPIO_FUNC12_OEN_SEL_S 10 7436 /* GPIO_FUNC12_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ 7437 /*description: invert the output value if you want to revert the output value 7438 setting the value to 1*/ 7439 #define GPIO_FUNC12_OUT_INV_SEL (BIT(9)) 7440 #define GPIO_FUNC12_OUT_INV_SEL_M (BIT(9)) 7441 #define GPIO_FUNC12_OUT_INV_SEL_V 0x1 7442 #define GPIO_FUNC12_OUT_INV_SEL_S 9 7443 /* GPIO_FUNC12_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ 7444 /*description: select one of the 256 output to 40 GPIO*/ 7445 #define GPIO_FUNC12_OUT_SEL 0x000001FF 7446 #define GPIO_FUNC12_OUT_SEL_M ((GPIO_FUNC12_OUT_SEL_V)<<(GPIO_FUNC12_OUT_SEL_S)) 7447 #define GPIO_FUNC12_OUT_SEL_V 0x1FF 7448 #define GPIO_FUNC12_OUT_SEL_S 0 7449 7450 #define GPIO_FUNC13_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0564) 7451 /* GPIO_FUNC13_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ 7452 /*description: invert the output enable value if you want to revert the output 7453 enable value setting the value to 1*/ 7454 #define GPIO_FUNC13_OEN_INV_SEL (BIT(11)) 7455 #define GPIO_FUNC13_OEN_INV_SEL_M (BIT(11)) 7456 #define GPIO_FUNC13_OEN_INV_SEL_V 0x1 7457 #define GPIO_FUNC13_OEN_INV_SEL_S 11 7458 /* GPIO_FUNC13_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ 7459 /*description: weather using the logical oen signal or not using the value setting 7460 by the register*/ 7461 #define GPIO_FUNC13_OEN_SEL (BIT(10)) 7462 #define GPIO_FUNC13_OEN_SEL_M (BIT(10)) 7463 #define GPIO_FUNC13_OEN_SEL_V 0x1 7464 #define GPIO_FUNC13_OEN_SEL_S 10 7465 /* GPIO_FUNC13_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ 7466 /*description: invert the output value if you want to revert the output value 7467 setting the value to 1*/ 7468 #define GPIO_FUNC13_OUT_INV_SEL (BIT(9)) 7469 #define GPIO_FUNC13_OUT_INV_SEL_M (BIT(9)) 7470 #define GPIO_FUNC13_OUT_INV_SEL_V 0x1 7471 #define GPIO_FUNC13_OUT_INV_SEL_S 9 7472 /* GPIO_FUNC13_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ 7473 /*description: select one of the 256 output to 40 GPIO*/ 7474 #define GPIO_FUNC13_OUT_SEL 0x000001FF 7475 #define GPIO_FUNC13_OUT_SEL_M ((GPIO_FUNC13_OUT_SEL_V)<<(GPIO_FUNC13_OUT_SEL_S)) 7476 #define GPIO_FUNC13_OUT_SEL_V 0x1FF 7477 #define GPIO_FUNC13_OUT_SEL_S 0 7478 7479 #define GPIO_FUNC14_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0568) 7480 /* GPIO_FUNC14_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ 7481 /*description: invert the output enable value if you want to revert the output 7482 enable value setting the value to 1*/ 7483 #define GPIO_FUNC14_OEN_INV_SEL (BIT(11)) 7484 #define GPIO_FUNC14_OEN_INV_SEL_M (BIT(11)) 7485 #define GPIO_FUNC14_OEN_INV_SEL_V 0x1 7486 #define GPIO_FUNC14_OEN_INV_SEL_S 11 7487 /* GPIO_FUNC14_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ 7488 /*description: weather using the logical oen signal or not using the value setting 7489 by the register*/ 7490 #define GPIO_FUNC14_OEN_SEL (BIT(10)) 7491 #define GPIO_FUNC14_OEN_SEL_M (BIT(10)) 7492 #define GPIO_FUNC14_OEN_SEL_V 0x1 7493 #define GPIO_FUNC14_OEN_SEL_S 10 7494 /* GPIO_FUNC14_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ 7495 /*description: invert the output value if you want to revert the output value 7496 setting the value to 1*/ 7497 #define GPIO_FUNC14_OUT_INV_SEL (BIT(9)) 7498 #define GPIO_FUNC14_OUT_INV_SEL_M (BIT(9)) 7499 #define GPIO_FUNC14_OUT_INV_SEL_V 0x1 7500 #define GPIO_FUNC14_OUT_INV_SEL_S 9 7501 /* GPIO_FUNC14_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ 7502 /*description: select one of the 256 output to 40 GPIO*/ 7503 #define GPIO_FUNC14_OUT_SEL 0x000001FF 7504 #define GPIO_FUNC14_OUT_SEL_M ((GPIO_FUNC14_OUT_SEL_V)<<(GPIO_FUNC14_OUT_SEL_S)) 7505 #define GPIO_FUNC14_OUT_SEL_V 0x1FF 7506 #define GPIO_FUNC14_OUT_SEL_S 0 7507 7508 #define GPIO_FUNC15_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x056c) 7509 /* GPIO_FUNC15_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ 7510 /*description: invert the output enable value if you want to revert the output 7511 enable value setting the value to 1*/ 7512 #define GPIO_FUNC15_OEN_INV_SEL (BIT(11)) 7513 #define GPIO_FUNC15_OEN_INV_SEL_M (BIT(11)) 7514 #define GPIO_FUNC15_OEN_INV_SEL_V 0x1 7515 #define GPIO_FUNC15_OEN_INV_SEL_S 11 7516 /* GPIO_FUNC15_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ 7517 /*description: weather using the logical oen signal or not using the value setting 7518 by the register*/ 7519 #define GPIO_FUNC15_OEN_SEL (BIT(10)) 7520 #define GPIO_FUNC15_OEN_SEL_M (BIT(10)) 7521 #define GPIO_FUNC15_OEN_SEL_V 0x1 7522 #define GPIO_FUNC15_OEN_SEL_S 10 7523 /* GPIO_FUNC15_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ 7524 /*description: invert the output value if you want to revert the output value 7525 setting the value to 1*/ 7526 #define GPIO_FUNC15_OUT_INV_SEL (BIT(9)) 7527 #define GPIO_FUNC15_OUT_INV_SEL_M (BIT(9)) 7528 #define GPIO_FUNC15_OUT_INV_SEL_V 0x1 7529 #define GPIO_FUNC15_OUT_INV_SEL_S 9 7530 /* GPIO_FUNC15_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ 7531 /*description: select one of the 256 output to 40 GPIO*/ 7532 #define GPIO_FUNC15_OUT_SEL 0x000001FF 7533 #define GPIO_FUNC15_OUT_SEL_M ((GPIO_FUNC15_OUT_SEL_V)<<(GPIO_FUNC15_OUT_SEL_S)) 7534 #define GPIO_FUNC15_OUT_SEL_V 0x1FF 7535 #define GPIO_FUNC15_OUT_SEL_S 0 7536 7537 #define GPIO_FUNC16_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0570) 7538 /* GPIO_FUNC16_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ 7539 /*description: invert the output enable value if you want to revert the output 7540 enable value setting the value to 1*/ 7541 #define GPIO_FUNC16_OEN_INV_SEL (BIT(11)) 7542 #define GPIO_FUNC16_OEN_INV_SEL_M (BIT(11)) 7543 #define GPIO_FUNC16_OEN_INV_SEL_V 0x1 7544 #define GPIO_FUNC16_OEN_INV_SEL_S 11 7545 /* GPIO_FUNC16_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ 7546 /*description: weather using the logical oen signal or not using the value setting 7547 by the register*/ 7548 #define GPIO_FUNC16_OEN_SEL (BIT(10)) 7549 #define GPIO_FUNC16_OEN_SEL_M (BIT(10)) 7550 #define GPIO_FUNC16_OEN_SEL_V 0x1 7551 #define GPIO_FUNC16_OEN_SEL_S 10 7552 /* GPIO_FUNC16_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ 7553 /*description: invert the output value if you want to revert the output value 7554 setting the value to 1*/ 7555 #define GPIO_FUNC16_OUT_INV_SEL (BIT(9)) 7556 #define GPIO_FUNC16_OUT_INV_SEL_M (BIT(9)) 7557 #define GPIO_FUNC16_OUT_INV_SEL_V 0x1 7558 #define GPIO_FUNC16_OUT_INV_SEL_S 9 7559 /* GPIO_FUNC16_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ 7560 /*description: select one of the 256 output to 40 GPIO*/ 7561 #define GPIO_FUNC16_OUT_SEL 0x000001FF 7562 #define GPIO_FUNC16_OUT_SEL_M ((GPIO_FUNC16_OUT_SEL_V)<<(GPIO_FUNC16_OUT_SEL_S)) 7563 #define GPIO_FUNC16_OUT_SEL_V 0x1FF 7564 #define GPIO_FUNC16_OUT_SEL_S 0 7565 7566 #define GPIO_FUNC17_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0574) 7567 /* GPIO_FUNC17_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ 7568 /*description: invert the output enable value if you want to revert the output 7569 enable value setting the value to 1*/ 7570 #define GPIO_FUNC17_OEN_INV_SEL (BIT(11)) 7571 #define GPIO_FUNC17_OEN_INV_SEL_M (BIT(11)) 7572 #define GPIO_FUNC17_OEN_INV_SEL_V 0x1 7573 #define GPIO_FUNC17_OEN_INV_SEL_S 11 7574 /* GPIO_FUNC17_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ 7575 /*description: weather using the logical oen signal or not using the value setting 7576 by the register*/ 7577 #define GPIO_FUNC17_OEN_SEL (BIT(10)) 7578 #define GPIO_FUNC17_OEN_SEL_M (BIT(10)) 7579 #define GPIO_FUNC17_OEN_SEL_V 0x1 7580 #define GPIO_FUNC17_OEN_SEL_S 10 7581 /* GPIO_FUNC17_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ 7582 /*description: invert the output value if you want to revert the output value 7583 setting the value to 1*/ 7584 #define GPIO_FUNC17_OUT_INV_SEL (BIT(9)) 7585 #define GPIO_FUNC17_OUT_INV_SEL_M (BIT(9)) 7586 #define GPIO_FUNC17_OUT_INV_SEL_V 0x1 7587 #define GPIO_FUNC17_OUT_INV_SEL_S 9 7588 /* GPIO_FUNC17_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ 7589 /*description: select one of the 256 output to 40 GPIO*/ 7590 #define GPIO_FUNC17_OUT_SEL 0x000001FF 7591 #define GPIO_FUNC17_OUT_SEL_M ((GPIO_FUNC17_OUT_SEL_V)<<(GPIO_FUNC17_OUT_SEL_S)) 7592 #define GPIO_FUNC17_OUT_SEL_V 0x1FF 7593 #define GPIO_FUNC17_OUT_SEL_S 0 7594 7595 #define GPIO_FUNC18_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0578) 7596 /* GPIO_FUNC18_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ 7597 /*description: invert the output enable value if you want to revert the output 7598 enable value setting the value to 1*/ 7599 #define GPIO_FUNC18_OEN_INV_SEL (BIT(11)) 7600 #define GPIO_FUNC18_OEN_INV_SEL_M (BIT(11)) 7601 #define GPIO_FUNC18_OEN_INV_SEL_V 0x1 7602 #define GPIO_FUNC18_OEN_INV_SEL_S 11 7603 /* GPIO_FUNC18_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ 7604 /*description: weather using the logical oen signal or not using the value setting 7605 by the register*/ 7606 #define GPIO_FUNC18_OEN_SEL (BIT(10)) 7607 #define GPIO_FUNC18_OEN_SEL_M (BIT(10)) 7608 #define GPIO_FUNC18_OEN_SEL_V 0x1 7609 #define GPIO_FUNC18_OEN_SEL_S 10 7610 /* GPIO_FUNC18_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ 7611 /*description: invert the output value if you want to revert the output value 7612 setting the value to 1*/ 7613 #define GPIO_FUNC18_OUT_INV_SEL (BIT(9)) 7614 #define GPIO_FUNC18_OUT_INV_SEL_M (BIT(9)) 7615 #define GPIO_FUNC18_OUT_INV_SEL_V 0x1 7616 #define GPIO_FUNC18_OUT_INV_SEL_S 9 7617 /* GPIO_FUNC18_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ 7618 /*description: select one of the 256 output to 40 GPIO*/ 7619 #define GPIO_FUNC18_OUT_SEL 0x000001FF 7620 #define GPIO_FUNC18_OUT_SEL_M ((GPIO_FUNC18_OUT_SEL_V)<<(GPIO_FUNC18_OUT_SEL_S)) 7621 #define GPIO_FUNC18_OUT_SEL_V 0x1FF 7622 #define GPIO_FUNC18_OUT_SEL_S 0 7623 7624 #define GPIO_FUNC19_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x057c) 7625 /* GPIO_FUNC19_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ 7626 /*description: invert the output enable value if you want to revert the output 7627 enable value setting the value to 1*/ 7628 #define GPIO_FUNC19_OEN_INV_SEL (BIT(11)) 7629 #define GPIO_FUNC19_OEN_INV_SEL_M (BIT(11)) 7630 #define GPIO_FUNC19_OEN_INV_SEL_V 0x1 7631 #define GPIO_FUNC19_OEN_INV_SEL_S 11 7632 /* GPIO_FUNC19_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ 7633 /*description: weather using the logical oen signal or not using the value setting 7634 by the register*/ 7635 #define GPIO_FUNC19_OEN_SEL (BIT(10)) 7636 #define GPIO_FUNC19_OEN_SEL_M (BIT(10)) 7637 #define GPIO_FUNC19_OEN_SEL_V 0x1 7638 #define GPIO_FUNC19_OEN_SEL_S 10 7639 /* GPIO_FUNC19_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ 7640 /*description: invert the output value if you want to revert the output value 7641 setting the value to 1*/ 7642 #define GPIO_FUNC19_OUT_INV_SEL (BIT(9)) 7643 #define GPIO_FUNC19_OUT_INV_SEL_M (BIT(9)) 7644 #define GPIO_FUNC19_OUT_INV_SEL_V 0x1 7645 #define GPIO_FUNC19_OUT_INV_SEL_S 9 7646 /* GPIO_FUNC19_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ 7647 /*description: select one of the 256 output to 40 GPIO*/ 7648 #define GPIO_FUNC19_OUT_SEL 0x000001FF 7649 #define GPIO_FUNC19_OUT_SEL_M ((GPIO_FUNC19_OUT_SEL_V)<<(GPIO_FUNC19_OUT_SEL_S)) 7650 #define GPIO_FUNC19_OUT_SEL_V 0x1FF 7651 #define GPIO_FUNC19_OUT_SEL_S 0 7652 7653 #define GPIO_FUNC20_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0580) 7654 /* GPIO_FUNC20_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ 7655 /*description: invert the output enable value if you want to revert the output 7656 enable value setting the value to 1*/ 7657 #define GPIO_FUNC20_OEN_INV_SEL (BIT(11)) 7658 #define GPIO_FUNC20_OEN_INV_SEL_M (BIT(11)) 7659 #define GPIO_FUNC20_OEN_INV_SEL_V 0x1 7660 #define GPIO_FUNC20_OEN_INV_SEL_S 11 7661 /* GPIO_FUNC20_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ 7662 /*description: weather using the logical oen signal or not using the value setting 7663 by the register*/ 7664 #define GPIO_FUNC20_OEN_SEL (BIT(10)) 7665 #define GPIO_FUNC20_OEN_SEL_M (BIT(10)) 7666 #define GPIO_FUNC20_OEN_SEL_V 0x1 7667 #define GPIO_FUNC20_OEN_SEL_S 10 7668 /* GPIO_FUNC20_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ 7669 /*description: invert the output value if you want to revert the output value 7670 setting the value to 1*/ 7671 #define GPIO_FUNC20_OUT_INV_SEL (BIT(9)) 7672 #define GPIO_FUNC20_OUT_INV_SEL_M (BIT(9)) 7673 #define GPIO_FUNC20_OUT_INV_SEL_V 0x1 7674 #define GPIO_FUNC20_OUT_INV_SEL_S 9 7675 /* GPIO_FUNC20_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ 7676 /*description: select one of the 256 output to 40 GPIO*/ 7677 #define GPIO_FUNC20_OUT_SEL 0x000001FF 7678 #define GPIO_FUNC20_OUT_SEL_M ((GPIO_FUNC20_OUT_SEL_V)<<(GPIO_FUNC20_OUT_SEL_S)) 7679 #define GPIO_FUNC20_OUT_SEL_V 0x1FF 7680 #define GPIO_FUNC20_OUT_SEL_S 0 7681 7682 #define GPIO_FUNC21_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0584) 7683 /* GPIO_FUNC21_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ 7684 /*description: invert the output enable value if you want to revert the output 7685 enable value setting the value to 1*/ 7686 #define GPIO_FUNC21_OEN_INV_SEL (BIT(11)) 7687 #define GPIO_FUNC21_OEN_INV_SEL_M (BIT(11)) 7688 #define GPIO_FUNC21_OEN_INV_SEL_V 0x1 7689 #define GPIO_FUNC21_OEN_INV_SEL_S 11 7690 /* GPIO_FUNC21_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ 7691 /*description: weather using the logical oen signal or not using the value setting 7692 by the register*/ 7693 #define GPIO_FUNC21_OEN_SEL (BIT(10)) 7694 #define GPIO_FUNC21_OEN_SEL_M (BIT(10)) 7695 #define GPIO_FUNC21_OEN_SEL_V 0x1 7696 #define GPIO_FUNC21_OEN_SEL_S 10 7697 /* GPIO_FUNC21_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ 7698 /*description: invert the output value if you want to revert the output value 7699 setting the value to 1*/ 7700 #define GPIO_FUNC21_OUT_INV_SEL (BIT(9)) 7701 #define GPIO_FUNC21_OUT_INV_SEL_M (BIT(9)) 7702 #define GPIO_FUNC21_OUT_INV_SEL_V 0x1 7703 #define GPIO_FUNC21_OUT_INV_SEL_S 9 7704 /* GPIO_FUNC21_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ 7705 /*description: select one of the 256 output to 40 GPIO*/ 7706 #define GPIO_FUNC21_OUT_SEL 0x000001FF 7707 #define GPIO_FUNC21_OUT_SEL_M ((GPIO_FUNC21_OUT_SEL_V)<<(GPIO_FUNC21_OUT_SEL_S)) 7708 #define GPIO_FUNC21_OUT_SEL_V 0x1FF 7709 #define GPIO_FUNC21_OUT_SEL_S 0 7710 7711 #define GPIO_FUNC22_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0588) 7712 /* GPIO_FUNC22_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ 7713 /*description: invert the output enable value if you want to revert the output 7714 enable value setting the value to 1*/ 7715 #define GPIO_FUNC22_OEN_INV_SEL (BIT(11)) 7716 #define GPIO_FUNC22_OEN_INV_SEL_M (BIT(11)) 7717 #define GPIO_FUNC22_OEN_INV_SEL_V 0x1 7718 #define GPIO_FUNC22_OEN_INV_SEL_S 11 7719 /* GPIO_FUNC22_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ 7720 /*description: weather using the logical oen signal or not using the value setting 7721 by the register*/ 7722 #define GPIO_FUNC22_OEN_SEL (BIT(10)) 7723 #define GPIO_FUNC22_OEN_SEL_M (BIT(10)) 7724 #define GPIO_FUNC22_OEN_SEL_V 0x1 7725 #define GPIO_FUNC22_OEN_SEL_S 10 7726 /* GPIO_FUNC22_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ 7727 /*description: invert the output value if you want to revert the output value 7728 setting the value to 1*/ 7729 #define GPIO_FUNC22_OUT_INV_SEL (BIT(9)) 7730 #define GPIO_FUNC22_OUT_INV_SEL_M (BIT(9)) 7731 #define GPIO_FUNC22_OUT_INV_SEL_V 0x1 7732 #define GPIO_FUNC22_OUT_INV_SEL_S 9 7733 /* GPIO_FUNC22_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ 7734 /*description: select one of the 256 output to 40 GPIO*/ 7735 #define GPIO_FUNC22_OUT_SEL 0x000001FF 7736 #define GPIO_FUNC22_OUT_SEL_M ((GPIO_FUNC22_OUT_SEL_V)<<(GPIO_FUNC22_OUT_SEL_S)) 7737 #define GPIO_FUNC22_OUT_SEL_V 0x1FF 7738 #define GPIO_FUNC22_OUT_SEL_S 0 7739 7740 #define GPIO_FUNC23_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x058c) 7741 /* GPIO_FUNC23_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ 7742 /*description: invert the output enable value if you want to revert the output 7743 enable value setting the value to 1*/ 7744 #define GPIO_FUNC23_OEN_INV_SEL (BIT(11)) 7745 #define GPIO_FUNC23_OEN_INV_SEL_M (BIT(11)) 7746 #define GPIO_FUNC23_OEN_INV_SEL_V 0x1 7747 #define GPIO_FUNC23_OEN_INV_SEL_S 11 7748 /* GPIO_FUNC23_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ 7749 /*description: weather using the logical oen signal or not using the value setting 7750 by the register*/ 7751 #define GPIO_FUNC23_OEN_SEL (BIT(10)) 7752 #define GPIO_FUNC23_OEN_SEL_M (BIT(10)) 7753 #define GPIO_FUNC23_OEN_SEL_V 0x1 7754 #define GPIO_FUNC23_OEN_SEL_S 10 7755 /* GPIO_FUNC23_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ 7756 /*description: invert the output value if you want to revert the output value 7757 setting the value to 1*/ 7758 #define GPIO_FUNC23_OUT_INV_SEL (BIT(9)) 7759 #define GPIO_FUNC23_OUT_INV_SEL_M (BIT(9)) 7760 #define GPIO_FUNC23_OUT_INV_SEL_V 0x1 7761 #define GPIO_FUNC23_OUT_INV_SEL_S 9 7762 /* GPIO_FUNC23_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ 7763 /*description: select one of the 256 output to 40 GPIO*/ 7764 #define GPIO_FUNC23_OUT_SEL 0x000001FF 7765 #define GPIO_FUNC23_OUT_SEL_M ((GPIO_FUNC23_OUT_SEL_V)<<(GPIO_FUNC23_OUT_SEL_S)) 7766 #define GPIO_FUNC23_OUT_SEL_V 0x1FF 7767 #define GPIO_FUNC23_OUT_SEL_S 0 7768 7769 #define GPIO_FUNC24_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0590) 7770 /* GPIO_FUNC24_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ 7771 /*description: invert the output enable value if you want to revert the output 7772 enable value setting the value to 1*/ 7773 #define GPIO_FUNC24_OEN_INV_SEL (BIT(11)) 7774 #define GPIO_FUNC24_OEN_INV_SEL_M (BIT(11)) 7775 #define GPIO_FUNC24_OEN_INV_SEL_V 0x1 7776 #define GPIO_FUNC24_OEN_INV_SEL_S 11 7777 /* GPIO_FUNC24_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ 7778 /*description: weather using the logical oen signal or not using the value setting 7779 by the register*/ 7780 #define GPIO_FUNC24_OEN_SEL (BIT(10)) 7781 #define GPIO_FUNC24_OEN_SEL_M (BIT(10)) 7782 #define GPIO_FUNC24_OEN_SEL_V 0x1 7783 #define GPIO_FUNC24_OEN_SEL_S 10 7784 /* GPIO_FUNC24_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ 7785 /*description: invert the output value if you want to revert the output value 7786 setting the value to 1*/ 7787 #define GPIO_FUNC24_OUT_INV_SEL (BIT(9)) 7788 #define GPIO_FUNC24_OUT_INV_SEL_M (BIT(9)) 7789 #define GPIO_FUNC24_OUT_INV_SEL_V 0x1 7790 #define GPIO_FUNC24_OUT_INV_SEL_S 9 7791 /* GPIO_FUNC24_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ 7792 /*description: select one of the 256 output to 40 GPIO*/ 7793 #define GPIO_FUNC24_OUT_SEL 0x000001FF 7794 #define GPIO_FUNC24_OUT_SEL_M ((GPIO_FUNC24_OUT_SEL_V)<<(GPIO_FUNC24_OUT_SEL_S)) 7795 #define GPIO_FUNC24_OUT_SEL_V 0x1FF 7796 #define GPIO_FUNC24_OUT_SEL_S 0 7797 7798 #define GPIO_FUNC25_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0594) 7799 /* GPIO_FUNC25_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ 7800 /*description: invert the output enable value if you want to revert the output 7801 enable value setting the value to 1*/ 7802 #define GPIO_FUNC25_OEN_INV_SEL (BIT(11)) 7803 #define GPIO_FUNC25_OEN_INV_SEL_M (BIT(11)) 7804 #define GPIO_FUNC25_OEN_INV_SEL_V 0x1 7805 #define GPIO_FUNC25_OEN_INV_SEL_S 11 7806 /* GPIO_FUNC25_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ 7807 /*description: weather using the logical oen signal or not using the value setting 7808 by the register*/ 7809 #define GPIO_FUNC25_OEN_SEL (BIT(10)) 7810 #define GPIO_FUNC25_OEN_SEL_M (BIT(10)) 7811 #define GPIO_FUNC25_OEN_SEL_V 0x1 7812 #define GPIO_FUNC25_OEN_SEL_S 10 7813 /* GPIO_FUNC25_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ 7814 /*description: invert the output value if you want to revert the output value 7815 setting the value to 1*/ 7816 #define GPIO_FUNC25_OUT_INV_SEL (BIT(9)) 7817 #define GPIO_FUNC25_OUT_INV_SEL_M (BIT(9)) 7818 #define GPIO_FUNC25_OUT_INV_SEL_V 0x1 7819 #define GPIO_FUNC25_OUT_INV_SEL_S 9 7820 /* GPIO_FUNC25_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ 7821 /*description: select one of the 256 output to 40 GPIO*/ 7822 #define GPIO_FUNC25_OUT_SEL 0x000001FF 7823 #define GPIO_FUNC25_OUT_SEL_M ((GPIO_FUNC25_OUT_SEL_V)<<(GPIO_FUNC25_OUT_SEL_S)) 7824 #define GPIO_FUNC25_OUT_SEL_V 0x1FF 7825 #define GPIO_FUNC25_OUT_SEL_S 0 7826 7827 #define GPIO_FUNC26_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0598) 7828 /* GPIO_FUNC26_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ 7829 /*description: invert the output enable value if you want to revert the output 7830 enable value setting the value to 1*/ 7831 #define GPIO_FUNC26_OEN_INV_SEL (BIT(11)) 7832 #define GPIO_FUNC26_OEN_INV_SEL_M (BIT(11)) 7833 #define GPIO_FUNC26_OEN_INV_SEL_V 0x1 7834 #define GPIO_FUNC26_OEN_INV_SEL_S 11 7835 /* GPIO_FUNC26_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ 7836 /*description: weather using the logical oen signal or not using the value setting 7837 by the register*/ 7838 #define GPIO_FUNC26_OEN_SEL (BIT(10)) 7839 #define GPIO_FUNC26_OEN_SEL_M (BIT(10)) 7840 #define GPIO_FUNC26_OEN_SEL_V 0x1 7841 #define GPIO_FUNC26_OEN_SEL_S 10 7842 /* GPIO_FUNC26_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ 7843 /*description: invert the output value if you want to revert the output value 7844 setting the value to 1*/ 7845 #define GPIO_FUNC26_OUT_INV_SEL (BIT(9)) 7846 #define GPIO_FUNC26_OUT_INV_SEL_M (BIT(9)) 7847 #define GPIO_FUNC26_OUT_INV_SEL_V 0x1 7848 #define GPIO_FUNC26_OUT_INV_SEL_S 9 7849 /* GPIO_FUNC26_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ 7850 /*description: select one of the 256 output to 40 GPIO*/ 7851 #define GPIO_FUNC26_OUT_SEL 0x000001FF 7852 #define GPIO_FUNC26_OUT_SEL_M ((GPIO_FUNC26_OUT_SEL_V)<<(GPIO_FUNC26_OUT_SEL_S)) 7853 #define GPIO_FUNC26_OUT_SEL_V 0x1FF 7854 #define GPIO_FUNC26_OUT_SEL_S 0 7855 7856 #define GPIO_FUNC27_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x059c) 7857 /* GPIO_FUNC27_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ 7858 /*description: invert the output enable value if you want to revert the output 7859 enable value setting the value to 1*/ 7860 #define GPIO_FUNC27_OEN_INV_SEL (BIT(11)) 7861 #define GPIO_FUNC27_OEN_INV_SEL_M (BIT(11)) 7862 #define GPIO_FUNC27_OEN_INV_SEL_V 0x1 7863 #define GPIO_FUNC27_OEN_INV_SEL_S 11 7864 /* GPIO_FUNC27_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ 7865 /*description: weather using the logical oen signal or not using the value setting 7866 by the register*/ 7867 #define GPIO_FUNC27_OEN_SEL (BIT(10)) 7868 #define GPIO_FUNC27_OEN_SEL_M (BIT(10)) 7869 #define GPIO_FUNC27_OEN_SEL_V 0x1 7870 #define GPIO_FUNC27_OEN_SEL_S 10 7871 /* GPIO_FUNC27_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ 7872 /*description: invert the output value if you want to revert the output value 7873 setting the value to 1*/ 7874 #define GPIO_FUNC27_OUT_INV_SEL (BIT(9)) 7875 #define GPIO_FUNC27_OUT_INV_SEL_M (BIT(9)) 7876 #define GPIO_FUNC27_OUT_INV_SEL_V 0x1 7877 #define GPIO_FUNC27_OUT_INV_SEL_S 9 7878 /* GPIO_FUNC27_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ 7879 /*description: select one of the 256 output to 40 GPIO*/ 7880 #define GPIO_FUNC27_OUT_SEL 0x000001FF 7881 #define GPIO_FUNC27_OUT_SEL_M ((GPIO_FUNC27_OUT_SEL_V)<<(GPIO_FUNC27_OUT_SEL_S)) 7882 #define GPIO_FUNC27_OUT_SEL_V 0x1FF 7883 #define GPIO_FUNC27_OUT_SEL_S 0 7884 7885 #define GPIO_FUNC28_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x05a0) 7886 /* GPIO_FUNC28_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ 7887 /*description: invert the output enable value if you want to revert the output 7888 enable value setting the value to 1*/ 7889 #define GPIO_FUNC28_OEN_INV_SEL (BIT(11)) 7890 #define GPIO_FUNC28_OEN_INV_SEL_M (BIT(11)) 7891 #define GPIO_FUNC28_OEN_INV_SEL_V 0x1 7892 #define GPIO_FUNC28_OEN_INV_SEL_S 11 7893 /* GPIO_FUNC28_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ 7894 /*description: weather using the logical oen signal or not using the value setting 7895 by the register*/ 7896 #define GPIO_FUNC28_OEN_SEL (BIT(10)) 7897 #define GPIO_FUNC28_OEN_SEL_M (BIT(10)) 7898 #define GPIO_FUNC28_OEN_SEL_V 0x1 7899 #define GPIO_FUNC28_OEN_SEL_S 10 7900 /* GPIO_FUNC28_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ 7901 /*description: invert the output value if you want to revert the output value 7902 setting the value to 1*/ 7903 #define GPIO_FUNC28_OUT_INV_SEL (BIT(9)) 7904 #define GPIO_FUNC28_OUT_INV_SEL_M (BIT(9)) 7905 #define GPIO_FUNC28_OUT_INV_SEL_V 0x1 7906 #define GPIO_FUNC28_OUT_INV_SEL_S 9 7907 /* GPIO_FUNC28_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ 7908 /*description: select one of the 256 output to 40 GPIO*/ 7909 #define GPIO_FUNC28_OUT_SEL 0x000001FF 7910 #define GPIO_FUNC28_OUT_SEL_M ((GPIO_FUNC28_OUT_SEL_V)<<(GPIO_FUNC28_OUT_SEL_S)) 7911 #define GPIO_FUNC28_OUT_SEL_V 0x1FF 7912 #define GPIO_FUNC28_OUT_SEL_S 0 7913 7914 #define GPIO_FUNC29_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x05a4) 7915 /* GPIO_FUNC29_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ 7916 /*description: invert the output enable value if you want to revert the output 7917 enable value setting the value to 1*/ 7918 #define GPIO_FUNC29_OEN_INV_SEL (BIT(11)) 7919 #define GPIO_FUNC29_OEN_INV_SEL_M (BIT(11)) 7920 #define GPIO_FUNC29_OEN_INV_SEL_V 0x1 7921 #define GPIO_FUNC29_OEN_INV_SEL_S 11 7922 /* GPIO_FUNC29_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ 7923 /*description: weather using the logical oen signal or not using the value setting 7924 by the register*/ 7925 #define GPIO_FUNC29_OEN_SEL (BIT(10)) 7926 #define GPIO_FUNC29_OEN_SEL_M (BIT(10)) 7927 #define GPIO_FUNC29_OEN_SEL_V 0x1 7928 #define GPIO_FUNC29_OEN_SEL_S 10 7929 /* GPIO_FUNC29_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ 7930 /*description: invert the output value if you want to revert the output value 7931 setting the value to 1*/ 7932 #define GPIO_FUNC29_OUT_INV_SEL (BIT(9)) 7933 #define GPIO_FUNC29_OUT_INV_SEL_M (BIT(9)) 7934 #define GPIO_FUNC29_OUT_INV_SEL_V 0x1 7935 #define GPIO_FUNC29_OUT_INV_SEL_S 9 7936 /* GPIO_FUNC29_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ 7937 /*description: select one of the 256 output to 40 GPIO*/ 7938 #define GPIO_FUNC29_OUT_SEL 0x000001FF 7939 #define GPIO_FUNC29_OUT_SEL_M ((GPIO_FUNC29_OUT_SEL_V)<<(GPIO_FUNC29_OUT_SEL_S)) 7940 #define GPIO_FUNC29_OUT_SEL_V 0x1FF 7941 #define GPIO_FUNC29_OUT_SEL_S 0 7942 7943 #define GPIO_FUNC30_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x05a8) 7944 /* GPIO_FUNC30_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ 7945 /*description: invert the output enable value if you want to revert the output 7946 enable value setting the value to 1*/ 7947 #define GPIO_FUNC30_OEN_INV_SEL (BIT(11)) 7948 #define GPIO_FUNC30_OEN_INV_SEL_M (BIT(11)) 7949 #define GPIO_FUNC30_OEN_INV_SEL_V 0x1 7950 #define GPIO_FUNC30_OEN_INV_SEL_S 11 7951 /* GPIO_FUNC30_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ 7952 /*description: weather using the logical oen signal or not using the value setting 7953 by the register*/ 7954 #define GPIO_FUNC30_OEN_SEL (BIT(10)) 7955 #define GPIO_FUNC30_OEN_SEL_M (BIT(10)) 7956 #define GPIO_FUNC30_OEN_SEL_V 0x1 7957 #define GPIO_FUNC30_OEN_SEL_S 10 7958 /* GPIO_FUNC30_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ 7959 /*description: invert the output value if you want to revert the output value 7960 setting the value to 1*/ 7961 #define GPIO_FUNC30_OUT_INV_SEL (BIT(9)) 7962 #define GPIO_FUNC30_OUT_INV_SEL_M (BIT(9)) 7963 #define GPIO_FUNC30_OUT_INV_SEL_V 0x1 7964 #define GPIO_FUNC30_OUT_INV_SEL_S 9 7965 /* GPIO_FUNC30_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ 7966 /*description: select one of the 256 output to 40 GPIO*/ 7967 #define GPIO_FUNC30_OUT_SEL 0x000001FF 7968 #define GPIO_FUNC30_OUT_SEL_M ((GPIO_FUNC30_OUT_SEL_V)<<(GPIO_FUNC30_OUT_SEL_S)) 7969 #define GPIO_FUNC30_OUT_SEL_V 0x1FF 7970 #define GPIO_FUNC30_OUT_SEL_S 0 7971 7972 #define GPIO_FUNC31_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x05ac) 7973 /* GPIO_FUNC31_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ 7974 /*description: invert the output enable value if you want to revert the output 7975 enable value setting the value to 1*/ 7976 #define GPIO_FUNC31_OEN_INV_SEL (BIT(11)) 7977 #define GPIO_FUNC31_OEN_INV_SEL_M (BIT(11)) 7978 #define GPIO_FUNC31_OEN_INV_SEL_V 0x1 7979 #define GPIO_FUNC31_OEN_INV_SEL_S 11 7980 /* GPIO_FUNC31_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ 7981 /*description: weather using the logical oen signal or not using the value setting 7982 by the register*/ 7983 #define GPIO_FUNC31_OEN_SEL (BIT(10)) 7984 #define GPIO_FUNC31_OEN_SEL_M (BIT(10)) 7985 #define GPIO_FUNC31_OEN_SEL_V 0x1 7986 #define GPIO_FUNC31_OEN_SEL_S 10 7987 /* GPIO_FUNC31_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ 7988 /*description: invert the output value if you want to revert the output value 7989 setting the value to 1*/ 7990 #define GPIO_FUNC31_OUT_INV_SEL (BIT(9)) 7991 #define GPIO_FUNC31_OUT_INV_SEL_M (BIT(9)) 7992 #define GPIO_FUNC31_OUT_INV_SEL_V 0x1 7993 #define GPIO_FUNC31_OUT_INV_SEL_S 9 7994 /* GPIO_FUNC31_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ 7995 /*description: select one of the 256 output to 40 GPIO*/ 7996 #define GPIO_FUNC31_OUT_SEL 0x000001FF 7997 #define GPIO_FUNC31_OUT_SEL_M ((GPIO_FUNC31_OUT_SEL_V)<<(GPIO_FUNC31_OUT_SEL_S)) 7998 #define GPIO_FUNC31_OUT_SEL_V 0x1FF 7999 #define GPIO_FUNC31_OUT_SEL_S 0 8000 8001 #define GPIO_FUNC32_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x05b0) 8002 /* GPIO_FUNC32_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ 8003 /*description: invert the output enable value if you want to revert the output 8004 enable value setting the value to 1*/ 8005 #define GPIO_FUNC32_OEN_INV_SEL (BIT(11)) 8006 #define GPIO_FUNC32_OEN_INV_SEL_M (BIT(11)) 8007 #define GPIO_FUNC32_OEN_INV_SEL_V 0x1 8008 #define GPIO_FUNC32_OEN_INV_SEL_S 11 8009 /* GPIO_FUNC32_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ 8010 /*description: weather using the logical oen signal or not using the value setting 8011 by the register*/ 8012 #define GPIO_FUNC32_OEN_SEL (BIT(10)) 8013 #define GPIO_FUNC32_OEN_SEL_M (BIT(10)) 8014 #define GPIO_FUNC32_OEN_SEL_V 0x1 8015 #define GPIO_FUNC32_OEN_SEL_S 10 8016 /* GPIO_FUNC32_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ 8017 /*description: invert the output value if you want to revert the output value 8018 setting the value to 1*/ 8019 #define GPIO_FUNC32_OUT_INV_SEL (BIT(9)) 8020 #define GPIO_FUNC32_OUT_INV_SEL_M (BIT(9)) 8021 #define GPIO_FUNC32_OUT_INV_SEL_V 0x1 8022 #define GPIO_FUNC32_OUT_INV_SEL_S 9 8023 /* GPIO_FUNC32_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ 8024 /*description: select one of the 256 output to 40 GPIO*/ 8025 #define GPIO_FUNC32_OUT_SEL 0x000001FF 8026 #define GPIO_FUNC32_OUT_SEL_M ((GPIO_FUNC32_OUT_SEL_V)<<(GPIO_FUNC32_OUT_SEL_S)) 8027 #define GPIO_FUNC32_OUT_SEL_V 0x1FF 8028 #define GPIO_FUNC32_OUT_SEL_S 0 8029 8030 #define GPIO_FUNC33_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x05b4) 8031 /* GPIO_FUNC33_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ 8032 /*description: invert the output enable value if you want to revert the output 8033 enable value setting the value to 1*/ 8034 #define GPIO_FUNC33_OEN_INV_SEL (BIT(11)) 8035 #define GPIO_FUNC33_OEN_INV_SEL_M (BIT(11)) 8036 #define GPIO_FUNC33_OEN_INV_SEL_V 0x1 8037 #define GPIO_FUNC33_OEN_INV_SEL_S 11 8038 /* GPIO_FUNC33_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ 8039 /*description: weather using the logical oen signal or not using the value setting 8040 by the register*/ 8041 #define GPIO_FUNC33_OEN_SEL (BIT(10)) 8042 #define GPIO_FUNC33_OEN_SEL_M (BIT(10)) 8043 #define GPIO_FUNC33_OEN_SEL_V 0x1 8044 #define GPIO_FUNC33_OEN_SEL_S 10 8045 /* GPIO_FUNC33_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ 8046 /*description: invert the output value if you want to revert the output value 8047 setting the value to 1*/ 8048 #define GPIO_FUNC33_OUT_INV_SEL (BIT(9)) 8049 #define GPIO_FUNC33_OUT_INV_SEL_M (BIT(9)) 8050 #define GPIO_FUNC33_OUT_INV_SEL_V 0x1 8051 #define GPIO_FUNC33_OUT_INV_SEL_S 9 8052 /* GPIO_FUNC33_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ 8053 /*description: select one of the 256 output to 40 GPIO*/ 8054 #define GPIO_FUNC33_OUT_SEL 0x000001FF 8055 #define GPIO_FUNC33_OUT_SEL_M ((GPIO_FUNC33_OUT_SEL_V)<<(GPIO_FUNC33_OUT_SEL_S)) 8056 #define GPIO_FUNC33_OUT_SEL_V 0x1FF 8057 #define GPIO_FUNC33_OUT_SEL_S 0 8058 8059 #define GPIO_FUNC34_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x05b8) 8060 /* GPIO_FUNC34_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ 8061 /*description: invert the output enable value if you want to revert the output 8062 enable value setting the value to 1*/ 8063 #define GPIO_FUNC34_OEN_INV_SEL (BIT(11)) 8064 #define GPIO_FUNC34_OEN_INV_SEL_M (BIT(11)) 8065 #define GPIO_FUNC34_OEN_INV_SEL_V 0x1 8066 #define GPIO_FUNC34_OEN_INV_SEL_S 11 8067 /* GPIO_FUNC34_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ 8068 /*description: weather using the logical oen signal or not using the value setting 8069 by the register*/ 8070 #define GPIO_FUNC34_OEN_SEL (BIT(10)) 8071 #define GPIO_FUNC34_OEN_SEL_M (BIT(10)) 8072 #define GPIO_FUNC34_OEN_SEL_V 0x1 8073 #define GPIO_FUNC34_OEN_SEL_S 10 8074 /* GPIO_FUNC34_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ 8075 /*description: invert the output value if you want to revert the output value 8076 setting the value to 1*/ 8077 #define GPIO_FUNC34_OUT_INV_SEL (BIT(9)) 8078 #define GPIO_FUNC34_OUT_INV_SEL_M (BIT(9)) 8079 #define GPIO_FUNC34_OUT_INV_SEL_V 0x1 8080 #define GPIO_FUNC34_OUT_INV_SEL_S 9 8081 /* GPIO_FUNC34_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ 8082 /*description: select one of the 256 output to 40 GPIO*/ 8083 #define GPIO_FUNC34_OUT_SEL 0x000001FF 8084 #define GPIO_FUNC34_OUT_SEL_M ((GPIO_FUNC34_OUT_SEL_V)<<(GPIO_FUNC34_OUT_SEL_S)) 8085 #define GPIO_FUNC34_OUT_SEL_V 0x1FF 8086 #define GPIO_FUNC34_OUT_SEL_S 0 8087 8088 #define GPIO_FUNC35_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x05bc) 8089 /* GPIO_FUNC35_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ 8090 /*description: invert the output enable value if you want to revert the output 8091 enable value setting the value to 1*/ 8092 #define GPIO_FUNC35_OEN_INV_SEL (BIT(11)) 8093 #define GPIO_FUNC35_OEN_INV_SEL_M (BIT(11)) 8094 #define GPIO_FUNC35_OEN_INV_SEL_V 0x1 8095 #define GPIO_FUNC35_OEN_INV_SEL_S 11 8096 /* GPIO_FUNC35_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ 8097 /*description: weather using the logical oen signal or not using the value setting 8098 by the register*/ 8099 #define GPIO_FUNC35_OEN_SEL (BIT(10)) 8100 #define GPIO_FUNC35_OEN_SEL_M (BIT(10)) 8101 #define GPIO_FUNC35_OEN_SEL_V 0x1 8102 #define GPIO_FUNC35_OEN_SEL_S 10 8103 /* GPIO_FUNC35_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ 8104 /*description: invert the output value if you want to revert the output value 8105 setting the value to 1*/ 8106 #define GPIO_FUNC35_OUT_INV_SEL (BIT(9)) 8107 #define GPIO_FUNC35_OUT_INV_SEL_M (BIT(9)) 8108 #define GPIO_FUNC35_OUT_INV_SEL_V 0x1 8109 #define GPIO_FUNC35_OUT_INV_SEL_S 9 8110 /* GPIO_FUNC35_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ 8111 /*description: select one of the 256 output to 40 GPIO*/ 8112 #define GPIO_FUNC35_OUT_SEL 0x000001FF 8113 #define GPIO_FUNC35_OUT_SEL_M ((GPIO_FUNC35_OUT_SEL_V)<<(GPIO_FUNC35_OUT_SEL_S)) 8114 #define GPIO_FUNC35_OUT_SEL_V 0x1FF 8115 #define GPIO_FUNC35_OUT_SEL_S 0 8116 8117 #define GPIO_FUNC36_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x05c0) 8118 /* GPIO_FUNC36_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ 8119 /*description: invert the output enable value if you want to revert the output 8120 enable value setting the value to 1*/ 8121 #define GPIO_FUNC36_OEN_INV_SEL (BIT(11)) 8122 #define GPIO_FUNC36_OEN_INV_SEL_M (BIT(11)) 8123 #define GPIO_FUNC36_OEN_INV_SEL_V 0x1 8124 #define GPIO_FUNC36_OEN_INV_SEL_S 11 8125 /* GPIO_FUNC36_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ 8126 /*description: weather using the logical oen signal or not using the value setting 8127 by the register*/ 8128 #define GPIO_FUNC36_OEN_SEL (BIT(10)) 8129 #define GPIO_FUNC36_OEN_SEL_M (BIT(10)) 8130 #define GPIO_FUNC36_OEN_SEL_V 0x1 8131 #define GPIO_FUNC36_OEN_SEL_S 10 8132 /* GPIO_FUNC36_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ 8133 /*description: invert the output value if you want to revert the output value 8134 setting the value to 1*/ 8135 #define GPIO_FUNC36_OUT_INV_SEL (BIT(9)) 8136 #define GPIO_FUNC36_OUT_INV_SEL_M (BIT(9)) 8137 #define GPIO_FUNC36_OUT_INV_SEL_V 0x1 8138 #define GPIO_FUNC36_OUT_INV_SEL_S 9 8139 /* GPIO_FUNC36_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ 8140 /*description: select one of the 256 output to 40 GPIO*/ 8141 #define GPIO_FUNC36_OUT_SEL 0x000001FF 8142 #define GPIO_FUNC36_OUT_SEL_M ((GPIO_FUNC36_OUT_SEL_V)<<(GPIO_FUNC36_OUT_SEL_S)) 8143 #define GPIO_FUNC36_OUT_SEL_V 0x1FF 8144 #define GPIO_FUNC36_OUT_SEL_S 0 8145 8146 #define GPIO_FUNC37_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x05c4) 8147 /* GPIO_FUNC37_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ 8148 /*description: invert the output enable value if you want to revert the output 8149 enable value setting the value to 1*/ 8150 #define GPIO_FUNC37_OEN_INV_SEL (BIT(11)) 8151 #define GPIO_FUNC37_OEN_INV_SEL_M (BIT(11)) 8152 #define GPIO_FUNC37_OEN_INV_SEL_V 0x1 8153 #define GPIO_FUNC37_OEN_INV_SEL_S 11 8154 /* GPIO_FUNC37_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ 8155 /*description: weather using the logical oen signal or not using the value setting 8156 by the register*/ 8157 #define GPIO_FUNC37_OEN_SEL (BIT(10)) 8158 #define GPIO_FUNC37_OEN_SEL_M (BIT(10)) 8159 #define GPIO_FUNC37_OEN_SEL_V 0x1 8160 #define GPIO_FUNC37_OEN_SEL_S 10 8161 /* GPIO_FUNC37_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ 8162 /*description: invert the output value if you want to revert the output value 8163 setting the value to 1*/ 8164 #define GPIO_FUNC37_OUT_INV_SEL (BIT(9)) 8165 #define GPIO_FUNC37_OUT_INV_SEL_M (BIT(9)) 8166 #define GPIO_FUNC37_OUT_INV_SEL_V 0x1 8167 #define GPIO_FUNC37_OUT_INV_SEL_S 9 8168 /* GPIO_FUNC37_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ 8169 /*description: select one of the 256 output to 40 GPIO*/ 8170 #define GPIO_FUNC37_OUT_SEL 0x000001FF 8171 #define GPIO_FUNC37_OUT_SEL_M ((GPIO_FUNC37_OUT_SEL_V)<<(GPIO_FUNC37_OUT_SEL_S)) 8172 #define GPIO_FUNC37_OUT_SEL_V 0x1FF 8173 #define GPIO_FUNC37_OUT_SEL_S 0 8174 8175 #define GPIO_FUNC38_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x05c8) 8176 /* GPIO_FUNC38_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ 8177 /*description: invert the output enable value if you want to revert the output 8178 enable value setting the value to 1*/ 8179 #define GPIO_FUNC38_OEN_INV_SEL (BIT(11)) 8180 #define GPIO_FUNC38_OEN_INV_SEL_M (BIT(11)) 8181 #define GPIO_FUNC38_OEN_INV_SEL_V 0x1 8182 #define GPIO_FUNC38_OEN_INV_SEL_S 11 8183 /* GPIO_FUNC38_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ 8184 /*description: weather using the logical oen signal or not using the value setting 8185 by the register*/ 8186 #define GPIO_FUNC38_OEN_SEL (BIT(10)) 8187 #define GPIO_FUNC38_OEN_SEL_M (BIT(10)) 8188 #define GPIO_FUNC38_OEN_SEL_V 0x1 8189 #define GPIO_FUNC38_OEN_SEL_S 10 8190 /* GPIO_FUNC38_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ 8191 /*description: invert the output value if you want to revert the output value 8192 setting the value to 1*/ 8193 #define GPIO_FUNC38_OUT_INV_SEL (BIT(9)) 8194 #define GPIO_FUNC38_OUT_INV_SEL_M (BIT(9)) 8195 #define GPIO_FUNC38_OUT_INV_SEL_V 0x1 8196 #define GPIO_FUNC38_OUT_INV_SEL_S 9 8197 /* GPIO_FUNC38_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ 8198 /*description: select one of the 256 output to 40 GPIO*/ 8199 #define GPIO_FUNC38_OUT_SEL 0x000001FF 8200 #define GPIO_FUNC38_OUT_SEL_M ((GPIO_FUNC38_OUT_SEL_V)<<(GPIO_FUNC38_OUT_SEL_S)) 8201 #define GPIO_FUNC38_OUT_SEL_V 0x1FF 8202 #define GPIO_FUNC38_OUT_SEL_S 0 8203 8204 #define GPIO_FUNC39_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x05cc) 8205 /* GPIO_FUNC39_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ 8206 /*description: invert the output enable value if you want to revert the output 8207 enable value setting the value to 1*/ 8208 #define GPIO_FUNC39_OEN_INV_SEL (BIT(11)) 8209 #define GPIO_FUNC39_OEN_INV_SEL_M (BIT(11)) 8210 #define GPIO_FUNC39_OEN_INV_SEL_V 0x1 8211 #define GPIO_FUNC39_OEN_INV_SEL_S 11 8212 /* GPIO_FUNC39_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ 8213 /*description: weather using the logical oen signal or not using the value setting 8214 by the register*/ 8215 #define GPIO_FUNC39_OEN_SEL (BIT(10)) 8216 #define GPIO_FUNC39_OEN_SEL_M (BIT(10)) 8217 #define GPIO_FUNC39_OEN_SEL_V 0x1 8218 #define GPIO_FUNC39_OEN_SEL_S 10 8219 /* GPIO_FUNC39_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ 8220 /*description: invert the output value if you want to revert the output value 8221 setting the value to 1*/ 8222 #define GPIO_FUNC39_OUT_INV_SEL (BIT(9)) 8223 #define GPIO_FUNC39_OUT_INV_SEL_M (BIT(9)) 8224 #define GPIO_FUNC39_OUT_INV_SEL_V 0x1 8225 #define GPIO_FUNC39_OUT_INV_SEL_S 9 8226 /* GPIO_FUNC39_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ 8227 /*description: select one of the 256 output to 40 GPIO*/ 8228 #define GPIO_FUNC39_OUT_SEL 0x000001FF 8229 #define GPIO_FUNC39_OUT_SEL_M ((GPIO_FUNC39_OUT_SEL_V)<<(GPIO_FUNC39_OUT_SEL_S)) 8230 #define GPIO_FUNC39_OUT_SEL_V 0x1FF 8231 #define GPIO_FUNC39_OUT_SEL_S 0 8232 8233 8234 8235 8236 #endif /*_SOC_GPIO_REG_H_ */ 8237
