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Searched refs:DR_REG_RTC_I2C_BASE (Results 1 – 12 of 12) sorted by relevance

/hal_espressif-3.5.0/components/soc/esp32c3/include/soc/
Drtc_i2c_reg.h22 #define RTC_I2C_SCL_LOW_PERIOD_REG (DR_REG_RTC_I2C_BASE + 0x0000)
30 #define RTC_I2C_CTRL_REG (DR_REG_RTC_I2C_BASE + 0x0004)
86 #define RTC_I2C_STATUS_REG (DR_REG_RTC_I2C_BASE + 0x0008)
148 #define RTC_I2C_TIMEOUT_REG (DR_REG_RTC_I2C_BASE + 0x000c)
156 #define RTC_I2C_SLAVE_ADDR_REG (DR_REG_RTC_I2C_BASE + 0x0010)
170 #define RTC_I2C_SCL_HIGH_REG (DR_REG_RTC_I2C_BASE + 0x0014)
178 #define RTC_I2C_SDA_DUTY_REG (DR_REG_RTC_I2C_BASE + 0x0018)
186 #define RTC_I2C_SCL_START_PERIOD_REG (DR_REG_RTC_I2C_BASE + 0x001c)
194 #define RTC_I2C_SCL_STOP_PERIOD_REG (DR_REG_RTC_I2C_BASE + 0x0020)
202 #define RTC_I2C_INT_CLR_REG (DR_REG_RTC_I2C_BASE + 0x0024)
[all …]
Dsoc.h50 #define DR_REG_RTC_I2C_BASE 0x6000e000 macro
/hal_espressif-3.5.0/components/soc/esp32s2/include/soc/
Drtc_i2c_reg.h32 #define RTC_I2C_SCL_LOW_PERIOD_REG (DR_REG_RTC_I2C_BASE + 0x0000)
40 #define RTC_I2C_CTRL_REG (DR_REG_RTC_I2C_BASE + 0x0004)
96 #define RTC_I2C_STATUS_REG (DR_REG_RTC_I2C_BASE + 0x0008)
158 #define RTC_I2C_TIMEOUT_REG (DR_REG_RTC_I2C_BASE + 0x000c)
166 #define RTC_I2C_SLAVE_ADDR_REG (DR_REG_RTC_I2C_BASE + 0x0010)
180 #define RTC_I2C_SCL_HIGH_REG (DR_REG_RTC_I2C_BASE + 0x0014)
188 #define RTC_I2C_SDA_DUTY_REG (DR_REG_RTC_I2C_BASE + 0x0018)
196 #define RTC_I2C_SCL_START_PERIOD_REG (DR_REG_RTC_I2C_BASE + 0x001c)
204 #define RTC_I2C_SCL_STOP_PERIOD_REG (DR_REG_RTC_I2C_BASE + 0x0020)
212 #define RTC_I2C_INT_CLR_REG (DR_REG_RTC_I2C_BASE + 0x0024)
[all …]
Dsoc.h56 #define DR_REG_RTC_I2C_BASE 0x3f408C00 macro
/hal_espressif-3.5.0/components/soc/esp32h2/include/soc/
Drtc_i2c_reg.h22 #define RTC_I2C_SCL_LOW_PERIOD_REG (DR_REG_RTC_I2C_BASE + 0x0000)
30 #define RTC_I2C_CTRL_REG (DR_REG_RTC_I2C_BASE + 0x0004)
86 #define RTC_I2C_STATUS_REG (DR_REG_RTC_I2C_BASE + 0x0008)
148 #define RTC_I2C_TIMEOUT_REG (DR_REG_RTC_I2C_BASE + 0x000c)
156 #define RTC_I2C_SLAVE_ADDR_REG (DR_REG_RTC_I2C_BASE + 0x0010)
170 #define RTC_I2C_SCL_HIGH_REG (DR_REG_RTC_I2C_BASE + 0x0014)
178 #define RTC_I2C_SDA_DUTY_REG (DR_REG_RTC_I2C_BASE + 0x0018)
186 #define RTC_I2C_SCL_START_PERIOD_REG (DR_REG_RTC_I2C_BASE + 0x001c)
194 #define RTC_I2C_SCL_STOP_PERIOD_REG (DR_REG_RTC_I2C_BASE + 0x0020)
202 #define RTC_I2C_INT_CLR_REG (DR_REG_RTC_I2C_BASE + 0x0024)
[all …]
Dsoc.h58 #define DR_REG_RTC_I2C_BASE 0x60008C00 macro
/hal_espressif-3.5.0/components/soc/esp32/include/soc/
Drtc_i2c_reg.h28 #define RTC_I2C_SCL_LOW_PERIOD_REG (DR_REG_RTC_I2C_BASE + 0x000)
36 #define RTC_I2C_CTRL_REG (DR_REG_RTC_I2C_BASE + 0x004)
74 #define RTC_I2C_DEBUG_STATUS_REG (DR_REG_RTC_I2C_BASE + 0x008)
130 #define RTC_I2C_TIMEOUT_REG (DR_REG_RTC_I2C_BASE + 0x00c)
138 #define RTC_I2C_SLAVE_ADDR_REG (DR_REG_RTC_I2C_BASE + 0x010)
155 #define RTC_I2C_DATA_REG (DR_REG_RTC_I2C_BASE + 0x01c)
162 #define RTC_I2C_INT_RAW_REG (DR_REG_RTC_I2C_BASE + 0x020)
195 #define RTC_I2C_INT_CLR_REG (DR_REG_RTC_I2C_BASE + 0x024)
231 #define RTC_I2C_INT_EN_REG (DR_REG_RTC_I2C_BASE + 0x028)
237 #define RTC_I2C_INT_ST_REG (DR_REG_RTC_I2C_BASE + 0x02c)
[all …]
Dsoc.h49 #define DR_REG_RTC_I2C_BASE 0x3ff48C00 macro
/hal_espressif-3.5.0/components/soc/esp32s3/include/soc/
Dsoc.h42 #define DR_REG_RTC_I2C_BASE 0x60008C00 macro
/hal_espressif-3.5.0/components/ulp/include/esp32s2/
Dulp.h297 } else if (reg < DR_REG_RTC_I2C_BASE){ in SOC_REG_TO_ULP_PERIPH_SEL()
/hal_espressif-3.5.0/components/ulp/include/esp32s3/
Dulp.h298 } else if (reg < DR_REG_RTC_I2C_BASE) { in SOC_REG_TO_ULP_PERIPH_SEL()
/hal_espressif-3.5.0/components/ulp/include/esp32/
Dulp.h331 } else if (reg < DR_REG_RTC_I2C_BASE){ in SOC_REG_TO_ULP_PERIPH_SEL()