1 // Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 // 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 #ifndef _SOC_SYSTEM_REG_H_ 15 #define _SOC_SYSTEM_REG_H_ 16 17 18 #ifdef __cplusplus 19 extern "C" { 20 #endif 21 #include "soc.h" 22 #define DPORT_ROM_CTRL_0_REG (DR_REG_SYSTEM_BASE + 0x000) 23 /* DPORT_ROM_FO : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ 24 /*description: */ 25 #define DPORT_ROM_FO 0x00000003 26 #define DPORT_ROM_FO_M ((DPORT_ROM_FO_V)<<(DPORT_ROM_FO_S)) 27 #define DPORT_ROM_FO_V 0x3 28 #define DPORT_ROM_FO_S 0 29 30 #define DPORT_ROM_CTRL_1_REG (DR_REG_SYSTEM_BASE + 0x004) 31 /* DPORT_ROM_FORCE_PU : R/W ;bitpos:[3:2] ;default: 2'b11 ; */ 32 /*description: */ 33 #define DPORT_ROM_FORCE_PU 0x00000003 34 #define DPORT_ROM_FORCE_PU_M ((DPORT_ROM_FORCE_PU_V)<<(DPORT_ROM_FORCE_PU_S)) 35 #define DPORT_ROM_FORCE_PU_V 0x3 36 #define DPORT_ROM_FORCE_PU_S 2 37 /* DPORT_ROM_FORCE_PD : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ 38 /*description: */ 39 #define DPORT_ROM_FORCE_PD 0x00000003 40 #define DPORT_ROM_FORCE_PD_M ((DPORT_ROM_FORCE_PD_V)<<(DPORT_ROM_FORCE_PD_S)) 41 #define DPORT_ROM_FORCE_PD_V 0x3 42 #define DPORT_ROM_FORCE_PD_S 0 43 44 #define DPORT_SRAM_CTRL_0_REG (DR_REG_SYSTEM_BASE + 0x008) 45 /* DPORT_SRAM_FO : R/W ;bitpos:[21:0] ;default: ~22'b0 ; */ 46 /*description: */ 47 #define DPORT_SRAM_FO 0x003FFFFF 48 #define DPORT_SRAM_FO_M ((DPORT_SRAM_FO_V)<<(DPORT_SRAM_FO_S)) 49 #define DPORT_SRAM_FO_V 0x3FFFFF 50 #define DPORT_SRAM_FO_S 0 51 52 #define DPORT_SRAM_CTRL_1_REG (DR_REG_SYSTEM_BASE + 0x00C) 53 /* DPORT_SRAM_FORCE_PD : R/W ;bitpos:[21:0] ;default: 22'b0 ; */ 54 /*description: */ 55 #define DPORT_SRAM_FORCE_PD 0x003FFFFF 56 #define DPORT_SRAM_FORCE_PD_M ((DPORT_SRAM_FORCE_PD_V)<<(DPORT_SRAM_FORCE_PD_S)) 57 #define DPORT_SRAM_FORCE_PD_V 0x3FFFFF 58 #define DPORT_SRAM_FORCE_PD_S 0 59 60 #define DPORT_PERI_CLK_EN_REG DPORT_CPU_PERI_CLK_EN_REG 61 #define DPORT_CPU_PERI_CLK_EN_REG (DR_REG_SYSTEM_BASE + 0x010) 62 /* DPORT_CLK_EN_DEDICATED_GPIO : R/W ;bitpos:[7] ;default: 1'b0 ; */ 63 /*description: */ 64 #define DPORT_CLK_EN_DEDICATED_GPIO (BIT(7)) 65 #define DPORT_CLK_EN_DEDICATED_GPIO_M (BIT(7)) 66 #define DPORT_CLK_EN_DEDICATED_GPIO_V 0x1 67 #define DPORT_CLK_EN_DEDICATED_GPIO_S 7 68 /* DPORT_CLK_EN_ASSIST_DEBUG : R/W ;bitpos:[6] ;default: 1'b0 ; */ 69 /*description: */ 70 #define DPORT_CLK_EN_ASSIST_DEBUG (BIT(6)) 71 #define DPORT_CLK_EN_ASSIST_DEBUG_M (BIT(6)) 72 #define DPORT_CLK_EN_ASSIST_DEBUG_V 0x1 73 #define DPORT_CLK_EN_ASSIST_DEBUG_S 6 74 75 /* NB: Digital signature reset will hold AES & RSA in reset */ 76 #define DPORT_PERI_EN_ASSIST_DEBUG DPORT_CLK_EN_ASSIST_DEBUG 77 78 #define DPORT_PERI_RST_EN_REG DPORT_CPU_PERI_RST_EN_REG 79 #define DPORT_CPU_PERI_RST_EN_REG (DR_REG_SYSTEM_BASE + 0x014) 80 /* DPORT_RST_EN_DEDICATED_GPIO : R/W ;bitpos:[7] ;default: 1'b1 ; */ 81 /*description: */ 82 #define DPORT_RST_EN_DEDICATED_GPIO (BIT(7)) 83 #define DPORT_RST_EN_DEDICATED_GPIO_M (BIT(7)) 84 #define DPORT_RST_EN_DEDICATED_GPIO_V 0x1 85 #define DPORT_RST_EN_DEDICATED_GPIO_S 7 86 /* DPORT_RST_EN_ASSIST_DEBUG : R/W ;bitpos:[6] ;default: 1'b1 ; */ 87 /*description: */ 88 #define DPORT_RST_EN_ASSIST_DEBUG (BIT(6)) 89 #define DPORT_RST_EN_ASSIST_DEBUG_M (BIT(6)) 90 #define DPORT_RST_EN_ASSIST_DEBUG_V 0x1 91 #define DPORT_RST_EN_ASSIST_DEBUG_S 6 92 93 #define DPORT_CPU_PER_CONF_REG (DR_REG_SYSTEM_BASE + 0x018) 94 /* DPORT_CPU_WAITI_DELAY_NUM : R/W ;bitpos:[7:4] ;default: 4'h0 ; */ 95 /*description: */ 96 #define DPORT_CPU_WAITI_DELAY_NUM 0x0000000F 97 #define DPORT_CPU_WAITI_DELAY_NUM_M ((DPORT_CPU_WAITI_DELAY_NUM_V)<<(DPORT_CPU_WAITI_DELAY_NUM_S)) 98 #define DPORT_CPU_WAITI_DELAY_NUM_V 0xF 99 #define DPORT_CPU_WAITI_DELAY_NUM_S 4 100 /* DPORT_CPU_WAIT_MODE_FORCE_ON : R/W ;bitpos:[3] ;default: 1'b1 ; */ 101 /*description: */ 102 #define DPORT_CPU_WAIT_MODE_FORCE_ON (BIT(3)) 103 #define DPORT_CPU_WAIT_MODE_FORCE_ON_M (BIT(3)) 104 #define DPORT_CPU_WAIT_MODE_FORCE_ON_V 0x1 105 #define DPORT_CPU_WAIT_MODE_FORCE_ON_S 3 106 /* DPORT_PLL_FREQ_SEL : R/W ;bitpos:[2] ;default: 1'b1 ; */ 107 /*description: */ 108 #define DPORT_PLL_FREQ_SEL (BIT(2)) 109 #define DPORT_PLL_FREQ_SEL_M (BIT(2)) 110 #define DPORT_PLL_FREQ_SEL_V 0x1 111 #define DPORT_PLL_FREQ_SEL_S 2 112 /* DPORT_CPUPERIOD_SEL : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ 113 /*description: */ 114 #define DPORT_CPUPERIOD_SEL 0x00000003 115 #define DPORT_CPUPERIOD_SEL_M ((DPORT_CPUPERIOD_SEL_V)<<(DPORT_CPUPERIOD_SEL_S)) 116 #define DPORT_CPUPERIOD_SEL_V 0x3 117 #define DPORT_CPUPERIOD_SEL_S 0 118 119 #define DPORT_JTAG_CTRL_0_REG (DR_REG_SYSTEM_BASE + 0x01C) 120 /* DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_0 : WOR ;bitpos:[31:0] ;default: 32'b0 ; */ 121 /*description: */ 122 #define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_0 0xFFFFFFFF 123 #define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_0_M ((DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_0_V)<<(DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_0_S)) 124 #define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_0_V 0xFFFFFFFF 125 #define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_0_S 0 126 127 #define DPORT_JTAG_CTRL_1_REG (DR_REG_SYSTEM_BASE + 0x020) 128 /* DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_1 : WOR ;bitpos:[31:0] ;default: 32'b0 ; */ 129 /*description: */ 130 #define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_1 0xFFFFFFFF 131 #define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_1_M ((DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_1_V)<<(DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_1_S)) 132 #define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_1_V 0xFFFFFFFF 133 #define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_1_S 0 134 135 #define DPORT_JTAG_CTRL_2_REG (DR_REG_SYSTEM_BASE + 0x024) 136 /* DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_2 : WOR ;bitpos:[31:0] ;default: 32'b0 ; */ 137 /*description: */ 138 #define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_2 0xFFFFFFFF 139 #define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_2_M ((DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_2_V)<<(DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_2_S)) 140 #define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_2_V 0xFFFFFFFF 141 #define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_2_S 0 142 143 #define DPORT_JTAG_CTRL_3_REG (DR_REG_SYSTEM_BASE + 0x028) 144 /* DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_3 : WOR ;bitpos:[31:0] ;default: 32'b0 ; */ 145 /*description: */ 146 #define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_3 0xFFFFFFFF 147 #define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_3_M ((DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_3_V)<<(DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_3_S)) 148 #define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_3_V 0xFFFFFFFF 149 #define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_3_S 0 150 151 #define DPORT_JTAG_CTRL_4_REG (DR_REG_SYSTEM_BASE + 0x02C) 152 /* DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_4 : WOR ;bitpos:[31:0] ;default: 32'b0 ; */ 153 /*description: */ 154 #define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_4 0xFFFFFFFF 155 #define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_4_M ((DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_4_V)<<(DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_4_S)) 156 #define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_4_V 0xFFFFFFFF 157 #define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_4_S 0 158 159 #define DPORT_JTAG_CTRL_5_REG (DR_REG_SYSTEM_BASE + 0x030) 160 /* DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_5 : WOR ;bitpos:[31:0] ;default: 32'b0 ; */ 161 /*description: */ 162 #define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_5 0xFFFFFFFF 163 #define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_5_M ((DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_5_V)<<(DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_5_S)) 164 #define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_5_V 0xFFFFFFFF 165 #define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_5_S 0 166 167 #define DPORT_JTAG_CTRL_6_REG (DR_REG_SYSTEM_BASE + 0x034) 168 /* DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_6 : WOR ;bitpos:[31:0] ;default: 32'b0 ; */ 169 /*description: */ 170 #define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_6 0xFFFFFFFF 171 #define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_6_M ((DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_6_V)<<(DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_6_S)) 172 #define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_6_V 0xFFFFFFFF 173 #define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_6_S 0 174 175 #define DPORT_JTAG_CTRL_7_REG (DR_REG_SYSTEM_BASE + 0x038) 176 /* DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_7 : WOR ;bitpos:[31:0] ;default: 32'b0 ; */ 177 /*description: */ 178 #define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_7 0xFFFFFFFF 179 #define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_7_M ((DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_7_V)<<(DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_7_S)) 180 #define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_7_V 0xFFFFFFFF 181 #define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_7_S 0 182 183 #define DPORT_MEM_PD_MASK_REG (DR_REG_SYSTEM_BASE + 0x03C) 184 /* DPORT_LSLP_MEM_PD_MASK : R/W ;bitpos:[0] ;default: 1'b1 ; */ 185 /*description: */ 186 #define DPORT_LSLP_MEM_PD_MASK (BIT(0)) 187 #define DPORT_LSLP_MEM_PD_MASK_M (BIT(0)) 188 #define DPORT_LSLP_MEM_PD_MASK_V 0x1 189 #define DPORT_LSLP_MEM_PD_MASK_S 0 190 191 #define DPORT_PERIP_CLK_EN_REG DPORT_PERIP_CLK_EN0_REG 192 #define DPORT_PERIP_CLK_EN0_REG (DR_REG_SYSTEM_BASE + 0x040) 193 /* DPORT_ADC2_ARB_CLK_EN : R/W ;bitpos:[30] ;default: 1'b1 ; */ 194 /*description: */ 195 #define DPORT_ADC2_ARB_CLK_EN (BIT(30)) 196 #define DPORT_ADC2_ARB_CLK_EN_M (BIT(30)) 197 #define DPORT_ADC2_ARB_CLK_EN_V 0x1 198 #define DPORT_ADC2_ARB_CLK_EN_S 30 199 /* DPORT_SYSTIMER_CLK_EN : R/W ;bitpos:[29] ;default: 1'b1 ; */ 200 /*description: */ 201 #define DPORT_SYSTIMER_CLK_EN (BIT(29)) 202 #define DPORT_SYSTIMER_CLK_EN_M (BIT(29)) 203 #define DPORT_SYSTIMER_CLK_EN_V 0x1 204 #define DPORT_SYSTIMER_CLK_EN_S 29 205 /* DPORT_APB_SARADC_CLK_EN : R/W ;bitpos:[28] ;default: 1'b1 ; */ 206 /*description: */ 207 #define DPORT_APB_SARADC_CLK_EN (BIT(28)) 208 #define DPORT_APB_SARADC_CLK_EN_M (BIT(28)) 209 #define DPORT_APB_SARADC_CLK_EN_V 0x1 210 #define DPORT_APB_SARADC_CLK_EN_S 28 211 /* DPORT_SPI3_DMA_CLK_EN : R/W ;bitpos:[27] ;default: 1'b1 ; */ 212 /*description: */ 213 #define DPORT_SPI3_DMA_CLK_EN (BIT(27)) 214 #define DPORT_SPI3_DMA_CLK_EN_M (BIT(27)) 215 #define DPORT_SPI3_DMA_CLK_EN_V 0x1 216 #define DPORT_SPI3_DMA_CLK_EN_S 27 217 /* DPORT_PWM3_CLK_EN : R/W ;bitpos:[26] ;default: 1'b0 ; */ 218 /*description: */ 219 #define DPORT_PWM3_CLK_EN (BIT(26)) 220 #define DPORT_PWM3_CLK_EN_M (BIT(26)) 221 #define DPORT_PWM3_CLK_EN_V 0x1 222 #define DPORT_PWM3_CLK_EN_S 26 223 /* DPORT_PWM2_CLK_EN : R/W ;bitpos:[25] ;default: 1'b0 ; */ 224 /*description: */ 225 #define DPORT_PWM2_CLK_EN (BIT(25)) 226 #define DPORT_PWM2_CLK_EN_M (BIT(25)) 227 #define DPORT_PWM2_CLK_EN_V 0x1 228 #define DPORT_PWM2_CLK_EN_S 25 229 /* DPORT_UART_MEM_CLK_EN : R/W ;bitpos:[24] ;default: 1'b1 ; */ 230 /*description: */ 231 #define DPORT_UART_MEM_CLK_EN (BIT(24)) 232 #define DPORT_UART_MEM_CLK_EN_M (BIT(24)) 233 #define DPORT_UART_MEM_CLK_EN_V 0x1 234 #define DPORT_UART_MEM_CLK_EN_S 24 235 /* DPORT_USB_CLK_EN : R/W ;bitpos:[23] ;default: 1'b1 ; */ 236 /*description: */ 237 #define DPORT_USB_CLK_EN (BIT(23)) 238 #define DPORT_USB_CLK_EN_M (BIT(23)) 239 #define DPORT_USB_CLK_EN_V 0x1 240 #define DPORT_USB_CLK_EN_S 23 241 /* DPORT_SPI2_DMA_CLK_EN : R/W ;bitpos:[22] ;default: 1'b1 ; */ 242 /*description: */ 243 #define DPORT_SPI2_DMA_CLK_EN (BIT(22)) 244 #define DPORT_SPI2_DMA_CLK_EN_M (BIT(22)) 245 #define DPORT_SPI2_DMA_CLK_EN_V 0x1 246 #define DPORT_SPI2_DMA_CLK_EN_S 22 247 /* DPORT_I2S1_CLK_EN : R/W ;bitpos:[21] ;default: 1'b0 ; */ 248 /*description: */ 249 #define DPORT_I2S1_CLK_EN (BIT(21)) 250 #define DPORT_I2S1_CLK_EN_M (BIT(21)) 251 #define DPORT_I2S1_CLK_EN_V 0x1 252 #define DPORT_I2S1_CLK_EN_S 21 253 /* DPORT_PWM1_CLK_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */ 254 /*description: */ 255 #define DPORT_PWM1_CLK_EN (BIT(20)) 256 #define DPORT_PWM1_CLK_EN_M (BIT(20)) 257 #define DPORT_PWM1_CLK_EN_V 0x1 258 #define DPORT_PWM1_CLK_EN_S 20 259 /* DPORT_TWAI_CLK_EN : R/W ;bitpos:[19] ;default: 1'b0 ; */ 260 /*description: */ 261 #define DPORT_TWAI_CLK_EN (BIT(19)) 262 #define DPORT_TWAI_CLK_EN_M (BIT(19)) 263 #define DPORT_TWAI_CLK_EN_V 0x1 264 #define DPORT_TWAI_CLK_EN_S 19 265 /* DPORT_I2C_EXT1_CLK_EN : R/W ;bitpos:[18] ;default: 1'b0 ; */ 266 /*description: */ 267 #define DPORT_I2C_EXT1_CLK_EN (BIT(18)) 268 #define DPORT_I2C_EXT1_CLK_EN_M (BIT(18)) 269 #define DPORT_I2C_EXT1_CLK_EN_V 0x1 270 #define DPORT_I2C_EXT1_CLK_EN_S 18 271 /* DPORT_PWM0_CLK_EN : R/W ;bitpos:[17] ;default: 1'b0 ; */ 272 /*description: */ 273 #define DPORT_PWM0_CLK_EN (BIT(17)) 274 #define DPORT_PWM0_CLK_EN_M (BIT(17)) 275 #define DPORT_PWM0_CLK_EN_V 0x1 276 #define DPORT_PWM0_CLK_EN_S 17 277 /* DPORT_SPI3_CLK_EN : R/W ;bitpos:[16] ;default: 1'b1 ; */ 278 /*description: */ 279 #define DPORT_SPI3_CLK_EN (BIT(16)) 280 #define DPORT_SPI3_CLK_EN_M (BIT(16)) 281 #define DPORT_SPI3_CLK_EN_V 0x1 282 #define DPORT_SPI3_CLK_EN_S 16 283 /* DPORT_TIMERGROUP1_CLK_EN : R/W ;bitpos:[15] ;default: 1'b1 ; */ 284 /*description: */ 285 #define DPORT_TIMERGROUP1_CLK_EN (BIT(15)) 286 #define DPORT_TIMERGROUP1_CLK_EN_M (BIT(15)) 287 #define DPORT_TIMERGROUP1_CLK_EN_V 0x1 288 #define DPORT_TIMERGROUP1_CLK_EN_S 15 289 /* DPORT_EFUSE_CLK_EN : R/W ;bitpos:[14] ;default: 1'b1 ; */ 290 /*description: */ 291 #define DPORT_EFUSE_CLK_EN (BIT(14)) 292 #define DPORT_EFUSE_CLK_EN_M (BIT(14)) 293 #define DPORT_EFUSE_CLK_EN_V 0x1 294 #define DPORT_EFUSE_CLK_EN_S 14 295 /* DPORT_TIMERGROUP_CLK_EN : R/W ;bitpos:[13] ;default: 1'b1 ; */ 296 /*description: */ 297 #define DPORT_TIMERGROUP_CLK_EN (BIT(13)) 298 #define DPORT_TIMERGROUP_CLK_EN_M (BIT(13)) 299 #define DPORT_TIMERGROUP_CLK_EN_V 0x1 300 #define DPORT_TIMERGROUP_CLK_EN_S 13 301 /* DPORT_UHCI1_CLK_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */ 302 /*description: */ 303 #define DPORT_UHCI1_CLK_EN (BIT(12)) 304 #define DPORT_UHCI1_CLK_EN_M (BIT(12)) 305 #define DPORT_UHCI1_CLK_EN_V 0x1 306 #define DPORT_UHCI1_CLK_EN_S 12 307 /* DPORT_LEDC_CLK_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */ 308 /*description: */ 309 #define DPORT_LEDC_CLK_EN (BIT(11)) 310 #define DPORT_LEDC_CLK_EN_M (BIT(11)) 311 #define DPORT_LEDC_CLK_EN_V 0x1 312 #define DPORT_LEDC_CLK_EN_S 11 313 /* DPORT_PCNT_CLK_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ 314 /*description: */ 315 #define DPORT_PCNT_CLK_EN (BIT(10)) 316 #define DPORT_PCNT_CLK_EN_M (BIT(10)) 317 #define DPORT_PCNT_CLK_EN_V 0x1 318 #define DPORT_PCNT_CLK_EN_S 10 319 /* DPORT_RMT_CLK_EN : R/W ;bitpos:[9] ;default: 1'b0 ; */ 320 /*description: */ 321 #define DPORT_RMT_CLK_EN (BIT(9)) 322 #define DPORT_RMT_CLK_EN_M (BIT(9)) 323 #define DPORT_RMT_CLK_EN_V 0x1 324 #define DPORT_RMT_CLK_EN_S 9 325 /* DPORT_UHCI0_CLK_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */ 326 /*description: */ 327 #define DPORT_UHCI0_CLK_EN (BIT(8)) 328 #define DPORT_UHCI0_CLK_EN_M (BIT(8)) 329 #define DPORT_UHCI0_CLK_EN_V 0x1 330 #define DPORT_UHCI0_CLK_EN_S 8 331 /* DPORT_I2C_EXT0_CLK_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */ 332 /*description: */ 333 #define DPORT_I2C_EXT0_CLK_EN (BIT(7)) 334 #define DPORT_I2C_EXT0_CLK_EN_M (BIT(7)) 335 #define DPORT_I2C_EXT0_CLK_EN_V 0x1 336 #define DPORT_I2C_EXT0_CLK_EN_S 7 337 /* DPORT_SPI2_CLK_EN : R/W ;bitpos:[6] ;default: 1'b1 ; */ 338 /*description: */ 339 #define DPORT_SPI2_CLK_EN (BIT(6)) 340 #define DPORT_SPI2_CLK_EN_M (BIT(6)) 341 #define DPORT_SPI2_CLK_EN_V 0x1 342 #define DPORT_SPI2_CLK_EN_S 6 343 /* DPORT_UART1_CLK_EN : R/W ;bitpos:[5] ;default: 1'b1 ; */ 344 /*description: */ 345 #define DPORT_UART1_CLK_EN (BIT(5)) 346 #define DPORT_UART1_CLK_EN_M (BIT(5)) 347 #define DPORT_UART1_CLK_EN_V 0x1 348 #define DPORT_UART1_CLK_EN_S 5 349 /* DPORT_I2S0_CLK_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */ 350 /*description: */ 351 #define DPORT_I2S0_CLK_EN (BIT(4)) 352 #define DPORT_I2S0_CLK_EN_M (BIT(4)) 353 #define DPORT_I2S0_CLK_EN_V 0x1 354 #define DPORT_I2S0_CLK_EN_S 4 355 /* DPORT_WDG_CLK_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */ 356 /*description: */ 357 #define DPORT_WDG_CLK_EN (BIT(3)) 358 #define DPORT_WDG_CLK_EN_M (BIT(3)) 359 #define DPORT_WDG_CLK_EN_V 0x1 360 #define DPORT_WDG_CLK_EN_S 3 361 /* DPORT_UART_CLK_EN : R/W ;bitpos:[2] ;default: 1'b1 ; */ 362 /*description: */ 363 #define DPORT_UART_CLK_EN (BIT(2)) 364 #define DPORT_UART_CLK_EN_M (BIT(2)) 365 #define DPORT_UART_CLK_EN_V 0x1 366 #define DPORT_UART_CLK_EN_S 2 367 /* DPORT_SPI01_CLK_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */ 368 /*description: */ 369 #define DPORT_SPI01_CLK_EN (BIT(1)) 370 #define DPORT_SPI01_CLK_EN_M (BIT(1)) 371 #define DPORT_SPI01_CLK_EN_V 0x1 372 #define DPORT_SPI01_CLK_EN_S 1 373 /* DPORT_TIMERS_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ 374 /*description: */ 375 #define DPORT_TIMERS_CLK_EN (BIT(0)) 376 #define DPORT_TIMERS_CLK_EN_M (BIT(0)) 377 #define DPORT_TIMERS_CLK_EN_V 0x1 378 #define DPORT_TIMERS_CLK_EN_S 0 379 380 #define DPORT_CPU_PERIP_CLK_EN1_REG DPORT_PERIP_CLK_EN1_REG 381 #define DPORT_PERIP_CLK_EN1_REG (DR_REG_SYSTEM_BASE + 0x044) 382 /* DPORT_CRYPTO_DMA_CLK_EN : R/W ;bitpos:[6] ;default: 1'b0 ; */ 383 /*description: */ 384 #define DPORT_CRYPTO_DMA_CLK_EN (BIT(6)) 385 #define DPORT_CRYPTO_DMA_CLK_EN_M (BIT(6)) 386 #define DPORT_CRYPTO_DMA_CLK_EN_V 0x1 387 #define DPORT_CRYPTO_DMA_CLK_EN_S 6 388 /* DPORT_CRYPTO_HMAC_CLK_EN : R/W ;bitpos:[5] ;default: 1'b0 ; */ 389 /*description: */ 390 #define DPORT_CRYPTO_HMAC_CLK_EN (BIT(5)) 391 #define DPORT_CRYPTO_HMAC_CLK_EN_M (BIT(5)) 392 #define DPORT_CRYPTO_HMAC_CLK_EN_V 0x1 393 #define DPORT_CRYPTO_HMAC_CLK_EN_S 5 394 /* DPORT_CRYPTO_DS_CLK_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */ 395 /*description: */ 396 #define DPORT_CRYPTO_DS_CLK_EN (BIT(4)) 397 #define DPORT_CRYPTO_DS_CLK_EN_M (BIT(4)) 398 #define DPORT_CRYPTO_DS_CLK_EN_V 0x1 399 #define DPORT_CRYPTO_DS_CLK_EN_S 4 400 /* DPORT_CRYPTO_RSA_CLK_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */ 401 /*description: */ 402 #define DPORT_CRYPTO_RSA_CLK_EN (BIT(3)) 403 #define DPORT_CRYPTO_RSA_CLK_EN_M (BIT(3)) 404 #define DPORT_CRYPTO_RSA_CLK_EN_V 0x1 405 #define DPORT_CRYPTO_RSA_CLK_EN_S 3 406 /* DPORT_CRYPTO_SHA_CLK_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */ 407 /*description: */ 408 #define DPORT_CRYPTO_SHA_CLK_EN (BIT(2)) 409 #define DPORT_CRYPTO_SHA_CLK_EN_M (BIT(2)) 410 #define DPORT_CRYPTO_SHA_CLK_EN_V 0x1 411 #define DPORT_CRYPTO_SHA_CLK_EN_S 2 412 /* DPORT_CRYPTO_AES_CLK_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */ 413 /*description: */ 414 #define DPORT_CRYPTO_AES_CLK_EN (BIT(1)) 415 #define DPORT_CRYPTO_AES_CLK_EN_M (BIT(1)) 416 #define DPORT_CRYPTO_AES_CLK_EN_V 0x1 417 #define DPORT_CRYPTO_AES_CLK_EN_S 1 418 419 #define DPORT_PERIP_RST_EN_REG DPORT_PERIP_RST_EN0_REG 420 #define DPORT_PERIP_RST_EN0_REG (DR_REG_SYSTEM_BASE + 0x048) 421 /* DPORT_ADC2_ARB_RST : R/W ;bitpos:[30] ;default: 1'b0 ; */ 422 /*description: */ 423 #define DPORT_ADC2_ARB_RST (BIT(30)) 424 #define DPORT_ADC2_ARB_RST_M (BIT(30)) 425 #define DPORT_ADC2_ARB_RST_V 0x1 426 #define DPORT_ADC2_ARB_RST_S 30 427 /* DPORT_SYSTIMER_RST : R/W ;bitpos:[29] ;default: 1'b0 ; */ 428 /*description: */ 429 #define DPORT_SYSTIMER_RST (BIT(29)) 430 #define DPORT_SYSTIMER_RST_M (BIT(29)) 431 #define DPORT_SYSTIMER_RST_V 0x1 432 #define DPORT_SYSTIMER_RST_S 29 433 /* DPORT_APB_SARADC_RST : R/W ;bitpos:[28] ;default: 1'b0 ; */ 434 /*description: */ 435 #define DPORT_APB_SARADC_RST (BIT(28)) 436 #define DPORT_APB_SARADC_RST_M (BIT(28)) 437 #define DPORT_APB_SARADC_RST_V 0x1 438 #define DPORT_APB_SARADC_RST_S 28 439 /* DPORT_SPI3_DMA_RST : R/W ;bitpos:[27] ;default: 1'b0 ; */ 440 /*description: */ 441 #define DPORT_SPI3_DMA_RST (BIT(27)) 442 #define DPORT_SPI3_DMA_RST_M (BIT(27)) 443 #define DPORT_SPI3_DMA_RST_V 0x1 444 #define DPORT_SPI3_DMA_RST_S 27 445 /* DPORT_PWM3_RST : R/W ;bitpos:[26] ;default: 1'b0 ; */ 446 /*description: */ 447 #define DPORT_PWM3_RST (BIT(26)) 448 #define DPORT_PWM3_RST_M (BIT(26)) 449 #define DPORT_PWM3_RST_V 0x1 450 #define DPORT_PWM3_RST_S 26 451 /* DPORT_PWM2_RST : R/W ;bitpos:[25] ;default: 1'b0 ; */ 452 /*description: */ 453 #define DPORT_PWM2_RST (BIT(25)) 454 #define DPORT_PWM2_RST_M (BIT(25)) 455 #define DPORT_PWM2_RST_V 0x1 456 #define DPORT_PWM2_RST_S 25 457 /* DPORT_UART_MEM_RST : R/W ;bitpos:[24] ;default: 1'b0 ; */ 458 /*description: */ 459 #define DPORT_UART_MEM_RST (BIT(24)) 460 #define DPORT_UART_MEM_RST_M (BIT(24)) 461 #define DPORT_UART_MEM_RST_V 0x1 462 #define DPORT_UART_MEM_RST_S 24 463 /* DPORT_USB_RST : R/W ;bitpos:[23] ;default: 1'b0 ; */ 464 /*description: */ 465 #define DPORT_USB_RST (BIT(23)) 466 #define DPORT_USB_RST_M (BIT(23)) 467 #define DPORT_USB_RST_V 0x1 468 #define DPORT_USB_RST_S 23 469 /* DPORT_SPI2_DMA_RST : R/W ;bitpos:[22] ;default: 1'b0 ; */ 470 /*description: */ 471 #define DPORT_SPI2_DMA_RST (BIT(22)) 472 #define DPORT_SPI2_DMA_RST_M (BIT(22)) 473 #define DPORT_SPI2_DMA_RST_V 0x1 474 #define DPORT_SPI2_DMA_RST_S 22 475 /* DPORT_I2S1_RST : R/W ;bitpos:[21] ;default: 1'b0 ; */ 476 /*description: */ 477 #define DPORT_I2S1_RST (BIT(21)) 478 #define DPORT_I2S1_RST_M (BIT(21)) 479 #define DPORT_I2S1_RST_V 0x1 480 #define DPORT_I2S1_RST_S 21 481 /* DPORT_PWM1_RST : R/W ;bitpos:[20] ;default: 1'b0 ; */ 482 /*description: */ 483 #define DPORT_PWM1_RST (BIT(20)) 484 #define DPORT_PWM1_RST_M (BIT(20)) 485 #define DPORT_PWM1_RST_V 0x1 486 #define DPORT_PWM1_RST_S 20 487 /* DPORT_TWAI_RST : R/W ;bitpos:[19] ;default: 1'b0 ; */ 488 /*description: */ 489 #define DPORT_TWAI_RST (BIT(19)) 490 #define DPORT_TWAI_RST_M (BIT(19)) 491 #define DPORT_TWAI_RST_V 0x1 492 #define DPORT_TWAI_RST_S 19 493 /* DPORT_I2C_EXT1_RST : R/W ;bitpos:[18] ;default: 1'b0 ; */ 494 /*description: */ 495 #define DPORT_I2C_EXT1_RST (BIT(18)) 496 #define DPORT_I2C_EXT1_RST_M (BIT(18)) 497 #define DPORT_I2C_EXT1_RST_V 0x1 498 #define DPORT_I2C_EXT1_RST_S 18 499 /* DPORT_PWM0_RST : R/W ;bitpos:[17] ;default: 1'b0 ; */ 500 /*description: */ 501 #define DPORT_PWM0_RST (BIT(17)) 502 #define DPORT_PWM0_RST_M (BIT(17)) 503 #define DPORT_PWM0_RST_V 0x1 504 #define DPORT_PWM0_RST_S 17 505 /* DPORT_SPI3_RST : R/W ;bitpos:[16] ;default: 1'b0 ; */ 506 /*description: */ 507 #define DPORT_SPI3_RST (BIT(16)) 508 #define DPORT_SPI3_RST_M (BIT(16)) 509 #define DPORT_SPI3_RST_V 0x1 510 #define DPORT_SPI3_RST_S 16 511 /* DPORT_TIMERGROUP1_RST : R/W ;bitpos:[15] ;default: 1'b0 ; */ 512 /*description: */ 513 #define DPORT_TIMERGROUP1_RST (BIT(15)) 514 #define DPORT_TIMERGROUP1_RST_M (BIT(15)) 515 #define DPORT_TIMERGROUP1_RST_V 0x1 516 #define DPORT_TIMERGROUP1_RST_S 15 517 /* DPORT_EFUSE_RST : R/W ;bitpos:[14] ;default: 1'b0 ; */ 518 /*description: */ 519 #define DPORT_EFUSE_RST (BIT(14)) 520 #define DPORT_EFUSE_RST_M (BIT(14)) 521 #define DPORT_EFUSE_RST_V 0x1 522 #define DPORT_EFUSE_RST_S 14 523 /* DPORT_TIMERGROUP_RST : R/W ;bitpos:[13] ;default: 1'b0 ; */ 524 /*description: */ 525 #define DPORT_TIMERGROUP_RST (BIT(13)) 526 #define DPORT_TIMERGROUP_RST_M (BIT(13)) 527 #define DPORT_TIMERGROUP_RST_V 0x1 528 #define DPORT_TIMERGROUP_RST_S 13 529 /* DPORT_UHCI1_RST : R/W ;bitpos:[12] ;default: 1'b0 ; */ 530 /*description: */ 531 #define DPORT_UHCI1_RST (BIT(12)) 532 #define DPORT_UHCI1_RST_M (BIT(12)) 533 #define DPORT_UHCI1_RST_V 0x1 534 #define DPORT_UHCI1_RST_S 12 535 /* DPORT_LEDC_RST : R/W ;bitpos:[11] ;default: 1'b0 ; */ 536 /*description: */ 537 #define DPORT_LEDC_RST (BIT(11)) 538 #define DPORT_LEDC_RST_M (BIT(11)) 539 #define DPORT_LEDC_RST_V 0x1 540 #define DPORT_LEDC_RST_S 11 541 /* DPORT_PCNT_RST : R/W ;bitpos:[10] ;default: 1'b0 ; */ 542 /*description: */ 543 #define DPORT_PCNT_RST (BIT(10)) 544 #define DPORT_PCNT_RST_M (BIT(10)) 545 #define DPORT_PCNT_RST_V 0x1 546 #define DPORT_PCNT_RST_S 10 547 /* DPORT_RMT_RST : R/W ;bitpos:[9] ;default: 1'b0 ; */ 548 /*description: */ 549 #define DPORT_RMT_RST (BIT(9)) 550 #define DPORT_RMT_RST_M (BIT(9)) 551 #define DPORT_RMT_RST_V 0x1 552 #define DPORT_RMT_RST_S 9 553 /* DPORT_UHCI0_RST : R/W ;bitpos:[8] ;default: 1'b0 ; */ 554 /*description: */ 555 #define DPORT_UHCI0_RST (BIT(8)) 556 #define DPORT_UHCI0_RST_M (BIT(8)) 557 #define DPORT_UHCI0_RST_V 0x1 558 #define DPORT_UHCI0_RST_S 8 559 /* DPORT_I2C_EXT0_RST : R/W ;bitpos:[7] ;default: 1'b0 ; */ 560 /*description: */ 561 #define DPORT_I2C_EXT0_RST (BIT(7)) 562 #define DPORT_I2C_EXT0_RST_M (BIT(7)) 563 #define DPORT_I2C_EXT0_RST_V 0x1 564 #define DPORT_I2C_EXT0_RST_S 7 565 /* DPORT_SPI2_RST : R/W ;bitpos:[6] ;default: 1'b0 ; */ 566 /*description: */ 567 #define DPORT_SPI2_RST (BIT(6)) 568 #define DPORT_SPI2_RST_M (BIT(6)) 569 #define DPORT_SPI2_RST_V 0x1 570 #define DPORT_SPI2_RST_S 6 571 /* DPORT_UART1_RST : R/W ;bitpos:[5] ;default: 1'b0 ; */ 572 /*description: */ 573 #define DPORT_UART1_RST (BIT(5)) 574 #define DPORT_UART1_RST_M (BIT(5)) 575 #define DPORT_UART1_RST_V 0x1 576 #define DPORT_UART1_RST_S 5 577 /* DPORT_I2S0_RST : R/W ;bitpos:[4] ;default: 1'b0 ; */ 578 /*description: */ 579 #define DPORT_I2S0_RST (BIT(4)) 580 #define DPORT_I2S0_RST_M (BIT(4)) 581 #define DPORT_I2S0_RST_V 0x1 582 #define DPORT_I2S0_RST_S 4 583 /* DPORT_WDG_RST : R/W ;bitpos:[3] ;default: 1'b0 ; */ 584 /*description: */ 585 #define DPORT_WDG_RST (BIT(3)) 586 #define DPORT_WDG_RST_M (BIT(3)) 587 #define DPORT_WDG_RST_V 0x1 588 #define DPORT_WDG_RST_S 3 589 /* DPORT_UART_RST : R/W ;bitpos:[2] ;default: 1'b0 ; */ 590 /*description: */ 591 #define DPORT_UART_RST (BIT(2)) 592 #define DPORT_UART_RST_M (BIT(2)) 593 #define DPORT_UART_RST_V 0x1 594 #define DPORT_UART_RST_S 2 595 /* DPORT_SPI01_RST : R/W ;bitpos:[1] ;default: 1'b0 ; */ 596 /*description: */ 597 #define DPORT_SPI01_RST (BIT(1)) 598 #define DPORT_SPI01_RST_M (BIT(1)) 599 #define DPORT_SPI01_RST_V 0x1 600 #define DPORT_SPI01_RST_S 1 601 /* DPORT_TIMERS_RST : R/W ;bitpos:[0] ;default: 1'b0 ; */ 602 /*description: */ 603 #define DPORT_TIMERS_RST (BIT(0)) 604 #define DPORT_TIMERS_RST_M (BIT(0)) 605 #define DPORT_TIMERS_RST_V 0x1 606 #define DPORT_TIMERS_RST_S 0 607 608 #define DPORT_CPU_PERIP_RST_EN1_REG DPORT_PERIP_RST_EN1_REG 609 #define DPORT_PERIP_RST_EN1_REG (DR_REG_SYSTEM_BASE + 0x04C) 610 /* DPORT_CRYPTO_DMA_RST : R/W ;bitpos:[6] ;default: 1'b1 ; */ 611 /*description: */ 612 #define DPORT_CRYPTO_DMA_RST (BIT(6)) 613 #define DPORT_CRYPTO_DMA_RST_M (BIT(6)) 614 #define DPORT_CRYPTO_DMA_RST_V 0x1 615 #define DPORT_CRYPTO_DMA_RST_S 6 616 /* DPORT_CRYPTO_HMAC_RST : R/W ;bitpos:[5] ;default: 1'b1 ; */ 617 /*description: */ 618 #define DPORT_CRYPTO_HMAC_RST (BIT(5)) 619 #define DPORT_CRYPTO_HMAC_RST_M (BIT(5)) 620 #define DPORT_CRYPTO_HMAC_RST_V 0x1 621 #define DPORT_CRYPTO_HMAC_RST_S 5 622 /* DPORT_CRYPTO_DS_RST : R/W ;bitpos:[4] ;default: 1'b1 ; */ 623 /*description: */ 624 #define DPORT_CRYPTO_DS_RST (BIT(4)) 625 #define DPORT_CRYPTO_DS_RST_M (BIT(4)) 626 #define DPORT_CRYPTO_DS_RST_V 0x1 627 #define DPORT_CRYPTO_DS_RST_S 4 628 /* DPORT_CRYPTO_RSA_RST : R/W ;bitpos:[3] ;default: 1'b1 ; */ 629 /*description: */ 630 #define DPORT_CRYPTO_RSA_RST (BIT(3)) 631 #define DPORT_CRYPTO_RSA_RST_M (BIT(3)) 632 #define DPORT_CRYPTO_RSA_RST_V 0x1 633 #define DPORT_CRYPTO_RSA_RST_S 3 634 /* DPORT_CRYPTO_SHA_RST : R/W ;bitpos:[2] ;default: 1'b1 ; */ 635 /*description: */ 636 #define DPORT_CRYPTO_SHA_RST (BIT(2)) 637 #define DPORT_CRYPTO_SHA_RST_M (BIT(2)) 638 #define DPORT_CRYPTO_SHA_RST_V 0x1 639 #define DPORT_CRYPTO_SHA_RST_S 2 640 /* DPORT_CRYPTO_AES_RST : R/W ;bitpos:[1] ;default: 1'b1 ; */ 641 /*description: */ 642 #define DPORT_CRYPTO_AES_RST (BIT(1)) 643 #define DPORT_CRYPTO_AES_RST_M (BIT(1)) 644 #define DPORT_CRYPTO_AES_RST_V 0x1 645 #define DPORT_CRYPTO_AES_RST_S 1 646 647 #define DPORT_BT_LPCK_DIV_INT_REG (DR_REG_SYSTEM_BASE + 0x050) 648 /* DPORT_BT_LPCK_DIV_NUM : R/W ;bitpos:[11:0] ;default: 12'd255 ; */ 649 /*description: */ 650 #define DPORT_BT_LPCK_DIV_NUM 0x00000FFF 651 #define DPORT_BT_LPCK_DIV_NUM_M ((DPORT_BT_LPCK_DIV_NUM_V)<<(DPORT_BT_LPCK_DIV_NUM_S)) 652 #define DPORT_BT_LPCK_DIV_NUM_V 0xFFF 653 #define DPORT_BT_LPCK_DIV_NUM_S 0 654 655 #define DPORT_BT_LPCK_DIV_FRAC_REG (DR_REG_SYSTEM_BASE + 0x054) 656 /* DPORT_LPCLK_RTC_EN : R/W ;bitpos:[28] ;default: 1'b0 ; */ 657 /*description: */ 658 #define DPORT_LPCLK_RTC_EN (BIT(28)) 659 #define DPORT_LPCLK_RTC_EN_M (BIT(28)) 660 #define DPORT_LPCLK_RTC_EN_V 0x1 661 #define DPORT_LPCLK_RTC_EN_S 28 662 /* DPORT_LPCLK_SEL_XTAL32K : R/W ;bitpos:[27] ;default: 1'b0 ; */ 663 /*description: */ 664 #define DPORT_LPCLK_SEL_XTAL32K (BIT(27)) 665 #define DPORT_LPCLK_SEL_XTAL32K_M (BIT(27)) 666 #define DPORT_LPCLK_SEL_XTAL32K_V 0x1 667 #define DPORT_LPCLK_SEL_XTAL32K_S 27 668 /* DPORT_LPCLK_SEL_XTAL : R/W ;bitpos:[26] ;default: 1'b0 ; */ 669 /*description: */ 670 #define DPORT_LPCLK_SEL_XTAL (BIT(26)) 671 #define DPORT_LPCLK_SEL_XTAL_M (BIT(26)) 672 #define DPORT_LPCLK_SEL_XTAL_V 0x1 673 #define DPORT_LPCLK_SEL_XTAL_S 26 674 /* DPORT_LPCLK_SEL_8M : R/W ;bitpos:[25] ;default: 1'b1 ; */ 675 /*description: */ 676 #define DPORT_LPCLK_SEL_8M (BIT(25)) 677 #define DPORT_LPCLK_SEL_8M_M (BIT(25)) 678 #define DPORT_LPCLK_SEL_8M_V 0x1 679 #define DPORT_LPCLK_SEL_8M_S 25 680 /* DPORT_LPCLK_SEL_RTC_SLOW : R/W ;bitpos:[24] ;default: 1'b0 ; */ 681 /*description: */ 682 #define DPORT_LPCLK_SEL_RTC_SLOW (BIT(24)) 683 #define DPORT_LPCLK_SEL_RTC_SLOW_M (BIT(24)) 684 #define DPORT_LPCLK_SEL_RTC_SLOW_V 0x1 685 #define DPORT_LPCLK_SEL_RTC_SLOW_S 24 686 /* DPORT_BT_LPCK_DIV_A : R/W ;bitpos:[23:12] ;default: 12'd1 ; */ 687 /*description: */ 688 #define DPORT_BT_LPCK_DIV_A 0x00000FFF 689 #define DPORT_BT_LPCK_DIV_A_M ((DPORT_BT_LPCK_DIV_A_V)<<(DPORT_BT_LPCK_DIV_A_S)) 690 #define DPORT_BT_LPCK_DIV_A_V 0xFFF 691 #define DPORT_BT_LPCK_DIV_A_S 12 692 /* DPORT_BT_LPCK_DIV_B : R/W ;bitpos:[11:0] ;default: 12'd1 ; */ 693 /*description: */ 694 #define DPORT_BT_LPCK_DIV_B 0x00000FFF 695 #define DPORT_BT_LPCK_DIV_B_M ((DPORT_BT_LPCK_DIV_B_V)<<(DPORT_BT_LPCK_DIV_B_S)) 696 #define DPORT_BT_LPCK_DIV_B_V 0xFFF 697 #define DPORT_BT_LPCK_DIV_B_S 0 698 699 #define DPORT_CPU_INTR_FROM_CPU_0_REG (DR_REG_SYSTEM_BASE + 0x058) 700 /* DPORT_CPU_INTR_FROM_CPU_0 : R/W ;bitpos:[0] ;default: 1'b0 ; */ 701 /*description: */ 702 #define DPORT_CPU_INTR_FROM_CPU_0 (BIT(0)) 703 #define DPORT_CPU_INTR_FROM_CPU_0_M (BIT(0)) 704 #define DPORT_CPU_INTR_FROM_CPU_0_V 0x1 705 #define DPORT_CPU_INTR_FROM_CPU_0_S 0 706 707 #define DPORT_CPU_INTR_FROM_CPU_1_REG (DR_REG_SYSTEM_BASE + 0x05C) 708 /* DPORT_CPU_INTR_FROM_CPU_1 : R/W ;bitpos:[0] ;default: 1'b0 ; */ 709 /*description: */ 710 #define DPORT_CPU_INTR_FROM_CPU_1 (BIT(0)) 711 #define DPORT_CPU_INTR_FROM_CPU_1_M (BIT(0)) 712 #define DPORT_CPU_INTR_FROM_CPU_1_V 0x1 713 #define DPORT_CPU_INTR_FROM_CPU_1_S 0 714 715 #define DPORT_CPU_INTR_FROM_CPU_2_REG (DR_REG_SYSTEM_BASE + 0x060) 716 /* DPORT_CPU_INTR_FROM_CPU_2 : R/W ;bitpos:[0] ;default: 1'b0 ; */ 717 /*description: */ 718 #define DPORT_CPU_INTR_FROM_CPU_2 (BIT(0)) 719 #define DPORT_CPU_INTR_FROM_CPU_2_M (BIT(0)) 720 #define DPORT_CPU_INTR_FROM_CPU_2_V 0x1 721 #define DPORT_CPU_INTR_FROM_CPU_2_S 0 722 723 #define DPORT_CPU_INTR_FROM_CPU_3_REG (DR_REG_SYSTEM_BASE + 0x064) 724 /* DPORT_CPU_INTR_FROM_CPU_3 : R/W ;bitpos:[0] ;default: 1'b0 ; */ 725 /*description: */ 726 #define DPORT_CPU_INTR_FROM_CPU_3 (BIT(0)) 727 #define DPORT_CPU_INTR_FROM_CPU_3_M (BIT(0)) 728 #define DPORT_CPU_INTR_FROM_CPU_3_V 0x1 729 #define DPORT_CPU_INTR_FROM_CPU_3_S 0 730 731 #define DPORT_RSA_PD_CTRL_REG (DR_REG_SYSTEM_BASE + 0x068) 732 /* DPORT_RSA_MEM_FORCE_PD : R/W ;bitpos:[2] ;default: 1'b0 ; */ 733 /*description: */ 734 #define DPORT_RSA_MEM_FORCE_PD (BIT(2)) 735 #define DPORT_RSA_MEM_FORCE_PD_M (BIT(2)) 736 #define DPORT_RSA_MEM_FORCE_PD_V 0x1 737 #define DPORT_RSA_MEM_FORCE_PD_S 2 738 /* DPORT_RSA_MEM_FORCE_PU : R/W ;bitpos:[1] ;default: 1'b0 ; */ 739 /*description: */ 740 #define DPORT_RSA_MEM_FORCE_PU (BIT(1)) 741 #define DPORT_RSA_MEM_FORCE_PU_M (BIT(1)) 742 #define DPORT_RSA_MEM_FORCE_PU_V 0x1 743 #define DPORT_RSA_MEM_FORCE_PU_S 1 744 /* DPORT_RSA_MEM_PD : R/W ;bitpos:[0] ;default: 1'b1 ; */ 745 /*description: */ 746 #define DPORT_RSA_MEM_PD (BIT(0)) 747 #define DPORT_RSA_MEM_PD_M (BIT(0)) 748 #define DPORT_RSA_MEM_PD_V 0x1 749 #define DPORT_RSA_MEM_PD_S 0 750 #define DPORT_RSA_PD DPORT_RSA_MEM_PD 751 752 #define DPORT_BUSTOEXTMEM_ENA_REG (DR_REG_SYSTEM_BASE + 0x06C) 753 /* DPORT_BUSTOEXTMEM_ENA : R/W ;bitpos:[0] ;default: 1'b1 ; */ 754 /*description: */ 755 #define DPORT_BUSTOEXTMEM_ENA (BIT(0)) 756 #define DPORT_BUSTOEXTMEM_ENA_M (BIT(0)) 757 #define DPORT_BUSTOEXTMEM_ENA_V 0x1 758 #define DPORT_BUSTOEXTMEM_ENA_S 0 759 760 #define DPORT_CACHE_CONTROL_REG (DR_REG_SYSTEM_BASE + 0x070) 761 /* DPORT_PRO_CACHE_RESET : R/W ;bitpos:[2] ;default: 1'b0 ; */ 762 /*description: */ 763 #define DPORT_PRO_CACHE_RESET (BIT(2)) 764 #define DPORT_PRO_CACHE_RESET_M (BIT(2)) 765 #define DPORT_PRO_CACHE_RESET_V 0x1 766 #define DPORT_PRO_CACHE_RESET_S 2 767 /* DPORT_PRO_DCACHE_CLK_ON : R/W ;bitpos:[1] ;default: 1'b1 ; */ 768 /*description: */ 769 #define DPORT_PRO_DCACHE_CLK_ON (BIT(1)) 770 #define DPORT_PRO_DCACHE_CLK_ON_M (BIT(1)) 771 #define DPORT_PRO_DCACHE_CLK_ON_V 0x1 772 #define DPORT_PRO_DCACHE_CLK_ON_S 1 773 /* DPORT_PRO_ICACHE_CLK_ON : R/W ;bitpos:[0] ;default: 1'b1 ; */ 774 /*description: */ 775 #define DPORT_PRO_ICACHE_CLK_ON (BIT(0)) 776 #define DPORT_PRO_ICACHE_CLK_ON_M (BIT(0)) 777 #define DPORT_PRO_ICACHE_CLK_ON_V 0x1 778 #define DPORT_PRO_ICACHE_CLK_ON_S 0 779 780 #define DPORT_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG (DR_REG_SYSTEM_BASE + 0x074) 781 /* DPORT_ENABLE_DOWNLOAD_MANUAL_ENCRYPT : R/W ;bitpos:[3] ;default: 1'b0 ; */ 782 /*description: */ 783 #define DPORT_ENABLE_DOWNLOAD_MANUAL_ENCRYPT (BIT(3)) 784 #define DPORT_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_M (BIT(3)) 785 #define DPORT_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_V 0x1 786 #define DPORT_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_S 3 787 /* DPORT_ENABLE_DOWNLOAD_G0CB_DECRYPT : R/W ;bitpos:[2] ;default: 1'b0 ; */ 788 /*description: */ 789 #define DPORT_ENABLE_DOWNLOAD_G0CB_DECRYPT (BIT(2)) 790 #define DPORT_ENABLE_DOWNLOAD_G0CB_DECRYPT_M (BIT(2)) 791 #define DPORT_ENABLE_DOWNLOAD_G0CB_DECRYPT_V 0x1 792 #define DPORT_ENABLE_DOWNLOAD_G0CB_DECRYPT_S 2 793 /* DPORT_ENABLE_DOWNLOAD_DB_ENCRYPT : R/W ;bitpos:[1] ;default: 1'b0 ; */ 794 /*description: */ 795 #define DPORT_ENABLE_DOWNLOAD_DB_ENCRYPT (BIT(1)) 796 #define DPORT_ENABLE_DOWNLOAD_DB_ENCRYPT_M (BIT(1)) 797 #define DPORT_ENABLE_DOWNLOAD_DB_ENCRYPT_V 0x1 798 #define DPORT_ENABLE_DOWNLOAD_DB_ENCRYPT_S 1 799 /* DPORT_ENABLE_SPI_MANUAL_ENCRYPT : R/W ;bitpos:[0] ;default: 1'b0 ; */ 800 /*description: */ 801 #define DPORT_ENABLE_SPI_MANUAL_ENCRYPT (BIT(0)) 802 #define DPORT_ENABLE_SPI_MANUAL_ENCRYPT_M (BIT(0)) 803 #define DPORT_ENABLE_SPI_MANUAL_ENCRYPT_V 0x1 804 #define DPORT_ENABLE_SPI_MANUAL_ENCRYPT_S 0 805 806 #define DPORT_RTC_FASTMEM_CONFIG_REG (DR_REG_SYSTEM_BASE + 0x078) 807 /* DPORT_RTC_MEM_CRC_FINISH : RO ;bitpos:[31] ;default: 1'b0 ; */ 808 /*description: */ 809 #define DPORT_RTC_MEM_CRC_FINISH (BIT(31)) 810 #define DPORT_RTC_MEM_CRC_FINISH_M (BIT(31)) 811 #define DPORT_RTC_MEM_CRC_FINISH_V 0x1 812 #define DPORT_RTC_MEM_CRC_FINISH_S 31 813 /* DPORT_RTC_MEM_CRC_LEN : R/W ;bitpos:[30:20] ;default: 11'h7ff ; */ 814 /*description: */ 815 #define DPORT_RTC_MEM_CRC_LEN 0x000007FF 816 #define DPORT_RTC_MEM_CRC_LEN_M ((DPORT_RTC_MEM_CRC_LEN_V)<<(DPORT_RTC_MEM_CRC_LEN_S)) 817 #define DPORT_RTC_MEM_CRC_LEN_V 0x7FF 818 #define DPORT_RTC_MEM_CRC_LEN_S 20 819 /* DPORT_RTC_MEM_CRC_ADDR : R/W ;bitpos:[19:9] ;default: 11'h0 ; */ 820 /*description: */ 821 #define DPORT_RTC_MEM_CRC_ADDR 0x000007FF 822 #define DPORT_RTC_MEM_CRC_ADDR_M ((DPORT_RTC_MEM_CRC_ADDR_V)<<(DPORT_RTC_MEM_CRC_ADDR_S)) 823 #define DPORT_RTC_MEM_CRC_ADDR_V 0x7FF 824 #define DPORT_RTC_MEM_CRC_ADDR_S 9 825 /* DPORT_RTC_MEM_CRC_START : R/W ;bitpos:[8] ;default: 1'b0 ; */ 826 /*description: */ 827 #define DPORT_RTC_MEM_CRC_START (BIT(8)) 828 #define DPORT_RTC_MEM_CRC_START_M (BIT(8)) 829 #define DPORT_RTC_MEM_CRC_START_V 0x1 830 #define DPORT_RTC_MEM_CRC_START_S 8 831 832 #define DPORT_RTC_FASTMEM_CRC_REG (DR_REG_SYSTEM_BASE + 0x07C) 833 /* DPORT_RTC_MEM_CRC_RES : RO ;bitpos:[31:0] ;default: 32'b0 ; */ 834 /*description: */ 835 #define DPORT_RTC_MEM_CRC_RES 0xFFFFFFFF 836 #define DPORT_RTC_MEM_CRC_RES_M ((DPORT_RTC_MEM_CRC_RES_V)<<(DPORT_RTC_MEM_CRC_RES_S)) 837 #define DPORT_RTC_MEM_CRC_RES_V 0xFFFFFFFF 838 #define DPORT_RTC_MEM_CRC_RES_S 0 839 840 #define DPORT_REDUNDANT_ECO_CTRL_REG (DR_REG_SYSTEM_BASE + 0x080) 841 /* DPORT_REDUNDANT_ECO_RESULT : RO ;bitpos:[1] ;default: 1'b0 ; */ 842 /*description: */ 843 #define DPORT_REDUNDANT_ECO_RESULT (BIT(1)) 844 #define DPORT_REDUNDANT_ECO_RESULT_M (BIT(1)) 845 #define DPORT_REDUNDANT_ECO_RESULT_V 0x1 846 #define DPORT_REDUNDANT_ECO_RESULT_S 1 847 /* DPORT_REDUNDANT_ECO_DRIVE : R/W ;bitpos:[0] ;default: 1'b0 ; */ 848 /*description: */ 849 #define DPORT_REDUNDANT_ECO_DRIVE (BIT(0)) 850 #define DPORT_REDUNDANT_ECO_DRIVE_M (BIT(0)) 851 #define DPORT_REDUNDANT_ECO_DRIVE_V 0x1 852 #define DPORT_REDUNDANT_ECO_DRIVE_S 0 853 854 #define SYSTEM_CLOCK_GATE_REG (DR_REG_SYSTEM_BASE + 0x084) 855 /* SYSTEM_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ 856 /*description: */ 857 #define SYSTEM_CLK_EN (BIT(0)) 858 #define SYSTEM_CLK_EN_M (BIT(0)) 859 #define SYSTEM_CLK_EN_V 0x1 860 #define SYSTEM_CLK_EN_S 0 861 862 #define DPORT_SRAM_CTRL_2_REG (DR_REG_SYSTEM_BASE + 0x088) 863 /* DPORT_SRAM_FORCE_PU : R/W ;bitpos:[21:0] ;default: 22'h3fffff ; */ 864 /*description: */ 865 #define DPORT_SRAM_FORCE_PU 0x003FFFFF 866 #define DPORT_SRAM_FORCE_PU_M ((DPORT_SRAM_FORCE_PU_V)<<(DPORT_SRAM_FORCE_PU_S)) 867 #define DPORT_SRAM_FORCE_PU_V 0x3FFFFF 868 #define DPORT_SRAM_FORCE_PU_S 0 869 870 #define DPORT_SYSCLK_CONF_REG (DR_REG_SYSTEM_BASE + 0x08C) 871 /* DPORT_CLK_DIV_EN : RO ;bitpos:[19] ;default: 1'd0 ; */ 872 /*description: */ 873 #define DPORT_CLK_DIV_EN (BIT(19)) 874 #define DPORT_CLK_DIV_EN_M (BIT(19)) 875 #define DPORT_CLK_DIV_EN_V 0x1 876 #define DPORT_CLK_DIV_EN_S 19 877 /* DPORT_CLK_XTAL_FREQ : RO ;bitpos:[18:12] ;default: 7'd0 ; */ 878 /*description: */ 879 #define DPORT_CLK_XTAL_FREQ 0x0000007F 880 #define DPORT_CLK_XTAL_FREQ_M ((DPORT_CLK_XTAL_FREQ_V)<<(DPORT_CLK_XTAL_FREQ_S)) 881 #define DPORT_CLK_XTAL_FREQ_V 0x7F 882 #define DPORT_CLK_XTAL_FREQ_S 12 883 /* DPORT_SOC_CLK_SEL : R/W ;bitpos:[11:10] ;default: 2'd0 ; */ 884 /*description: */ 885 #define DPORT_SOC_CLK_SEL 0x00000003 886 #define DPORT_SOC_CLK_SEL_M ((DPORT_SOC_CLK_SEL_V)<<(DPORT_SOC_CLK_SEL_S)) 887 #define DPORT_SOC_CLK_SEL_V 0x3 888 #define DPORT_SOC_CLK_SEL_S 10 889 #define DPORT_SOC_CLK_SEL_XTL 0 890 #define DPORT_SOC_CLK_SEL_PLL 1 891 #define DPORT_SOC_CLK_SEL_8M 2 892 #define DPORT_SOC_CLK_SEL_APLL 3 893 /* DPORT_PRE_DIV_CNT : R/W ;bitpos:[9:0] ;default: 10'h1 ; */ 894 /*description: */ 895 #define DPORT_PRE_DIV_CNT 0x000003FF 896 #define DPORT_PRE_DIV_CNT_M ((DPORT_PRE_DIV_CNT_V)<<(DPORT_PRE_DIV_CNT_S)) 897 #define DPORT_PRE_DIV_CNT_V 0x3FF 898 #define DPORT_PRE_DIV_CNT_S 0 899 900 #define SYSTEM_DATE_REG (DR_REG_SYSTEM_BASE + 0xFFC) 901 /* SYSTEM_DATE : R/W ;bitpos:[27:0] ;default: 28'h1908020 ; */ 902 /*description: */ 903 #define SYSTEM_DATE 0x0FFFFFFF 904 #define SYSTEM_DATE_M ((SYSTEM_DATE_V)<<(SYSTEM_DATE_S)) 905 #define SYSTEM_DATE_V 0xFFFFFFF 906 #define SYSTEM_DATE_S 0 907 908 #ifdef __cplusplus 909 } 910 #endif 911 912 913 914 #endif /*_SOC_SYSTEM_REG_H_ */ 915
