Searched refs:write_reg (Results 1 – 25 of 38) sorted by relevance
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25 self.write_reg(self.REGS.EFUSE_STATUS_REG, 1)55 self.write_reg(addr, 0)56 self.write_reg(self.REGS.EFUSE_STATUS_REG, 1)58 self.write_reg(addr, 0)59 self.write_reg(self.REGS.EFUSE_STATUS_REG, 1)
179 self.write_reg(r, 0)193 self.write_reg(self.REGS.EFUSE_CONF_REG, self.REGS.EFUSE_WRITE_OP_CODE)194 self.write_reg(self.REGS.EFUSE_CMD_REG, self.REGS.EFUSE_PGM_CMD | (block << 2))201 self.write_reg(self.REGS.EFUSE_CONF_REG, self.REGS.EFUSE_READ_OP_CODE)206 self.write_reg(
173 self.write_reg(r, 0)187 self.write_reg(self.REGS.EFUSE_CONF_REG, self.REGS.EFUSE_WRITE_OP_CODE)188 self.write_reg(self.REGS.EFUSE_CMD_REG, self.REGS.EFUSE_PGM_CMD | (block << 2))195 self.write_reg(self.REGS.EFUSE_CONF_REG, self.REGS.EFUSE_READ_OP_CODE)200 self.write_reg(
27 self.write_reg(self.REGS.EFUSE_STATUS_REG, 1)57 self.write_reg(addr, 0)58 self.write_reg(self.REGS.EFUSE_STATUS_REG, 1)60 self.write_reg(addr, 0)61 self.write_reg(self.REGS.EFUSE_STATUS_REG, 1)
168 self.write_reg(r, 0)182 self.write_reg(self.REGS.EFUSE_CONF_REG, self.REGS.EFUSE_WRITE_OP_CODE)183 self.write_reg(self.REGS.EFUSE_CMD_REG, self.REGS.EFUSE_PGM_CMD | (block << 2))190 self.write_reg(self.REGS.EFUSE_CONF_REG, self.REGS.EFUSE_READ_OP_CODE)195 self.write_reg(
60 self.write_reg(self.REGS.EFUSE_REG_CMD, self.REGS.EFUSE_CMD_WRITE)62 self.write_reg(self.REGS.EFUSE_REG_CONF, self.REGS.EFUSE_CONF_READ)63 self.write_reg(self.REGS.EFUSE_REG_CMD, self.REGS.EFUSE_CMD_READ)69 self.write_reg(addr, 0)74 self.write_reg(addr, 0)
222 self.write_reg(self.REGS.EFUSE_REG_CONF, self.REGS.EFUSE_CONF_WRITE)223 self.write_reg(self.REGS.EFUSE_REG_CMD, self.REGS.EFUSE_CMD_WRITE)239 self.write_reg(self.REGS.EFUSE_REG_CONF, self.REGS.EFUSE_CONF_READ)240 self.write_reg(self.REGS.EFUSE_REG_CMD, self.REGS.EFUSE_CMD_READ)
714 def write_reg(self, addr, value, mask=0xFFFFFFFF, delay_us=0, delay_after_us=0): member in ESPLoader736 self.write_reg(addr, val)1242 self.write_reg(SPI_MOSI_DLEN_REG, mosi_bits - 1)1244 self.write_reg(SPI_MISO_DLEN_REG, miso_bits - 1)1251 self.write_reg(SPI_USR1_REG, flags)1268 self.write_reg(SPI_DATA_LEN_REG, flags)1301 self.write_reg(SPI_USR_REG, flags)1302 self.write_reg(1306 self.write_reg(SPI_ADDR_REG, addr)1308 self.write_reg(SPI_W0_REG, 0) # clear data register before we read it[all …]
182 self.write_reg(self.RTC_CNTL_WDTWPROTECT_REG, self.RTC_CNTL_WDT_WKEY)183 self.write_reg(self.RTC_CNTL_WDTCONFIG0_REG, 0)184 self.write_reg(self.RTC_CNTL_WDTWPROTECT_REG, 0)
245 self.write_reg(self.RTC_CNTL_WDTWPROTECT_REG, self.RTC_CNTL_WDT_WKEY)246 self.write_reg(self.RTC_CNTL_WDTCONFIG0_REG, 0)247 self.write_reg(self.RTC_CNTL_WDTWPROTECT_REG, 0)
267 struct sip_cmd_write_reg *write_reg = (struct sip_cmd_write_reg*) (data + sizeof(*hdr)); in esp32_send_sip_command() local268 len = sizeof(*hdr) + sizeof(*write_reg); in esp32_send_sip_command()270 write_reg->addr = GPIO_ENABLE_W1TS_REG; in esp32_send_sip_command()271 write_reg->val = BIT(0) | BIT(2) | BIT(4); /* Turn of RGB LEDs on WROVER-KIT */ in esp32_send_sip_command()
43 static void write_reg(esp_efuse_block_t blk, unsigned int num_reg, uint32_t value);145 write_reg(efuse_block, num_reg, reg_to_write); in esp_efuse_utility_write_cnt()252 write_reg(efuse_block, num_reg, reg_to_write);274 static void write_reg(esp_efuse_block_t blk, unsigned int num_reg, uint32_t value) function
61 def write_reg(self, addr, value, mask=0xFFFFFFFF, delay_us=0, delay_after_us=0): member in EmulateEfuseControllerBase76 self.write_reg(blk.wr_addr + (4 * n), value)109 self.write_reg(wr_addr, 0)
31 …esp_err_t (*write_reg)(void *ctx, uint8_t addr, uint8_t value, uint8_t* value_o, uint32_t wait_ms); member
