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Searched refs:uxCriticalNesting (Results 1 – 5 of 5) sorted by relevance

/hal_espressif-3.4.0/components/freertos/port/riscv/
Dport.c112 static UBaseType_t uxCriticalNesting = 0; variable
133 uxCriticalNesting = 0; in xPortStartScheduler()
164 configASSERT(uxCriticalNesting == ~0UL); in prvTaskExitError()
269 uxCriticalNesting++; in vPortEnterCritical()
271 if (uxCriticalNesting == 1) { in vPortEnterCritical()
278 if (uxCriticalNesting > 0) { in vPortExitCritical()
279 uxCriticalNesting--; in vPortExitCritical()
280 if (uxCriticalNesting == 0) { in vPortExitCritical()
349 …while (uxSchedulerRunning && uxCriticalNesting == 0 && REG_READ(SYSTEM_CPU_INTR_FROM_CPU_0_REG) !=… in vPortYield()
/hal_espressif-3.4.0/components/freertos/
Dtasks.c298 …UBaseType_t uxCriticalNesting; /*< Holds the critical section nesting depth for ports that do not … member
1058 pxNewTCB->uxCriticalNesting = ( UBaseType_t ) 0U; in prvInitialiseNewTask()
4983 ( pxCurrentTCB[xPortGetCoreID()]->uxCriticalNesting )++; in vTaskEnterCritical()
4991 if( pxCurrentTCB[xPortGetCoreID()]->uxCriticalNesting == 1 ) in vTaskEnterCritical()
5011 if( pxCurrentTCB[xPortGetCoreID()]->uxCriticalNesting > 0U ) in vTaskExitCritical()
5013 ( pxCurrentTCB[xPortGetCoreID()]->uxCriticalNesting )--; in vTaskExitCritical()
5015 if( pxCurrentTCB[xPortGetCoreID()]->uxCriticalNesting == 0U ) in vTaskExitCritical()
/hal_espressif-3.4.0/tools/test_idf_size/
Dapp_esp32h2.map7410 .sbss.uxCriticalNesting
Dapp_esp32c3.map7532 .sbss.uxCriticalNesting
Doverflow_esp32c3.map33993 .sbss.uxCriticalNesting