| /hal_espressif-3.4.0/components/esp_hw_support/port/esp32s3/ |
| D | opiram_psram.c | 195 static void s_print_psram_info(opi_psram_mode_reg_t *reg_val) in s_print_psram_info() argument
197 …ESP_EARLY_LOGI(TAG, "vendor id : 0x%02x (%s)", reg_val->mr1.vendor_id, reg_val->mr1.vendor_id == 0… in s_print_psram_info()
198 …ESP_EARLY_LOGI(TAG, "dev id : 0x%02x (generation %d)", reg_val->mr2.dev_id, reg_val->mr2.dev_id… in s_print_psram_info()
199 …ESP_EARLY_LOGI(TAG, "density : 0x%02x (%d Mbit)", reg_val->mr2.density, reg_val->mr2.density == … in s_print_psram_info()
200 … reg_val->mr2.density == 0X3 ? 64 : in s_print_psram_info()
201 … reg_val->mr2.density == 0x5 ? 128 : in s_print_psram_info()
202 … reg_val->mr2.density == 0x7 ? 256 : 0); in s_print_psram_info()
203 …ESP_EARLY_LOGI(TAG, "good-die : 0x%02x (%s)", reg_val->mr2.gb, reg_val->mr2.gb == 1 ? "Pass" : "F… in s_print_psram_info()
204 …ESP_EARLY_LOGI(TAG, "Latency : 0x%02x (%s)", reg_val->mr0.lt, reg_val->mr0.lt == 1 ? "Fixed" : "… in s_print_psram_info()
205 …ESP_EARLY_LOGI(TAG, "VCC : 0x%02x (%s)", reg_val->mr3.vcc, reg_val->mr3.vcc == 1 ? "3V" : "1… in s_print_psram_info()
[all …]
|
| /hal_espressif-3.4.0/components/spi_flash/esp32s3/ |
| D | spi_timing_config.c | 57 uint32_t reg_val = 0; in spi_timing_config_set_core_clock() local
61 reg_val = 0; in spi_timing_config_set_core_clock()
64 reg_val = 1; in spi_timing_config_set_core_clock()
67 reg_val = 2; in spi_timing_config_set_core_clock()
70 reg_val = 3; in spi_timing_config_set_core_clock()
76 REG_SET_FIELD(SPI_MEM_CORE_CLK_SEL_REG(spi_num), SPI_MEM_CORE_CLK_SEL, reg_val); in spi_timing_config_set_core_clock()
128 uint32_t reg_val = 0; in spi_timing_config_flash_set_din_mode_num() local
129 …reg_val = (REG_READ(SPI_MEM_DIN_MODE_REG(spi_num)) & (~(SPI_MEM_DIN0_MODE_M | SPI_MEM_DIN1_MODE_M … in spi_timing_config_flash_set_din_mode_num()
132 REG_WRITE(SPI_MEM_DIN_MODE_REG(spi_num), reg_val); in spi_timing_config_flash_set_din_mode_num()
134 …reg_val = (REG_READ(SPI_MEM_DIN_NUM_REG(spi_num)) & (~(SPI_MEM_DIN0_NUM_M | SPI_MEM_DIN1_NUM_M | S… in spi_timing_config_flash_set_din_mode_num()
[all …]
|
| D | spi_flash_oct_flash_init.c | 96 uint16_t reg_val = 0; in s_set_flash_ouput_driver_strength() local
127 reg_val = (((cr_reg_val & 0xf8) | strength) << 8) | sr_reg_val; in s_set_flash_ouput_driver_strength()
137 (uint8_t*)®_val, data_bit_len, in s_set_flash_ouput_driver_strength()
|
| /hal_espressif-3.4.0/components/hal/esp32c3/include/hal/ |
| D | memprot_ll.h | 32 constrain_reg_fields_t reg_val; in memprot_ll_get_split_addr_from_reg() local
33 reg_val.val = regval; in memprot_ll_get_split_addr_from_reg()
35 uint32_t off = reg_val.splitaddr << 9; in memprot_ll_get_split_addr_from_reg()
37 if (reg_val.cat0 == 0x1 || reg_val.cat0 == 0x2) { in memprot_ll_get_split_addr_from_reg()
39 } else if (reg_val.cat1 == 0x1 || reg_val.cat1 == 0x2) { in memprot_ll_get_split_addr_from_reg()
41 } else if (reg_val.cat2 == 0x1 || reg_val.cat2 == 0x2) { in memprot_ll_get_split_addr_from_reg()
|
| D | spi_ll.h | 717 spi_ll_clock_val_t reg_val; in spi_ll_master_set_clock() local
718 int freq = spi_ll_master_cal_clock(fapb, hz, duty_cycle, ®_val); in spi_ll_master_set_clock()
719 spi_ll_master_set_clock_by_reg(hw, ®_val); in spi_ll_master_set_clock()
|
| /hal_espressif-3.4.0/components/sdmmc/test/ |
| D | test_sdio.c | 226 uint32_t reg_val; in esp32_slave_init_extra() local
227 TEST_ESP_OK( slave_slc_reg_read(card, SLCCONF1, ®_val) ); in esp32_slave_init_extra()
228 reg_val &= ~(SLC_SLC0_RX_STITCH_EN | SLC_SLC0_TX_STITCH_EN); in esp32_slave_init_extra()
229 TEST_ESP_OK( slave_slc_reg_write(card, SLCCONF1, reg_val) ); in esp32_slave_init_extra()
231 TEST_ESP_OK( slave_slc_reg_read(card, SLC0TX_LINK, ®_val) ); in esp32_slave_init_extra()
232 reg_val |= SLC_SLC0_TXLINK_START; in esp32_slave_init_extra()
233 TEST_ESP_OK( slave_slc_reg_write(card, SLC0TX_LINK, reg_val) ); in esp32_slave_init_extra()
|
| /hal_espressif-3.4.0/components/esp_hw_support/ |
| D | regi2c_ctrl.c | 63 static DRAM_ATTR uint8_t reg_val[REGI2C_ANA_CALI_BYTE_NUM]; variable
68 reg_val[i] = regi2c_ctrl_read_reg(I2C_SAR_ADC, I2C_SAR_ADC_HOSTID, i); in regi2c_analog_cali_reg_read()
75 regi2c_ctrl_write_reg(I2C_SAR_ADC, I2C_SAR_ADC_HOSTID, i, reg_val[i]); in regi2c_analog_cali_reg_write()
|
| /hal_espressif-3.4.0/components/esptool_py/esptool/esptool/targets/ |
| D | esp32.py | 313 reg_val = RTC_CNTL_SDIO_FORCE # override efuse setting
314 reg_val |= RTC_CNTL_SDIO_PD_EN
316 reg_val |= RTC_CNTL_XPD_SDIO_REG # enable internal LDO
318 reg_val |= (
321 self.write_reg(RTC_CNTL_SDIO_CONF_REG, reg_val)
|
| /hal_espressif-3.4.0/components/espcoredump/src/port/xtensa/ |
| D | core_dump_port.c | 87 uint32_t reg_val; member
202 s_extra_info.exccause.reg_val = exc_frame->exccause; in esp_core_dump_get_regs_from_stack()
204 s_extra_info.excvaddr.reg_val = exc_frame->excvaddr; in esp_core_dump_get_regs_from_stack()
254 s_extra_info.exccause.reg_val = COREDUMP_INVALID_CAUSE_VALUE; in esp_core_dump_port_init()
475 summary->ex_info.exc_vaddr = ei->excvaddr.reg_val; in esp_core_dump_summary_parse_extra_info()
476 summary->ex_info.exc_cause = ei->exccause.reg_val; in esp_core_dump_summary_parse_extra_info()
486 summary->ex_info.epcx[ei->extra_regs[i].reg_index - EPC_1] = ei->extra_regs[i].reg_val; in esp_core_dump_summary_parse_extra_info()
|
| /hal_espressif-3.4.0/components/esp_hw_support/test/ |
| D | test_fastbus.c | 119 int reg_val = (1 << UART_RXFIFO_FULL_THRHD_S); variable
120 WRITE_PERI_REG(UART_CONF1_REG(1), reg_val);
|
| /hal_espressif-3.4.0/components/hal/esp32s3/include/hal/ |
| D | lcd_ll.h | 235 uint32_t reg_val = 0; in lcd_ll_set_data_delay_ticks() local
237 reg_val |= (delay & 0x03) << (2 * i); in lcd_ll_set_data_delay_ticks()
239 dev->lcd_data_dout_mode.val = reg_val; in lcd_ll_set_data_delay_ticks()
|
| D | spi_ll.h | 727 spi_ll_clock_val_t reg_val; in spi_ll_master_set_clock() local
728 int freq = spi_ll_master_cal_clock(fapb, hz, duty_cycle, ®_val); in spi_ll_master_set_clock()
729 spi_ll_master_set_clock_by_reg(hw, ®_val); in spi_ll_master_set_clock()
|
| /hal_espressif-3.4.0/tools/ |
| D | gdb_panic_server.py | 250 reg_val = self.panic_info.regs.get(reg_name, 0)
251 reg_bytes = struct.pack('<L', reg_val)
|
| /hal_espressif-3.4.0/components/hal/esp32/include/hal/ |
| D | spi_ll.h | 642 spi_ll_clock_val_t reg_val; in spi_ll_master_set_clock() local
643 int freq = spi_ll_master_cal_clock(fapb, hz, duty_cycle, ®_val); in spi_ll_master_set_clock()
644 spi_ll_master_set_clock_by_reg(hw, ®_val); in spi_ll_master_set_clock()
|
| /hal_espressif-3.4.0/components/hal/esp32h2/include/hal/ |
| D | spi_ll.h | 720 spi_ll_clock_val_t reg_val; in spi_ll_master_set_clock() local
721 int freq = spi_ll_master_cal_clock(fapb, hz, duty_cycle, ®_val); in spi_ll_master_set_clock()
722 spi_ll_master_set_clock_by_reg(hw, ®_val); in spi_ll_master_set_clock()
|
| /hal_espressif-3.4.0/components/ulp/include/esp32s2/ |
| D | ulp.h | 439 #define I_ST(reg_val, reg_addr, offset_) { .st = { \ argument
440 .dreg = reg_val, \
|
| /hal_espressif-3.4.0/components/ulp/include/esp32s3/ |
| D | ulp.h | 439 #define I_ST(reg_val, reg_addr, offset_) { .st = { \ argument
440 .dreg = reg_val, \
|
| /hal_espressif-3.4.0/components/hal/esp32s2/include/hal/ |
| D | spi_ll.h | 684 spi_ll_clock_val_t reg_val; in spi_ll_master_set_clock() local
685 int freq = spi_ll_master_cal_clock(fapb, hz, duty_cycle, ®_val); in spi_ll_master_set_clock()
686 spi_ll_master_set_clock_by_reg(hw, ®_val); in spi_ll_master_set_clock()
|
| /hal_espressif-3.4.0/components/ulp/include/esp32/ |
| D | ulp.h | 473 #define I_ST(reg_val, reg_addr, offset_) { .st = { \ argument
474 .dreg = reg_val, \
|
