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Searched refs:int_ena (Results 1 – 25 of 135) sorted by relevance

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/hal_espressif-3.4.0/components/hal/esp32c3/include/hal/
Drmt_ll.h282 dev->int_ena.val |= mask; in rmt_ll_enable_interrupt()
284 dev->int_ena.val &= ~mask; in rmt_ll_enable_interrupt()
291 dev->int_ena.val |= (1 << channel); in rmt_ll_enable_tx_end_interrupt()
293 dev->int_ena.val &= ~(1 << channel); in rmt_ll_enable_tx_end_interrupt()
300 dev->int_ena.val |= (1 << (channel + 4)); in rmt_ll_enable_tx_err_interrupt()
302 dev->int_ena.val &= ~(1 << (channel + 4)); in rmt_ll_enable_tx_err_interrupt()
309 dev->int_ena.val |= (1 << (channel + 2)); in rmt_ll_enable_rx_end_interrupt()
311 dev->int_ena.val &= ~(1 << (channel + 2)); in rmt_ll_enable_rx_end_interrupt()
318 dev->int_ena.val |= (1 << (channel + 6)); in rmt_ll_enable_rx_err_interrupt()
320 dev->int_ena.val &= ~(1 << (channel + 6)); in rmt_ll_enable_rx_err_interrupt()
[all …]
Di2c_ll.h246 hw->int_ena.val |= mask; in i2c_ll_enable_intr_mask()
259 hw->int_ena.val &= (~mask); in i2c_ll_disable_intr_mask()
663 hw->int_ena.val = I2C_LL_MASTER_TX_INT; in i2c_ll_master_enable_tx_it()
676 hw->int_ena.val = I2C_LL_MASTER_RX_INT; in i2c_ll_master_enable_rx_it()
688 hw->int_ena.val &= (~I2C_LL_MASTER_TX_INT); in i2c_ll_master_disable_tx_it()
700 hw->int_ena.val &= (~I2C_LL_MASTER_RX_INT); in i2c_ll_master_disable_rx_it()
736 hw->int_ena.val |= I2C_LL_SLAVE_TX_INT; in i2c_ll_slave_enable_tx_it()
748 hw->int_ena.val |= I2C_LL_SLAVE_RX_INT; in i2c_ll_slave_enable_rx_it()
760 hw->int_ena.val &= (~I2C_LL_SLAVE_TX_INT); in i2c_ll_slave_disable_tx_it()
772 hw->int_ena.val &= (~I2C_LL_SLAVE_RX_INT); in i2c_ll_slave_disable_rx_it()
Dusb_serial_jtag_ll.h51 USB_SERIAL_JTAG.int_ena.val |= mask; in usb_serial_jtag_ll_ena_intr_mask()
63 USB_SERIAL_JTAG.int_ena.val &= (~mask); in usb_serial_jtag_ll_disable_intr_mask()
95 return USB_SERIAL_JTAG.int_ena.val; in usb_serial_jtag_ll_get_intr_ena_status()
Duhci_ll.h104 hw->int_ena.val |= intr_mask; in uhci_ll_enable_intr()
109 hw->int_ena.val &= (~intr_mask); in uhci_ll_disable_intr()
/hal_espressif-3.4.0/components/hal/esp32h2/include/hal/
Drmt_ll.h281 dev->int_ena.val |= mask; in rmt_ll_enable_interrupt()
283 dev->int_ena.val &= ~mask; in rmt_ll_enable_interrupt()
290 dev->int_ena.val |= (1 << channel); in rmt_ll_enable_tx_end_interrupt()
292 dev->int_ena.val &= ~(1 << channel); in rmt_ll_enable_tx_end_interrupt()
299 dev->int_ena.val |= (1 << (channel + 4)); in rmt_ll_enable_tx_err_interrupt()
301 dev->int_ena.val &= ~(1 << (channel + 4)); in rmt_ll_enable_tx_err_interrupt()
308 dev->int_ena.val |= (1 << (channel + 2)); in rmt_ll_enable_rx_end_interrupt()
310 dev->int_ena.val &= ~(1 << (channel + 2)); in rmt_ll_enable_rx_end_interrupt()
317 dev->int_ena.val |= (1 << (channel + 6)); in rmt_ll_enable_rx_err_interrupt()
319 dev->int_ena.val &= ~(1 << (channel + 6)); in rmt_ll_enable_rx_err_interrupt()
[all …]
Di2c_ll.h242 hw->int_ena.val |= mask; in i2c_ll_enable_intr_mask()
255 hw->int_ena.val &= (~mask); in i2c_ll_disable_intr_mask()
646 hw->int_ena.val = I2C_LL_MASTER_TX_INT; in i2c_ll_master_enable_tx_it()
659 hw->int_ena.val = I2C_LL_MASTER_RX_INT; in i2c_ll_master_enable_rx_it()
671 hw->int_ena.val &= (~I2C_LL_MASTER_TX_INT); in i2c_ll_master_disable_tx_it()
683 hw->int_ena.val &= (~I2C_LL_MASTER_RX_INT); in i2c_ll_master_disable_rx_it()
719 hw->int_ena.val |= I2C_LL_SLAVE_TX_INT; in i2c_ll_slave_enable_tx_it()
731 hw->int_ena.val |= I2C_LL_SLAVE_RX_INT; in i2c_ll_slave_enable_rx_it()
743 hw->int_ena.val &= (~I2C_LL_SLAVE_TX_INT); in i2c_ll_slave_disable_tx_it()
755 hw->int_ena.val &= (~I2C_LL_SLAVE_RX_INT); in i2c_ll_slave_disable_rx_it()
Dusb_serial_jtag_ll.h53 USB_SERIAL_JTAG.int_ena.val |= mask; in usb_serial_jtag_ll_ena_intr_mask()
65 USB_SERIAL_JTAG.int_ena.val &= (~mask); in usb_serial_jtag_ll_disable_intr_mask()
97 return USB_SERIAL_JTAG.int_ena.val; in usb_serial_jtag_ll_get_intr_ena_status()
Duhci_ll.h104 hw->int_ena.val |= intr_mask; in uhci_ll_enable_intr()
109 hw->int_ena.val &= (~intr_mask); in uhci_ll_disable_intr()
/hal_espressif-3.4.0/components/hal/esp32s3/include/hal/
Drmt_ll.h284 dev->int_ena.val |= mask; in rmt_ll_enable_interrupt()
286 dev->int_ena.val &= ~mask; in rmt_ll_enable_interrupt()
293 dev->int_ena.val |= (1 << channel); in rmt_ll_enable_tx_end_interrupt()
295 dev->int_ena.val &= ~(1 << channel); in rmt_ll_enable_tx_end_interrupt()
302 dev->int_ena.val |= (1 << (channel + 4)); in rmt_ll_enable_tx_err_interrupt()
304 dev->int_ena.val &= ~(1 << (channel + 4)); in rmt_ll_enable_tx_err_interrupt()
311 dev->int_ena.val |= (1 << (channel + 16)); in rmt_ll_enable_rx_end_interrupt()
313 dev->int_ena.val &= ~(1 << (channel + 16)); in rmt_ll_enable_rx_end_interrupt()
320 dev->int_ena.val |= (1 << (channel + 20)); in rmt_ll_enable_rx_err_interrupt()
322 dev->int_ena.val &= ~(1 << (channel + 20)); in rmt_ll_enable_rx_err_interrupt()
[all …]
Di2c_ll.h237 hw->int_ena.val |= mask; in i2c_ll_enable_intr_mask()
250 hw->int_ena.val &= (~mask); in i2c_ll_disable_intr_mask()
657 hw->int_ena.val = I2C_LL_MASTER_TX_INT; in i2c_ll_master_enable_tx_it()
670 hw->int_ena.val = I2C_LL_MASTER_RX_INT; in i2c_ll_master_enable_rx_it()
682 hw->int_ena.val &= (~I2C_LL_MASTER_TX_INT); in i2c_ll_master_disable_tx_it()
694 hw->int_ena.val &= (~I2C_LL_MASTER_RX_INT); in i2c_ll_master_disable_rx_it()
730 hw->int_ena.val |= I2C_LL_SLAVE_TX_INT; in i2c_ll_slave_enable_tx_it()
742 hw->int_ena.val |= I2C_LL_SLAVE_RX_INT; in i2c_ll_slave_enable_rx_it()
754 hw->int_ena.val &= (~I2C_LL_SLAVE_TX_INT); in i2c_ll_slave_disable_tx_it()
766 hw->int_ena.val &= (~I2C_LL_SLAVE_RX_INT); in i2c_ll_slave_disable_rx_it()
Dmcpwm_ll.h82 mcpwm->int_ena.val = 0; in mcpwm_ll_intr_disable_all()
186 mcpwm->int_ena.val |= 1 << (timer_id + 0); in mcpwm_ll_intr_enable_timer_stop()
188 mcpwm->int_ena.val &= ~(1 << (timer_id + 0)); in mcpwm_ll_intr_enable_timer_stop()
195 mcpwm->int_ena.val |= 1 << (timer_id + 3); in mcpwm_ll_intr_enable_timer_tez()
197 mcpwm->int_ena.val &= ~(1 << (timer_id + 3)); in mcpwm_ll_intr_enable_timer_tez()
204 mcpwm->int_ena.val |= 1 << (timer_id + 6); in mcpwm_ll_intr_enable_timer_tep()
206 mcpwm->int_ena.val &= ~(1 << (timer_id + 6)); in mcpwm_ll_intr_enable_timer_tep()
213 mcpwm->int_ena.val |= 1 << (9 + fault_id); // enter fault interrupt in mcpwm_ll_intr_enable_fault_enter()
215 mcpwm->int_ena.val &= ~(1 << (9 + fault_id)); in mcpwm_ll_intr_enable_fault_enter()
222 mcpwm->int_ena.val |= 1 << (12 + fault_id); // exit fault interrupt in mcpwm_ll_intr_enable_fault_exit()
[all …]
Dusb_serial_jtag_ll.h51 USB_SERIAL_JTAG.int_ena.val |= mask; in usb_serial_jtag_ll_ena_intr_mask()
63 USB_SERIAL_JTAG.int_ena.val &= (~mask); in usb_serial_jtag_ll_disable_intr_mask()
95 return USB_SERIAL_JTAG.int_ena.val; in usb_serial_jtag_ll_get_intr_ena_status()
Duhci_ll.h105 hw->int_ena.val |= intr_mask; in uhci_ll_enable_intr()
110 hw->int_ena.val &= (~intr_mask); in uhci_ll_disable_intr()
Dgdma_ll.h94 dev->channel[channel].in.int_ena.val |= mask; in gdma_ll_rx_enable_interrupt()
96 dev->channel[channel].in.int_ena.val &= ~mask; in gdma_ll_rx_enable_interrupt()
330 dev->channel[channel].out.int_ena.val |= mask; in gdma_ll_tx_enable_interrupt()
332 dev->channel[channel].out.int_ena.val &= ~mask; in gdma_ll_tx_enable_interrupt()
Dadc_ll.h930 RTCCNTL.int_ena.rtc_saradc1 = 1; in adc_ll_rtc_intr_enable()
933 RTCCNTL.int_ena.rtc_saradc2 = 1; in adc_ll_rtc_intr_enable()
946 RTCCNTL.int_ena.rtc_saradc1 = 0; in adc_ll_rtc_intr_disable()
949 RTCCNTL.int_ena.rtc_saradc2 = 0; in adc_ll_rtc_intr_disable()
/hal_espressif-3.4.0/components/hal/esp32/include/hal/
Drmt_ll.h231 dev->int_ena.val |= mask; in rmt_ll_enable_interrupt()
233 dev->int_ena.val &= ~mask; in rmt_ll_enable_interrupt()
239 dev->int_ena.val &= ~(1 << (channel * 3)); in rmt_ll_enable_tx_end_interrupt()
240 dev->int_ena.val |= (enable << (channel * 3)); in rmt_ll_enable_tx_end_interrupt()
245 dev->int_ena.val &= ~(1 << (channel * 3 + 1)); in rmt_ll_enable_rx_end_interrupt()
246 dev->int_ena.val |= (enable << (channel * 3 + 1)); in rmt_ll_enable_rx_end_interrupt()
251 dev->int_ena.val &= ~(1 << (channel * 3 + 2)); in rmt_ll_enable_tx_err_interrupt()
252 dev->int_ena.val |= (enable << (channel * 3 + 2)); in rmt_ll_enable_tx_err_interrupt()
257 dev->int_ena.val &= ~(1 << (channel * 3 + 2)); in rmt_ll_enable_rx_err_interrupt()
258 dev->int_ena.val |= (enable << (channel * 3 + 2)); in rmt_ll_enable_rx_err_interrupt()
[all …]
Di2c_ll.h211 hw->int_ena.val |= mask; in i2c_ll_enable_intr_mask()
224 hw->int_ena.val &= (~mask); in i2c_ll_disable_intr_mask()
629 hw->int_ena.val = I2C_LL_MASTER_TX_INT; in i2c_ll_master_enable_tx_it()
642 hw->int_ena.val = I2C_LL_MASTER_RX_INT; in i2c_ll_master_enable_rx_it()
654 hw->int_ena.val &= (~I2C_LL_MASTER_TX_INT); in i2c_ll_master_disable_tx_it()
666 hw->int_ena.val &= (~I2C_LL_MASTER_RX_INT); in i2c_ll_master_disable_rx_it()
702 hw->int_ena.val |= I2C_LL_SLAVE_TX_INT; in i2c_ll_slave_enable_tx_it()
714 hw->int_ena.val |= I2C_LL_SLAVE_RX_INT; in i2c_ll_slave_enable_rx_it()
726 hw->int_ena.val &= (~I2C_LL_SLAVE_TX_INT); in i2c_ll_slave_disable_tx_it()
738 hw->int_ena.val &= (~I2C_LL_SLAVE_RX_INT); in i2c_ll_slave_disable_rx_it()
Di2s_ll.h328 hw->int_ena.val |= mask; in i2s_ll_enable_intr()
330 hw->int_ena.val &= ~mask; in i2s_ll_enable_intr()
341 hw->int_ena.out_eof = 1; in i2s_ll_tx_enable_intr()
342 hw->int_ena.out_dscr_err = 1; in i2s_ll_tx_enable_intr()
352 hw->int_ena.out_eof = 0; in i2s_ll_tx_disable_intr()
353 hw->int_ena.out_dscr_err = 0; in i2s_ll_tx_disable_intr()
363 hw->int_ena.in_suc_eof = 1; in i2s_ll_rx_enable_intr()
364 hw->int_ena.in_dscr_err = 1; in i2s_ll_rx_enable_intr()
374 hw->int_ena.in_suc_eof = 0; in i2s_ll_rx_disable_intr()
375 hw->int_ena.in_dscr_err = 0; in i2s_ll_rx_disable_intr()
Dmcpwm_ll.h81 mcpwm->int_ena.val = 0; in mcpwm_ll_intr_disable_all()
185 mcpwm->int_ena.val |= 1 << (timer_id + 0); in mcpwm_ll_intr_enable_timer_stop()
187 mcpwm->int_ena.val &= ~(1 << (timer_id + 0)); in mcpwm_ll_intr_enable_timer_stop()
194 mcpwm->int_ena.val |= 1 << (timer_id + 3); in mcpwm_ll_intr_enable_timer_tez()
196 mcpwm->int_ena.val &= ~(1 << (timer_id + 3)); in mcpwm_ll_intr_enable_timer_tez()
203 mcpwm->int_ena.val |= 1 << (timer_id + 6); in mcpwm_ll_intr_enable_timer_tep()
205 mcpwm->int_ena.val &= ~(1 << (timer_id + 6)); in mcpwm_ll_intr_enable_timer_tep()
212 mcpwm->int_ena.val |= 1 << (9 + fault_id); // enter fault interrupt in mcpwm_ll_intr_enable_fault_enter()
214 mcpwm->int_ena.val &= ~(1 << (9 + fault_id)); in mcpwm_ll_intr_enable_fault_enter()
221 mcpwm->int_ena.val |= 1 << (12 + fault_id); // exit fault interrupt in mcpwm_ll_intr_enable_fault_exit()
[all …]
Dgpio_ll.h277 hw->pin[gpio_num].int_ena = GPIO_LL_PRO_CPU_INTR_ENA; //enable pro cpu intr in gpio_ll_intr_enable_on_core()
279 hw->pin[gpio_num].int_ena = GPIO_LL_APP_CPU_INTR_ENA; //enable pro cpu intr in gpio_ll_intr_enable_on_core()
291 hw->pin[gpio_num].int_ena = 0; //disable GPIO intr in gpio_ll_intr_disable()
/hal_espressif-3.4.0/components/hal/esp32s2/include/hal/
Drmt_ll.h259 dev->int_ena.val |= mask; in rmt_ll_enable_interrupt()
261 dev->int_ena.val &= ~mask; in rmt_ll_enable_interrupt()
267 dev->int_ena.val &= ~(1 << (channel * 3)); in rmt_ll_enable_tx_end_interrupt()
268 dev->int_ena.val |= (enable << (channel * 3)); in rmt_ll_enable_tx_end_interrupt()
273 dev->int_ena.val &= ~(1 << (channel * 3 + 1)); in rmt_ll_enable_rx_end_interrupt()
274 dev->int_ena.val |= (enable << (channel * 3 + 1)); in rmt_ll_enable_rx_end_interrupt()
279 dev->int_ena.val &= ~(1 << (channel * 3 + 2)); in rmt_ll_enable_tx_err_interrupt()
280 dev->int_ena.val |= (enable << (channel * 3 + 2)); in rmt_ll_enable_tx_err_interrupt()
285 dev->int_ena.val &= ~(1 << (channel * 3 + 2)); in rmt_ll_enable_rx_err_interrupt()
286 dev->int_ena.val |= (enable << (channel * 3 + 2)); in rmt_ll_enable_rx_err_interrupt()
[all …]
Di2s_ll.h324 hw->int_ena.val |= mask; in i2s_ll_enable_intr()
326 hw->int_ena.val &= ~mask; in i2s_ll_enable_intr()
337 hw->int_ena.out_eof = 1; in i2s_ll_tx_enable_intr()
338 hw->int_ena.out_dscr_err = 1; in i2s_ll_tx_enable_intr()
348 hw->int_ena.out_eof = 0; in i2s_ll_tx_disable_intr()
349 hw->int_ena.out_dscr_err = 0; in i2s_ll_tx_disable_intr()
359 hw->int_ena.in_suc_eof = 1; in i2s_ll_rx_enable_intr()
360 hw->int_ena.in_dscr_err = 1; in i2s_ll_rx_enable_intr()
370 hw->int_ena.in_suc_eof = 0; in i2s_ll_rx_disable_intr()
371 hw->int_ena.in_dscr_err = 0; in i2s_ll_rx_disable_intr()
Di2c_ll.h216 hw->int_ena.val |= mask; in i2c_ll_enable_intr_mask()
229 hw->int_ena.val &= (~mask); in i2c_ll_disable_intr_mask()
637 hw->int_ena.val = I2C_LL_MASTER_TX_INT; in i2c_ll_master_enable_tx_it()
650 hw->int_ena.val = I2C_LL_MASTER_RX_INT; in i2c_ll_master_enable_rx_it()
662 hw->int_ena.val &= (~I2C_LL_MASTER_TX_INT); in i2c_ll_master_disable_tx_it()
674 hw->int_ena.val &= (~I2C_LL_MASTER_RX_INT); in i2c_ll_master_disable_rx_it()
710 hw->int_ena.val |= I2C_LL_SLAVE_TX_INT; in i2c_ll_slave_enable_tx_it()
722 hw->int_ena.val |= I2C_LL_SLAVE_RX_INT; in i2c_ll_slave_enable_rx_it()
734 hw->int_ena.val &= (~I2C_LL_SLAVE_TX_INT); in i2c_ll_slave_disable_tx_it()
746 hw->int_ena.val &= (~I2C_LL_SLAVE_RX_INT); in i2c_ll_slave_disable_rx_it()
Dtouch_sensor_ll.h493 RTCCNTL.int_ena.rtc_touch_done = 1; in touch_ll_intr_enable()
496 RTCCNTL.int_ena.rtc_touch_active = 1; in touch_ll_intr_enable()
499 RTCCNTL.int_ena.rtc_touch_inactive = 1; in touch_ll_intr_enable()
502 RTCCNTL.int_ena.rtc_touch_scan_done = 1; in touch_ll_intr_enable()
505 RTCCNTL.int_ena.rtc_touch_timeout = 1; in touch_ll_intr_enable()
517 RTCCNTL.int_ena.rtc_touch_done = 0; in touch_ll_intr_disable()
520 RTCCNTL.int_ena.rtc_touch_active = 0; in touch_ll_intr_disable()
523 RTCCNTL.int_ena.rtc_touch_inactive = 0; in touch_ll_intr_disable()
526 RTCCNTL.int_ena.rtc_touch_scan_done = 0; in touch_ll_intr_disable()
529 RTCCNTL.int_ena.rtc_touch_timeout = 0; in touch_ll_intr_disable()
/hal_espressif-3.4.0/components/driver/
Dadc_deprecated.c252 APB_SARADC.int_ena.adc1_thres = 1; in adc_ll_digi_intr_enable()
255 APB_SARADC.int_ena.adc1_done = 1; in adc_ll_digi_intr_enable()
259 APB_SARADC.int_ena.adc2_thres = 1; in adc_ll_digi_intr_enable()
262 APB_SARADC.int_ena.adc2_done = 1; in adc_ll_digi_intr_enable()
290 APB_SARADC.int_ena.adc1_thres = 0; in adc_ll_digi_intr_disable()
293 APB_SARADC.int_ena.adc1_done = 0; in adc_ll_digi_intr_disable()
297 APB_SARADC.int_ena.adc2_thres = 0; in adc_ll_digi_intr_disable()
300 APB_SARADC.int_ena.adc2_done = 0; in adc_ll_digi_intr_disable()

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