1 /** Copyright 2020 Espressif Systems (Shanghai) PTE LTD
2  *
3  *  Licensed under the Apache License, Version 2.0 (the "License");
4  *  you may not use this file except in compliance with the License.
5  *  You may obtain a copy of the License at
6  *
7  *  http://www.apache.org/licenses/LICENSE-2.0
8  *
9  *  Unless required by applicable law or agreed to in writing, software
10  *  distributed under the License is distributed on an "AS IS" BASIS,
11  *  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12  *  See the License for the specific language governing permissions and
13  *  limitations under the License.
14  */
15 #pragma once
16 
17 #include <stdint.h>
18 #ifdef __cplusplus
19 extern "C" {
20 #endif
21 
22 /** Interrupt Registers */
23 /** Type of dma_int_raw register
24  *  Raw interrupt status
25  */
26 typedef union {
27     struct {
28         /** dma_in_done_int_raw : RO; bitpos: [0]; default: 0;
29          *  This is the interrupt raw bit. Triggered when the last data of frame is received or
30          *  the receive buffer is full indicated by inlink descriptor.
31          */
32         uint32_t dma_in_done_int_raw: 1;
33         /** dma_in_suc_eof_int_raw : RO; bitpos: [1]; default: 0;
34          *  This is the interrupt raw bit. Triggered when the last data of one frame is
35          *  received.
36          */
37         uint32_t dma_in_suc_eof_int_raw: 1;
38         /** dma_out_done_int_raw : RO; bitpos: [2]; default: 0;
39          *  This is the interrupt raw bit. Triggered when all data indicated by one outlink
40          *  descriptor has been pushed into Tx FIFO.
41          */
42         uint32_t dma_out_done_int_raw: 1;
43         /** dma_out_eof_int_raw : RO; bitpos: [3]; default: 0;
44          *  This is the interrupt raw bit. Triggered when the last data with EOF flag has been
45          *  pushed into Tx FIFO.
46          */
47         uint32_t dma_out_eof_int_raw: 1;
48         /** dma_in_dscr_err_int_raw : RO; bitpos: [4]; default: 0;
49          *  This is the interrupt raw bit. Triggered when detecting inlink descriptor error,
50          *  including owner error, the second and third word error of inlink descriptor.
51          */
52         uint32_t dma_in_dscr_err_int_raw: 1;
53         /** dma_out_dscr_err_int_raw : RO; bitpos: [5]; default: 0;
54          *  This is the interrupt raw bit. Triggered when detecting outlink descriptor error,
55          *  including owner error, the second and third word error of outlink descriptor.
56          */
57         uint32_t dma_out_dscr_err_int_raw: 1;
58         /** dma_in_dscr_empty_int_raw : RO; bitpos: [6]; default: 0;
59          *  This is the interrupt raw bit. Triggered when receiving data is completed and no
60          *  more inlink descriptor.
61          */
62         uint32_t dma_in_dscr_empty_int_raw: 1;
63         /** dma_out_total_eof_int_raw : RO; bitpos: [7]; default: 0;
64          *  This is the interrupt raw bit. Triggered when data corresponding to all outlink
65          *  descriptor and the last descriptor with valid EOF is transmitted out.
66          */
67         uint32_t dma_out_total_eof_int_raw: 1;
68         /** dma_crc_done_int_raw : RO; bitpos: [8]; default: 0;
69          *  This is the interrupt raw bit. Triggered when crc calculation is done.
70          */
71         uint32_t dma_crc_done_int_raw: 1;
72         uint32_t reserved9: 23;
73     };
74     uint32_t val;
75 } cp_dma_int_raw_reg_t;
76 
77 /** Type of dma_int_st register
78  *  Masked interrupt status
79  */
80 typedef union {
81     struct {
82         /** dma_in_done_int_st : RO; bitpos: [0]; default: 0;
83          *  This is the masked interrupt bit for cp_in_done_int interrupt when
84          *  cp_in_done_int_ena is set to 1.
85          */
86         uint32_t dma_in_done_int_st: 1;
87         /** dma_in_suc_eof_int_st : RO; bitpos: [1]; default: 0;
88          *  This is the masked interrupt bit for cp_in_suc_eof_int interrupt when
89          *  cp_in_suc_eof_int_ena is set to 1.
90          */
91         uint32_t dma_in_suc_eof_int_st: 1;
92         /** dma_out_done_int_st : RO; bitpos: [2]; default: 0;
93          *  This is the masked interrupt bit for cp_out_done_int interrupt when
94          *  cp_out_done_int_ena is set to 1.
95          */
96         uint32_t dma_out_done_int_st: 1;
97         /** dma_out_eof_int_st : RO; bitpos: [3]; default: 0;
98          *  This is the masked interrupt bit for cp_out_eof_int interrupt when
99          *  cp_out_eof_int_ena is set to 1.
100          */
101         uint32_t dma_out_eof_int_st: 1;
102         /** dma_in_dscr_err_int_st : RO; bitpos: [4]; default: 0;
103          *  This is the masked interrupt bit for cp_in_dscr_err_int interrupt when
104          *  cp_in_dscr_err_int_ena is set to 1.
105          */
106         uint32_t dma_in_dscr_err_int_st: 1;
107         /** dma_out_dscr_err_int_st : RO; bitpos: [5]; default: 0;
108          *  This is the masked interrupt bit for cp_out_dscr_err_int interrupt when
109          *  cp_out_dscr_err_int_ena is set to 1.
110          */
111         uint32_t dma_out_dscr_err_int_st: 1;
112         /** dma_in_dscr_empty_int_st : RO; bitpos: [6]; default: 0;
113          *  This is the masked interrupt bit for cp_in_dscr_empty_int interrupt when
114          *  cp_in_dscr_empty_int_ena is set to 1.
115          */
116         uint32_t dma_in_dscr_empty_int_st: 1;
117         /** dma_out_total_eof_int_st : RO; bitpos: [7]; default: 0;
118          *  This is the masked interrupt bit for cp_out_total_eof_int interrupt when
119          *  cp_out_total_eof_int_ena is set to 1.
120          */
121         uint32_t dma_out_total_eof_int_st: 1;
122         /** dma_crc_done_int_st : RO; bitpos: [8]; default: 0;
123          *  This is the masked interrupt bit for cp_crc_done_int interrupt when
124          *  cp_crc_done_int_ena is set to 1.
125          */
126         uint32_t dma_crc_done_int_st: 1;
127         uint32_t reserved9: 23;
128     };
129     uint32_t val;
130 } cp_dma_int_st_reg_t;
131 
132 /** Type of dma_int_ena register
133  *  Interrupt enable bits
134  */
135 typedef union {
136     struct {
137         /** dma_in_done_int_ena : R/W; bitpos: [0]; default: 0;
138          *  This is the interrupt enable bit for cp_in_done_int interrupt.
139          */
140         uint32_t dma_in_done_int_ena: 1;
141         /** dma_in_suc_eof_int_ena : R/W; bitpos: [1]; default: 0;
142          *  This is the interrupt enable bit for cp_in_suc_eof_int interrupt.
143          */
144         uint32_t dma_in_suc_eof_int_ena: 1;
145         /** dma_out_done_int_ena : R/W; bitpos: [2]; default: 0;
146          *  This is the interrupt enable bit for cp_out_done_int interrupt.
147          */
148         uint32_t dma_out_done_int_ena: 1;
149         /** dma_out_eof_int_ena : R/W; bitpos: [3]; default: 0;
150          *  This is the interrupt enable bit for cp_out_eof_int interrupt.
151          */
152         uint32_t dma_out_eof_int_ena: 1;
153         /** dma_in_dscr_err_int_ena : R/W; bitpos: [4]; default: 0;
154          *  This is the interrupt enable bit for cp_in_dscr_err_int interrupt.
155          */
156         uint32_t dma_in_dscr_err_int_ena: 1;
157         /** dma_out_dscr_err_int_ena : R/W; bitpos: [5]; default: 0;
158          *  This is the interrupt enable bit for cp_out_dscr_err_int interrupt.
159          */
160         uint32_t dma_out_dscr_err_int_ena: 1;
161         /** dma_in_dscr_empty_int_ena : R/W; bitpos: [6]; default: 0;
162          *  This is the interrupt enable bit for cp_in_dscr_empty_int interrupt.
163          */
164         uint32_t dma_in_dscr_empty_int_ena: 1;
165         /** dma_out_total_eof_int_ena : R/W; bitpos: [7]; default: 0;
166          *  This is the interrupt enable bit for cp_out_total_eof_int interrupt.
167          */
168         uint32_t dma_out_total_eof_int_ena: 1;
169         /** dma_crc_done_int_ena : R/W; bitpos: [8]; default: 0;
170          *  This is the interrupt enable bit for cp_crc_done_int interrupt.
171          */
172         uint32_t dma_crc_done_int_ena: 1;
173         uint32_t reserved9: 23;
174     };
175     uint32_t val;
176 } cp_dma_int_ena_reg_t;
177 
178 /** Type of dma_int_clr register
179  *  Interrupt clear bits
180  */
181 typedef union {
182     struct {
183         /** dma_in_done_int_clr : WO; bitpos: [0]; default: 0;
184          *  Set this bit to clear cp_in_done_int interrupt.
185          */
186         uint32_t dma_in_done_int_clr: 1;
187         /** dma_in_suc_eof_int_clr : WO; bitpos: [1]; default: 0;
188          *  Set this bit to clear cp_in_suc_eof_int interrupt.
189          */
190         uint32_t dma_in_suc_eof_int_clr: 1;
191         /** dma_out_done_int_clr : WO; bitpos: [2]; default: 0;
192          *  Set this bit to clear cp_out_done_int interrupt.
193          */
194         uint32_t dma_out_done_int_clr: 1;
195         /** dma_out_eof_int_clr : WO; bitpos: [3]; default: 0;
196          *  Set this bit to clear cp_out_eof_int interrupt.
197          */
198         uint32_t dma_out_eof_int_clr: 1;
199         /** dma_in_dscr_err_int_clr : WO; bitpos: [4]; default: 0;
200          *  Set this bit to clear cp_in_dscr_err_int interrupt.
201          */
202         uint32_t dma_in_dscr_err_int_clr: 1;
203         /** dma_out_dscr_err_int_clr : WO; bitpos: [5]; default: 0;
204          *  Set this bit to clear cp_out_dscr_err_int interrupt.
205          */
206         uint32_t dma_out_dscr_err_int_clr: 1;
207         /** dma_in_dscr_empty_int_clr : WO; bitpos: [6]; default: 0;
208          *  Set this bit to clear cp_in_dscr_empty_int interrupt.
209          */
210         uint32_t dma_in_dscr_empty_int_clr: 1;
211         /** dma_out_total_eof_int_clr : WO; bitpos: [7]; default: 0;
212          *  Set this bit to clear cp_out_total_eof_int interrupt.
213          */
214         uint32_t dma_out_total_eof_int_clr: 1;
215         /** dma_crc_done_int_clr : WO; bitpos: [8]; default: 0;
216          *  Set this bit to clear cp_crc_done_int interrupt.
217          */
218         uint32_t dma_crc_done_int_clr: 1;
219         uint32_t reserved9: 23;
220     };
221     uint32_t val;
222 } cp_dma_int_clr_reg_t;
223 
224 
225 /** Configuration Registers */
226 /** Type of dma_out_link register
227  *  Link descriptor address and control
228  */
229 typedef union {
230     struct {
231         /** dma_outlink_addr : R/W; bitpos: [19:0]; default: 0;
232          *  This register is used to specify the least significant 20 bits of the first outlink
233          *  descriptor's address.
234          */
235         uint32_t dma_outlink_addr: 20;
236         uint32_t reserved_20: 8;
237         /** dma_outlink_stop : R/W; bitpos: [28]; default: 0;
238          *  Set this bit to stop dealing with the outlink descriptor.
239          */
240         uint32_t dma_outlink_stop: 1;
241         /** dma_outlink_start : R/W; bitpos: [29]; default: 0;
242          *  Set this bit to start a new outlink descriptor.
243          */
244         uint32_t dma_outlink_start: 1;
245         /** dma_outlink_restart : R/W; bitpos: [30]; default: 0;
246          *  Set this bit to restart the outlink descriptpr from the last address.
247          */
248         uint32_t dma_outlink_restart: 1;
249         /** dma_outlink_park : RO; bitpos: [31]; default: 0;
250          *  1: the outlink descriptor's FSM is in idle state.
251          *  0: the outlink descriptor's FSM is working.
252          */
253         uint32_t dma_outlink_park: 1;
254     };
255     uint32_t val;
256 } cp_dma_out_link_reg_t;
257 
258 /** Type of dma_in_link register
259  *  Link descriptor address and control
260  */
261 typedef union {
262     struct {
263         /** dma_inlink_addr : R/W; bitpos: [19:0]; default: 0;
264          *  This register is used to specify the least significant 20 bits of the first inlink
265          *  descriptor's address.
266          */
267         uint32_t dma_inlink_addr: 20;
268         uint32_t reserved_20: 8;
269         /** dma_inlink_stop : R/W; bitpos: [28]; default: 0;
270          *  Set this bit to stop dealing with the inlink descriptors.
271          */
272         uint32_t dma_inlink_stop: 1;
273         /** dma_inlink_start : R/W; bitpos: [29]; default: 0;
274          *  Set this bit to start dealing with the inlink descriptors.
275          */
276         uint32_t dma_inlink_start: 1;
277         /** dma_inlink_restart : R/W; bitpos: [30]; default: 0;
278          *  Set this bit to restart new inlink descriptors.
279          */
280         uint32_t dma_inlink_restart: 1;
281         /** dma_inlink_park : RO; bitpos: [31]; default: 0;
282          *  1: the inlink descriptor's FSM is in idle state.
283          *  0: the inlink descriptor's FSM is working.
284          */
285         uint32_t dma_inlink_park: 1;
286     };
287     uint32_t val;
288 } cp_dma_in_link_reg_t;
289 
290 /** Type of dma_conf register
291  *  Copy DMA configuration register
292  */
293 typedef union {
294     struct {
295         /** dma_in_rst : R/W; bitpos: [0]; default: 0;
296          *  Set this bit to reset in_inf state machine.
297          */
298         uint32_t dma_in_rst: 1;
299         /** dma_out_rst : R/W; bitpos: [1]; default: 0;
300          *  Set this bit to reset out_inf state machine.
301          */
302         uint32_t dma_out_rst: 1;
303         /** dma_cmdfifo_rst : R/W; bitpos: [2]; default: 0;
304          *  Set this bit to reset in_cmd fifo and out_cmd fifo.
305          */
306         uint32_t dma_cmdfifo_rst: 1;
307         /** dma_fifo_rst : R/W; bitpos: [3]; default: 0;
308          *  Set this bit to reset data in receive FIFO.
309          */
310         uint32_t dma_fifo_rst: 1;
311         /** dma_out_owner : R/W; bitpos: [4]; default: 0;
312          *  This is used to configure the owner bit in OUT descriptor. This is effective only
313          *  when you set reg_out_auto_wrback.
314          */
315         uint32_t dma_out_owner: 1;
316         /** dma_in_owner : R/W; bitpos: [5]; default: 0;
317          *  This is used to configure the owner bit in IN descriptor.
318          */
319         uint32_t dma_in_owner: 1;
320         /** dma_out_auto_wrback : R/W; bitpos: [6]; default: 0;
321          *  This bit is used to write back out descriptor when hardware has already used this
322          *  descriptor.
323          */
324         uint32_t dma_out_auto_wrback: 1;
325         /** dma_check_owner : R/W; bitpos: [7]; default: 0;
326          *  Set this bit to enable owner bit check in descriptor.
327          */
328         uint32_t dma_check_owner: 1;
329         /** dma_crc_cal_reset : R/W; bitpos: [8]; default: 0;
330          *  Set this bit to reset crc calculation.
331          */
332         uint32_t dma_crc_cal_reset: 1;
333         /** dma_crc_cal_en : R/W; bitpos: [9]; default: 0;
334          *  Set this bit enable crc calculation function.
335          */
336         uint32_t dma_crc_cal_en: 1;
337         /** dma_crc_big_endian_en : R/W; bitpos: [10]; default: 0;
338          *  Set this bit to reorder the bit of data which will be send to excute crc.
339          */
340         uint32_t dma_crc_big_endian_en: 1;
341         /** dma_crc_out_reverse_en : R/W; bitpos: [11]; default: 0;
342          *  Set this bit to reverse the crc calculation result.
343          */
344         uint32_t dma_crc_out_reverse_en: 1;
345         uint32_t reserved_12: 19;
346         /** dma_clk_en : R/W; bitpos: [31]; default: 0;
347          *  1'b1: Force clock on for register. 1'b0: Support clock only when application writes
348          *  registers.
349          */
350         uint32_t dma_clk_en: 1;
351     };
352     uint32_t val;
353 } cp_dma_conf_reg_t;
354 
355 
356 /** Status Registers */
357 /** Type of dma_out_eof_des_addr register
358  *  Outlink descriptor address when EOF occurs
359  */
360 typedef union {
361     struct {
362         /** dma_out_eof_des_addr : RO; bitpos: [31:0]; default: 0;
363          *  This register stores the address of the outlink descriptor when the EOF bit in this
364          *  descriptor is 1.
365          */
366         uint32_t dma_out_eof_des_addr: 32;
367     };
368     uint32_t val;
369 } cp_dma_out_eof_des_addr_reg_t;
370 
371 /** Type of dma_in_eof_des_addr register
372  *  Inlink descriptor address when EOF occurs
373  */
374 typedef union {
375     struct {
376         /** dma_in_suc_eof_des_addr : RO; bitpos: [31:0]; default: 0;
377          *  This register stores the address of the inlink descriptor when received successful
378          *  EOF.
379          */
380         uint32_t dma_in_suc_eof_des_addr: 32;
381     };
382     uint32_t val;
383 } cp_dma_in_eof_des_addr_reg_t;
384 
385 /** Type of dma_out_eof_bfr_des_addr register
386  *  Outlink descriptor address before the last outlink descriptor
387  */
388 typedef union {
389     struct {
390         /** dma_out_eof_bfr_des_addr : RO; bitpos: [31:0]; default: 0;
391          *  This register stores the address of the outlink descriptor before the last outlink
392          *  descriptor.
393          */
394         uint32_t dma_out_eof_bfr_des_addr: 32;
395     };
396     uint32_t val;
397 } cp_dma_out_eof_bfr_des_addr_reg_t;
398 
399 /** Type of dma_inlink_dscr register
400  *  Address of current inlink descriptor
401  */
402 typedef union {
403     struct {
404         /** dma_inlink_dscr : RO; bitpos: [31:0]; default: 0;
405          *  The address of the current inlink descriptor x.
406          */
407         uint32_t dma_inlink_dscr: 32;
408     };
409     uint32_t val;
410 } cp_dma_inlink_dscr_reg_t;
411 
412 /** Type of dma_inlink_dscr_bf0 register
413  *  Address of last inlink descriptor
414  */
415 typedef union {
416     struct {
417         /** dma_inlink_dscr_bf0 : RO; bitpos: [31:0]; default: 0;
418          *  The address of the last inlink descriptor x-1.
419          */
420         uint32_t dma_inlink_dscr_bf0: 32;
421     };
422     uint32_t val;
423 } cp_dma_inlink_dscr_bf0_reg_t;
424 
425 /** Type of dma_inlink_dscr_bf1 register
426  *  Address of the second-to-last inlink descriptor
427  */
428 typedef union {
429     struct {
430         /** dma_inlink_dscr_bf1 : RO; bitpos: [31:0]; default: 0;
431          *  The address of the second-to-last inlink descriptor x-2.
432          */
433         uint32_t dma_inlink_dscr_bf1: 32;
434     };
435     uint32_t val;
436 } cp_dma_inlink_dscr_bf1_reg_t;
437 
438 /** Type of dma_outlink_dscr register
439  *  Address of current outlink descriptor
440  */
441 typedef union {
442     struct {
443         /** dma_outlink_dscr : RO; bitpos: [31:0]; default: 0;
444          *  The address of the current outlink descriptor y.
445          */
446         uint32_t dma_outlink_dscr: 32;
447     };
448     uint32_t val;
449 } cp_dma_outlink_dscr_reg_t;
450 
451 /** Type of dma_outlink_dscr_bf0 register
452  *  Address of last outlink descriptor
453  */
454 typedef union {
455     struct {
456         /** dma_outlink_dscr_bf0 : RO; bitpos: [31:0]; default: 0;
457          *  The address of the last outlink descriptor y-1.
458          */
459         uint32_t dma_outlink_dscr_bf0: 32;
460     };
461     uint32_t val;
462 } cp_dma_outlink_dscr_bf0_reg_t;
463 
464 /** Type of dma_outlink_dscr_bf1 register
465  *  Address of the second-to-last outlink descriptor
466  */
467 typedef union {
468     struct {
469         /** dma_outlink_dscr_bf1 : RO; bitpos: [31:0]; default: 0;
470          *  The address of the second-to-last outlink descriptor y-2.
471          */
472         uint32_t dma_outlink_dscr_bf1: 32;
473     };
474     uint32_t val;
475 } cp_dma_outlink_dscr_bf1_reg_t;
476 
477 /** Type of dma_in_st register
478  *  Status register of receiving data
479  */
480 typedef union {
481     struct {
482         /** dma_inlink_dscr_addr : RO; bitpos: [17:0]; default: 0;
483          *  This register stores the current inlink descriptor's address.
484          */
485         uint32_t dma_inlink_dscr_addr: 18;
486         /** dma_in_dscr_state : RO; bitpos: [19:18]; default: 0;
487          *  Reserved.
488          */
489         uint32_t dma_in_dscr_state: 2;
490         /** dma_in_state : RO; bitpos: [22:20]; default: 0;
491          *  Reserved.
492          */
493         uint32_t dma_in_state: 3;
494         /** dma_fifo_empty : RO; bitpos: [23]; default: 0;
495          *  Copy DMA FIFO empty signal.
496          */
497         uint32_t dma_fifo_empty: 1;
498         uint32_t reserved24: 8;
499     };
500     uint32_t val;
501 } cp_dma_in_st_reg_t;
502 
503 /** Type of dma_out_st register
504  *  Status register of transmitting data
505  */
506 typedef union {
507     struct {
508         /** dma_outlink_dscr_addr : RO; bitpos: [17:0]; default: 0;
509          *  This register stores the current outlink descriptor's address.
510          */
511         uint32_t dma_outlink_dscr_addr: 18;
512         /** dma_out_dscr_state : RO; bitpos: [19:18]; default: 0;
513          *  Reserved.
514          */
515         uint32_t dma_out_dscr_state: 2;
516         /** dma_out_state : RO; bitpos: [22:20]; default: 0;
517          *  Reserved.
518          */
519         uint32_t dma_out_state: 3;
520         /** dma_fifo_full : RO; bitpos: [23]; default: 0;
521          *  Copy DMA FIFO full signal.
522          */
523         uint32_t dma_fifo_full: 1;
524         uint32_t reserved24: 8;
525     };
526     uint32_t val;
527 } cp_dma_out_st_reg_t;
528 
529 /** Type of dma_crc_out register
530  *  CRC result register
531  */
532 typedef union {
533     struct {
534         /** dma_crc_result : RO; bitpos: [31:0]; default: 0;
535          *  This register stores the result of CRC.
536          */
537         uint32_t dma_crc_result: 32;
538     };
539     uint32_t val;
540 } cp_dma_crc_out_reg_t;
541 
542 /** Type of dma_date register
543  *  Copy DMA version register
544  */
545 typedef union {
546     struct {
547         /** dma_dma_date : R/W; bitpos: [31:0]; default: 403185664;
548          *  This is the version register.
549          */
550         uint32_t dma_dma_date: 32;
551     };
552     uint32_t val;
553 } cp_dma_date_reg_t;
554 
555 
556 typedef struct {
557     volatile cp_dma_int_raw_reg_t dma_int_raw;
558     volatile cp_dma_int_st_reg_t dma_int_st;
559     volatile cp_dma_int_ena_reg_t dma_int_ena;
560     volatile cp_dma_int_clr_reg_t dma_int_clr;
561     volatile cp_dma_out_link_reg_t dma_out_link;
562     volatile cp_dma_in_link_reg_t dma_in_link;
563     volatile cp_dma_out_eof_des_addr_reg_t dma_out_eof_des_addr;
564     volatile cp_dma_in_eof_des_addr_reg_t dma_in_eof_des_addr;
565     volatile cp_dma_out_eof_bfr_des_addr_reg_t dma_out_eof_bfr_des_addr;
566     volatile cp_dma_inlink_dscr_reg_t dma_inlink_dscr;
567     volatile cp_dma_inlink_dscr_bf0_reg_t dma_inlink_dscr_bf0;
568     volatile cp_dma_inlink_dscr_bf1_reg_t dma_inlink_dscr_bf1;
569     volatile cp_dma_outlink_dscr_reg_t dma_outlink_dscr;
570     volatile cp_dma_outlink_dscr_bf0_reg_t dma_outlink_dscr_bf0;
571     volatile cp_dma_outlink_dscr_bf1_reg_t dma_outlink_dscr_bf1;
572     volatile cp_dma_conf_reg_t dma_conf;
573     volatile cp_dma_in_st_reg_t dma_in_st;
574     volatile cp_dma_out_st_reg_t dma_out_st;
575     volatile cp_dma_crc_out_reg_t dma_crc_out;
576     uint32_t reserved_04c;
577     uint32_t reserved_050;
578     uint32_t reserved_054;
579     uint32_t reserved_058;
580     uint32_t reserved_05c;
581     uint32_t reserved_060;
582     uint32_t reserved_064;
583     uint32_t reserved_068;
584     uint32_t reserved_06c;
585     uint32_t reserved_070;
586     uint32_t reserved_074;
587     uint32_t reserved_078;
588     uint32_t reserved_07c;
589     uint32_t reserved_080;
590     uint32_t reserved_084;
591     uint32_t reserved_088;
592     uint32_t reserved_08c;
593     uint32_t reserved_090;
594     uint32_t reserved_094;
595     uint32_t reserved_098;
596     uint32_t reserved_09c;
597     uint32_t reserved_0a0;
598     uint32_t reserved_0a4;
599     uint32_t reserved_0a8;
600     uint32_t reserved_0ac;
601     uint32_t reserved_0b0;
602     uint32_t reserved_0b4;
603     uint32_t reserved_0b8;
604     uint32_t reserved_0bc;
605     uint32_t reserved_0c0;
606     uint32_t reserved_0c4;
607     uint32_t reserved_0c8;
608     uint32_t reserved_0cc;
609     uint32_t reserved_0d0;
610     uint32_t reserved_0d4;
611     uint32_t reserved_0d8;
612     uint32_t reserved_0dc;
613     uint32_t reserved_0e0;
614     uint32_t reserved_0e4;
615     uint32_t reserved_0e8;
616     uint32_t reserved_0ec;
617     uint32_t reserved_0f0;
618     uint32_t reserved_0f4;
619     uint32_t reserved_0f8;
620     volatile cp_dma_date_reg_t dma_date;
621 } cp_dma_dev_t;
622 
623 _Static_assert(sizeof(cp_dma_dev_t) == 0x100, "cp_dma_dev_t should occupy 0x100 bytes in memory");
624 
625 extern cp_dma_dev_t CP_DMA;
626 
627 #ifdef __cplusplus
628 }
629 #endif
630