| /hal_espressif-3.4.0/components/hal/esp32/include/hal/ |
| D | rmt_ll.h | 123 HAL_FORCE_MODIFY_U32_REG_FIELD(dev->conf_ch[channel].conf0, div_cnt, div); in rmt_ll_tx_set_channel_clock_div()
128 HAL_FORCE_MODIFY_U32_REG_FIELD(dev->conf_ch[channel].conf0, div_cnt, div); in rmt_ll_rx_set_channel_clock_div()
133 uint32_t div = HAL_FORCE_READ_U32_REG_FIELD(dev->conf_ch[channel].conf0, div_cnt); in rmt_ll_tx_get_channel_clock_div()
139 uint32_t div = HAL_FORCE_READ_U32_REG_FIELD(dev->conf_ch[channel].conf0, div_cnt); in rmt_ll_rx_get_channel_clock_div()
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| /hal_espressif-3.4.0/components/hal/esp32s2/include/hal/ |
| D | rmt_ll.h | 125 HAL_FORCE_MODIFY_U32_REG_FIELD(dev->conf_ch[channel].conf0, div_cnt, div); in rmt_ll_tx_set_channel_clock_div()
130 HAL_FORCE_MODIFY_U32_REG_FIELD(dev->conf_ch[channel].conf0, div_cnt, div); in rmt_ll_rx_set_channel_clock_div()
135 uint32_t div = HAL_FORCE_READ_U32_REG_FIELD(dev->conf_ch[channel].conf0, div_cnt); in rmt_ll_tx_get_channel_clock_div()
141 uint32_t div = HAL_FORCE_READ_U32_REG_FIELD(dev->conf_ch[channel].conf0, div_cnt); in rmt_ll_rx_get_channel_clock_div()
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| /hal_espressif-3.4.0/components/hal/esp32c3/include/hal/ |
| D | rmt_ll.h | 140 HAL_FORCE_MODIFY_U32_REG_FIELD(dev->tx_conf[channel], div_cnt, div); in rmt_ll_tx_set_channel_clock_div()
145 HAL_FORCE_MODIFY_U32_REG_FIELD(dev->rx_conf[channel].conf0, div_cnt, div); in rmt_ll_rx_set_channel_clock_div()
150 return HAL_FORCE_READ_U32_REG_FIELD(dev->tx_conf[channel], div_cnt); in rmt_ll_tx_get_channel_clock_div()
155 return HAL_FORCE_READ_U32_REG_FIELD(dev->rx_conf[channel].conf0, div_cnt); in rmt_ll_rx_get_channel_clock_div()
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| /hal_espressif-3.4.0/components/hal/esp32h2/include/hal/ |
| D | rmt_ll.h | 139 HAL_FORCE_MODIFY_U32_REG_FIELD(dev->tx_conf[channel], div_cnt, div); in rmt_ll_tx_set_channel_clock_div()
144 HAL_FORCE_MODIFY_U32_REG_FIELD(dev->rx_conf[channel].conf0, div_cnt, div); in rmt_ll_rx_set_channel_clock_div()
149 return HAL_FORCE_READ_U32_REG_FIELD(dev->tx_conf[channel], div_cnt); in rmt_ll_tx_get_channel_clock_div()
154 return HAL_FORCE_READ_U32_REG_FIELD(dev->rx_conf[channel].conf0, div_cnt); in rmt_ll_rx_get_channel_clock_div()
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| /hal_espressif-3.4.0/components/soc/esp32h2/include/soc/ |
| D | rmt_struct.h | 35 uint32_t div_cnt: 8; member
50 uint32_t div_cnt: 8; member
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| /hal_espressif-3.4.0/components/soc/esp32c3/include/soc/ |
| D | rmt_struct.h | 35 uint32_t div_cnt: 8; member
50 uint32_t div_cnt: 8; member
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| /hal_espressif-3.4.0/components/driver/include/driver/ |
| D | rmt.h | 177 esp_err_t rmt_set_clk_div(rmt_channel_t channel, uint8_t div_cnt);
189 esp_err_t rmt_get_clk_div(rmt_channel_t channel, uint8_t *div_cnt);
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| /hal_espressif-3.4.0/components/driver/test/ |
| D | test_rmt.c | 134 uint8_t div_cnt; variable
148 TEST_ESP_OK(rmt_get_clk_div(channel, &div_cnt));
149 TEST_ASSERT_EQUAL_UINT8(160, div_cnt);
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| /hal_espressif-3.4.0/components/driver/ |
| D | rmt.c | 143 esp_err_t rmt_set_clk_div(rmt_channel_t channel, uint8_t div_cnt) in rmt_set_clk_div() argument
148 … rmt_ll_rx_set_channel_clock_div(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel), div_cnt); in rmt_set_clk_div()
150 rmt_ll_tx_set_channel_clock_div(rmt_contex.hal.regs, channel, div_cnt); in rmt_set_clk_div()
156 esp_err_t rmt_get_clk_div(rmt_channel_t channel, uint8_t *div_cnt) in rmt_get_clk_div() argument
159 ESP_RETURN_ON_FALSE(div_cnt, ESP_ERR_INVALID_ARG, TAG, RMT_ADDR_ERROR_STR); in rmt_get_clk_div()
162 …*div_cnt = (uint8_t)rmt_ll_rx_get_channel_clock_div(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(cha… in rmt_get_clk_div()
164 *div_cnt = (uint8_t)rmt_ll_tx_get_channel_clock_div(rmt_contex.hal.regs, channel); in rmt_get_clk_div()
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| /hal_espressif-3.4.0/components/soc/esp32/include/soc/ |
| D | rmt_struct.h | 30 …uint32_t div_cnt: 8; /*This register is used to configure the frequency divide… member
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| /hal_espressif-3.4.0/components/soc/esp32s2/include/soc/ |
| D | rmt_struct.h | 38 uint32_t div_cnt: 8; member
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