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/hal_espressif-3.4.0/components/esp_hw_support/test/
Dtest_fp.c215 float IRAM_ATTR test_fp_benchmark_fp_divide(int counts, unsigned *cycles) in test_fp_benchmark_fp_divide() argument
226 *cycles = (after - before) / counts; in test_fp_benchmark_fp_divide()
234 unsigned cycles = 0; variable
239 float f = test_fp_benchmark_fp_divide(COUNTS, &cycles);
242 printf("Per division = %d cycles\n", cycles);
244 TEST_PERFORMANCE_LESS_THAN(CYCLES_PER_DIV, "%d cycles", cycles);
248 float IRAM_ATTR test_fp_benchmark_fp_sqrt(int counts, unsigned *cycles) in test_fp_benchmark_fp_sqrt() argument
259 *cycles = (after - before) / counts; in test_fp_benchmark_fp_sqrt()
267 unsigned cycles = 0; variable
272 float f = test_fp_benchmark_fp_sqrt(COUNTS, &cycles);
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/hal_espressif-3.4.0/docs/en/api-guides/
Dulp_instruction_set.rst10 …ns which work with peripherals (TSENS, ADC, I2C) take variable number of cycles, depending on peri…
76 …LP coprocessor needs certain number of clock cycles to fetch each instruction, plus certain number…
80 - 2 clock cycles — for instructions following ALU and branch instructions.
81 - 4 clock cycles — in other cases.
94 2 cycle to execute, 4 cycles to fetch next instruction
119 2 cycles to execute, 4 cycles to fetch next instruction
155 2 cycles to execute, 4 cycles to fetch next instruction
189 2 cycles to execute, 4 cycles to fetch next instruction
224 2 cycles to execute, 4 cycles to fetch next instruction
260 2 cycles to execute, 4 cycles to fetch next instruction
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Dulps2_instruction_set.rst10 …ns which work with peripherals (TSENS, ADC, I2C) take variable number of cycles, depending on peri…
78 …LP coprocessor needs certain number of clock cycles to fetch each instruction, plus certain number…
82 - 2 clock cycles — for instructions following ALU and branch instructions.
83 - 4 clock cycles — in other cases.
105 2 cycle to execute, 4 cycles to fetch next instruction
130 2 cycles to execute, 4 cycles to fetch next instruction
166 2 cycles to execute, 4 cycles to fetch next instruction
200 2 cycles to execute, 4 cycles to fetch next instruction
235 2 cycles to execute, 4 cycles to fetch next instruction
270 2 cycles to execute, 4 cycles to fetch next instruction
[all …]
/hal_espressif-3.4.0/examples/system/perfmon/
DREADME.md40 Value = 750, select = 0, mask = 0001. Counts cycles.
41 Amount of cycles
86 Value = 0, select = 3, mask = 0002. Data-related GlobalStall cycles.
88 Value = 0, select = 3, mask = 0004. Data-related GlobalStall cycles.
90 Value = 0, select = 3, mask = 0008. Data-related GlobalStall cycles.
92 Value = 0, select = 3, mask = 0010. Data-related GlobalStall cycles.
94 Value = 0, select = 3, mask = 0020. Data-related GlobalStall cycles.
96 Value = 0, select = 3, mask = 0040. Data-related GlobalStall cycles.
98 Value = 0, select = 3, mask = 0080. Data-related GlobalStall cycles.
100 Value = 0, select = 3, mask = 0100. Data-related GlobalStall cycles.
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/hal_espressif-3.4.0/components/xtensa/include/xtensa/
Dxtruntime.h218 extern void _xtos_timer_0_delta( int cycles );
221 extern void _xtos_timer_1_delta( int cycles );
224 extern void _xtos_timer_2_delta( int cycles );
227 extern void _xtos_timer_3_delta( int cycles );
/hal_espressif-3.4.0/components/soc/esp32s2/include/soc/
Drtc.h58 #define RTC_SLOW_CLK_X32K_CAL_TIMEOUT_THRES(cycles) (cycles << 12) argument
59 #define RTC_SLOW_CLK_8MD256_CAL_TIMEOUT_THRES(cycles) (cycles << 12) argument
60 #define RTC_SLOW_CLK_90K_CAL_TIMEOUT_THRES(cycles) (cycles << 10) argument
/hal_espressif-3.4.0/components/soc/esp32c3/include/soc/
Drtc.h50 #define RTC_SLOW_CLK_X32K_CAL_TIMEOUT_THRES(cycles) (cycles << 12) argument
51 #define RTC_SLOW_CLK_8MD256_CAL_TIMEOUT_THRES(cycles) (cycles << 12) argument
52 #define RTC_SLOW_CLK_150K_CAL_TIMEOUT_THRES(cycles) (cycles << 10) argument
/hal_espressif-3.4.0/components/soc/esp32s3/include/soc/
Drtc.h51 #define RTC_SLOW_CLK_X32K_CAL_TIMEOUT_THRES(cycles) (cycles << 12) argument
52 #define RTC_SLOW_CLK_8MD256_CAL_TIMEOUT_THRES(cycles) (cycles << 12) argument
53 #define RTC_SLOW_CLK_150K_CAL_TIMEOUT_THRES(cycles) (cycles << 10) argument
/hal_espressif-3.4.0/components/soc/esp32h2/include/soc/
Drtc.h56 #define RTC_SLOW_CLK_X32K_CAL_TIMEOUT_THRES(cycles) (cycles << 12) argument
57 #define RTC_SLOW_CLK_RC32K_CAL_TIMEOUT_THRES(cycles) (cycles << 12) argument
58 #define RTC_SLOW_CLK_150K_CAL_TIMEOUT_THRES(cycles) (cycles << 10) argument
/hal_espressif-3.4.0/components/ulp/ulp_riscv/
Dulp_riscv_utils.c43 void ulp_riscv_delay_cycles(uint32_t cycles) in ulp_riscv_delay_cycles() argument
47 while ((ULP_RISCV_GET_CCOUNT() - start) < cycles) { in ulp_riscv_delay_cycles()
/hal_espressif-3.4.0/tools/unit-test-app/components/test_utils/
Dccomp_timer_impl_riscv.c91 int64_t cycles = s_status[cpu_hal_get_core_id()].ccount; in ccomp_timer_impl_get_time() local
92 return (cycles * 1000000) / esp_clk_cpu_freq(); in ccomp_timer_impl_get_time()
Dccomp_timer_impl_xtensa.c194 int64_t cycles = s_status[xPortGetCoreID()].ccount; in ccomp_timer_impl_get_time() local
195 return ((cycles - stalls) * 1000000) / esp_clk_cpu_freq(); in ccomp_timer_impl_get_time()
/hal_espressif-3.4.0/components/ulp/include/esp32s2/
Dulp.h121 uint32_t cycles : 16; /*!< Number of cycles to sleep */ member
212 uint32_t cycles : 16; /*!< TBD, cycles used for measurement */ member
266 .cycles = cycles_, \
422 .cycles = 0, \
/hal_espressif-3.4.0/components/ulp/include/esp32s3/
Dulp.h121 uint32_t cycles : 16; /*!< Number of cycles to sleep */ member
212 uint32_t cycles : 16; /*!< TBD, cycles used for measurement */ member
266 .cycles = cycles_, \
423 .cycles = 0, \
/hal_espressif-3.4.0/components/bt/controller/esp32c3/
Dbt.c173 uint32_t (* _btdm_lpcycles_2_hus)(uint32_t cycles, uint32_t *error_corr);
300 static uint32_t IRAM_ATTR btdm_lpcycles_2_hus(uint32_t cycles, uint32_t *error_corr);
627 static uint32_t IRAM_ATTR btdm_lpcycles_2_hus(uint32_t cycles, uint32_t *error_corr) in btdm_lpcycles_2_hus() argument
630 uint64_t res = (uint64_t)btdm_lpcycle_us * cycles * 2; in btdm_lpcycles_2_hus()
648 uint64_t cycles = ((uint64_t)(hus) << btdm_lpcycle_us_frac) / btdm_lpcycle_us; in btdm_hus_2_lpcycles() local
649 cycles >>= 1; in btdm_hus_2_lpcycles()
651 return (uint32_t)cycles; in btdm_hus_2_lpcycles()
/hal_espressif-3.4.0/components/bt/controller/esp32s3/
Dbt.c172 uint32_t (* _btdm_lpcycles_2_hus)(uint32_t cycles, uint32_t *error_corr);
298 static uint32_t IRAM_ATTR btdm_lpcycles_2_hus(uint32_t cycles, uint32_t *error_corr);
614 static uint32_t IRAM_ATTR btdm_lpcycles_2_hus(uint32_t cycles, uint32_t *error_corr) in btdm_lpcycles_2_hus() argument
617 uint64_t res = (uint64_t)btdm_lpcycle_us * cycles * 2; in btdm_lpcycles_2_hus()
635 uint64_t cycles = ((uint64_t)(hus) << btdm_lpcycle_us_frac) / btdm_lpcycle_us; in btdm_hus_2_lpcycles() local
636 cycles >>= 1; in btdm_hus_2_lpcycles()
638 return (uint32_t)cycles; in btdm_hus_2_lpcycles()
/hal_espressif-3.4.0/zephyr/esp32c3/src/bt/
Desp_bt_adapter.c150 uint32_t (* _btdm_lpcycles_2_hus)(uint32_t cycles, uint32_t *error_corr);
250 static uint32_t btdm_lpcycles_2_hus(uint32_t cycles, uint32_t *error_corr);
706 static uint32_t IRAM_ATTR btdm_lpcycles_2_hus(uint32_t cycles, uint32_t *error_corr) in btdm_lpcycles_2_hus() argument
709 uint64_t res = (uint64_t)btdm_lpcycle_us * cycles * 2; in btdm_lpcycles_2_hus()
728 uint64_t cycles = ((uint64_t)(hus) << btdm_lpcycle_us_frac) / btdm_lpcycle_us; in btdm_hus_2_lpcycles() local
729 cycles >>= 1; in btdm_hus_2_lpcycles()
731 return (uint32_t)cycles; in btdm_hus_2_lpcycles()
/hal_espressif-3.4.0/zephyr/esp32s3/src/bt/
Desp_bt_adapter.c149 uint32_t (* _btdm_lpcycles_2_hus)(uint32_t cycles, uint32_t *error_corr);
249 static uint32_t btdm_lpcycles_2_hus(uint32_t cycles, uint32_t *error_corr);
697 static uint32_t IRAM_ATTR btdm_lpcycles_2_hus(uint32_t cycles, uint32_t *error_corr) in btdm_lpcycles_2_hus() argument
700 uint64_t res = (uint64_t)btdm_lpcycle_us * cycles * 2; in btdm_lpcycles_2_hus()
719 uint64_t cycles = ((uint64_t)(hus) << btdm_lpcycle_us_frac) / btdm_lpcycle_us; in btdm_hus_2_lpcycles() local
720 cycles >>= 1; in btdm_hus_2_lpcycles()
722 return (uint32_t)cycles; in btdm_hus_2_lpcycles()
/hal_espressif-3.4.0/components/hal/
Dspi_flash_hal_common.inc96 * transaction. We have to output all ones in these cycles because we don't need this feature.
123 // Add dummy cycles to compensate for latency of GPIO matrix and external delay, if necessary...
153 //No extra dummy cycles for compensation if no input data
/hal_espressif-3.4.0/zephyr/esp32/src/bt/
Desp_bt_adapter.c123 uint32_t (*_btdm_lpcycles_2_us)(uint32_t cycles);
234 static uint32_t btdm_lpcycles_2_us(uint32_t cycles);
684 static uint32_t IRAM_ATTR btdm_lpcycles_2_us(uint32_t cycles) in btdm_lpcycles_2_us() argument
688 uint64_t us = (uint64_t)btdm_lpcycle_us * cycles; in btdm_lpcycles_2_us()
702 uint64_t cycles = ((uint64_t)(us) << btdm_lpcycle_us_frac) / btdm_lpcycle_us; in btdm_us_2_lpcycles() local
704 return (uint32_t)cycles; in btdm_us_2_lpcycles()
/hal_espressif-3.4.0/components/ulp/ulp_riscv/include/ulp_riscv/
Dulp_riscv_utils.h77 void ulp_riscv_delay_cycles(uint32_t cycles);
/hal_espressif-3.4.0/components/ulp/include/esp32/
Dulp.h133 uint32_t cycles : 16; /*!< Number of cycles to sleep */ member
243 uint32_t cycles : 16; /*!< TBD, cycles used for measurement */ member
300 .cycles = cycles_, \
456 .cycles = 0, \
/hal_espressif-3.4.0/components/bt/controller/esp32/
Dbt.c159 uint32_t (* _btdm_lpcycles_2_us)(uint32_t cycles);
314 static uint32_t IRAM_ATTR btdm_lpcycles_2_us(uint32_t cycles);
1061 static uint32_t IRAM_ATTR btdm_lpcycles_2_us(uint32_t cycles) in btdm_lpcycles_2_us() argument
1065 uint64_t us = (uint64_t)btdm_lpcycle_us * cycles; in btdm_lpcycles_2_us()
1078 uint64_t cycles = ((uint64_t)(us) << btdm_lpcycle_us_frac) / btdm_lpcycle_us; in btdm_us_2_lpcycles() local
1080 return (uint32_t)cycles; in btdm_us_2_lpcycles()
/hal_espressif-3.4.0/components/esp32c3/
DKconfig158 int "Number of cycles for RTC_SLOW_CLK calibration"
166 frequency. This option sets the number of RTC_SLOW_CLK cycles measured
/hal_espressif-3.4.0/docs/en/api-reference/protocols/
Desp_spi_slave_protocol.rst62 In some IO modes, more data wires can be use to send the data. As a result, the SPI clock cycles
68 | Mode | command WN | address WN | dummy cycles | data WN |

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