1 // Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 // 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 #ifndef _SOC_EXTMEM_STRUCT_H_ 15 #define _SOC_EXTMEM_STRUCT_H_ 16 17 18 #include <stdint.h> 19 #ifdef __cplusplus 20 extern "C" { 21 #endif 22 23 typedef volatile struct extmem_dev_s { 24 union { 25 struct { 26 uint32_t dcache_enable : 1; /*The bit is used to activate the data cache. 0: disable, 1: enable*/ 27 uint32_t reserved1 : 1; /*Reserved*/ 28 uint32_t dcache_size_mode : 1; /*The bit is used to configure cache memory size.0: 32KB, 1: 64KB*/ 29 uint32_t dcache_blocksize_mode : 2; /*The bit is used to configure cache block size.0: 16 bytes, 1: 32 bytes,2: 64 bytes*/ 30 uint32_t reserved5 : 27; 31 }; 32 uint32_t val; 33 } dcache_ctrl; 34 union { 35 struct { 36 uint32_t dcache_shut_core0_bus : 1; /*The bit is used to disable core0 dbus, 0: enable, 1: disable*/ 37 uint32_t dcache_shut_core1_bus : 1; /*The bit is used to disable core1 dbus, 0: enable, 1: disable*/ 38 uint32_t reserved2 : 30; 39 }; 40 uint32_t val; 41 } dcache_ctrl1; 42 union { 43 struct { 44 uint32_t dcache_tag_mem_force_on : 1; /*The bit is used to close clock gating of dcache tag memory. 1: close gating, 0: open clock gating.*/ 45 uint32_t dcache_tag_mem_force_pd : 1; /*The bit is used to power dcache tag memory down, 0: follow rtc_lslp_pd, 1: power down*/ 46 uint32_t dcache_tag_mem_force_pu : 1; /*The bit is used to power dcache tag memory up, 0: follow rtc_lslp_pd, 1: power up*/ 47 uint32_t reserved3 : 29; 48 }; 49 uint32_t val; 50 } dcache_tag_power_ctrl; 51 union { 52 struct { 53 uint32_t dcache_prelock_sct0_en : 1; /*The bit is used to enable the first section of prelock function.*/ 54 uint32_t dcache_prelock_sct1_en : 1; /*The bit is used to enable the second section of prelock function.*/ 55 uint32_t reserved2 : 30; 56 }; 57 uint32_t val; 58 } dcache_prelock_ctrl; 59 uint32_t dcache_prelock_sct0_addr; 60 uint32_t dcache_prelock_sct1_addr; 61 union { 62 struct { 63 uint32_t dcache_prelock_sct1_size : 16; /*The bits are used to configure the second length of data locking, which is combined with DCACHE_PRELOCK_SCT1_ADDR_REG*/ 64 uint32_t dcache_prelock_sct0_size : 16; /*The bits are used to configure the first length of data locking, which is combined with DCACHE_PRELOCK_SCT0_ADDR_REG*/ 65 }; 66 uint32_t val; 67 } dcache_prelock_sct_size; 68 union { 69 struct { 70 uint32_t dcache_lock_ena : 1; /*The bit is used to enable lock operation. It will be cleared by hardware after lock operation done.*/ 71 uint32_t dcache_unlock_ena : 1; /*The bit is used to enable unlock operation. It will be cleared by hardware after unlock operation done.*/ 72 uint32_t dcache_lock_done : 1; /*The bit is used to indicate unlock/lock operation is finished.*/ 73 uint32_t reserved3 : 29; 74 }; 75 uint32_t val; 76 } dcache_lock_ctrl; 77 uint32_t dcache_lock_addr; 78 union { 79 struct { 80 uint32_t dcache_lock_size : 16; /*The bits are used to configure the length for lock operations. The bits are the counts of cache block. It should be combined with DCACHE_LOCK_ADDR_REG.*/ 81 uint32_t reserved16 : 16; 82 }; 83 uint32_t val; 84 } dcache_lock_size; 85 union { 86 struct { 87 uint32_t dcache_invalidate_ena : 1; /*The bit is used to enable invalidate operation. It will be cleared by hardware after invalidate operation done.*/ 88 uint32_t dcache_writeback_ena : 1; /*The bit is used to enable writeback operation. It will be cleared by hardware after writeback operation done.*/ 89 uint32_t dcache_clean_ena : 1; /*The bit is used to enable clean operation. It will be cleared by hardware after clean operation done.*/ 90 uint32_t dcache_sync_done : 1; /*The bit is used to indicate clean/writeback/invalidate operation is finished.*/ 91 uint32_t reserved4 : 28; 92 }; 93 uint32_t val; 94 } dcache_sync_ctrl; 95 uint32_t dcache_sync_addr; 96 union { 97 struct { 98 uint32_t dcache_sync_size : 23; /*The bits are used to configure the length for sync operations. The bits are the counts of cache block. It should be combined with DCACHE_SYNC_ADDR_REG.*/ 99 uint32_t reserved23 : 9; 100 }; 101 uint32_t val; 102 } dcache_sync_size; 103 union { 104 struct { 105 uint32_t dcache_occupy_ena : 1; /*The bit is used to enable occupy operation. It will be cleared by hardware after issuing Auot-Invalidate Operation.*/ 106 uint32_t dcache_occupy_done : 1; /*The bit is used to indicate occupy operation is finished.*/ 107 uint32_t reserved2 : 30; 108 }; 109 uint32_t val; 110 } dcache_occupy_ctrl; 111 uint32_t dcache_occupy_addr; 112 union { 113 struct { 114 uint32_t dcache_occupy_size : 16; /*The bits are used to configure the length for occupy operation. The bits are the counts of cache block. It should be combined with DCACHE_OCCUPY_ADDR_REG.*/ 115 uint32_t reserved16 : 16; 116 }; 117 uint32_t val; 118 } dcache_occupy_size; 119 union { 120 struct { 121 uint32_t dcache_preload_ena : 1; /*The bit is used to enable preload operation. It will be cleared by hardware after preload operation done.*/ 122 uint32_t dcache_preload_done : 1; /*The bit is used to indicate preload operation is finished.*/ 123 uint32_t dcache_preload_order : 1; /*The bit is used to configure the direction of preload operation. 1: descending, 0: ascending.*/ 124 uint32_t reserved3 : 29; 125 }; 126 uint32_t val; 127 } dcache_preload_ctrl; 128 uint32_t dcache_preload_addr; 129 union { 130 struct { 131 uint32_t dcache_preload_size : 16; /*The bits are used to configure the length for preload operation. The bits are the counts of cache block. It should be combined with DCACHE_PRELOAD_ADDR_REG..*/ 132 uint32_t reserved16 : 16; 133 }; 134 uint32_t val; 135 } dcache_preload_size; 136 union { 137 struct { 138 uint32_t dcache_autoload_sct0_ena : 1; /*The bits are used to enable the first section for autoload operation.*/ 139 uint32_t dcache_autoload_sct1_ena : 1; /*The bits are used to enable the second section for autoload operation.*/ 140 uint32_t dcache_autoload_ena : 1; /*The bit is used to enable and disable autoload operation. It is combined with dcache_autoload_done. 1: enable, 0: disable. */ 141 uint32_t dcache_autoload_done : 1; /*The bit is used to indicate autoload operation is finished.*/ 142 uint32_t dcache_autoload_order : 1; /*The bits are used to configure the direction of autoload. 1: descending, 0: ascending.*/ 143 uint32_t dcache_autoload_rqst : 2; /*The bits are used to configure trigger conditions for autoload. 0/3: cache miss, 1: cache hit, 2: both cache miss and hit.*/ 144 uint32_t dcache_autoload_size : 2; /*The bits are used to configure the numbers of the cache block for the issuing autoload operation.*/ 145 uint32_t dcache_autoload_buffer_clear : 1; /*The bit is used to clear autoload buffer in dcache.*/ 146 uint32_t reserved10 : 22; 147 }; 148 uint32_t val; 149 } dcache_autoload_ctrl; 150 uint32_t dcache_autoload_sct0_addr; 151 union { 152 struct { 153 uint32_t dcache_autoload_sct0_size : 27; /*The bits are used to configure the length of the first section for autoload operation. It should be combined with dcache_autoload_sct0_ena.*/ 154 uint32_t reserved27 : 5; 155 }; 156 uint32_t val; 157 } dcache_autoload_sct0_size; 158 uint32_t dcache_autoload_sct1_addr; 159 union { 160 struct { 161 uint32_t dcache_autoload_sct1_size : 27; /*The bits are used to configure the length of the second section for autoload operation. It should be combined with dcache_autoload_sct1_ena.*/ 162 uint32_t reserved27 : 5; 163 }; 164 uint32_t val; 165 } dcache_autoload_sct1_size; 166 union { 167 struct { 168 uint32_t icache_enable : 1; /*The bit is used to activate the data cache. 0: disable, 1: enable*/ 169 uint32_t icache_way_mode : 1; /*The bit is used to configure cache way mode.0: 4-way, 1: 8-way*/ 170 uint32_t icache_size_mode : 1; /*The bit is used to configure cache memory size.0: 16KB, 1: 32KB*/ 171 uint32_t icache_blocksize_mode : 1; /*The bit is used to configure cache block size.0: 16 bytes, 1: 32 bytes*/ 172 uint32_t reserved4 : 28; 173 }; 174 uint32_t val; 175 } icache_ctrl; 176 union { 177 struct { 178 uint32_t icache_shut_core0_bus : 1; /*The bit is used to disable core0 ibus, 0: enable, 1: disable*/ 179 uint32_t icache_shut_core1_bus : 1; /*The bit is used to disable core1 ibus, 0: enable, 1: disable*/ 180 uint32_t reserved2 : 30; 181 }; 182 uint32_t val; 183 } icache_ctrl1; 184 union { 185 struct { 186 uint32_t icache_tag_mem_force_on : 1; /*The bit is used to close clock gating of icache tag memory. 1: close gating, 0: open clock gating.*/ 187 uint32_t icache_tag_mem_force_pd : 1; /*The bit is used to power icache tag memory down, 0: follow rtc_lslp, 1: power down*/ 188 uint32_t icache_tag_mem_force_pu : 1; /*The bit is used to power icache tag memory up, 0: follow rtc_lslp, 1: power up*/ 189 uint32_t reserved3 : 29; 190 }; 191 uint32_t val; 192 } icache_tag_power_ctrl; 193 union { 194 struct { 195 uint32_t icache_prelock_sct0_en : 1; /*The bit is used to enable the first section of prelock function.*/ 196 uint32_t icache_prelock_sct1_en : 1; /*The bit is used to enable the second section of prelock function.*/ 197 uint32_t reserved2 : 30; 198 }; 199 uint32_t val; 200 } icache_prelock_ctrl; 201 uint32_t icache_prelock_sct0_addr; 202 uint32_t icache_prelock_sct1_addr; 203 union { 204 struct { 205 uint32_t icache_prelock_sct1_size : 16; /*The bits are used to configure the second length of data locking, which is combined with ICACHE_PRELOCK_SCT1_ADDR_REG*/ 206 uint32_t icache_prelock_sct0_size : 16; /*The bits are used to configure the first length of data locking, which is combined with ICACHE_PRELOCK_SCT0_ADDR_REG*/ 207 }; 208 uint32_t val; 209 } icache_prelock_sct_size; 210 union { 211 struct { 212 uint32_t icache_lock_ena : 1; /*The bit is used to enable lock operation. It will be cleared by hardware after lock operation done.*/ 213 uint32_t icache_unlock_ena : 1; /*The bit is used to enable unlock operation. It will be cleared by hardware after unlock operation done.*/ 214 uint32_t icache_lock_done : 1; /*The bit is used to indicate unlock/lock operation is finished.*/ 215 uint32_t reserved3 : 29; 216 }; 217 uint32_t val; 218 } icache_lock_ctrl; 219 uint32_t icache_lock_addr; 220 union { 221 struct { 222 uint32_t icache_lock_size : 16; /*The bits are used to configure the length for lock operations. The bits are the counts of cache block. It should be combined with ICACHE_LOCK_ADDR_REG.*/ 223 uint32_t reserved16 : 16; 224 }; 225 uint32_t val; 226 } icache_lock_size; 227 union { 228 struct { 229 uint32_t icache_invalidate_ena : 1; /*The bit is used to enable invalidate operation. It will be cleared by hardware after invalidate operation done.*/ 230 uint32_t icache_sync_done : 1; /*The bit is used to indicate invalidate operation is finished.*/ 231 uint32_t reserved2 : 30; 232 }; 233 uint32_t val; 234 } icache_sync_ctrl; 235 uint32_t icache_sync_addr; 236 union { 237 struct { 238 uint32_t icache_sync_size : 23; /*The bits are used to configure the length for sync operations. The bits are the counts of cache block. It should be combined with ICACHE_SYNC_ADDR_REG.*/ 239 uint32_t reserved23 : 9; 240 }; 241 uint32_t val; 242 } icache_sync_size; 243 union { 244 struct { 245 uint32_t icache_preload_ena : 1; /*The bit is used to enable preload operation. It will be cleared by hardware after preload operation done.*/ 246 uint32_t icache_preload_done : 1; /*The bit is used to indicate preload operation is finished.*/ 247 uint32_t icache_preload_order : 1; /*The bit is used to configure the direction of preload operation. 1: descending, 0: ascending.*/ 248 uint32_t reserved3 : 29; 249 }; 250 uint32_t val; 251 } icache_preload_ctrl; 252 uint32_t icache_preload_addr; 253 union { 254 struct { 255 uint32_t icache_preload_size : 16; /*The bits are used to configure the length for preload operation. The bits are the counts of cache block. It should be combined with ICACHE_PRELOAD_ADDR_REG..*/ 256 uint32_t reserved16 : 16; 257 }; 258 uint32_t val; 259 } icache_preload_size; 260 union { 261 struct { 262 uint32_t icache_autoload_sct0_ena : 1; /*The bits are used to enable the first section for autoload operation.*/ 263 uint32_t icache_autoload_sct1_ena : 1; /*The bits are used to enable the second section for autoload operation.*/ 264 uint32_t icache_autoload_ena : 1; /*The bit is used to enable and disable autoload operation. It is combined with icache_autoload_done. 1: enable, 0: disable. */ 265 uint32_t icache_autoload_done : 1; /*The bit is used to indicate autoload operation is finished.*/ 266 uint32_t icache_autoload_order : 1; /*The bits are used to configure the direction of autoload. 1: descending, 0: ascending.*/ 267 uint32_t icache_autoload_rqst : 2; /*The bits are used to configure trigger conditions for autoload. 0/3: cache miss, 1: cache hit, 2: both cache miss and hit.*/ 268 uint32_t icache_autoload_size : 2; /*The bits are used to configure the numbers of the cache block for the issuing autoload operation.*/ 269 uint32_t icache_autoload_buffer_clear : 1; /*The bit is used to clear autoload buffer in icache.*/ 270 uint32_t reserved10 : 22; 271 }; 272 uint32_t val; 273 } icache_autoload_ctrl; 274 uint32_t icache_autoload_sct0_addr; 275 union { 276 struct { 277 uint32_t icache_autoload_sct0_size : 27; /*The bits are used to configure the length of the first section for autoload operation. It should be combined with icache_autoload_sct0_ena.*/ 278 uint32_t reserved27 : 5; 279 }; 280 uint32_t val; 281 } icache_autoload_sct0_size; 282 uint32_t icache_autoload_sct1_addr; 283 union { 284 struct { 285 uint32_t icache_autoload_sct1_size : 27; /*The bits are used to configure the length of the second section for autoload operation. It should be combined with icache_autoload_sct1_ena.*/ 286 uint32_t reserved27 : 5; 287 }; 288 uint32_t val; 289 } icache_autoload_sct1_size; 290 uint32_t ibus_to_flash_start_vaddr; 291 uint32_t ibus_to_flash_end_vaddr; 292 uint32_t dbus_to_flash_start_vaddr; 293 uint32_t dbus_to_flash_end_vaddr; 294 union { 295 struct { 296 uint32_t dcache_acs_cnt_clr : 1; /*The bit is used to clear dcache counter.*/ 297 uint32_t icache_acs_cnt_clr : 1; /*The bit is used to clear icache counter.*/ 298 uint32_t reserved2 : 30; 299 }; 300 uint32_t val; 301 } cache_acs_cnt_clr; 302 uint32_t ibus_acs_miss_cnt; 303 uint32_t ibus_acs_cnt; 304 uint32_t dbus_acs_flash_miss_cnt; 305 uint32_t dbus_acs_spiram_miss_cnt; 306 uint32_t dbus_acs_cnt; 307 union { 308 struct { 309 uint32_t icache_sync_op_fault : 1; /*The bit is used to enable interrupt by sync configurations fault.*/ 310 uint32_t icache_preload_op_fault : 1; /*The bit is used to enable interrupt by preload configurations fault.*/ 311 uint32_t dcache_sync_op_fault : 1; /*The bit is used to enable interrupt by sync configurations fault.*/ 312 uint32_t dcache_preload_op_fault : 1; /*The bit is used to enable interrupt by preload configurations fault.*/ 313 uint32_t dcache_write_flash : 1; /*The bit is used to enable interrupt by dcache trying to write flash.*/ 314 uint32_t mmu_entry_fault : 1; /*The bit is used to enable interrupt by mmu entry fault.*/ 315 uint32_t dcache_occupy_exc : 1; /*The bit is used to enable interrupt by dcache trying to replace a line whose blocks all have been occupied by occupy-mode.*/ 316 uint32_t ibus_cnt_ovf : 1; /*The bit is used to enable interrupt by ibus counter overflow.*/ 317 uint32_t dbus_cnt_ovf : 1; /*The bit is used to enable interrupt by dbus counter overflow.*/ 318 uint32_t reserved9 : 23; 319 }; 320 uint32_t val; 321 } cache_ilg_int_ena; 322 union { 323 struct { 324 uint32_t icache_sync_op_fault : 1; /*The bit is used to clear interrupt by sync configurations fault.*/ 325 uint32_t icache_preload_op_fault : 1; /*The bit is used to clear interrupt by preload configurations fault.*/ 326 uint32_t dcache_sync_op_fault : 1; /*The bit is used to clear interrupt by sync configurations fault.*/ 327 uint32_t dcache_preload_op_fault : 1; /*The bit is used to clear interrupt by preload configurations fault.*/ 328 uint32_t dcache_write_flash : 1; /*The bit is used to clear interrupt by dcache trying to write flash.*/ 329 uint32_t mmu_entry_fault : 1; /*The bit is used to clear interrupt by mmu entry fault.*/ 330 uint32_t dcache_occupy_exc : 1; /*The bit is used to clear interrupt by dcache trying to replace a line whose blocks all have been occupied by occupy-mode.*/ 331 uint32_t ibus_cnt_ovf : 1; /*The bit is used to clear interrupt by ibus counter overflow.*/ 332 uint32_t dbus_cnt_ovf : 1; /*The bit is used to clear interrupt by dbus counter overflow.*/ 333 uint32_t reserved9 : 23; 334 }; 335 uint32_t val; 336 } cache_ilg_int_clr; 337 union { 338 struct { 339 uint32_t icache_sync_op_fault_st : 1; /*The bit is used to indicate interrupt by sync configurations fault.*/ 340 uint32_t icache_preload_op_fault_st : 1; /*The bit is used to indicate interrupt by preload configurations fault.*/ 341 uint32_t dcache_sync_op_fault_st : 1; /*The bit is used to indicate interrupt by sync configurations fault.*/ 342 uint32_t dcache_preload_op_fault_st : 1; /*The bit is used to indicate interrupt by preload configurations fault.*/ 343 uint32_t dcache_write_flash_st : 1; /*The bit is used to indicate interrupt by dcache trying to write flash.*/ 344 uint32_t mmu_entry_fault_st : 1; /*The bit is used to indicate interrupt by mmu entry fault.*/ 345 uint32_t dcache_occupy_exc_st : 1; /*The bit is used to indicate interrupt by dcache trying to replace a line whose blocks all have been occupied by occupy-mode.*/ 346 uint32_t ibus_acs_cnt_ovf_st : 1; /*The bit is used to indicate interrupt by ibus access flash/spiram counter overflow.*/ 347 uint32_t ibus_acs_miss_cnt_ovf_st : 1; /*The bit is used to indicate interrupt by ibus access flash/spiram miss counter overflow.*/ 348 uint32_t dbus_acs_cnt_ovf_st : 1; /*The bit is used to indicate interrupt by dbus access flash/spiram counter overflow.*/ 349 uint32_t dbus_acs_flash_miss_cnt_ovf_st: 1; /*The bit is used to indicate interrupt by dbus access flash miss counter overflow.*/ 350 uint32_t dbus_acs_spiram_miss_cnt_ovf_st: 1; /*The bit is used to indicate interrupt by dbus access spiram miss counter overflow.*/ 351 uint32_t reserved12 : 20; 352 }; 353 uint32_t val; 354 } cache_ilg_int_st; 355 union { 356 struct { 357 uint32_t core0_ibus_acs_msk_ic : 1; /*The bit is used to enable interrupt by cpu access icache while the corresponding ibus is disabled which include speculative access.*/ 358 uint32_t core0_ibus_wr_ic : 1; /*The bit is used to enable interrupt by ibus trying to write icache*/ 359 uint32_t core0_ibus_reject : 1; /*The bit is used to enable interrupt by authentication fail.*/ 360 uint32_t core0_dbus_acs_msk_dc : 1; /*The bit is used to enable interrupt by cpu access dcache while the corresponding dbus is disabled which include speculative access.*/ 361 uint32_t core0_dbus_reject : 1; /*The bit is used to enable interrupt by authentication fail.*/ 362 uint32_t reserved5 : 27; 363 }; 364 uint32_t val; 365 } core0_acs_cache_int_ena; 366 union { 367 struct { 368 uint32_t core0_ibus_acs_msk_ic : 1; /*The bit is used to clear interrupt by cpu access icache while the corresponding ibus is disabled or icache is disabled which include speculative access.*/ 369 uint32_t core0_ibus_wr_ic : 1; /*The bit is used to clear interrupt by ibus trying to write icache*/ 370 uint32_t core0_ibus_reject : 1; /*The bit is used to clear interrupt by authentication fail.*/ 371 uint32_t core0_dbus_acs_msk_dc : 1; /*The bit is used to clear interrupt by cpu access dcache while the corresponding dbus is disabled or dcache is disabled which include speculative access.*/ 372 uint32_t core0_dbus_reject : 1; /*The bit is used to clear interrupt by authentication fail.*/ 373 uint32_t reserved5 : 27; 374 }; 375 uint32_t val; 376 } core0_acs_cache_int_clr; 377 union { 378 struct { 379 uint32_t core0_ibus_acs_msk_icache_st : 1; /*The bit is used to indicate interrupt by cpu access icache while the core0_ibus is disabled or icache is disabled which include speculative access.*/ 380 uint32_t core0_ibus_wr_icache_st : 1; /*The bit is used to indicate interrupt by ibus trying to write icache*/ 381 uint32_t core0_ibus_reject_st : 1; /*The bit is used to indicate interrupt by authentication fail.*/ 382 uint32_t core0_dbus_acs_msk_dcache_st : 1; /*The bit is used to indicate interrupt by cpu access dcache while the core0_dbus is disabled or dcache is disabled which include speculative access.*/ 383 uint32_t core0_dbus_reject_st : 1; /*The bit is used to indicate interrupt by authentication fail.*/ 384 uint32_t reserved5 : 27; 385 }; 386 uint32_t val; 387 } core0_acs_cache_int_st; 388 union { 389 struct { 390 uint32_t core1_ibus_acs_msk_ic : 1; /*The bit is used to enable interrupt by cpu access icache while the corresponding ibus is disabled which include speculative access.*/ 391 uint32_t core1_ibus_wr_ic : 1; /*The bit is used to enable interrupt by ibus trying to write icache*/ 392 uint32_t core1_ibus_reject : 1; /*The bit is used to enable interrupt by authentication fail.*/ 393 uint32_t core1_dbus_acs_msk_dc : 1; /*The bit is used to enable interrupt by cpu access dcache while the corresponding dbus is disabled which include speculative access.*/ 394 uint32_t core1_dbus_reject : 1; /*The bit is used to enable interrupt by authentication fail.*/ 395 uint32_t reserved5 : 27; 396 }; 397 uint32_t val; 398 } core1_acs_cache_int_ena; 399 union { 400 struct { 401 uint32_t core1_ibus_acs_msk_ic : 1; /*The bit is used to clear interrupt by cpu access icache while the corresponding ibus is disabled or icache is disabled which include speculative access.*/ 402 uint32_t core1_ibus_wr_ic : 1; /*The bit is used to clear interrupt by ibus trying to write icache*/ 403 uint32_t core1_ibus_reject : 1; /*The bit is used to clear interrupt by authentication fail.*/ 404 uint32_t core1_dbus_acs_msk_dc : 1; /*The bit is used to clear interrupt by cpu access dcache while the corresponding dbus is disabled or dcache is disabled which include speculative access.*/ 405 uint32_t core1_dbus_reject : 1; /*The bit is used to clear interrupt by authentication fail.*/ 406 uint32_t reserved5 : 27; 407 }; 408 uint32_t val; 409 } core1_acs_cache_int_clr; 410 union { 411 struct { 412 uint32_t core1_ibus_acs_msk_icache_st : 1; /*The bit is used to indicate interrupt by cpu access icache while the core1_ibus is disabled or icache is disabled which include speculative access.*/ 413 uint32_t core1_ibus_wr_icache_st : 1; /*The bit is used to indicate interrupt by ibus trying to write icache*/ 414 uint32_t core1_ibus_reject_st : 1; /*The bit is used to indicate interrupt by authentication fail.*/ 415 uint32_t core1_dbus_acs_msk_dcache_st : 1; /*The bit is used to indicate interrupt by cpu access dcache while the core1_dbus is disabled or dcache is disabled which include speculative access.*/ 416 uint32_t core1_dbus_reject_st : 1; /*The bit is used to indicate interrupt by authentication fail.*/ 417 uint32_t reserved5 : 27; 418 }; 419 uint32_t val; 420 } core1_acs_cache_int_st; 421 union { 422 struct { 423 uint32_t core0_dbus_tag_attr : 3; /*The bits are used to indicate the attribute of data from external memory when authentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able.*/ 424 uint32_t core0_dbus_attr : 3; /*The bits are used to indicate the attribute of CPU access dbus when authentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able.*/ 425 uint32_t core0_dbus_world : 1; /*The bit is used to indicate the world of CPU access dbus when authentication fail. 0: WORLD0, 1: WORLD1*/ 426 uint32_t reserved7 : 25; 427 }; 428 uint32_t val; 429 } core0_dbus_reject_st; 430 uint32_t core0_dbus_reject_vaddr; 431 union { 432 struct { 433 uint32_t core0_ibus_tag_attr : 3; /*The bits are used to indicate the attribute of data from external memory when authentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able.*/ 434 uint32_t core0_ibus_attr : 3; /*The bits are used to indicate the attribute of CPU access ibus when authentication fail. 0: invalidate, 1: execute-able, 2: read-able*/ 435 uint32_t core0_ibus_world : 1; /*The bit is used to indicate the world of CPU access ibus when authentication fail. 0: WORLD0, 1: WORLD1*/ 436 uint32_t reserved7 : 25; 437 }; 438 uint32_t val; 439 } core0_ibus_reject_st; 440 uint32_t core0_ibus_reject_vaddr; 441 union { 442 struct { 443 uint32_t core1_dbus_tag_attr : 3; /*The bits are used to indicate the attribute of data from external memory when authentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able.*/ 444 uint32_t core1_dbus_attr : 3; /*The bits are used to indicate the attribute of CPU access dbus when authentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able.*/ 445 uint32_t core1_dbus_world : 1; /*The bit is used to indicate the world of CPU access dbus when authentication fail. 0: WORLD0, 1: WORLD1*/ 446 uint32_t reserved7 : 25; 447 }; 448 uint32_t val; 449 } core1_dbus_reject_st; 450 uint32_t core1_dbus_reject_vaddr; 451 union { 452 struct { 453 uint32_t core1_ibus_tag_attr : 3; /*The bits are used to indicate the attribute of data from external memory when authentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able.*/ 454 uint32_t core1_ibus_attr : 3; /*The bits are used to indicate the attribute of CPU access ibus when authentication fail. 0: invalidate, 1: execute-able, 2: read-able*/ 455 uint32_t core1_ibus_world : 1; /*The bit is used to indicate the world of CPU access ibus when authentication fail. 0: WORLD0, 1: WORLD1*/ 456 uint32_t reserved7 : 25; 457 }; 458 uint32_t val; 459 } core1_ibus_reject_st; 460 uint32_t core1_ibus_reject_vaddr; 461 union { 462 struct { 463 uint32_t cache_mmu_fault_content : 16; /*The bits are used to indicate the content of mmu entry which cause mmu fault..*/ 464 uint32_t cache_mmu_fault_code : 4; /*The right-most 3 bits are used to indicate the operations which cause mmu fault occurrence. 0: default, 1: cpu miss, 2: preload miss, 3: writeback, 4: cpu miss evict recovery address, 5: load miss evict recovery address, 6: external dma tx, 7: external dma rx. The most significant bit is used to indicate this operation occurs in which one icache. */ 465 uint32_t reserved20 : 12; 466 }; 467 uint32_t val; 468 } cache_mmu_fault_content; 469 uint32_t cache_mmu_fault_vaddr; 470 union { 471 struct { 472 uint32_t cache_flash_wrap_around : 1; /*The bit is used to enable wrap around mode when read data from flash.*/ 473 uint32_t cache_sram_rd_wrap_around : 1; /*The bit is used to enable wrap around mode when read data from spiram.*/ 474 uint32_t reserved2 : 30; 475 }; 476 uint32_t val; 477 } cache_wrap_around_ctrl; 478 union { 479 struct { 480 uint32_t cache_mmu_mem_force_on : 1; /*The bit is used to enable clock gating to save power when access mmu memory, 0: enable, 1: disable*/ 481 uint32_t cache_mmu_mem_force_pd : 1; /*The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power down*/ 482 uint32_t cache_mmu_mem_force_pu : 1; /*The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power up*/ 483 uint32_t reserved3 : 29; 484 }; 485 uint32_t val; 486 } cache_mmu_power_ctrl; 487 union { 488 struct { 489 uint32_t icache_state : 12; /*The bit is used to indicate whether icache main fsm is in idle state or not. 1: in idle state, 0: not in idle state*/ 490 uint32_t dcache_state : 12; /*The bit is used to indicate whether dcache main fsm is in idle state or not. 1: in idle state, 0: not in idle state*/ 491 uint32_t reserved24 : 8; 492 }; 493 uint32_t val; 494 } cache_state; 495 union { 496 struct { 497 uint32_t record_disable_db_encrypt : 1; /*Reserved.*/ 498 uint32_t record_disable_g0cb_decrypt : 1; /*Reserved.*/ 499 uint32_t reserved2 : 30; 500 }; 501 uint32_t val; 502 } cache_encrypt_decrypt_record_disable; 503 union { 504 struct { 505 uint32_t clk_force_on_manual_crypt : 1; /*The bit is used to close clock gating of manual crypt clock. 1: close gating, 0: open clock gating.*/ 506 uint32_t clk_force_on_auto_crypt : 1; /*The bit is used to close clock gating of automatic crypt clock. 1: close gating, 0: open clock gating.*/ 507 uint32_t clk_force_on_crypt : 1; /*The bit is used to close clock gating of external memory encrypt and decrypt clock. 1: close gating, 0: open clock gating.*/ 508 uint32_t reserved3 : 29; 509 }; 510 uint32_t val; 511 } cache_encrypt_decrypt_clk_force_on; 512 union { 513 struct { 514 uint32_t alloc_wb_hold_arbiter : 1; /*Reserved.*/ 515 uint32_t reserved1 : 31; 516 }; 517 uint32_t val; 518 } cache_bridge_arbiter_ctrl; 519 union { 520 struct { 521 uint32_t icache_preload_ist : 1; /*The bit is used to indicate the interrupt by icache pre-load done.*/ 522 uint32_t icache_preload_iena : 1; /*The bit is used to enable the interrupt by icache pre-load done.*/ 523 uint32_t icache_preload_iclr : 1; /*The bit is used to clear the interrupt by icache pre-load done.*/ 524 uint32_t dcache_preload_ist : 1; /*The bit is used to indicate the interrupt by dcache pre-load done.*/ 525 uint32_t dcache_preload_iena : 1; /*The bit is used to enable the interrupt by dcache pre-load done.*/ 526 uint32_t dcache_preload_iclr : 1; /*The bit is used to clear the interrupt by dcache pre-load done.*/ 527 uint32_t reserved6 : 26; 528 }; 529 uint32_t val; 530 } cache_preload_int_ctrl; 531 union { 532 struct { 533 uint32_t icache_sync_ist : 1; /*The bit is used to indicate the interrupt by icache sync done.*/ 534 uint32_t icache_sync_iena : 1; /*The bit is used to enable the interrupt by icache sync done.*/ 535 uint32_t icache_sync_iclr : 1; /*The bit is used to clear the interrupt by icache sync done.*/ 536 uint32_t dcache_sync_ist : 1; /*The bit is used to indicate the interrupt by dcache sync done.*/ 537 uint32_t dcache_sync_iena : 1; /*The bit is used to enable the interrupt by dcache sync done.*/ 538 uint32_t dcache_sync_iclr : 1; /*The bit is used to clear the interrupt by dcache sync done.*/ 539 uint32_t reserved6 : 26; 540 }; 541 uint32_t val; 542 } cache_sync_int_ctrl; 543 union { 544 struct { 545 uint32_t cache_mmu_owner : 24; /*The bits are used to specify the owner of MMU.bit0: icache, bit1: dcache, bit2: dma, bit3: reserved.*/ 546 uint32_t reserved24 : 8; 547 }; 548 uint32_t val; 549 } cache_mmu_owner; 550 union { 551 struct { 552 uint32_t cache_ignore_preload_mmu_entry_fault: 1; /*The bit is used to disable checking mmu entry fault by preload operation.*/ 553 uint32_t cache_ignore_sync_mmu_entry_fault: 1; /*The bit is used to disable checking mmu entry fault by sync operation.*/ 554 uint32_t cache_trace_ena : 1; /*The bit is used to enable cache trace function.*/ 555 uint32_t reserved3 : 29; 556 }; 557 uint32_t val; 558 } cache_conf_misc; 559 union { 560 struct { 561 uint32_t dcache_freeze_ena : 1; /*The bit is used to enable dcache freeze mode*/ 562 uint32_t dcache_freeze_mode : 1; /*The bit is used to configure freeze mode, 0: assert busy if CPU miss 1: assert hit if CPU miss*/ 563 uint32_t dcache_freeze_done : 1; /*The bit is used to indicate dcache freeze success*/ 564 uint32_t reserved3 : 29; 565 }; 566 uint32_t val; 567 } dcache_freeze; 568 union { 569 struct { 570 uint32_t icache_freeze_ena : 1; /*The bit is used to enable icache freeze mode*/ 571 uint32_t icache_freeze_mode : 1; /*The bit is used to configure freeze mode, 0: assert busy if CPU miss 1: assert hit if CPU miss*/ 572 uint32_t icache_freeze_done : 1; /*The bit is used to indicate icache freeze success*/ 573 uint32_t reserved3 : 29; 574 }; 575 uint32_t val; 576 } icache_freeze; 577 union { 578 struct { 579 uint32_t icache_atomic_operate_ena : 1; /*The bit is used to activate icache atomic operation protection. In this case, sync/lock operation can not interrupt miss-work. This feature does not work during invalidateAll operation.*/ 580 uint32_t reserved1 : 31; 581 }; 582 uint32_t val; 583 } icache_atomic_operate_ena; 584 union { 585 struct { 586 uint32_t dcache_atomic_operate_ena : 1; /*The bit is used to activate dcache atomic operation protection. In this case, sync/lock/occupy operation can not interrupt miss-work. This feature does not work during invalidateAll operation.*/ 587 uint32_t reserved1 : 31; 588 }; 589 uint32_t val; 590 } dcache_atomic_operate_ena; 591 union { 592 struct { 593 uint32_t cache_request_bypass : 1; /*The bit is used to disable request recording which could cause performance issue*/ 594 uint32_t reserved1 : 31; 595 }; 596 uint32_t val; 597 } cache_request; 598 union { 599 struct { 600 uint32_t clk_en : 1; /*Reserved.*/ 601 uint32_t reserved1 : 31; 602 }; 603 uint32_t val; 604 } clock_gate; 605 uint32_t reserved_168; 606 uint32_t reserved_16c; 607 uint32_t reserved_170; 608 uint32_t reserved_174; 609 uint32_t reserved_178; 610 uint32_t reserved_17c; 611 union { 612 struct { 613 uint32_t icache_tag_object : 1; /*Set this bit to set icache tag memory as object. This bit should be onehot with the others fields inside this register.*/ 614 uint32_t dcache_tag_object : 1; /*Set this bit to set dcache tag memory as object. This bit should be onehot with the others fields inside this register.*/ 615 uint32_t reserved2 : 30; /*Reserved*/ 616 }; 617 uint32_t val; 618 } cache_tag_object_ctrl; 619 union { 620 struct { 621 uint32_t cache_tag_way_object : 3; /*Set this bits to select which way of the tag-object will be accessed. 0: way0, 1: way1, 2: way2, 3: way3, .., 7: way7.*/ 622 uint32_t reserved3 : 29; /*Reserved*/ 623 }; 624 uint32_t val; 625 } cache_tag_way_object; 626 uint32_t cache_vaddr; 627 uint32_t cache_tag_content; 628 uint32_t reserved_190; 629 uint32_t reserved_194; 630 uint32_t reserved_198; 631 uint32_t reserved_19c; 632 uint32_t reserved_1a0; 633 uint32_t reserved_1a4; 634 uint32_t reserved_1a8; 635 uint32_t reserved_1ac; 636 uint32_t reserved_1b0; 637 uint32_t reserved_1b4; 638 uint32_t reserved_1b8; 639 uint32_t reserved_1bc; 640 uint32_t reserved_1c0; 641 uint32_t reserved_1c4; 642 uint32_t reserved_1c8; 643 uint32_t reserved_1cc; 644 uint32_t reserved_1d0; 645 uint32_t reserved_1d4; 646 uint32_t reserved_1d8; 647 uint32_t reserved_1dc; 648 uint32_t reserved_1e0; 649 uint32_t reserved_1e4; 650 uint32_t reserved_1e8; 651 uint32_t reserved_1ec; 652 uint32_t reserved_1f0; 653 uint32_t reserved_1f4; 654 uint32_t reserved_1f8; 655 uint32_t reserved_1fc; 656 uint32_t reserved_200; 657 uint32_t reserved_204; 658 uint32_t reserved_208; 659 uint32_t reserved_20c; 660 uint32_t reserved_210; 661 uint32_t reserved_214; 662 uint32_t reserved_218; 663 uint32_t reserved_21c; 664 uint32_t reserved_220; 665 uint32_t reserved_224; 666 uint32_t reserved_228; 667 uint32_t reserved_22c; 668 uint32_t reserved_230; 669 uint32_t reserved_234; 670 uint32_t reserved_238; 671 uint32_t reserved_23c; 672 uint32_t reserved_240; 673 uint32_t reserved_244; 674 uint32_t reserved_248; 675 uint32_t reserved_24c; 676 uint32_t reserved_250; 677 uint32_t reserved_254; 678 uint32_t reserved_258; 679 uint32_t reserved_25c; 680 uint32_t reserved_260; 681 uint32_t reserved_264; 682 uint32_t reserved_268; 683 uint32_t reserved_26c; 684 uint32_t reserved_270; 685 uint32_t reserved_274; 686 uint32_t reserved_278; 687 uint32_t reserved_27c; 688 uint32_t reserved_280; 689 uint32_t reserved_284; 690 uint32_t reserved_288; 691 uint32_t reserved_28c; 692 uint32_t reserved_290; 693 uint32_t reserved_294; 694 uint32_t reserved_298; 695 uint32_t reserved_29c; 696 uint32_t reserved_2a0; 697 uint32_t reserved_2a4; 698 uint32_t reserved_2a8; 699 uint32_t reserved_2ac; 700 uint32_t reserved_2b0; 701 uint32_t reserved_2b4; 702 uint32_t reserved_2b8; 703 uint32_t reserved_2bc; 704 uint32_t reserved_2c0; 705 uint32_t reserved_2c4; 706 uint32_t reserved_2c8; 707 uint32_t reserved_2cc; 708 uint32_t reserved_2d0; 709 uint32_t reserved_2d4; 710 uint32_t reserved_2d8; 711 uint32_t reserved_2dc; 712 uint32_t reserved_2e0; 713 uint32_t reserved_2e4; 714 uint32_t reserved_2e8; 715 uint32_t reserved_2ec; 716 uint32_t reserved_2f0; 717 uint32_t reserved_2f4; 718 uint32_t reserved_2f8; 719 uint32_t reserved_2fc; 720 uint32_t reserved_300; 721 uint32_t reserved_304; 722 uint32_t reserved_308; 723 uint32_t reserved_30c; 724 uint32_t reserved_310; 725 uint32_t reserved_314; 726 uint32_t reserved_318; 727 uint32_t reserved_31c; 728 uint32_t reserved_320; 729 uint32_t reserved_324; 730 uint32_t reserved_328; 731 uint32_t reserved_32c; 732 uint32_t reserved_330; 733 uint32_t reserved_334; 734 uint32_t reserved_338; 735 uint32_t reserved_33c; 736 uint32_t reserved_340; 737 uint32_t reserved_344; 738 uint32_t reserved_348; 739 uint32_t reserved_34c; 740 uint32_t reserved_350; 741 uint32_t reserved_354; 742 uint32_t reserved_358; 743 uint32_t reserved_35c; 744 uint32_t reserved_360; 745 uint32_t reserved_364; 746 uint32_t reserved_368; 747 uint32_t reserved_36c; 748 uint32_t reserved_370; 749 uint32_t reserved_374; 750 uint32_t reserved_378; 751 uint32_t reserved_37c; 752 uint32_t reserved_380; 753 uint32_t reserved_384; 754 uint32_t reserved_388; 755 uint32_t reserved_38c; 756 uint32_t reserved_390; 757 uint32_t reserved_394; 758 uint32_t reserved_398; 759 uint32_t reserved_39c; 760 uint32_t reserved_3a0; 761 uint32_t reserved_3a4; 762 uint32_t reserved_3a8; 763 uint32_t reserved_3ac; 764 uint32_t reserved_3b0; 765 uint32_t reserved_3b4; 766 uint32_t reserved_3b8; 767 uint32_t reserved_3bc; 768 uint32_t reserved_3c0; 769 uint32_t reserved_3c4; 770 uint32_t reserved_3c8; 771 uint32_t reserved_3cc; 772 uint32_t reserved_3d0; 773 uint32_t reserved_3d4; 774 uint32_t reserved_3d8; 775 uint32_t reserved_3dc; 776 uint32_t reserved_3e0; 777 uint32_t reserved_3e4; 778 uint32_t reserved_3e8; 779 uint32_t reserved_3ec; 780 uint32_t reserved_3f0; 781 uint32_t reserved_3f4; 782 uint32_t reserved_3f8; 783 union { 784 struct { 785 uint32_t extmem_reg_date : 28; /*version information.*/ 786 uint32_t reserved28 : 4; 787 }; 788 uint32_t val; 789 } date; 790 } extmem_dev_t; 791 extern extmem_dev_t EXTMEM; 792 #ifdef __cplusplus 793 } 794 #endif 795 796 797 798 #endif /*_SOC_EXTMEM_STRUCT_H_ */ 799
