1 /** Copyright 2021 Espressif Systems (Shanghai) PTE LTD 2 * 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 */ 15 #pragma once 16 17 #include <stdint.h> 18 #ifdef __cplusplus 19 extern "C" { 20 #endif 21 22 /** Group: FIFO R/W registers */ 23 /** Type of chndata register 24 * The read and write data register for CHANNELn by apb fifo access. 25 */ 26 typedef union { 27 struct { 28 /** chndata : RO; bitpos: [31:0]; default: 0; 29 * Read and write data for channel n via APB FIFO. 30 */ 31 uint32_t chndata: 32; 32 }; 33 uint32_t val; 34 } rmt_chndata_reg_t; 35 36 /** Type of chmdata register 37 * The read and write data register for CHANNEL$n by apb fifo access. 38 */ 39 typedef union { 40 struct { 41 /** chmdata : RO; bitpos: [31:0]; default: 0; 42 * Read and write data for channel $n via APB FIFO. 43 */ 44 uint32_t chmdata: 32; 45 }; 46 uint32_t val; 47 } rmt_chmdata_reg_t; 48 49 50 /** Group: Configuration registers */ 51 /** Type of chnconf0 register 52 * Channel n configure register 0 53 */ 54 typedef union { 55 struct { 56 /** tx_start_n : WT; bitpos: [0]; default: 0; 57 * Set this bit to start sending data on CHANNELn. 58 */ 59 uint32_t tx_start_n: 1; 60 /** mem_rd_rst_n : WT; bitpos: [1]; default: 0; 61 * Set this bit to reset read ram address for CHANNELn by accessing transmitter. 62 */ 63 uint32_t mem_rd_rst_n: 1; 64 /** apb_mem_rst_n : WT; bitpos: [2]; default: 0; 65 * Set this bit to reset W/R ram address for CHANNELn by accessing apb fifo. 66 */ 67 uint32_t apb_mem_rst_n: 1; 68 /** tx_conti_mode_n : R/W; bitpos: [3]; default: 0; 69 * Set this bit to restart transmission from the first data to the last data in 70 * CHANNELn. 71 */ 72 uint32_t tx_conti_mode_n: 1; 73 /** mem_tx_wrap_en_n : R/W; bitpos: [4]; default: 0; 74 * This is the channel n enable bit for wraparound mode: it will resume sending at the 75 * start when the data to be sent is more than its memory size. 76 */ 77 uint32_t mem_tx_wrap_en_n: 1; 78 /** idle_out_lv_n : R/W; bitpos: [5]; default: 0; 79 * This bit configures the level of output signal in CHANNELn when the latter is in 80 * IDLE state. 81 */ 82 uint32_t idle_out_lv_n: 1; 83 /** idle_out_en_n : R/W; bitpos: [6]; default: 0; 84 * This is the output enable-control bit for CHANNELn in IDLE state. 85 */ 86 uint32_t idle_out_en_n: 1; 87 /** tx_stop_n : R/W/SC; bitpos: [7]; default: 0; 88 * Set this bit to stop the transmitter of CHANNELn sending data out. 89 */ 90 uint32_t tx_stop_n: 1; 91 /** div_cnt_n : R/W; bitpos: [15:8]; default: 2; 92 * This register is used to configure the divider for clock of CHANNELn. 93 */ 94 uint32_t div_cnt_n: 8; 95 /** mem_size_n : R/W; bitpos: [19:16]; default: 1; 96 * This register is used to configure the maximum size of memory allocated to CHANNELn. 97 */ 98 uint32_t mem_size_n: 4; 99 /** carrier_eff_en_n : R/W; bitpos: [20]; default: 1; 100 * 1: Add carrier modulation on the output signal only at the send data state for 101 * CHANNELn. 0: Add carrier modulation on the output signal at all state for CHANNELn. 102 * Only valid when RMT_CARRIER_EN_CHn is 1. 103 */ 104 uint32_t carrier_eff_en_n: 1; 105 /** carrier_en_n : R/W; bitpos: [21]; default: 1; 106 * This is the carrier modulation enable-control bit for CHANNELn. 1: Add carrier 107 * modulation in the output signal. 0: No carrier modulation in sig_out. 108 */ 109 uint32_t carrier_en_n: 1; 110 /** carrier_out_lv_n : R/W; bitpos: [22]; default: 1; 111 * This bit is used to configure the position of carrier wave for CHANNELn. 112 * 113 * 1'h0: add carrier wave on low level. 114 * 115 * 1'h1: add carrier wave on high level. 116 */ 117 uint32_t carrier_out_lv_n: 1; 118 /** afifo_rst_n : WT; bitpos: [23]; default: 0; 119 * Reserved 120 */ 121 uint32_t afifo_rst_n: 1; 122 /** conf_update_n : WT; bitpos: [24]; default: 0; 123 * synchronization bit for CHANNELn 124 */ 125 uint32_t conf_update_n: 1; 126 uint32_t reserved_25: 7; 127 }; 128 uint32_t val; 129 } rmt_chnconf0_reg_t; 130 131 typedef struct { 132 /** Type of chmconf0 register 133 * Channel m configure register 0 134 */ 135 union { 136 struct { 137 /** div_cnt_m : R/W; bitpos: [7:0]; default: 2; 138 * This register is used to configure the divider for clock of CHANNELm. 139 */ 140 uint32_t div_cnt_m: 8; 141 /** idle_thres_m : R/W; bitpos: [22:8]; default: 32767; 142 * When no edge is detected on the input signal and continuous clock cycles is longer 143 * than this register value, received process is finished. 144 */ 145 uint32_t idle_thres_m: 15; 146 uint32_t reserved_23: 1; 147 /** mem_size_m : R/W; bitpos: [27:24]; default: 1; 148 * This register is used to configure the maximum size of memory allocated to CHANNELm. 149 */ 150 uint32_t mem_size_m: 4; 151 /** carrier_en_m : R/W; bitpos: [28]; default: 1; 152 * This is the carrier modulation enable-control bit for CHANNELm. 1: Add carrier 153 * modulation in the output signal. 0: No carrier modulation in sig_out. 154 */ 155 uint32_t carrier_en_m: 1; 156 /** carrier_out_lv_m : R/W; bitpos: [29]; default: 1; 157 * This bit is used to configure the position of carrier wave for CHANNELm. 158 * 159 * 1'h0: add carrier wave on low level. 160 * 161 * 1'h1: add carrier wave on high level. 162 */ 163 uint32_t carrier_out_lv_m: 1; 164 uint32_t reserved_30: 2; 165 }; 166 uint32_t val; 167 } conf0; 168 169 /** Type of chmconf1 register 170 * Channel m configure register 1 171 */ 172 union { 173 struct { 174 /** rx_en_m : R/W; bitpos: [0]; default: 0; 175 * Set this bit to enable receiver to receive data on CHANNELm. 176 */ 177 uint32_t rx_en_m: 1; 178 /** mem_wr_rst_m : WT; bitpos: [1]; default: 0; 179 * Set this bit to reset write ram address for CHANNELm by accessing receiver. 180 */ 181 uint32_t mem_wr_rst_m: 1; 182 /** apb_mem_rst_m : WT; bitpos: [2]; default: 0; 183 * Set this bit to reset W/R ram address for CHANNELm by accessing apb fifo. 184 */ 185 uint32_t apb_mem_rst_m: 1; 186 /** mem_owner_m : R/W/SC; bitpos: [3]; default: 1; 187 * This register marks the ownership of CHANNELm's ram block. 188 * 189 * 1'h1: Receiver is using the ram. 190 * 191 * 1'h0: APB bus is using the ram. 192 */ 193 uint32_t mem_owner_m: 1; 194 /** rx_filter_en_m : R/W; bitpos: [4]; default: 0; 195 * This is the receive filter's enable bit for CHANNELm. 196 */ 197 uint32_t rx_filter_en_m: 1; 198 /** rx_filter_thres_m : R/W; bitpos: [12:5]; default: 15; 199 * Ignores the input pulse when its width is smaller than this register value in APB 200 * clock periods (in receive mode). 201 */ 202 uint32_t rx_filter_thres_m: 8; 203 /** mem_rx_wrap_en_m : R/W; bitpos: [13]; default: 0; 204 * This is the channel m enable bit for wraparound mode: it will resume receiving at 205 * the start when the data to be received is more than its memory size. 206 */ 207 uint32_t mem_rx_wrap_en_m: 1; 208 /** afifo_rst_m : WT; bitpos: [14]; default: 0; 209 * Reserved 210 */ 211 uint32_t afifo_rst_m: 1; 212 /** conf_update_m : WT; bitpos: [15]; default: 0; 213 * synchronization bit for CHANNELm 214 */ 215 uint32_t conf_update_m: 1; 216 uint32_t reserved_16: 16; 217 }; 218 uint32_t val; 219 } conf1; 220 } rmt_chmconf_reg_t; 221 222 /** Type of chm_rx_carrier_rm register 223 * Channel m carrier remove register 224 */ 225 typedef union { 226 struct { 227 /** carrier_low_thres_chm : R/W; bitpos: [15:0]; default: 0; 228 * The low level period in a carrier modulation mode is 229 * (REG_RMT_REG_CARRIER_LOW_THRES_CHm + 1) for channel m. 230 */ 231 uint32_t carrier_low_thres_chm: 16; 232 /** carrier_high_thres_chm : R/W; bitpos: [31:16]; default: 0; 233 * The high level period in a carrier modulation mode is 234 * (REG_RMT_REG_CARRIER_HIGH_THRES_CHm + 1) for channel m. 235 */ 236 uint32_t carrier_high_thres_chm: 16; 237 }; 238 uint32_t val; 239 } rmt_chm_rx_carrier_rm_reg_t; 240 241 /** Type of sys_conf register 242 * RMT apb configuration register 243 */ 244 typedef union { 245 struct { 246 /** apb_fifo_mask : R/W; bitpos: [0]; default: 0; 247 * 1'h1: access memory directly. 1'h0: access memory by FIFO. 248 */ 249 uint32_t apb_fifo_mask: 1; 250 /** mem_clk_force_on : R/W; bitpos: [1]; default: 0; 251 * Set this bit to enable the clock for RMT memory. 252 */ 253 uint32_t mem_clk_force_on: 1; 254 /** mem_force_pd : R/W; bitpos: [2]; default: 0; 255 * Set this bit to power down RMT memory. 256 */ 257 uint32_t mem_force_pd: 1; 258 /** mem_force_pu : R/W; bitpos: [3]; default: 0; 259 * 1: Disable RMT memory light sleep power down function. 0: Power down RMT memory 260 * when RMT is in light sleep mode. 261 */ 262 uint32_t mem_force_pu: 1; 263 /** sclk_div_num : R/W; bitpos: [11:4]; default: 1; 264 * the integral part of the fractional divisor 265 */ 266 uint32_t sclk_div_num: 8; 267 /** sclk_div_a : R/W; bitpos: [17:12]; default: 0; 268 * the numerator of the fractional part of the fractional divisor 269 */ 270 uint32_t sclk_div_a: 6; 271 /** sclk_div_b : R/W; bitpos: [23:18]; default: 0; 272 * the denominator of the fractional part of the fractional divisor 273 */ 274 uint32_t sclk_div_b: 6; 275 /** sclk_sel : R/W; bitpos: [25:24]; default: 1; 276 * choose the clock source of rmt_sclk. 1:CLK_80Mhz;2:CLK_8MHz; 2:XTAL 277 */ 278 uint32_t sclk_sel: 2; 279 /** sclk_active : R/W; bitpos: [26]; default: 1; 280 * rmt_sclk switch 281 */ 282 uint32_t sclk_active: 1; 283 uint32_t reserved_27: 4; 284 /** clk_en : R/W; bitpos: [31]; default: 0; 285 * RMT register clock gate enable signal. 1: Power up the drive clock of registers. 0: 286 * Power down the drive clock of registers 287 */ 288 uint32_t clk_en: 1; 289 }; 290 uint32_t val; 291 } rmt_sys_conf_reg_t; 292 293 /** Type of ref_cnt_rst register 294 * RMT clock divider reset register 295 */ 296 typedef union { 297 struct { 298 /** ref_cnt_rst_ch0 : WT; bitpos: [0]; default: 0; 299 * This register is used to reset the clock divider of CHANNEL0. 300 */ 301 uint32_t ref_cnt_rst_ch0: 1; 302 /** ref_cnt_rst_ch1 : WT; bitpos: [1]; default: 0; 303 * This register is used to reset the clock divider of CHANNEL1. 304 */ 305 uint32_t ref_cnt_rst_ch1: 1; 306 /** ref_cnt_rst_ch2 : WT; bitpos: [2]; default: 0; 307 * This register is used to reset the clock divider of CHANNEL2. 308 */ 309 uint32_t ref_cnt_rst_ch2: 1; 310 /** ref_cnt_rst_ch3 : WT; bitpos: [3]; default: 0; 311 * This register is used to reset the clock divider of CHANNEL3. 312 */ 313 uint32_t ref_cnt_rst_ch3: 1; 314 /** ref_cnt_rst_ch4 : WT; bitpos: [4]; default: 0; 315 * This register is used to reset the clock divider of CHANNEL4. 316 */ 317 uint32_t ref_cnt_rst_ch4: 1; 318 /** ref_cnt_rst_ch5 : WT; bitpos: [5]; default: 0; 319 * This register is used to reset the clock divider of CHANNEL5. 320 */ 321 uint32_t ref_cnt_rst_ch5: 1; 322 /** ref_cnt_rst_ch6 : WT; bitpos: [6]; default: 0; 323 * This register is used to reset the clock divider of CHANNEL6. 324 */ 325 uint32_t ref_cnt_rst_ch6: 1; 326 /** ref_cnt_rst_ch7 : WT; bitpos: [7]; default: 0; 327 * This register is used to reset the clock divider of CHANNEL7. 328 */ 329 uint32_t ref_cnt_rst_ch7: 1; 330 uint32_t reserved_8: 24; 331 }; 332 uint32_t val; 333 } rmt_ref_cnt_rst_reg_t; 334 335 336 /** Group: Status registers */ 337 /** Type of chnstatus register 338 * Channel n status register 339 */ 340 typedef union { 341 struct { 342 /** mem_raddr_ex_n : RO; bitpos: [9:0]; default: 0; 343 * This register records the memory address offset when transmitter of CHANNELn is 344 * using the RAM. 345 */ 346 uint32_t mem_raddr_ex_n: 10; 347 uint32_t reserved_10: 1; 348 /** apb_mem_waddr_n : RO; bitpos: [20:11]; default: 0; 349 * This register records the memory address offset when writes RAM over APB bus. 350 */ 351 uint32_t apb_mem_waddr_n: 10; 352 uint32_t reserved_21: 1; 353 /** state_n : RO; bitpos: [24:22]; default: 0; 354 * This register records the FSM status of CHANNELn. 355 */ 356 uint32_t state_n: 3; 357 /** mem_empty_n : RO; bitpos: [25]; default: 0; 358 * This status bit will be set when the data to be set is more than memory size and 359 * the wraparound mode is disabled. 360 */ 361 uint32_t mem_empty_n: 1; 362 /** apb_mem_wr_err_n : RO; bitpos: [26]; default: 0; 363 * This status bit will be set if the offset address out of memory size when writes 364 * via APB bus. 365 */ 366 uint32_t apb_mem_wr_err_n: 1; 367 uint32_t reserved_27: 5; 368 }; 369 uint32_t val; 370 } rmt_chnstatus_reg_t; 371 372 /** Type of chmstatus register 373 * Channel m status register 374 */ 375 typedef union { 376 struct { 377 /** mem_waddr_ex_m : RO; bitpos: [9:0]; default: 192; 378 * This register records the memory address offset when receiver of CHANNELm is using 379 * the RAM. 380 */ 381 uint32_t mem_waddr_ex_m: 10; 382 uint32_t reserved_10: 1; 383 /** apb_mem_raddr_m : RO; bitpos: [20:11]; default: 192; 384 * This register records the memory address offset when reads RAM over APB bus. 385 */ 386 uint32_t apb_mem_raddr_m: 10; 387 uint32_t reserved_21: 1; 388 /** state_m : RO; bitpos: [24:22]; default: 0; 389 * This register records the FSM status of CHANNELm. 390 */ 391 uint32_t state_m: 3; 392 /** mem_owner_err_m : RO; bitpos: [25]; default: 0; 393 * This status bit will be set when the ownership of memory block is wrong. 394 */ 395 uint32_t mem_owner_err_m: 1; 396 /** mem_full_m : RO; bitpos: [26]; default: 0; 397 * This status bit will be set if the receiver receives more data than the memory size. 398 */ 399 uint32_t mem_full_m: 1; 400 /** apb_mem_rd_err_m : RO; bitpos: [27]; default: 0; 401 * This status bit will be set if the offset address out of memory size when reads via 402 * APB bus. 403 */ 404 uint32_t apb_mem_rd_err_m: 1; 405 uint32_t reserved_28: 4; 406 }; 407 uint32_t val; 408 } rmt_chmstatus_reg_t; 409 410 411 /** Group: Interrupt registers */ 412 /** Type of int_raw register 413 * Raw interrupt status 414 */ 415 typedef union { 416 struct { 417 /** ch0_tx_end_int_raw : R/WTC/SS; bitpos: [0]; default: 0; 418 * The interrupt raw bit for CHANNEL0. Triggered when transmission done. 419 */ 420 uint32_t ch0_tx_end_int_raw: 1; 421 /** ch1_tx_end_int_raw : R/WTC/SS; bitpos: [1]; default: 0; 422 * The interrupt raw bit for CHANNEL1. Triggered when transmission done. 423 */ 424 uint32_t ch1_tx_end_int_raw: 1; 425 /** ch2_tx_end_int_raw : R/WTC/SS; bitpos: [2]; default: 0; 426 * The interrupt raw bit for CHANNEL2. Triggered when transmission done. 427 */ 428 uint32_t ch2_tx_end_int_raw: 1; 429 /** ch3_tx_end_int_raw : R/WTC/SS; bitpos: [3]; default: 0; 430 * The interrupt raw bit for CHANNEL3. Triggered when transmission done. 431 */ 432 uint32_t ch3_tx_end_int_raw: 1; 433 /** ch0_err_int_raw : R/WTC/SS; bitpos: [4]; default: 0; 434 * The interrupt raw bit for CHANNEL0. Triggered when error occurs. 435 */ 436 uint32_t ch0_err_int_raw: 1; 437 /** ch1_err_int_raw : R/WTC/SS; bitpos: [5]; default: 0; 438 * The interrupt raw bit for CHANNEL1. Triggered when error occurs. 439 */ 440 uint32_t ch1_err_int_raw: 1; 441 /** ch2_err_int_raw : R/WTC/SS; bitpos: [6]; default: 0; 442 * The interrupt raw bit for CHANNEL2. Triggered when error occurs. 443 */ 444 uint32_t ch2_err_int_raw: 1; 445 /** ch3_err_int_raw : R/WTC/SS; bitpos: [7]; default: 0; 446 * The interrupt raw bit for CHANNEL3. Triggered when error occurs. 447 */ 448 uint32_t ch3_err_int_raw: 1; 449 /** ch0_tx_thr_event_int_raw : R/WTC/SS; bitpos: [8]; default: 0; 450 * The interrupt raw bit for CHANNEL0. Triggered when transmitter sent more data than 451 * configured value. 452 */ 453 uint32_t ch0_tx_thr_event_int_raw: 1; 454 /** ch1_tx_thr_event_int_raw : R/WTC/SS; bitpos: [9]; default: 0; 455 * The interrupt raw bit for CHANNEL1. Triggered when transmitter sent more data than 456 * configured value. 457 */ 458 uint32_t ch1_tx_thr_event_int_raw: 1; 459 /** ch2_tx_thr_event_int_raw : R/WTC/SS; bitpos: [10]; default: 0; 460 * The interrupt raw bit for CHANNEL2. Triggered when transmitter sent more data than 461 * configured value. 462 */ 463 uint32_t ch2_tx_thr_event_int_raw: 1; 464 /** ch3_tx_thr_event_int_raw : R/WTC/SS; bitpos: [11]; default: 0; 465 * The interrupt raw bit for CHANNEL3. Triggered when transmitter sent more data than 466 * configured value. 467 */ 468 uint32_t ch3_tx_thr_event_int_raw: 1; 469 /** ch0_tx_loop_int_raw : R/WTC/SS; bitpos: [12]; default: 0; 470 * The interrupt raw bit for CHANNEL0. Triggered when the loop count reaches the 471 * configured threshold value. 472 */ 473 uint32_t ch0_tx_loop_int_raw: 1; 474 /** ch1_tx_loop_int_raw : R/WTC/SS; bitpos: [13]; default: 0; 475 * The interrupt raw bit for CHANNEL1. Triggered when the loop count reaches the 476 * configured threshold value. 477 */ 478 uint32_t ch1_tx_loop_int_raw: 1; 479 /** ch2_tx_loop_int_raw : R/WTC/SS; bitpos: [14]; default: 0; 480 * The interrupt raw bit for CHANNEL2. Triggered when the loop count reaches the 481 * configured threshold value. 482 */ 483 uint32_t ch2_tx_loop_int_raw: 1; 484 /** ch3_tx_loop_int_raw : R/WTC/SS; bitpos: [15]; default: 0; 485 * The interrupt raw bit for CHANNEL3. Triggered when the loop count reaches the 486 * configured threshold value. 487 */ 488 uint32_t ch3_tx_loop_int_raw: 1; 489 /** ch4_rx_end_int_raw : R/WTC/SS; bitpos: [16]; default: 0; 490 * The interrupt raw bit for CHANNEL4. Triggered when reception done. 491 */ 492 uint32_t ch4_rx_end_int_raw: 1; 493 /** ch5_rx_end_int_raw : R/WTC/SS; bitpos: [17]; default: 0; 494 * The interrupt raw bit for CHANNEL5. Triggered when reception done. 495 */ 496 uint32_t ch5_rx_end_int_raw: 1; 497 /** ch6_rx_end_int_raw : R/WTC/SS; bitpos: [18]; default: 0; 498 * The interrupt raw bit for CHANNEL6. Triggered when reception done. 499 */ 500 uint32_t ch6_rx_end_int_raw: 1; 501 /** ch7_rx_end_int_raw : R/WTC/SS; bitpos: [19]; default: 0; 502 * The interrupt raw bit for CHANNEL7. Triggered when reception done. 503 */ 504 uint32_t ch7_rx_end_int_raw: 1; 505 /** ch4_err_int_raw : R/WTC/SS; bitpos: [20]; default: 0; 506 * The interrupt raw bit for CHANNEL4. Triggered when error occurs. 507 */ 508 uint32_t ch4_err_int_raw: 1; 509 /** ch5_err_int_raw : R/WTC/SS; bitpos: [21]; default: 0; 510 * The interrupt raw bit for CHANNEL5. Triggered when error occurs. 511 */ 512 uint32_t ch5_err_int_raw: 1; 513 /** ch6_err_int_raw : R/WTC/SS; bitpos: [22]; default: 0; 514 * The interrupt raw bit for CHANNEL6. Triggered when error occurs. 515 */ 516 uint32_t ch6_err_int_raw: 1; 517 /** ch7_err_int_raw : R/WTC/SS; bitpos: [23]; default: 0; 518 * The interrupt raw bit for CHANNEL7. Triggered when error occurs. 519 */ 520 uint32_t ch7_err_int_raw: 1; 521 /** ch4_rx_thr_event_int_raw : R/WTC/SS; bitpos: [24]; default: 0; 522 * The interrupt raw bit for CHANNEL4. Triggered when receiver receive more data than 523 * configured value. 524 */ 525 uint32_t ch4_rx_thr_event_int_raw: 1; 526 /** ch5_rx_thr_event_int_raw : R/WTC/SS; bitpos: [25]; default: 0; 527 * The interrupt raw bit for CHANNEL5. Triggered when receiver receive more data than 528 * configured value. 529 */ 530 uint32_t ch5_rx_thr_event_int_raw: 1; 531 /** ch6_rx_thr_event_int_raw : R/WTC/SS; bitpos: [26]; default: 0; 532 * The interrupt raw bit for CHANNEL6. Triggered when receiver receive more data than 533 * configured value. 534 */ 535 uint32_t ch6_rx_thr_event_int_raw: 1; 536 /** ch7_rx_thr_event_int_raw : R/WTC/SS; bitpos: [27]; default: 0; 537 * The interrupt raw bit for CHANNEL7. Triggered when receiver receive more data than 538 * configured value. 539 */ 540 uint32_t ch7_rx_thr_event_int_raw: 1; 541 /** ch3_dma_access_fail_int_raw : R/WTC/SS; bitpos: [28]; default: 0; 542 * The interrupt raw bit for CHANNEL3. Triggered when dma accessing CHANNEL3 fails. 543 */ 544 uint32_t ch3_dma_access_fail_int_raw: 1; 545 /** ch7_dma_access_fail_int_raw : R/WTC/SS; bitpos: [29]; default: 0; 546 * The interrupt raw bit for CHANNEL7. Triggered when dma accessing CHANNEL7 fails. 547 */ 548 uint32_t ch7_dma_access_fail_int_raw: 1; 549 uint32_t reserved_30: 2; 550 }; 551 uint32_t val; 552 } rmt_int_raw_reg_t; 553 554 /** Type of int_st register 555 * Masked interrupt status 556 */ 557 typedef union { 558 struct { 559 /** ch0_tx_end_int_st : RO; bitpos: [0]; default: 0; 560 * The masked interrupt status bit for CH0_TX_END_INT. 561 */ 562 uint32_t ch0_tx_end_int_st: 1; 563 /** ch1_tx_end_int_st : RO; bitpos: [1]; default: 0; 564 * The masked interrupt status bit for CH1_TX_END_INT. 565 */ 566 uint32_t ch1_tx_end_int_st: 1; 567 /** ch2_tx_end_int_st : RO; bitpos: [2]; default: 0; 568 * The masked interrupt status bit for CH2_TX_END_INT. 569 */ 570 uint32_t ch2_tx_end_int_st: 1; 571 /** ch3_tx_end_int_st : RO; bitpos: [3]; default: 0; 572 * The masked interrupt status bit for CH3_TX_END_INT. 573 */ 574 uint32_t ch3_tx_end_int_st: 1; 575 /** ch0_err_int_st : RO; bitpos: [4]; default: 0; 576 * The masked interrupt status bit for CH0_ERR_INT. 577 */ 578 uint32_t ch0_err_int_st: 1; 579 /** ch1_err_int_st : RO; bitpos: [5]; default: 0; 580 * The masked interrupt status bit for CH1_ERR_INT. 581 */ 582 uint32_t ch1_err_int_st: 1; 583 /** ch2_err_int_st : RO; bitpos: [6]; default: 0; 584 * The masked interrupt status bit for CH2_ERR_INT. 585 */ 586 uint32_t ch2_err_int_st: 1; 587 /** ch3_err_int_st : RO; bitpos: [7]; default: 0; 588 * The masked interrupt status bit for CH3_ERR_INT. 589 */ 590 uint32_t ch3_err_int_st: 1; 591 /** ch0_tx_thr_event_int_st : RO; bitpos: [8]; default: 0; 592 * The masked interrupt status bit for CH0_TX_THR_EVENT_INT. 593 */ 594 uint32_t ch0_tx_thr_event_int_st: 1; 595 /** ch1_tx_thr_event_int_st : RO; bitpos: [9]; default: 0; 596 * The masked interrupt status bit for CH1_TX_THR_EVENT_INT. 597 */ 598 uint32_t ch1_tx_thr_event_int_st: 1; 599 /** ch2_tx_thr_event_int_st : RO; bitpos: [10]; default: 0; 600 * The masked interrupt status bit for CH2_TX_THR_EVENT_INT. 601 */ 602 uint32_t ch2_tx_thr_event_int_st: 1; 603 /** ch3_tx_thr_event_int_st : RO; bitpos: [11]; default: 0; 604 * The masked interrupt status bit for CH3_TX_THR_EVENT_INT. 605 */ 606 uint32_t ch3_tx_thr_event_int_st: 1; 607 /** ch0_tx_loop_int_st : RO; bitpos: [12]; default: 0; 608 * The masked interrupt status bit for CH0_TX_LOOP_INT. 609 */ 610 uint32_t ch0_tx_loop_int_st: 1; 611 /** ch1_tx_loop_int_st : RO; bitpos: [13]; default: 0; 612 * The masked interrupt status bit for CH1_TX_LOOP_INT. 613 */ 614 uint32_t ch1_tx_loop_int_st: 1; 615 /** ch2_tx_loop_int_st : RO; bitpos: [14]; default: 0; 616 * The masked interrupt status bit for CH2_TX_LOOP_INT. 617 */ 618 uint32_t ch2_tx_loop_int_st: 1; 619 /** ch3_tx_loop_int_st : RO; bitpos: [15]; default: 0; 620 * The masked interrupt status bit for CH3_TX_LOOP_INT. 621 */ 622 uint32_t ch3_tx_loop_int_st: 1; 623 /** ch4_rx_end_int_st : RO; bitpos: [16]; default: 0; 624 * The masked interrupt status bit for CH4_RX_END_INT. 625 */ 626 uint32_t ch4_rx_end_int_st: 1; 627 /** ch5_rx_end_int_st : RO; bitpos: [17]; default: 0; 628 * The masked interrupt status bit for CH5_RX_END_INT. 629 */ 630 uint32_t ch5_rx_end_int_st: 1; 631 /** ch6_rx_end_int_st : RO; bitpos: [18]; default: 0; 632 * The masked interrupt status bit for CH6_RX_END_INT. 633 */ 634 uint32_t ch6_rx_end_int_st: 1; 635 /** ch7_rx_end_int_st : RO; bitpos: [19]; default: 0; 636 * The masked interrupt status bit for CH7_RX_END_INT. 637 */ 638 uint32_t ch7_rx_end_int_st: 1; 639 /** ch4_err_int_st : RO; bitpos: [20]; default: 0; 640 * The masked interrupt status bit for CH4_ERR_INT. 641 */ 642 uint32_t ch4_err_int_st: 1; 643 /** ch5_err_int_st : RO; bitpos: [21]; default: 0; 644 * The masked interrupt status bit for CH5_ERR_INT. 645 */ 646 uint32_t ch5_err_int_st: 1; 647 /** ch6_err_int_st : RO; bitpos: [22]; default: 0; 648 * The masked interrupt status bit for CH6_ERR_INT. 649 */ 650 uint32_t ch6_err_int_st: 1; 651 /** ch7_err_int_st : RO; bitpos: [23]; default: 0; 652 * The masked interrupt status bit for CH7_ERR_INT. 653 */ 654 uint32_t ch7_err_int_st: 1; 655 /** ch4_rx_thr_event_int_st : RO; bitpos: [24]; default: 0; 656 * The masked interrupt status bit for CH4_RX_THR_EVENT_INT. 657 */ 658 uint32_t ch4_rx_thr_event_int_st: 1; 659 /** ch5_rx_thr_event_int_st : RO; bitpos: [25]; default: 0; 660 * The masked interrupt status bit for CH5_RX_THR_EVENT_INT. 661 */ 662 uint32_t ch5_rx_thr_event_int_st: 1; 663 /** ch6_rx_thr_event_int_st : RO; bitpos: [26]; default: 0; 664 * The masked interrupt status bit for CH6_RX_THR_EVENT_INT. 665 */ 666 uint32_t ch6_rx_thr_event_int_st: 1; 667 /** ch7_rx_thr_event_int_st : RO; bitpos: [27]; default: 0; 668 * The masked interrupt status bit for CH7_RX_THR_EVENT_INT. 669 */ 670 uint32_t ch7_rx_thr_event_int_st: 1; 671 /** ch3_dma_access_fail_int_st : RO; bitpos: [28]; default: 0; 672 * The masked interrupt status bit for CH3_DMA_ACCESS_FAIL_INT. 673 */ 674 uint32_t ch3_dma_access_fail_int_st: 1; 675 /** ch7_dma_access_fail_int_st : RO; bitpos: [29]; default: 0; 676 * The masked interrupt status bit for CH7_DMA_ACCESS_FAIL_INT. 677 */ 678 uint32_t ch7_dma_access_fail_int_st: 1; 679 uint32_t reserved_30: 2; 680 }; 681 uint32_t val; 682 } rmt_int_st_reg_t; 683 684 /** Type of int_ena register 685 * Interrupt enable bits 686 */ 687 typedef union { 688 struct { 689 /** ch0_tx_end_int_ena : R/W; bitpos: [0]; default: 0; 690 * The interrupt enable bit for CH0_TX_END_INT. 691 */ 692 uint32_t ch0_tx_end_int_ena: 1; 693 /** ch1_tx_end_int_ena : R/W; bitpos: [1]; default: 0; 694 * The interrupt enable bit for CH1_TX_END_INT. 695 */ 696 uint32_t ch1_tx_end_int_ena: 1; 697 /** ch2_tx_end_int_ena : R/W; bitpos: [2]; default: 0; 698 * The interrupt enable bit for CH2_TX_END_INT. 699 */ 700 uint32_t ch2_tx_end_int_ena: 1; 701 /** ch3_tx_end_int_ena : R/W; bitpos: [3]; default: 0; 702 * The interrupt enable bit for CH3_TX_END_INT. 703 */ 704 uint32_t ch3_tx_end_int_ena: 1; 705 /** ch0_err_int_ena : R/W; bitpos: [4]; default: 0; 706 * The interrupt enable bit for CH0_ERR_INT. 707 */ 708 uint32_t ch0_err_int_ena: 1; 709 /** ch1_err_int_ena : R/W; bitpos: [5]; default: 0; 710 * The interrupt enable bit for CH1_ERR_INT. 711 */ 712 uint32_t ch1_err_int_ena: 1; 713 /** ch2_err_int_ena : R/W; bitpos: [6]; default: 0; 714 * The interrupt enable bit for CH2_ERR_INT. 715 */ 716 uint32_t ch2_err_int_ena: 1; 717 /** ch3_err_int_ena : R/W; bitpos: [7]; default: 0; 718 * The interrupt enable bit for CH3_ERR_INT. 719 */ 720 uint32_t ch3_err_int_ena: 1; 721 /** ch0_tx_thr_event_int_ena : R/W; bitpos: [8]; default: 0; 722 * The interrupt enable bit for CH0_TX_THR_EVENT_INT. 723 */ 724 uint32_t ch0_tx_thr_event_int_ena: 1; 725 /** ch1_tx_thr_event_int_ena : R/W; bitpos: [9]; default: 0; 726 * The interrupt enable bit for CH1_TX_THR_EVENT_INT. 727 */ 728 uint32_t ch1_tx_thr_event_int_ena: 1; 729 /** ch2_tx_thr_event_int_ena : R/W; bitpos: [10]; default: 0; 730 * The interrupt enable bit for CH2_TX_THR_EVENT_INT. 731 */ 732 uint32_t ch2_tx_thr_event_int_ena: 1; 733 /** ch3_tx_thr_event_int_ena : R/W; bitpos: [11]; default: 0; 734 * The interrupt enable bit for CH3_TX_THR_EVENT_INT. 735 */ 736 uint32_t ch3_tx_thr_event_int_ena: 1; 737 /** ch0_tx_loop_int_ena : R/W; bitpos: [12]; default: 0; 738 * The interrupt enable bit for CH0_TX_LOOP_INT. 739 */ 740 uint32_t ch0_tx_loop_int_ena: 1; 741 /** ch1_tx_loop_int_ena : R/W; bitpos: [13]; default: 0; 742 * The interrupt enable bit for CH1_TX_LOOP_INT. 743 */ 744 uint32_t ch1_tx_loop_int_ena: 1; 745 /** ch2_tx_loop_int_ena : R/W; bitpos: [14]; default: 0; 746 * The interrupt enable bit for CH2_TX_LOOP_INT. 747 */ 748 uint32_t ch2_tx_loop_int_ena: 1; 749 /** ch3_tx_loop_int_ena : R/W; bitpos: [15]; default: 0; 750 * The interrupt enable bit for CH3_TX_LOOP_INT. 751 */ 752 uint32_t ch3_tx_loop_int_ena: 1; 753 /** ch4_rx_end_int_ena : R/W; bitpos: [16]; default: 0; 754 * The interrupt enable bit for CH4_RX_END_INT. 755 */ 756 uint32_t ch4_rx_end_int_ena: 1; 757 /** ch5_rx_end_int_ena : R/W; bitpos: [17]; default: 0; 758 * The interrupt enable bit for CH5_RX_END_INT. 759 */ 760 uint32_t ch5_rx_end_int_ena: 1; 761 /** ch6_rx_end_int_ena : R/W; bitpos: [18]; default: 0; 762 * The interrupt enable bit for CH6_RX_END_INT. 763 */ 764 uint32_t ch6_rx_end_int_ena: 1; 765 /** ch7_rx_end_int_ena : R/W; bitpos: [19]; default: 0; 766 * The interrupt enable bit for CH7_RX_END_INT. 767 */ 768 uint32_t ch7_rx_end_int_ena: 1; 769 /** ch4_err_int_ena : R/W; bitpos: [20]; default: 0; 770 * The interrupt enable bit for CH4_ERR_INT. 771 */ 772 uint32_t ch4_err_int_ena: 1; 773 /** ch5_err_int_ena : R/W; bitpos: [21]; default: 0; 774 * The interrupt enable bit for CH5_ERR_INT. 775 */ 776 uint32_t ch5_err_int_ena: 1; 777 /** ch6_err_int_ena : R/W; bitpos: [22]; default: 0; 778 * The interrupt enable bit for CH6_ERR_INT. 779 */ 780 uint32_t ch6_err_int_ena: 1; 781 /** ch7_err_int_ena : R/W; bitpos: [23]; default: 0; 782 * The interrupt enable bit for CH7_ERR_INT. 783 */ 784 uint32_t ch7_err_int_ena: 1; 785 /** ch4_rx_thr_event_int_ena : R/W; bitpos: [24]; default: 0; 786 * The interrupt enable bit for CH4_RX_THR_EVENT_INT. 787 */ 788 uint32_t ch4_rx_thr_event_int_ena: 1; 789 /** ch5_rx_thr_event_int_ena : R/W; bitpos: [25]; default: 0; 790 * The interrupt enable bit for CH5_RX_THR_EVENT_INT. 791 */ 792 uint32_t ch5_rx_thr_event_int_ena: 1; 793 /** ch6_rx_thr_event_int_ena : R/W; bitpos: [26]; default: 0; 794 * The interrupt enable bit for CH6_RX_THR_EVENT_INT. 795 */ 796 uint32_t ch6_rx_thr_event_int_ena: 1; 797 /** ch7_rx_thr_event_int_ena : R/W; bitpos: [27]; default: 0; 798 * The interrupt enable bit for CH7_RX_THR_EVENT_INT. 799 */ 800 uint32_t ch7_rx_thr_event_int_ena: 1; 801 /** ch3_dma_access_fail_int_ena : R/W; bitpos: [28]; default: 0; 802 * The interrupt enable bit for CH3_DMA_ACCESS_FAIL_INT. 803 */ 804 uint32_t ch3_dma_access_fail_int_ena: 1; 805 /** ch7_dma_access_fail_int_ena : R/W; bitpos: [29]; default: 0; 806 * The interrupt enable bit for CH7_DMA_ACCESS_FAIL_INT. 807 */ 808 uint32_t ch7_dma_access_fail_int_ena: 1; 809 uint32_t reserved_30: 2; 810 }; 811 uint32_t val; 812 } rmt_int_ena_reg_t; 813 814 /** Type of int_clr register 815 * Interrupt clear bits 816 */ 817 typedef union { 818 struct { 819 /** ch0_tx_end_int_clr : WT; bitpos: [0]; default: 0; 820 * Set this bit to clear theCH0_TX_END_INT interrupt. 821 */ 822 uint32_t ch0_tx_end_int_clr: 1; 823 /** ch1_tx_end_int_clr : WT; bitpos: [1]; default: 0; 824 * Set this bit to clear theCH1_TX_END_INT interrupt. 825 */ 826 uint32_t ch1_tx_end_int_clr: 1; 827 /** ch2_tx_end_int_clr : WT; bitpos: [2]; default: 0; 828 * Set this bit to clear theCH2_TX_END_INT interrupt. 829 */ 830 uint32_t ch2_tx_end_int_clr: 1; 831 /** ch3_tx_end_int_clr : WT; bitpos: [3]; default: 0; 832 * Set this bit to clear theCH3_TX_END_INT interrupt. 833 */ 834 uint32_t ch3_tx_end_int_clr: 1; 835 /** ch0_err_int_clr : WT; bitpos: [4]; default: 0; 836 * Set this bit to clear theCH0_ERR_INT interrupt. 837 */ 838 uint32_t ch0_err_int_clr: 1; 839 /** ch1_err_int_clr : WT; bitpos: [5]; default: 0; 840 * Set this bit to clear theCH1_ERR_INT interrupt. 841 */ 842 uint32_t ch1_err_int_clr: 1; 843 /** ch2_err_int_clr : WT; bitpos: [6]; default: 0; 844 * Set this bit to clear theCH2_ERR_INT interrupt. 845 */ 846 uint32_t ch2_err_int_clr: 1; 847 /** ch3_err_int_clr : WT; bitpos: [7]; default: 0; 848 * Set this bit to clear theCH3_ERR_INT interrupt. 849 */ 850 uint32_t ch3_err_int_clr: 1; 851 /** ch0_tx_thr_event_int_clr : WT; bitpos: [8]; default: 0; 852 * Set this bit to clear theCH0_TX_THR_EVENT_INT interrupt. 853 */ 854 uint32_t ch0_tx_thr_event_int_clr: 1; 855 /** ch1_tx_thr_event_int_clr : WT; bitpos: [9]; default: 0; 856 * Set this bit to clear theCH1_TX_THR_EVENT_INT interrupt. 857 */ 858 uint32_t ch1_tx_thr_event_int_clr: 1; 859 /** ch2_tx_thr_event_int_clr : WT; bitpos: [10]; default: 0; 860 * Set this bit to clear theCH2_TX_THR_EVENT_INT interrupt. 861 */ 862 uint32_t ch2_tx_thr_event_int_clr: 1; 863 /** ch3_tx_thr_event_int_clr : WT; bitpos: [11]; default: 0; 864 * Set this bit to clear theCH3_TX_THR_EVENT_INT interrupt. 865 */ 866 uint32_t ch3_tx_thr_event_int_clr: 1; 867 /** ch0_tx_loop_int_clr : WT; bitpos: [12]; default: 0; 868 * Set this bit to clear theCH0_TX_LOOP_INT interrupt. 869 */ 870 uint32_t ch0_tx_loop_int_clr: 1; 871 /** ch1_tx_loop_int_clr : WT; bitpos: [13]; default: 0; 872 * Set this bit to clear theCH1_TX_LOOP_INT interrupt. 873 */ 874 uint32_t ch1_tx_loop_int_clr: 1; 875 /** ch2_tx_loop_int_clr : WT; bitpos: [14]; default: 0; 876 * Set this bit to clear theCH2_TX_LOOP_INT interrupt. 877 */ 878 uint32_t ch2_tx_loop_int_clr: 1; 879 /** ch3_tx_loop_int_clr : WT; bitpos: [15]; default: 0; 880 * Set this bit to clear theCH3_TX_LOOP_INT interrupt. 881 */ 882 uint32_t ch3_tx_loop_int_clr: 1; 883 /** ch4_rx_end_int_clr : WT; bitpos: [16]; default: 0; 884 * Set this bit to clear theCH4_RX_END_INT interrupt. 885 */ 886 uint32_t ch4_rx_end_int_clr: 1; 887 /** ch5_rx_end_int_clr : WT; bitpos: [17]; default: 0; 888 * Set this bit to clear theCH5_RX_END_INT interrupt. 889 */ 890 uint32_t ch5_rx_end_int_clr: 1; 891 /** ch6_rx_end_int_clr : WT; bitpos: [18]; default: 0; 892 * Set this bit to clear theCH6_RX_END_INT interrupt. 893 */ 894 uint32_t ch6_rx_end_int_clr: 1; 895 /** ch7_rx_end_int_clr : WT; bitpos: [19]; default: 0; 896 * Set this bit to clear theCH7_RX_END_INT interrupt. 897 */ 898 uint32_t ch7_rx_end_int_clr: 1; 899 /** ch4_err_int_clr : WT; bitpos: [20]; default: 0; 900 * Set this bit to clear theCH4_ERR_INT interrupt. 901 */ 902 uint32_t ch4_err_int_clr: 1; 903 /** ch5_err_int_clr : WT; bitpos: [21]; default: 0; 904 * Set this bit to clear theCH5_ERR_INT interrupt. 905 */ 906 uint32_t ch5_err_int_clr: 1; 907 /** ch6_err_int_clr : WT; bitpos: [22]; default: 0; 908 * Set this bit to clear theCH6_ERR_INT interrupt. 909 */ 910 uint32_t ch6_err_int_clr: 1; 911 /** ch7_err_int_clr : WT; bitpos: [23]; default: 0; 912 * Set this bit to clear theCH7_ERR_INT interrupt. 913 */ 914 uint32_t ch7_err_int_clr: 1; 915 /** ch4_rx_thr_event_int_clr : WT; bitpos: [24]; default: 0; 916 * Set this bit to clear theCH4_RX_THR_EVENT_INT interrupt. 917 */ 918 uint32_t ch4_rx_thr_event_int_clr: 1; 919 /** ch5_rx_thr_event_int_clr : WT; bitpos: [25]; default: 0; 920 * Set this bit to clear theCH5_RX_THR_EVENT_INT interrupt. 921 */ 922 uint32_t ch5_rx_thr_event_int_clr: 1; 923 /** ch6_rx_thr_event_int_clr : WT; bitpos: [26]; default: 0; 924 * Set this bit to clear theCH6_RX_THR_EVENT_INT interrupt. 925 */ 926 uint32_t ch6_rx_thr_event_int_clr: 1; 927 /** ch7_rx_thr_event_int_clr : WT; bitpos: [27]; default: 0; 928 * Set this bit to clear theCH7_RX_THR_EVENT_INT interrupt. 929 */ 930 uint32_t ch7_rx_thr_event_int_clr: 1; 931 /** ch3_dma_access_fail_int_clr : WT; bitpos: [28]; default: 0; 932 * Set this bit to clear the CH3_DMA_ACCESS_FAIL_INT interrupt. 933 */ 934 uint32_t ch3_dma_access_fail_int_clr: 1; 935 /** ch7_dma_access_fail_int_clr : WT; bitpos: [29]; default: 0; 936 * Set this bit to clear the CH7_DMA_ACCESS_FAIL_INT interrupt. 937 */ 938 uint32_t ch7_dma_access_fail_int_clr: 1; 939 uint32_t reserved_30: 2; 940 }; 941 uint32_t val; 942 } rmt_int_clr_reg_t; 943 944 945 /** Group: Carrier wave duty cycle registers */ 946 /** Type of chncarrier_duty register 947 * Channel n duty cycle configuration register 948 */ 949 typedef union { 950 struct { 951 /** carrier_low_chn : R/W; bitpos: [15:0]; default: 64; 952 * This register is used to configure carrier wave 's low level clock period for 953 * CHANNELn. 954 */ 955 uint32_t carrier_low_chn: 16; 956 /** carrier_high_chn : R/W; bitpos: [31:16]; default: 64; 957 * This register is used to configure carrier wave 's high level clock period for 958 * CHANNELn. 959 */ 960 uint32_t carrier_high_chn: 16; 961 }; 962 uint32_t val; 963 } rmt_chncarrier_duty_reg_t; 964 965 966 /** Group: Tx event configuration registers */ 967 /** Type of chn_tx_lim register 968 * Channel n Tx event configuration register 969 */ 970 typedef union { 971 struct { 972 /** tx_lim_chn : R/W; bitpos: [8:0]; default: 128; 973 * This register is used to configure the maximum entries that CHANNELn can send out. 974 */ 975 uint32_t tx_lim_chn: 9; 976 /** tx_loop_num_chn : R/W; bitpos: [18:9]; default: 0; 977 * This register is used to configure the maximum loop count when tx_conti_mode is 978 * valid. 979 */ 980 uint32_t tx_loop_num_chn: 10; 981 /** tx_loop_cnt_en_chn : R/W; bitpos: [19]; default: 0; 982 * This register is the enabled bit for loop count. 983 */ 984 uint32_t tx_loop_cnt_en_chn: 1; 985 /** loop_count_reset_chn : WT; bitpos: [20]; default: 0; 986 * This register is used to reset the loop count when tx_conti_mode is valid. 987 */ 988 uint32_t loop_count_reset_chn: 1; 989 /** loop_stop_en_chn : R/W; bitpos: [21]; default: 0; 990 * This bit is used to enable the loop send stop function after the loop counter 991 * counts to loop number for CHANNELn. 992 */ 993 uint32_t loop_stop_en_chn: 1; 994 uint32_t reserved_22: 10; 995 }; 996 uint32_t val; 997 } rmt_chn_tx_lim_reg_t; 998 999 /** Type of tx_sim register 1000 * RMT TX synchronous register 1001 */ 1002 typedef union { 1003 struct { 1004 /** tx_sim_ch0 : R/W; bitpos: [0]; default: 0; 1005 * Set this bit to enable CHANNEL0 to start sending data synchronously with other 1006 * enabled channels. 1007 */ 1008 uint32_t tx_sim_ch0: 1; 1009 /** tx_sim_ch1 : R/W; bitpos: [1]; default: 0; 1010 * Set this bit to enable CHANNEL1 to start sending data synchronously with other 1011 * enabled channels. 1012 */ 1013 uint32_t tx_sim_ch1: 1; 1014 /** tx_sim_ch2 : R/W; bitpos: [2]; default: 0; 1015 * Set this bit to enable CHANNEL2 to start sending data synchronously with other 1016 * enabled channels. 1017 */ 1018 uint32_t tx_sim_ch2: 1; 1019 /** tx_sim_ch3 : R/W; bitpos: [3]; default: 0; 1020 * Set this bit to enable CHANNEL3 to start sending data synchronously with other 1021 * enabled channels. 1022 */ 1023 uint32_t tx_sim_ch3: 1; 1024 /** tx_sim_en : R/W; bitpos: [4]; default: 0; 1025 * This register is used to enable multiple of channels to start sending data 1026 * synchronously. 1027 */ 1028 uint32_t tx_sim_en: 1; 1029 uint32_t reserved_5: 27; 1030 }; 1031 uint32_t val; 1032 } rmt_tx_sim_reg_t; 1033 1034 1035 /** Group: Rx event configuration registers */ 1036 /** Type of chm_rx_lim register 1037 * Channel m Rx event configuration register 1038 */ 1039 typedef union { 1040 struct { 1041 /** chm_rx_lim_reg : R/W; bitpos: [8:0]; default: 128; 1042 * This register is used to configure the maximum entries that CHANNELm can receive. 1043 */ 1044 uint32_t chm_rx_lim_reg: 9; 1045 uint32_t reserved_9: 23; 1046 }; 1047 uint32_t val; 1048 } rmt_chm_rx_lim_reg_t; 1049 1050 1051 /** Group: Version register */ 1052 /** Type of date register 1053 * RMT version register 1054 */ 1055 typedef union { 1056 struct { 1057 /** date : R/W; bitpos: [27:0]; default: 34607489; 1058 * This is the version register. 1059 */ 1060 uint32_t date: 28; 1061 uint32_t reserved_28: 4; 1062 }; 1063 uint32_t val; 1064 } rmt_date_reg_t; 1065 1066 1067 typedef struct { 1068 volatile rmt_chndata_reg_t chndata[4]; 1069 volatile rmt_chmdata_reg_t chmdata[4]; 1070 volatile rmt_chnconf0_reg_t chnconf0[4]; 1071 volatile rmt_chmconf_reg_t chmconf[4]; 1072 volatile rmt_chnstatus_reg_t chnstatus[4]; 1073 volatile rmt_chmstatus_reg_t chmstatus[4]; 1074 volatile rmt_int_raw_reg_t int_raw; 1075 volatile rmt_int_st_reg_t int_st; 1076 volatile rmt_int_ena_reg_t int_ena; 1077 volatile rmt_int_clr_reg_t int_clr; 1078 volatile rmt_chncarrier_duty_reg_t chncarrier_duty[4]; 1079 volatile rmt_chm_rx_carrier_rm_reg_t chm_rx_carrier_rm[4]; 1080 volatile rmt_chn_tx_lim_reg_t chn_tx_lim[4]; 1081 volatile rmt_chm_rx_lim_reg_t chm_rx_lim[4]; 1082 volatile rmt_sys_conf_reg_t sys_conf; 1083 volatile rmt_tx_sim_reg_t tx_sim; 1084 volatile rmt_ref_cnt_rst_reg_t ref_cnt_rst; 1085 volatile rmt_date_reg_t date; 1086 } rmt_dev_t; 1087 1088 #ifndef __cplusplus 1089 _Static_assert(sizeof(rmt_dev_t) == 0xd0, "Invalid size of rmt_dev_t structure"); 1090 #endif 1091 1092 typedef struct { 1093 union { 1094 struct { 1095 uint32_t duration0 : 15; 1096 uint32_t level0 : 1; 1097 uint32_t duration1 : 15; 1098 uint32_t level1 : 1; 1099 }; 1100 uint32_t val; 1101 }; 1102 } rmt_item32_t; 1103 1104 typedef struct { 1105 struct { 1106 volatile rmt_item32_t data32[48]; 1107 } chan[8]; 1108 } rmt_mem_t; 1109 1110 #ifndef __cplusplus 1111 _Static_assert(sizeof(rmt_item32_t) == 0x04, "Invalid size of rmt_item32_t structure"); 1112 _Static_assert(sizeof(rmt_mem_t) == 0x04 * 8 * 48, "Invalid size of rmt_mem_t structure"); 1113 #endif 1114 1115 extern rmt_dev_t RMT; 1116 extern rmt_mem_t RMTMEM; 1117 1118 #ifdef __cplusplus 1119 } 1120 #endif 1121
