1 // Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 // 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 #ifndef _SOC_SYSTEM_REG_H_ 15 #define _SOC_SYSTEM_REG_H_ 16 17 18 #include "soc.h" 19 #ifdef __cplusplus 20 extern "C" { 21 #endif 22 23 #define SYSTEM_CORE_1_CONTROL_0_REG (DR_REG_SYSTEM_BASE + 0x0) 24 /* SYSTEM_CONTROL_CORE_1_RESETTING : R/W ;bitpos:[2] ;default: 1'b1 ; */ 25 /*description: .*/ 26 #define SYSTEM_CONTROL_CORE_1_RESETTING (BIT(2)) 27 #define SYSTEM_CONTROL_CORE_1_RESETTING_M (BIT(2)) 28 #define SYSTEM_CONTROL_CORE_1_RESETTING_V 0x1 29 #define SYSTEM_CONTROL_CORE_1_RESETTING_S 2 30 /* SYSTEM_CONTROL_CORE_1_CLKGATE_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */ 31 /*description: .*/ 32 #define SYSTEM_CONTROL_CORE_1_CLKGATE_EN (BIT(1)) 33 #define SYSTEM_CONTROL_CORE_1_CLKGATE_EN_M (BIT(1)) 34 #define SYSTEM_CONTROL_CORE_1_CLKGATE_EN_V 0x1 35 #define SYSTEM_CONTROL_CORE_1_CLKGATE_EN_S 1 36 /* SYSTEM_CONTROL_CORE_1_RUNSTALL : R/W ;bitpos:[0] ;default: 1'b0 ; */ 37 /*description: .*/ 38 #define SYSTEM_CONTROL_CORE_1_RUNSTALL (BIT(0)) 39 #define SYSTEM_CONTROL_CORE_1_RUNSTALL_M (BIT(0)) 40 #define SYSTEM_CONTROL_CORE_1_RUNSTALL_V 0x1 41 #define SYSTEM_CONTROL_CORE_1_RUNSTALL_S 0 42 43 #define SYSTEM_CORE_1_CONTROL_1_REG (DR_REG_SYSTEM_BASE + 0x4) 44 /* SYSTEM_CONTROL_CORE_1_MESSAGE : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ 45 /*description: .*/ 46 #define SYSTEM_CONTROL_CORE_1_MESSAGE 0xFFFFFFFF 47 #define SYSTEM_CONTROL_CORE_1_MESSAGE_M ((SYSTEM_CONTROL_CORE_1_MESSAGE_V)<<(SYSTEM_CONTROL_CORE_1_MESSAGE_S)) 48 #define SYSTEM_CONTROL_CORE_1_MESSAGE_V 0xFFFFFFFF 49 #define SYSTEM_CONTROL_CORE_1_MESSAGE_S 0 50 51 #define SYSTEM_CPU_PERI_CLK_EN_REG (DR_REG_SYSTEM_BASE + 0x8) 52 /* SYSTEM_CLK_EN_DEDICATED_GPIO : R/W ;bitpos:[7] ;default: 1'b0 ; */ 53 /*description: .*/ 54 #define SYSTEM_CLK_EN_DEDICATED_GPIO (BIT(7)) 55 #define SYSTEM_CLK_EN_DEDICATED_GPIO_M (BIT(7)) 56 #define SYSTEM_CLK_EN_DEDICATED_GPIO_V 0x1 57 #define SYSTEM_CLK_EN_DEDICATED_GPIO_S 7 58 /* SYSTEM_CLK_EN_ASSIST_DEBUG : R/W ;bitpos:[6] ;default: 1'b0 ; */ 59 /*description: .*/ 60 #define SYSTEM_CLK_EN_ASSIST_DEBUG (BIT(6)) 61 #define SYSTEM_CLK_EN_ASSIST_DEBUG_M (BIT(6)) 62 #define SYSTEM_CLK_EN_ASSIST_DEBUG_V 0x1 63 #define SYSTEM_CLK_EN_ASSIST_DEBUG_S 6 64 65 #define SYSTEM_CPU_PERI_RST_EN_REG (DR_REG_SYSTEM_BASE + 0xC) 66 /* SYSTEM_RST_EN_DEDICATED_GPIO : R/W ;bitpos:[7] ;default: 1'b1 ; */ 67 /*description: .*/ 68 #define SYSTEM_RST_EN_DEDICATED_GPIO (BIT(7)) 69 #define SYSTEM_RST_EN_DEDICATED_GPIO_M (BIT(7)) 70 #define SYSTEM_RST_EN_DEDICATED_GPIO_V 0x1 71 #define SYSTEM_RST_EN_DEDICATED_GPIO_S 7 72 /* SYSTEM_RST_EN_ASSIST_DEBUG : R/W ;bitpos:[6] ;default: 1'b1 ; */ 73 /*description: .*/ 74 #define SYSTEM_RST_EN_ASSIST_DEBUG (BIT(6)) 75 #define SYSTEM_RST_EN_ASSIST_DEBUG_M (BIT(6)) 76 #define SYSTEM_RST_EN_ASSIST_DEBUG_V 0x1 77 #define SYSTEM_RST_EN_ASSIST_DEBUG_S 6 78 79 #define SYSTEM_CPU_PER_CONF_REG (DR_REG_SYSTEM_BASE + 0x10) 80 /* SYSTEM_CPU_WAITI_DELAY_NUM : R/W ;bitpos:[7:4] ;default: 4'h0 ; */ 81 /*description: .*/ 82 #define SYSTEM_CPU_WAITI_DELAY_NUM 0x0000000F 83 #define SYSTEM_CPU_WAITI_DELAY_NUM_M ((SYSTEM_CPU_WAITI_DELAY_NUM_V)<<(SYSTEM_CPU_WAITI_DELAY_NUM_S)) 84 #define SYSTEM_CPU_WAITI_DELAY_NUM_V 0xF 85 #define SYSTEM_CPU_WAITI_DELAY_NUM_S 4 86 /* SYSTEM_CPU_WAIT_MODE_FORCE_ON : R/W ;bitpos:[3] ;default: 1'b1 ; */ 87 /*description: .*/ 88 #define SYSTEM_CPU_WAIT_MODE_FORCE_ON (BIT(3)) 89 #define SYSTEM_CPU_WAIT_MODE_FORCE_ON_M (BIT(3)) 90 #define SYSTEM_CPU_WAIT_MODE_FORCE_ON_V 0x1 91 #define SYSTEM_CPU_WAIT_MODE_FORCE_ON_S 3 92 /* SYSTEM_PLL_FREQ_SEL : R/W ;bitpos:[2] ;default: 1'b1 ; */ 93 /*description: .*/ 94 #define SYSTEM_PLL_FREQ_SEL (BIT(2)) 95 #define SYSTEM_PLL_FREQ_SEL_M (BIT(2)) 96 #define SYSTEM_PLL_FREQ_SEL_V 0x1 97 #define SYSTEM_PLL_FREQ_SEL_S 2 98 /* SYSTEM_CPUPERIOD_SEL : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ 99 /*description: .*/ 100 #define SYSTEM_CPUPERIOD_SEL 0x00000003 101 #define SYSTEM_CPUPERIOD_SEL_M ((SYSTEM_CPUPERIOD_SEL_V)<<(SYSTEM_CPUPERIOD_SEL_S)) 102 #define SYSTEM_CPUPERIOD_SEL_V 0x3 103 #define SYSTEM_CPUPERIOD_SEL_S 0 104 105 #define SYSTEM_MEM_PD_MASK_REG (DR_REG_SYSTEM_BASE + 0x14) 106 /* SYSTEM_LSLP_MEM_PD_MASK : R/W ;bitpos:[0] ;default: 1'b1 ; */ 107 /*description: .*/ 108 #define SYSTEM_LSLP_MEM_PD_MASK (BIT(0)) 109 #define SYSTEM_LSLP_MEM_PD_MASK_M (BIT(0)) 110 #define SYSTEM_LSLP_MEM_PD_MASK_V 0x1 111 #define SYSTEM_LSLP_MEM_PD_MASK_S 0 112 113 #define SYSTEM_PERIP_CLK_EN0_REG (DR_REG_SYSTEM_BASE + 0x18) 114 /* SYSTEM_SPI4_CLK_EN : R/W ;bitpos:[31] ;default: 1'h1 ; */ 115 /*description: .*/ 116 #define SYSTEM_SPI4_CLK_EN (BIT(31)) 117 #define SYSTEM_SPI4_CLK_EN_M (BIT(31)) 118 #define SYSTEM_SPI4_CLK_EN_V 0x1 119 #define SYSTEM_SPI4_CLK_EN_S 31 120 /* SYSTEM_ADC2_ARB_CLK_EN : R/W ;bitpos:[30] ;default: 1'b1 ; */ 121 /*description: .*/ 122 #define SYSTEM_ADC2_ARB_CLK_EN (BIT(30)) 123 #define SYSTEM_ADC2_ARB_CLK_EN_M (BIT(30)) 124 #define SYSTEM_ADC2_ARB_CLK_EN_V 0x1 125 #define SYSTEM_ADC2_ARB_CLK_EN_S 30 126 /* SYSTEM_SYSTIMER_CLK_EN : R/W ;bitpos:[29] ;default: 1'b1 ; */ 127 /*description: .*/ 128 #define SYSTEM_SYSTIMER_CLK_EN (BIT(29)) 129 #define SYSTEM_SYSTIMER_CLK_EN_M (BIT(29)) 130 #define SYSTEM_SYSTIMER_CLK_EN_V 0x1 131 #define SYSTEM_SYSTIMER_CLK_EN_S 29 132 /* SYSTEM_APB_SARADC_CLK_EN : R/W ;bitpos:[28] ;default: 1'b1 ; */ 133 /*description: .*/ 134 #define SYSTEM_APB_SARADC_CLK_EN (BIT(28)) 135 #define SYSTEM_APB_SARADC_CLK_EN_M (BIT(28)) 136 #define SYSTEM_APB_SARADC_CLK_EN_V 0x1 137 #define SYSTEM_APB_SARADC_CLK_EN_S 28 138 /* SYSTEM_SPI3_DMA_CLK_EN : R/W ;bitpos:[27] ;default: 1'b1 ; */ 139 /*description: .*/ 140 #define SYSTEM_SPI3_DMA_CLK_EN (BIT(27)) 141 #define SYSTEM_SPI3_DMA_CLK_EN_M (BIT(27)) 142 #define SYSTEM_SPI3_DMA_CLK_EN_V 0x1 143 #define SYSTEM_SPI3_DMA_CLK_EN_S 27 144 /* SYSTEM_PWM3_CLK_EN : R/W ;bitpos:[26] ;default: 1'b0 ; */ 145 /*description: .*/ 146 #define SYSTEM_PWM3_CLK_EN (BIT(26)) 147 #define SYSTEM_PWM3_CLK_EN_M (BIT(26)) 148 #define SYSTEM_PWM3_CLK_EN_V 0x1 149 #define SYSTEM_PWM3_CLK_EN_S 26 150 /* SYSTEM_PWM2_CLK_EN : R/W ;bitpos:[25] ;default: 1'b0 ; */ 151 /*description: .*/ 152 #define SYSTEM_PWM2_CLK_EN (BIT(25)) 153 #define SYSTEM_PWM2_CLK_EN_M (BIT(25)) 154 #define SYSTEM_PWM2_CLK_EN_V 0x1 155 #define SYSTEM_PWM2_CLK_EN_S 25 156 /* SYSTEM_UART_MEM_CLK_EN : R/W ;bitpos:[24] ;default: 1'b1 ; */ 157 /*description: .*/ 158 #define SYSTEM_UART_MEM_CLK_EN (BIT(24)) 159 #define SYSTEM_UART_MEM_CLK_EN_M (BIT(24)) 160 #define SYSTEM_UART_MEM_CLK_EN_V 0x1 161 #define SYSTEM_UART_MEM_CLK_EN_S 24 162 /* SYSTEM_USB_CLK_EN : R/W ;bitpos:[23] ;default: 1'b1 ; */ 163 /*description: .*/ 164 #define SYSTEM_USB_CLK_EN (BIT(23)) 165 #define SYSTEM_USB_CLK_EN_M (BIT(23)) 166 #define SYSTEM_USB_CLK_EN_V 0x1 167 #define SYSTEM_USB_CLK_EN_S 23 168 /* SYSTEM_SPI2_DMA_CLK_EN : R/W ;bitpos:[22] ;default: 1'b1 ; */ 169 /*description: .*/ 170 #define SYSTEM_SPI2_DMA_CLK_EN (BIT(22)) 171 #define SYSTEM_SPI2_DMA_CLK_EN_M (BIT(22)) 172 #define SYSTEM_SPI2_DMA_CLK_EN_V 0x1 173 #define SYSTEM_SPI2_DMA_CLK_EN_S 22 174 /* SYSTEM_I2S1_CLK_EN : R/W ;bitpos:[21] ;default: 1'b0 ; */ 175 /*description: .*/ 176 #define SYSTEM_I2S1_CLK_EN (BIT(21)) 177 #define SYSTEM_I2S1_CLK_EN_M (BIT(21)) 178 #define SYSTEM_I2S1_CLK_EN_V 0x1 179 #define SYSTEM_I2S1_CLK_EN_S 21 180 /* SYSTEM_PWM1_CLK_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */ 181 /*description: .*/ 182 #define SYSTEM_PWM1_CLK_EN (BIT(20)) 183 #define SYSTEM_PWM1_CLK_EN_M (BIT(20)) 184 #define SYSTEM_PWM1_CLK_EN_V 0x1 185 #define SYSTEM_PWM1_CLK_EN_S 20 186 /* SYSTEM_TWAI_CLK_EN : R/W ;bitpos:[19] ;default: 1'b0 ; */ 187 /*description: .*/ 188 #define SYSTEM_TWAI_CLK_EN (BIT(19)) 189 #define SYSTEM_TWAI_CLK_EN_M (BIT(19)) 190 #define SYSTEM_TWAI_CLK_EN_V 0x1 191 #define SYSTEM_TWAI_CLK_EN_S 19 192 /* SYSTEM_I2C_EXT1_CLK_EN : R/W ;bitpos:[18] ;default: 1'b0 ; */ 193 /*description: .*/ 194 #define SYSTEM_I2C_EXT1_CLK_EN (BIT(18)) 195 #define SYSTEM_I2C_EXT1_CLK_EN_M (BIT(18)) 196 #define SYSTEM_I2C_EXT1_CLK_EN_V 0x1 197 #define SYSTEM_I2C_EXT1_CLK_EN_S 18 198 /* SYSTEM_PWM0_CLK_EN : R/W ;bitpos:[17] ;default: 1'b0 ; */ 199 /*description: .*/ 200 #define SYSTEM_PWM0_CLK_EN (BIT(17)) 201 #define SYSTEM_PWM0_CLK_EN_M (BIT(17)) 202 #define SYSTEM_PWM0_CLK_EN_V 0x1 203 #define SYSTEM_PWM0_CLK_EN_S 17 204 /* SYSTEM_SPI3_CLK_EN : R/W ;bitpos:[16] ;default: 1'b1 ; */ 205 /*description: .*/ 206 #define SYSTEM_SPI3_CLK_EN (BIT(16)) 207 #define SYSTEM_SPI3_CLK_EN_M (BIT(16)) 208 #define SYSTEM_SPI3_CLK_EN_V 0x1 209 #define SYSTEM_SPI3_CLK_EN_S 16 210 /* SYSTEM_TIMERGROUP1_CLK_EN : R/W ;bitpos:[15] ;default: 1'b1 ; */ 211 /*description: .*/ 212 #define SYSTEM_TIMERGROUP1_CLK_EN (BIT(15)) 213 #define SYSTEM_TIMERGROUP1_CLK_EN_M (BIT(15)) 214 #define SYSTEM_TIMERGROUP1_CLK_EN_V 0x1 215 #define SYSTEM_TIMERGROUP1_CLK_EN_S 15 216 /* SYSTEM_EFUSE_CLK_EN : R/W ;bitpos:[14] ;default: 1'b1 ; */ 217 /*description: .*/ 218 #define SYSTEM_EFUSE_CLK_EN (BIT(14)) 219 #define SYSTEM_EFUSE_CLK_EN_M (BIT(14)) 220 #define SYSTEM_EFUSE_CLK_EN_V 0x1 221 #define SYSTEM_EFUSE_CLK_EN_S 14 222 /* SYSTEM_TIMERGROUP_CLK_EN : R/W ;bitpos:[13] ;default: 1'b1 ; */ 223 /*description: .*/ 224 #define SYSTEM_TIMERGROUP_CLK_EN (BIT(13)) 225 #define SYSTEM_TIMERGROUP_CLK_EN_M (BIT(13)) 226 #define SYSTEM_TIMERGROUP_CLK_EN_V 0x1 227 #define SYSTEM_TIMERGROUP_CLK_EN_S 13 228 /* SYSTEM_UHCI1_CLK_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */ 229 /*description: .*/ 230 #define SYSTEM_UHCI1_CLK_EN (BIT(12)) 231 #define SYSTEM_UHCI1_CLK_EN_M (BIT(12)) 232 #define SYSTEM_UHCI1_CLK_EN_V 0x1 233 #define SYSTEM_UHCI1_CLK_EN_S 12 234 /* SYSTEM_LEDC_CLK_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */ 235 /*description: .*/ 236 #define SYSTEM_LEDC_CLK_EN (BIT(11)) 237 #define SYSTEM_LEDC_CLK_EN_M (BIT(11)) 238 #define SYSTEM_LEDC_CLK_EN_V 0x1 239 #define SYSTEM_LEDC_CLK_EN_S 11 240 /* SYSTEM_PCNT_CLK_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ 241 /*description: .*/ 242 #define SYSTEM_PCNT_CLK_EN (BIT(10)) 243 #define SYSTEM_PCNT_CLK_EN_M (BIT(10)) 244 #define SYSTEM_PCNT_CLK_EN_V 0x1 245 #define SYSTEM_PCNT_CLK_EN_S 10 246 /* SYSTEM_RMT_CLK_EN : R/W ;bitpos:[9] ;default: 1'b0 ; */ 247 /*description: .*/ 248 #define SYSTEM_RMT_CLK_EN (BIT(9)) 249 #define SYSTEM_RMT_CLK_EN_M (BIT(9)) 250 #define SYSTEM_RMT_CLK_EN_V 0x1 251 #define SYSTEM_RMT_CLK_EN_S 9 252 /* SYSTEM_UHCI0_CLK_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */ 253 /*description: .*/ 254 #define SYSTEM_UHCI0_CLK_EN (BIT(8)) 255 #define SYSTEM_UHCI0_CLK_EN_M (BIT(8)) 256 #define SYSTEM_UHCI0_CLK_EN_V 0x1 257 #define SYSTEM_UHCI0_CLK_EN_S 8 258 /* SYSTEM_I2C_EXT0_CLK_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */ 259 /*description: .*/ 260 #define SYSTEM_I2C_EXT0_CLK_EN (BIT(7)) 261 #define SYSTEM_I2C_EXT0_CLK_EN_M (BIT(7)) 262 #define SYSTEM_I2C_EXT0_CLK_EN_V 0x1 263 #define SYSTEM_I2C_EXT0_CLK_EN_S 7 264 /* SYSTEM_SPI2_CLK_EN : R/W ;bitpos:[6] ;default: 1'b1 ; */ 265 /*description: .*/ 266 #define SYSTEM_SPI2_CLK_EN (BIT(6)) 267 #define SYSTEM_SPI2_CLK_EN_M (BIT(6)) 268 #define SYSTEM_SPI2_CLK_EN_V 0x1 269 #define SYSTEM_SPI2_CLK_EN_S 6 270 /* SYSTEM_UART1_CLK_EN : R/W ;bitpos:[5] ;default: 1'b1 ; */ 271 /*description: .*/ 272 #define SYSTEM_UART1_CLK_EN (BIT(5)) 273 #define SYSTEM_UART1_CLK_EN_M (BIT(5)) 274 #define SYSTEM_UART1_CLK_EN_V 0x1 275 #define SYSTEM_UART1_CLK_EN_S 5 276 /* SYSTEM_I2S0_CLK_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */ 277 /*description: .*/ 278 #define SYSTEM_I2S0_CLK_EN (BIT(4)) 279 #define SYSTEM_I2S0_CLK_EN_M (BIT(4)) 280 #define SYSTEM_I2S0_CLK_EN_V 0x1 281 #define SYSTEM_I2S0_CLK_EN_S 4 282 /* SYSTEM_WDG_CLK_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */ 283 /*description: .*/ 284 #define SYSTEM_WDG_CLK_EN (BIT(3)) 285 #define SYSTEM_WDG_CLK_EN_M (BIT(3)) 286 #define SYSTEM_WDG_CLK_EN_V 0x1 287 #define SYSTEM_WDG_CLK_EN_S 3 288 /* SYSTEM_UART_CLK_EN : R/W ;bitpos:[2] ;default: 1'b1 ; */ 289 /*description: .*/ 290 #define SYSTEM_UART_CLK_EN (BIT(2)) 291 #define SYSTEM_UART_CLK_EN_M (BIT(2)) 292 #define SYSTEM_UART_CLK_EN_V 0x1 293 #define SYSTEM_UART_CLK_EN_S 2 294 /* SYSTEM_SPI01_CLK_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */ 295 /*description: .*/ 296 #define SYSTEM_SPI01_CLK_EN (BIT(1)) 297 #define SYSTEM_SPI01_CLK_EN_M (BIT(1)) 298 #define SYSTEM_SPI01_CLK_EN_V 0x1 299 #define SYSTEM_SPI01_CLK_EN_S 1 300 /* SYSTEM_TIMERS_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ 301 /*description: .*/ 302 #define SYSTEM_TIMERS_CLK_EN (BIT(0)) 303 #define SYSTEM_TIMERS_CLK_EN_M (BIT(0)) 304 #define SYSTEM_TIMERS_CLK_EN_V 0x1 305 #define SYSTEM_TIMERS_CLK_EN_S 0 306 307 #define SYSTEM_PERIP_CLK_EN1_REG (DR_REG_SYSTEM_BASE + 0x1C) 308 /* SYSTEM_USB_DEVICE_CLK_EN : R/W ;bitpos:[10] ;default: 1'b1 ; */ 309 /*description: .*/ 310 #define SYSTEM_USB_DEVICE_CLK_EN (BIT(10)) 311 #define SYSTEM_USB_DEVICE_CLK_EN_M (BIT(10)) 312 #define SYSTEM_USB_DEVICE_CLK_EN_V 0x1 313 #define SYSTEM_USB_DEVICE_CLK_EN_S 10 314 /* SYSTEM_UART2_CLK_EN : R/W ;bitpos:[9] ;default: 1'b1 ; */ 315 /*description: .*/ 316 #define SYSTEM_UART2_CLK_EN (BIT(9)) 317 #define SYSTEM_UART2_CLK_EN_M (BIT(9)) 318 #define SYSTEM_UART2_CLK_EN_V 0x1 319 #define SYSTEM_UART2_CLK_EN_S 9 320 /* SYSTEM_LCD_CAM_CLK_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */ 321 /*description: .*/ 322 #define SYSTEM_LCD_CAM_CLK_EN (BIT(8)) 323 #define SYSTEM_LCD_CAM_CLK_EN_M (BIT(8)) 324 #define SYSTEM_LCD_CAM_CLK_EN_V 0x1 325 #define SYSTEM_LCD_CAM_CLK_EN_S 8 326 /* SYSTEM_SDIO_HOST_CLK_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */ 327 /*description: .*/ 328 #define SYSTEM_SDIO_HOST_CLK_EN (BIT(7)) 329 #define SYSTEM_SDIO_HOST_CLK_EN_M (BIT(7)) 330 #define SYSTEM_SDIO_HOST_CLK_EN_V 0x1 331 #define SYSTEM_SDIO_HOST_CLK_EN_S 7 332 /* SYSTEM_DMA_CLK_EN : R/W ;bitpos:[6] ;default: 1'b0 ; */ 333 /*description: .*/ 334 #define SYSTEM_DMA_CLK_EN (BIT(6)) 335 #define SYSTEM_DMA_CLK_EN_M (BIT(6)) 336 #define SYSTEM_DMA_CLK_EN_V 0x1 337 #define SYSTEM_DMA_CLK_EN_S 6 338 /* SYSTEM_CRYPTO_HMAC_CLK_EN : R/W ;bitpos:[5] ;default: 1'b0 ; */ 339 /*description: .*/ 340 #define SYSTEM_CRYPTO_HMAC_CLK_EN (BIT(5)) 341 #define SYSTEM_CRYPTO_HMAC_CLK_EN_M (BIT(5)) 342 #define SYSTEM_CRYPTO_HMAC_CLK_EN_V 0x1 343 #define SYSTEM_CRYPTO_HMAC_CLK_EN_S 5 344 /* SYSTEM_CRYPTO_DS_CLK_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */ 345 /*description: .*/ 346 #define SYSTEM_CRYPTO_DS_CLK_EN (BIT(4)) 347 #define SYSTEM_CRYPTO_DS_CLK_EN_M (BIT(4)) 348 #define SYSTEM_CRYPTO_DS_CLK_EN_V 0x1 349 #define SYSTEM_CRYPTO_DS_CLK_EN_S 4 350 /* SYSTEM_CRYPTO_RSA_CLK_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */ 351 /*description: .*/ 352 #define SYSTEM_CRYPTO_RSA_CLK_EN (BIT(3)) 353 #define SYSTEM_CRYPTO_RSA_CLK_EN_M (BIT(3)) 354 #define SYSTEM_CRYPTO_RSA_CLK_EN_V 0x1 355 #define SYSTEM_CRYPTO_RSA_CLK_EN_S 3 356 /* SYSTEM_CRYPTO_SHA_CLK_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */ 357 /*description: .*/ 358 #define SYSTEM_CRYPTO_SHA_CLK_EN (BIT(2)) 359 #define SYSTEM_CRYPTO_SHA_CLK_EN_M (BIT(2)) 360 #define SYSTEM_CRYPTO_SHA_CLK_EN_V 0x1 361 #define SYSTEM_CRYPTO_SHA_CLK_EN_S 2 362 /* SYSTEM_CRYPTO_AES_CLK_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */ 363 /*description: .*/ 364 #define SYSTEM_CRYPTO_AES_CLK_EN (BIT(1)) 365 #define SYSTEM_CRYPTO_AES_CLK_EN_M (BIT(1)) 366 #define SYSTEM_CRYPTO_AES_CLK_EN_V 0x1 367 #define SYSTEM_CRYPTO_AES_CLK_EN_S 1 368 /* SYSTEM_PERI_BACKUP_CLK_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ 369 /*description: .*/ 370 #define SYSTEM_PERI_BACKUP_CLK_EN (BIT(0)) 371 #define SYSTEM_PERI_BACKUP_CLK_EN_M (BIT(0)) 372 #define SYSTEM_PERI_BACKUP_CLK_EN_V 0x1 373 #define SYSTEM_PERI_BACKUP_CLK_EN_S 0 374 375 #define SYSTEM_PERIP_RST_EN0_REG (DR_REG_SYSTEM_BASE + 0x20) 376 /* SYSTEM_SPI4_RST : R/W ;bitpos:[31] ;default: 1'h0 ; */ 377 /*description: .*/ 378 #define SYSTEM_SPI4_RST (BIT(31)) 379 #define SYSTEM_SPI4_RST_M (BIT(31)) 380 #define SYSTEM_SPI4_RST_V 0x1 381 #define SYSTEM_SPI4_RST_S 31 382 /* SYSTEM_ADC2_ARB_RST : R/W ;bitpos:[30] ;default: 1'b0 ; */ 383 /*description: .*/ 384 #define SYSTEM_ADC2_ARB_RST (BIT(30)) 385 #define SYSTEM_ADC2_ARB_RST_M (BIT(30)) 386 #define SYSTEM_ADC2_ARB_RST_V 0x1 387 #define SYSTEM_ADC2_ARB_RST_S 30 388 /* SYSTEM_SYSTIMER_RST : R/W ;bitpos:[29] ;default: 1'b0 ; */ 389 /*description: .*/ 390 #define SYSTEM_SYSTIMER_RST (BIT(29)) 391 #define SYSTEM_SYSTIMER_RST_M (BIT(29)) 392 #define SYSTEM_SYSTIMER_RST_V 0x1 393 #define SYSTEM_SYSTIMER_RST_S 29 394 /* SYSTEM_APB_SARADC_RST : R/W ;bitpos:[28] ;default: 1'b0 ; */ 395 /*description: .*/ 396 #define SYSTEM_APB_SARADC_RST (BIT(28)) 397 #define SYSTEM_APB_SARADC_RST_M (BIT(28)) 398 #define SYSTEM_APB_SARADC_RST_V 0x1 399 #define SYSTEM_APB_SARADC_RST_S 28 400 /* SYSTEM_SPI3_DMA_RST : R/W ;bitpos:[27] ;default: 1'b0 ; */ 401 /*description: .*/ 402 #define SYSTEM_SPI3_DMA_RST (BIT(27)) 403 #define SYSTEM_SPI3_DMA_RST_M (BIT(27)) 404 #define SYSTEM_SPI3_DMA_RST_V 0x1 405 #define SYSTEM_SPI3_DMA_RST_S 27 406 /* SYSTEM_PWM3_RST : R/W ;bitpos:[26] ;default: 1'b0 ; */ 407 /*description: .*/ 408 #define SYSTEM_PWM3_RST (BIT(26)) 409 #define SYSTEM_PWM3_RST_M (BIT(26)) 410 #define SYSTEM_PWM3_RST_V 0x1 411 #define SYSTEM_PWM3_RST_S 26 412 /* SYSTEM_PWM2_RST : R/W ;bitpos:[25] ;default: 1'b0 ; */ 413 /*description: .*/ 414 #define SYSTEM_PWM2_RST (BIT(25)) 415 #define SYSTEM_PWM2_RST_M (BIT(25)) 416 #define SYSTEM_PWM2_RST_V 0x1 417 #define SYSTEM_PWM2_RST_S 25 418 /* SYSTEM_UART_MEM_RST : R/W ;bitpos:[24] ;default: 1'b0 ; */ 419 /*description: .*/ 420 #define SYSTEM_UART_MEM_RST (BIT(24)) 421 #define SYSTEM_UART_MEM_RST_M (BIT(24)) 422 #define SYSTEM_UART_MEM_RST_V 0x1 423 #define SYSTEM_UART_MEM_RST_S 24 424 /* SYSTEM_USB_RST : R/W ;bitpos:[23] ;default: 1'b0 ; */ 425 /*description: .*/ 426 #define SYSTEM_USB_RST (BIT(23)) 427 #define SYSTEM_USB_RST_M (BIT(23)) 428 #define SYSTEM_USB_RST_V 0x1 429 #define SYSTEM_USB_RST_S 23 430 /* SYSTEM_SPI2_DMA_RST : R/W ;bitpos:[22] ;default: 1'b0 ; */ 431 /*description: .*/ 432 #define SYSTEM_SPI2_DMA_RST (BIT(22)) 433 #define SYSTEM_SPI2_DMA_RST_M (BIT(22)) 434 #define SYSTEM_SPI2_DMA_RST_V 0x1 435 #define SYSTEM_SPI2_DMA_RST_S 22 436 /* SYSTEM_I2S1_RST : R/W ;bitpos:[21] ;default: 1'b0 ; */ 437 /*description: .*/ 438 #define SYSTEM_I2S1_RST (BIT(21)) 439 #define SYSTEM_I2S1_RST_M (BIT(21)) 440 #define SYSTEM_I2S1_RST_V 0x1 441 #define SYSTEM_I2S1_RST_S 21 442 /* SYSTEM_PWM1_RST : R/W ;bitpos:[20] ;default: 1'b0 ; */ 443 /*description: .*/ 444 #define SYSTEM_PWM1_RST (BIT(20)) 445 #define SYSTEM_PWM1_RST_M (BIT(20)) 446 #define SYSTEM_PWM1_RST_V 0x1 447 #define SYSTEM_PWM1_RST_S 20 448 /* SYSTEM_TWAI_RST : R/W ;bitpos:[19] ;default: 1'b0 ; */ 449 /*description: .*/ 450 #define SYSTEM_TWAI_RST (BIT(19)) 451 #define SYSTEM_TWAI_RST_M (BIT(19)) 452 #define SYSTEM_TWAI_RST_V 0x1 453 #define SYSTEM_TWAI_RST_S 19 454 /* SYSTEM_I2C_EXT1_RST : R/W ;bitpos:[18] ;default: 1'b0 ; */ 455 /*description: .*/ 456 #define SYSTEM_I2C_EXT1_RST (BIT(18)) 457 #define SYSTEM_I2C_EXT1_RST_M (BIT(18)) 458 #define SYSTEM_I2C_EXT1_RST_V 0x1 459 #define SYSTEM_I2C_EXT1_RST_S 18 460 /* SYSTEM_PWM0_RST : R/W ;bitpos:[17] ;default: 1'b0 ; */ 461 /*description: .*/ 462 #define SYSTEM_PWM0_RST (BIT(17)) 463 #define SYSTEM_PWM0_RST_M (BIT(17)) 464 #define SYSTEM_PWM0_RST_V 0x1 465 #define SYSTEM_PWM0_RST_S 17 466 /* SYSTEM_SPI3_RST : R/W ;bitpos:[16] ;default: 1'b0 ; */ 467 /*description: .*/ 468 #define SYSTEM_SPI3_RST (BIT(16)) 469 #define SYSTEM_SPI3_RST_M (BIT(16)) 470 #define SYSTEM_SPI3_RST_V 0x1 471 #define SYSTEM_SPI3_RST_S 16 472 /* SYSTEM_TIMERGROUP1_RST : R/W ;bitpos:[15] ;default: 1'b0 ; */ 473 /*description: .*/ 474 #define SYSTEM_TIMERGROUP1_RST (BIT(15)) 475 #define SYSTEM_TIMERGROUP1_RST_M (BIT(15)) 476 #define SYSTEM_TIMERGROUP1_RST_V 0x1 477 #define SYSTEM_TIMERGROUP1_RST_S 15 478 /* SYSTEM_EFUSE_RST : R/W ;bitpos:[14] ;default: 1'b0 ; */ 479 /*description: .*/ 480 #define SYSTEM_EFUSE_RST (BIT(14)) 481 #define SYSTEM_EFUSE_RST_M (BIT(14)) 482 #define SYSTEM_EFUSE_RST_V 0x1 483 #define SYSTEM_EFUSE_RST_S 14 484 /* SYSTEM_TIMERGROUP_RST : R/W ;bitpos:[13] ;default: 1'b0 ; */ 485 /*description: .*/ 486 #define SYSTEM_TIMERGROUP_RST (BIT(13)) 487 #define SYSTEM_TIMERGROUP_RST_M (BIT(13)) 488 #define SYSTEM_TIMERGROUP_RST_V 0x1 489 #define SYSTEM_TIMERGROUP_RST_S 13 490 /* SYSTEM_UHCI1_RST : R/W ;bitpos:[12] ;default: 1'b0 ; */ 491 /*description: .*/ 492 #define SYSTEM_UHCI1_RST (BIT(12)) 493 #define SYSTEM_UHCI1_RST_M (BIT(12)) 494 #define SYSTEM_UHCI1_RST_V 0x1 495 #define SYSTEM_UHCI1_RST_S 12 496 /* SYSTEM_LEDC_RST : R/W ;bitpos:[11] ;default: 1'b0 ; */ 497 /*description: .*/ 498 #define SYSTEM_LEDC_RST (BIT(11)) 499 #define SYSTEM_LEDC_RST_M (BIT(11)) 500 #define SYSTEM_LEDC_RST_V 0x1 501 #define SYSTEM_LEDC_RST_S 11 502 /* SYSTEM_PCNT_RST : R/W ;bitpos:[10] ;default: 1'b0 ; */ 503 /*description: .*/ 504 #define SYSTEM_PCNT_RST (BIT(10)) 505 #define SYSTEM_PCNT_RST_M (BIT(10)) 506 #define SYSTEM_PCNT_RST_V 0x1 507 #define SYSTEM_PCNT_RST_S 10 508 /* SYSTEM_RMT_RST : R/W ;bitpos:[9] ;default: 1'b0 ; */ 509 /*description: .*/ 510 #define SYSTEM_RMT_RST (BIT(9)) 511 #define SYSTEM_RMT_RST_M (BIT(9)) 512 #define SYSTEM_RMT_RST_V 0x1 513 #define SYSTEM_RMT_RST_S 9 514 /* SYSTEM_UHCI0_RST : R/W ;bitpos:[8] ;default: 1'b0 ; */ 515 /*description: .*/ 516 #define SYSTEM_UHCI0_RST (BIT(8)) 517 #define SYSTEM_UHCI0_RST_M (BIT(8)) 518 #define SYSTEM_UHCI0_RST_V 0x1 519 #define SYSTEM_UHCI0_RST_S 8 520 /* SYSTEM_I2C_EXT0_RST : R/W ;bitpos:[7] ;default: 1'b0 ; */ 521 /*description: .*/ 522 #define SYSTEM_I2C_EXT0_RST (BIT(7)) 523 #define SYSTEM_I2C_EXT0_RST_M (BIT(7)) 524 #define SYSTEM_I2C_EXT0_RST_V 0x1 525 #define SYSTEM_I2C_EXT0_RST_S 7 526 /* SYSTEM_SPI2_RST : R/W ;bitpos:[6] ;default: 1'b0 ; */ 527 /*description: .*/ 528 #define SYSTEM_SPI2_RST (BIT(6)) 529 #define SYSTEM_SPI2_RST_M (BIT(6)) 530 #define SYSTEM_SPI2_RST_V 0x1 531 #define SYSTEM_SPI2_RST_S 6 532 /* SYSTEM_UART1_RST : R/W ;bitpos:[5] ;default: 1'b0 ; */ 533 /*description: .*/ 534 #define SYSTEM_UART1_RST (BIT(5)) 535 #define SYSTEM_UART1_RST_M (BIT(5)) 536 #define SYSTEM_UART1_RST_V 0x1 537 #define SYSTEM_UART1_RST_S 5 538 /* SYSTEM_I2S0_RST : R/W ;bitpos:[4] ;default: 1'b0 ; */ 539 /*description: .*/ 540 #define SYSTEM_I2S0_RST (BIT(4)) 541 #define SYSTEM_I2S0_RST_M (BIT(4)) 542 #define SYSTEM_I2S0_RST_V 0x1 543 #define SYSTEM_I2S0_RST_S 4 544 /* SYSTEM_WDG_RST : R/W ;bitpos:[3] ;default: 1'b0 ; */ 545 /*description: .*/ 546 #define SYSTEM_WDG_RST (BIT(3)) 547 #define SYSTEM_WDG_RST_M (BIT(3)) 548 #define SYSTEM_WDG_RST_V 0x1 549 #define SYSTEM_WDG_RST_S 3 550 /* SYSTEM_UART_RST : R/W ;bitpos:[2] ;default: 1'b0 ; */ 551 /*description: .*/ 552 #define SYSTEM_UART_RST (BIT(2)) 553 #define SYSTEM_UART_RST_M (BIT(2)) 554 #define SYSTEM_UART_RST_V 0x1 555 #define SYSTEM_UART_RST_S 2 556 /* SYSTEM_SPI01_RST : R/W ;bitpos:[1] ;default: 1'b0 ; */ 557 /*description: .*/ 558 #define SYSTEM_SPI01_RST (BIT(1)) 559 #define SYSTEM_SPI01_RST_M (BIT(1)) 560 #define SYSTEM_SPI01_RST_V 0x1 561 #define SYSTEM_SPI01_RST_S 1 562 /* SYSTEM_TIMERS_RST : R/W ;bitpos:[0] ;default: 1'b0 ; */ 563 /*description: .*/ 564 #define SYSTEM_TIMERS_RST (BIT(0)) 565 #define SYSTEM_TIMERS_RST_M (BIT(0)) 566 #define SYSTEM_TIMERS_RST_V 0x1 567 #define SYSTEM_TIMERS_RST_S 0 568 569 #define SYSTEM_PERIP_RST_EN1_REG (DR_REG_SYSTEM_BASE + 0x24) 570 /* SYSTEM_USB_DEVICE_RST : R/W ;bitpos:[10] ;default: 1'b0 ; */ 571 /*description: .*/ 572 #define SYSTEM_USB_DEVICE_RST (BIT(10)) 573 #define SYSTEM_USB_DEVICE_RST_M (BIT(10)) 574 #define SYSTEM_USB_DEVICE_RST_V 0x1 575 #define SYSTEM_USB_DEVICE_RST_S 10 576 /* SYSTEM_UART2_RST : R/W ;bitpos:[9] ;default: 1'b0 ; */ 577 /*description: .*/ 578 #define SYSTEM_UART2_RST (BIT(9)) 579 #define SYSTEM_UART2_RST_M (BIT(9)) 580 #define SYSTEM_UART2_RST_V 0x1 581 #define SYSTEM_UART2_RST_S 9 582 /* SYSTEM_LCD_CAM_RST : R/W ;bitpos:[8] ;default: 1'b1 ; */ 583 /*description: .*/ 584 #define SYSTEM_LCD_CAM_RST (BIT(8)) 585 #define SYSTEM_LCD_CAM_RST_M (BIT(8)) 586 #define SYSTEM_LCD_CAM_RST_V 0x1 587 #define SYSTEM_LCD_CAM_RST_S 8 588 /* SYSTEM_SDIO_HOST_RST : R/W ;bitpos:[7] ;default: 1'b1 ; */ 589 /*description: .*/ 590 #define SYSTEM_SDIO_HOST_RST (BIT(7)) 591 #define SYSTEM_SDIO_HOST_RST_M (BIT(7)) 592 #define SYSTEM_SDIO_HOST_RST_V 0x1 593 #define SYSTEM_SDIO_HOST_RST_S 7 594 /* SYSTEM_DMA_RST : R/W ;bitpos:[6] ;default: 1'b1 ; */ 595 /*description: .*/ 596 #define SYSTEM_DMA_RST (BIT(6)) 597 #define SYSTEM_DMA_RST_M (BIT(6)) 598 #define SYSTEM_DMA_RST_V 0x1 599 #define SYSTEM_DMA_RST_S 6 600 /* SYSTEM_CRYPTO_HMAC_RST : R/W ;bitpos:[5] ;default: 1'b1 ; */ 601 /*description: .*/ 602 #define SYSTEM_CRYPTO_HMAC_RST (BIT(5)) 603 #define SYSTEM_CRYPTO_HMAC_RST_M (BIT(5)) 604 #define SYSTEM_CRYPTO_HMAC_RST_V 0x1 605 #define SYSTEM_CRYPTO_HMAC_RST_S 5 606 /* SYSTEM_CRYPTO_DS_RST : R/W ;bitpos:[4] ;default: 1'b1 ; */ 607 /*description: .*/ 608 #define SYSTEM_CRYPTO_DS_RST (BIT(4)) 609 #define SYSTEM_CRYPTO_DS_RST_M (BIT(4)) 610 #define SYSTEM_CRYPTO_DS_RST_V 0x1 611 #define SYSTEM_CRYPTO_DS_RST_S 4 612 /* SYSTEM_CRYPTO_RSA_RST : R/W ;bitpos:[3] ;default: 1'b1 ; */ 613 /*description: .*/ 614 #define SYSTEM_CRYPTO_RSA_RST (BIT(3)) 615 #define SYSTEM_CRYPTO_RSA_RST_M (BIT(3)) 616 #define SYSTEM_CRYPTO_RSA_RST_V 0x1 617 #define SYSTEM_CRYPTO_RSA_RST_S 3 618 /* SYSTEM_CRYPTO_SHA_RST : R/W ;bitpos:[2] ;default: 1'b1 ; */ 619 /*description: .*/ 620 #define SYSTEM_CRYPTO_SHA_RST (BIT(2)) 621 #define SYSTEM_CRYPTO_SHA_RST_M (BIT(2)) 622 #define SYSTEM_CRYPTO_SHA_RST_V 0x1 623 #define SYSTEM_CRYPTO_SHA_RST_S 2 624 /* SYSTEM_CRYPTO_AES_RST : R/W ;bitpos:[1] ;default: 1'b1 ; */ 625 /*description: .*/ 626 #define SYSTEM_CRYPTO_AES_RST (BIT(1)) 627 #define SYSTEM_CRYPTO_AES_RST_M (BIT(1)) 628 #define SYSTEM_CRYPTO_AES_RST_V 0x1 629 #define SYSTEM_CRYPTO_AES_RST_S 1 630 /* SYSTEM_PERI_BACKUP_RST : R/W ;bitpos:[0] ;default: 1'b0 ; */ 631 /*description: .*/ 632 #define SYSTEM_PERI_BACKUP_RST (BIT(0)) 633 #define SYSTEM_PERI_BACKUP_RST_M (BIT(0)) 634 #define SYSTEM_PERI_BACKUP_RST_V 0x1 635 #define SYSTEM_PERI_BACKUP_RST_S 0 636 637 #define SYSTEM_BT_LPCK_DIV_INT_REG (DR_REG_SYSTEM_BASE + 0x28) 638 /* SYSTEM_BT_LPCK_DIV_NUM : R/W ;bitpos:[11:0] ;default: 12'd255 ; */ 639 /*description: .*/ 640 #define SYSTEM_BT_LPCK_DIV_NUM 0x00000FFF 641 #define SYSTEM_BT_LPCK_DIV_NUM_M ((SYSTEM_BT_LPCK_DIV_NUM_V)<<(SYSTEM_BT_LPCK_DIV_NUM_S)) 642 #define SYSTEM_BT_LPCK_DIV_NUM_V 0xFFF 643 #define SYSTEM_BT_LPCK_DIV_NUM_S 0 644 645 #define SYSTEM_BT_LPCK_DIV_FRAC_REG (DR_REG_SYSTEM_BASE + 0x2C) 646 /* SYSTEM_LPCLK_RTC_EN : R/W ;bitpos:[28] ;default: 1'b0 ; */ 647 /*description: .*/ 648 #define SYSTEM_LPCLK_RTC_EN (BIT(28)) 649 #define SYSTEM_LPCLK_RTC_EN_M (BIT(28)) 650 #define SYSTEM_LPCLK_RTC_EN_V 0x1 651 #define SYSTEM_LPCLK_RTC_EN_S 28 652 /* SYSTEM_LPCLK_SEL_XTAL32K : R/W ;bitpos:[27] ;default: 1'b0 ; */ 653 /*description: .*/ 654 #define SYSTEM_LPCLK_SEL_XTAL32K (BIT(27)) 655 #define SYSTEM_LPCLK_SEL_XTAL32K_M (BIT(27)) 656 #define SYSTEM_LPCLK_SEL_XTAL32K_V 0x1 657 #define SYSTEM_LPCLK_SEL_XTAL32K_S 27 658 /* SYSTEM_LPCLK_SEL_XTAL : R/W ;bitpos:[26] ;default: 1'b0 ; */ 659 /*description: .*/ 660 #define SYSTEM_LPCLK_SEL_XTAL (BIT(26)) 661 #define SYSTEM_LPCLK_SEL_XTAL_M (BIT(26)) 662 #define SYSTEM_LPCLK_SEL_XTAL_V 0x1 663 #define SYSTEM_LPCLK_SEL_XTAL_S 26 664 /* SYSTEM_LPCLK_SEL_8M : R/W ;bitpos:[25] ;default: 1'b1 ; */ 665 /*description: .*/ 666 #define SYSTEM_LPCLK_SEL_8M (BIT(25)) 667 #define SYSTEM_LPCLK_SEL_8M_M (BIT(25)) 668 #define SYSTEM_LPCLK_SEL_8M_V 0x1 669 #define SYSTEM_LPCLK_SEL_8M_S 25 670 /* SYSTEM_LPCLK_SEL_RTC_SLOW : R/W ;bitpos:[24] ;default: 1'b0 ; */ 671 /*description: .*/ 672 #define SYSTEM_LPCLK_SEL_RTC_SLOW (BIT(24)) 673 #define SYSTEM_LPCLK_SEL_RTC_SLOW_M (BIT(24)) 674 #define SYSTEM_LPCLK_SEL_RTC_SLOW_V 0x1 675 #define SYSTEM_LPCLK_SEL_RTC_SLOW_S 24 676 /* SYSTEM_BT_LPCK_DIV_A : R/W ;bitpos:[23:12] ;default: 12'd1 ; */ 677 /*description: .*/ 678 #define SYSTEM_BT_LPCK_DIV_A 0x00000FFF 679 #define SYSTEM_BT_LPCK_DIV_A_M ((SYSTEM_BT_LPCK_DIV_A_V)<<(SYSTEM_BT_LPCK_DIV_A_S)) 680 #define SYSTEM_BT_LPCK_DIV_A_V 0xFFF 681 #define SYSTEM_BT_LPCK_DIV_A_S 12 682 /* SYSTEM_BT_LPCK_DIV_B : R/W ;bitpos:[11:0] ;default: 12'd1 ; */ 683 /*description: .*/ 684 #define SYSTEM_BT_LPCK_DIV_B 0x00000FFF 685 #define SYSTEM_BT_LPCK_DIV_B_M ((SYSTEM_BT_LPCK_DIV_B_V)<<(SYSTEM_BT_LPCK_DIV_B_S)) 686 #define SYSTEM_BT_LPCK_DIV_B_V 0xFFF 687 #define SYSTEM_BT_LPCK_DIV_B_S 0 688 689 #define SYSTEM_CPU_INTR_FROM_CPU_0_REG (DR_REG_SYSTEM_BASE + 0x30) 690 /* SYSTEM_CPU_INTR_FROM_CPU_0 : R/W ;bitpos:[0] ;default: 1'b0 ; */ 691 /*description: .*/ 692 #define SYSTEM_CPU_INTR_FROM_CPU_0 (BIT(0)) 693 #define SYSTEM_CPU_INTR_FROM_CPU_0_M (BIT(0)) 694 #define SYSTEM_CPU_INTR_FROM_CPU_0_V 0x1 695 #define SYSTEM_CPU_INTR_FROM_CPU_0_S 0 696 697 #define SYSTEM_CPU_INTR_FROM_CPU_1_REG (DR_REG_SYSTEM_BASE + 0x34) 698 /* SYSTEM_CPU_INTR_FROM_CPU_1 : R/W ;bitpos:[0] ;default: 1'b0 ; */ 699 /*description: .*/ 700 #define SYSTEM_CPU_INTR_FROM_CPU_1 (BIT(0)) 701 #define SYSTEM_CPU_INTR_FROM_CPU_1_M (BIT(0)) 702 #define SYSTEM_CPU_INTR_FROM_CPU_1_V 0x1 703 #define SYSTEM_CPU_INTR_FROM_CPU_1_S 0 704 705 #define SYSTEM_CPU_INTR_FROM_CPU_2_REG (DR_REG_SYSTEM_BASE + 0x38) 706 /* SYSTEM_CPU_INTR_FROM_CPU_2 : R/W ;bitpos:[0] ;default: 1'b0 ; */ 707 /*description: .*/ 708 #define SYSTEM_CPU_INTR_FROM_CPU_2 (BIT(0)) 709 #define SYSTEM_CPU_INTR_FROM_CPU_2_M (BIT(0)) 710 #define SYSTEM_CPU_INTR_FROM_CPU_2_V 0x1 711 #define SYSTEM_CPU_INTR_FROM_CPU_2_S 0 712 713 #define SYSTEM_CPU_INTR_FROM_CPU_3_REG (DR_REG_SYSTEM_BASE + 0x3C) 714 /* SYSTEM_CPU_INTR_FROM_CPU_3 : R/W ;bitpos:[0] ;default: 1'b0 ; */ 715 /*description: .*/ 716 #define SYSTEM_CPU_INTR_FROM_CPU_3 (BIT(0)) 717 #define SYSTEM_CPU_INTR_FROM_CPU_3_M (BIT(0)) 718 #define SYSTEM_CPU_INTR_FROM_CPU_3_V 0x1 719 #define SYSTEM_CPU_INTR_FROM_CPU_3_S 0 720 721 #define SYSTEM_RSA_PD_CTRL_REG (DR_REG_SYSTEM_BASE + 0x40) 722 /* SYSTEM_RSA_MEM_FORCE_PD : R/W ;bitpos:[2] ;default: 1'b0 ; */ 723 /*description: .*/ 724 #define SYSTEM_RSA_MEM_FORCE_PD (BIT(2)) 725 #define SYSTEM_RSA_MEM_FORCE_PD_M (BIT(2)) 726 #define SYSTEM_RSA_MEM_FORCE_PD_V 0x1 727 #define SYSTEM_RSA_MEM_FORCE_PD_S 2 728 /* SYSTEM_RSA_MEM_FORCE_PU : R/W ;bitpos:[1] ;default: 1'b0 ; */ 729 /*description: .*/ 730 #define SYSTEM_RSA_MEM_FORCE_PU (BIT(1)) 731 #define SYSTEM_RSA_MEM_FORCE_PU_M (BIT(1)) 732 #define SYSTEM_RSA_MEM_FORCE_PU_V 0x1 733 #define SYSTEM_RSA_MEM_FORCE_PU_S 1 734 /* SYSTEM_RSA_MEM_PD : R/W ;bitpos:[0] ;default: 1'b1 ; */ 735 /*description: .*/ 736 #define SYSTEM_RSA_MEM_PD (BIT(0)) 737 #define SYSTEM_RSA_MEM_PD_M (BIT(0)) 738 #define SYSTEM_RSA_MEM_PD_V 0x1 739 #define SYSTEM_RSA_MEM_PD_S 0 740 741 #define SYSTEM_EDMA_CTRL_REG (DR_REG_SYSTEM_BASE + 0x44) 742 /* SYSTEM_EDMA_RESET : R/W ;bitpos:[1] ;default: 1'b0 ; */ 743 /*description: .*/ 744 #define SYSTEM_EDMA_RESET (BIT(1)) 745 #define SYSTEM_EDMA_RESET_M (BIT(1)) 746 #define SYSTEM_EDMA_RESET_V 0x1 747 #define SYSTEM_EDMA_RESET_S 1 748 /* SYSTEM_EDMA_CLK_ON : R/W ;bitpos:[0] ;default: 1'b1 ; */ 749 /*description: .*/ 750 #define SYSTEM_EDMA_CLK_ON (BIT(0)) 751 #define SYSTEM_EDMA_CLK_ON_M (BIT(0)) 752 #define SYSTEM_EDMA_CLK_ON_V 0x1 753 #define SYSTEM_EDMA_CLK_ON_S 0 754 755 #define SYSTEM_CACHE_CONTROL_REG (DR_REG_SYSTEM_BASE + 0x48) 756 /* SYSTEM_DCACHE_RESET : R/W ;bitpos:[3] ;default: 1'b0 ; */ 757 /*description: .*/ 758 #define SYSTEM_DCACHE_RESET (BIT(3)) 759 #define SYSTEM_DCACHE_RESET_M (BIT(3)) 760 #define SYSTEM_DCACHE_RESET_V 0x1 761 #define SYSTEM_DCACHE_RESET_S 3 762 /* SYSTEM_DCACHE_CLK_ON : R/W ;bitpos:[2] ;default: 1'b1 ; */ 763 /*description: .*/ 764 #define SYSTEM_DCACHE_CLK_ON (BIT(2)) 765 #define SYSTEM_DCACHE_CLK_ON_M (BIT(2)) 766 #define SYSTEM_DCACHE_CLK_ON_V 0x1 767 #define SYSTEM_DCACHE_CLK_ON_S 2 768 /* SYSTEM_ICACHE_RESET : R/W ;bitpos:[1] ;default: 1'b0 ; */ 769 /*description: .*/ 770 #define SYSTEM_ICACHE_RESET (BIT(1)) 771 #define SYSTEM_ICACHE_RESET_M (BIT(1)) 772 #define SYSTEM_ICACHE_RESET_V 0x1 773 #define SYSTEM_ICACHE_RESET_S 1 774 /* SYSTEM_ICACHE_CLK_ON : R/W ;bitpos:[0] ;default: 1'b1 ; */ 775 /*description: .*/ 776 #define SYSTEM_ICACHE_CLK_ON (BIT(0)) 777 #define SYSTEM_ICACHE_CLK_ON_M (BIT(0)) 778 #define SYSTEM_ICACHE_CLK_ON_V 0x1 779 #define SYSTEM_ICACHE_CLK_ON_S 0 780 781 #define SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG (DR_REG_SYSTEM_BASE + 0x4C) 782 /* SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT : R/W ;bitpos:[3] ;default: 1'b0 ; */ 783 /*description: .*/ 784 #define SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT (BIT(3)) 785 #define SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_M (BIT(3)) 786 #define SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_V 0x1 787 #define SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_S 3 788 /* SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT : R/W ;bitpos:[2] ;default: 1'b0 ; */ 789 /*description: .*/ 790 #define SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT (BIT(2)) 791 #define SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_M (BIT(2)) 792 #define SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_V 0x1 793 #define SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_S 2 794 /* SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT : R/W ;bitpos:[1] ;default: 1'b0 ; */ 795 /*description: .*/ 796 #define SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT (BIT(1)) 797 #define SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_M (BIT(1)) 798 #define SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_V 0x1 799 #define SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_S 1 800 /* SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT : R/W ;bitpos:[0] ;default: 1'b0 ; */ 801 /*description: .*/ 802 #define SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT (BIT(0)) 803 #define SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_M (BIT(0)) 804 #define SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_V 0x1 805 #define SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_S 0 806 807 #define SYSTEM_RTC_FASTMEM_CONFIG_REG (DR_REG_SYSTEM_BASE + 0x50) 808 /* SYSTEM_RTC_MEM_CRC_FINISH : RO ;bitpos:[31] ;default: 1'b0 ; */ 809 /*description: .*/ 810 #define SYSTEM_RTC_MEM_CRC_FINISH (BIT(31)) 811 #define SYSTEM_RTC_MEM_CRC_FINISH_M (BIT(31)) 812 #define SYSTEM_RTC_MEM_CRC_FINISH_V 0x1 813 #define SYSTEM_RTC_MEM_CRC_FINISH_S 31 814 /* SYSTEM_RTC_MEM_CRC_LEN : R/W ;bitpos:[30:20] ;default: 11'h7ff ; */ 815 /*description: .*/ 816 #define SYSTEM_RTC_MEM_CRC_LEN 0x000007FF 817 #define SYSTEM_RTC_MEM_CRC_LEN_M ((SYSTEM_RTC_MEM_CRC_LEN_V)<<(SYSTEM_RTC_MEM_CRC_LEN_S)) 818 #define SYSTEM_RTC_MEM_CRC_LEN_V 0x7FF 819 #define SYSTEM_RTC_MEM_CRC_LEN_S 20 820 /* SYSTEM_RTC_MEM_CRC_ADDR : R/W ;bitpos:[19:9] ;default: 11'h0 ; */ 821 /*description: .*/ 822 #define SYSTEM_RTC_MEM_CRC_ADDR 0x000007FF 823 #define SYSTEM_RTC_MEM_CRC_ADDR_M ((SYSTEM_RTC_MEM_CRC_ADDR_V)<<(SYSTEM_RTC_MEM_CRC_ADDR_S)) 824 #define SYSTEM_RTC_MEM_CRC_ADDR_V 0x7FF 825 #define SYSTEM_RTC_MEM_CRC_ADDR_S 9 826 /* SYSTEM_RTC_MEM_CRC_START : R/W ;bitpos:[8] ;default: 1'b0 ; */ 827 /*description: .*/ 828 #define SYSTEM_RTC_MEM_CRC_START (BIT(8)) 829 #define SYSTEM_RTC_MEM_CRC_START_M (BIT(8)) 830 #define SYSTEM_RTC_MEM_CRC_START_V 0x1 831 #define SYSTEM_RTC_MEM_CRC_START_S 8 832 833 #define SYSTEM_RTC_FASTMEM_CRC_REG (DR_REG_SYSTEM_BASE + 0x54) 834 /* SYSTEM_RTC_MEM_CRC_RES : RO ;bitpos:[31:0] ;default: 32'b0 ; */ 835 /*description: .*/ 836 #define SYSTEM_RTC_MEM_CRC_RES 0xFFFFFFFF 837 #define SYSTEM_RTC_MEM_CRC_RES_M ((SYSTEM_RTC_MEM_CRC_RES_V)<<(SYSTEM_RTC_MEM_CRC_RES_S)) 838 #define SYSTEM_RTC_MEM_CRC_RES_V 0xFFFFFFFF 839 #define SYSTEM_RTC_MEM_CRC_RES_S 0 840 841 #define SYSTEM_REDUNDANT_ECO_CTRL_REG (DR_REG_SYSTEM_BASE + 0x58) 842 /* SYSTEM_REDUNDANT_ECO_RESULT : RO ;bitpos:[1] ;default: 1'b0 ; */ 843 /*description: .*/ 844 #define SYSTEM_REDUNDANT_ECO_RESULT (BIT(1)) 845 #define SYSTEM_REDUNDANT_ECO_RESULT_M (BIT(1)) 846 #define SYSTEM_REDUNDANT_ECO_RESULT_V 0x1 847 #define SYSTEM_REDUNDANT_ECO_RESULT_S 1 848 /* SYSTEM_REDUNDANT_ECO_DRIVE : R/W ;bitpos:[0] ;default: 1'b0 ; */ 849 /*description: .*/ 850 #define SYSTEM_REDUNDANT_ECO_DRIVE (BIT(0)) 851 #define SYSTEM_REDUNDANT_ECO_DRIVE_M (BIT(0)) 852 #define SYSTEM_REDUNDANT_ECO_DRIVE_V 0x1 853 #define SYSTEM_REDUNDANT_ECO_DRIVE_S 0 854 855 #define SYSTEM_CLOCK_GATE_REG (DR_REG_SYSTEM_BASE + 0x5C) 856 /* SYSTEM_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ 857 /*description: .*/ 858 #define SYSTEM_CLK_EN (BIT(0)) 859 #define SYSTEM_CLK_EN_M (BIT(0)) 860 #define SYSTEM_CLK_EN_V 0x1 861 #define SYSTEM_CLK_EN_S 0 862 863 #define SYSTEM_SYSCLK_CONF_REG (DR_REG_SYSTEM_BASE + 0x60) 864 /* SYSTEM_CLK_DIV_EN : RO ;bitpos:[19] ;default: 1'd0 ; */ 865 /*description: .*/ 866 #define SYSTEM_CLK_DIV_EN (BIT(19)) 867 #define SYSTEM_CLK_DIV_EN_M (BIT(19)) 868 #define SYSTEM_CLK_DIV_EN_V 0x1 869 #define SYSTEM_CLK_DIV_EN_S 19 870 /* SYSTEM_CLK_XTAL_FREQ : RO ;bitpos:[18:12] ;default: 7'd0 ; */ 871 /*description: .*/ 872 #define SYSTEM_CLK_XTAL_FREQ 0x0000007F 873 #define SYSTEM_CLK_XTAL_FREQ_M ((SYSTEM_CLK_XTAL_FREQ_V)<<(SYSTEM_CLK_XTAL_FREQ_S)) 874 #define SYSTEM_CLK_XTAL_FREQ_V 0x7F 875 #define SYSTEM_CLK_XTAL_FREQ_S 12 876 /* SYSTEM_SOC_CLK_SEL : R/W ;bitpos:[11:10] ;default: 2'd0 ; */ 877 /*description: .*/ 878 #define SYSTEM_SOC_CLK_SEL 0x00000003 879 #define SYSTEM_SOC_CLK_SEL_M ((SYSTEM_SOC_CLK_SEL_V)<<(SYSTEM_SOC_CLK_SEL_S)) 880 #define SYSTEM_SOC_CLK_SEL_V 0x3 881 #define SYSTEM_SOC_CLK_SEL_S 10 882 /* SYSTEM_PRE_DIV_CNT : R/W ;bitpos:[9:0] ;default: 10'h1 ; */ 883 /*description: .*/ 884 #define SYSTEM_PRE_DIV_CNT 0x000003FF 885 #define SYSTEM_PRE_DIV_CNT_M ((SYSTEM_PRE_DIV_CNT_V)<<(SYSTEM_PRE_DIV_CNT_S)) 886 #define SYSTEM_PRE_DIV_CNT_V 0x3FF 887 #define SYSTEM_PRE_DIV_CNT_S 0 888 889 #define SYSTEM_MEM_PVT_REG (DR_REG_SYSTEM_BASE + 0x64) 890 /* SYSTEM_MEM_VT_SEL : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ 891 /*description: .*/ 892 #define SYSTEM_MEM_VT_SEL 0x00000003 893 #define SYSTEM_MEM_VT_SEL_M ((SYSTEM_MEM_VT_SEL_V)<<(SYSTEM_MEM_VT_SEL_S)) 894 #define SYSTEM_MEM_VT_SEL_V 0x3 895 #define SYSTEM_MEM_VT_SEL_S 22 896 /* SYSTEM_MEM_TIMING_ERR_CNT : RO ;bitpos:[21:6] ;default: 16'h0 ; */ 897 /*description: .*/ 898 #define SYSTEM_MEM_TIMING_ERR_CNT 0x0000FFFF 899 #define SYSTEM_MEM_TIMING_ERR_CNT_M ((SYSTEM_MEM_TIMING_ERR_CNT_V)<<(SYSTEM_MEM_TIMING_ERR_CNT_S)) 900 #define SYSTEM_MEM_TIMING_ERR_CNT_V 0xFFFF 901 #define SYSTEM_MEM_TIMING_ERR_CNT_S 6 902 /* SYSTEM_MEM_PVT_MONITOR_EN : R/W ;bitpos:[5] ;default: 1'b0 ; */ 903 /*description: .*/ 904 #define SYSTEM_MEM_PVT_MONITOR_EN (BIT(5)) 905 #define SYSTEM_MEM_PVT_MONITOR_EN_M (BIT(5)) 906 #define SYSTEM_MEM_PVT_MONITOR_EN_V 0x1 907 #define SYSTEM_MEM_PVT_MONITOR_EN_S 5 908 /* SYSTEM_MEM_ERR_CNT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ 909 /*description: .*/ 910 #define SYSTEM_MEM_ERR_CNT_CLR (BIT(4)) 911 #define SYSTEM_MEM_ERR_CNT_CLR_M (BIT(4)) 912 #define SYSTEM_MEM_ERR_CNT_CLR_V 0x1 913 #define SYSTEM_MEM_ERR_CNT_CLR_S 4 914 /* SYSTEM_MEM_PATH_LEN : R/W ;bitpos:[3:0] ;default: 4'h3 ; */ 915 /*description: .*/ 916 #define SYSTEM_MEM_PATH_LEN 0x0000000F 917 #define SYSTEM_MEM_PATH_LEN_M ((SYSTEM_MEM_PATH_LEN_V)<<(SYSTEM_MEM_PATH_LEN_S)) 918 #define SYSTEM_MEM_PATH_LEN_V 0xF 919 #define SYSTEM_MEM_PATH_LEN_S 0 920 921 #define SYSTEM_COMB_PVT_LVT_CONF_REG (DR_REG_SYSTEM_BASE + 0x68) 922 /* SYSTEM_COMB_PVT_MONITOR_EN_LVT : R/W ;bitpos:[6] ;default: 1'b0 ; */ 923 /*description: .*/ 924 #define SYSTEM_COMB_PVT_MONITOR_EN_LVT (BIT(6)) 925 #define SYSTEM_COMB_PVT_MONITOR_EN_LVT_M (BIT(6)) 926 #define SYSTEM_COMB_PVT_MONITOR_EN_LVT_V 0x1 927 #define SYSTEM_COMB_PVT_MONITOR_EN_LVT_S 6 928 /* SYSTEM_COMB_ERR_CNT_CLR_LVT : WO ;bitpos:[5] ;default: 1'b0 ; */ 929 /*description: .*/ 930 #define SYSTEM_COMB_ERR_CNT_CLR_LVT (BIT(5)) 931 #define SYSTEM_COMB_ERR_CNT_CLR_LVT_M (BIT(5)) 932 #define SYSTEM_COMB_ERR_CNT_CLR_LVT_V 0x1 933 #define SYSTEM_COMB_ERR_CNT_CLR_LVT_S 5 934 /* SYSTEM_COMB_PATH_LEN_LVT : R/W ;bitpos:[4:0] ;default: 5'h3 ; */ 935 /*description: .*/ 936 #define SYSTEM_COMB_PATH_LEN_LVT 0x0000001F 937 #define SYSTEM_COMB_PATH_LEN_LVT_M ((SYSTEM_COMB_PATH_LEN_LVT_V)<<(SYSTEM_COMB_PATH_LEN_LVT_S)) 938 #define SYSTEM_COMB_PATH_LEN_LVT_V 0x1F 939 #define SYSTEM_COMB_PATH_LEN_LVT_S 0 940 941 #define SYSTEM_COMB_PVT_NVT_CONF_REG (DR_REG_SYSTEM_BASE + 0x6C) 942 /* SYSTEM_COMB_PVT_MONITOR_EN_NVT : R/W ;bitpos:[6] ;default: 1'b0 ; */ 943 /*description: .*/ 944 #define SYSTEM_COMB_PVT_MONITOR_EN_NVT (BIT(6)) 945 #define SYSTEM_COMB_PVT_MONITOR_EN_NVT_M (BIT(6)) 946 #define SYSTEM_COMB_PVT_MONITOR_EN_NVT_V 0x1 947 #define SYSTEM_COMB_PVT_MONITOR_EN_NVT_S 6 948 /* SYSTEM_COMB_ERR_CNT_CLR_NVT : WO ;bitpos:[5] ;default: 1'b0 ; */ 949 /*description: .*/ 950 #define SYSTEM_COMB_ERR_CNT_CLR_NVT (BIT(5)) 951 #define SYSTEM_COMB_ERR_CNT_CLR_NVT_M (BIT(5)) 952 #define SYSTEM_COMB_ERR_CNT_CLR_NVT_V 0x1 953 #define SYSTEM_COMB_ERR_CNT_CLR_NVT_S 5 954 /* SYSTEM_COMB_PATH_LEN_NVT : R/W ;bitpos:[4:0] ;default: 5'h3 ; */ 955 /*description: .*/ 956 #define SYSTEM_COMB_PATH_LEN_NVT 0x0000001F 957 #define SYSTEM_COMB_PATH_LEN_NVT_M ((SYSTEM_COMB_PATH_LEN_NVT_V)<<(SYSTEM_COMB_PATH_LEN_NVT_S)) 958 #define SYSTEM_COMB_PATH_LEN_NVT_V 0x1F 959 #define SYSTEM_COMB_PATH_LEN_NVT_S 0 960 961 #define SYSTEM_COMB_PVT_HVT_CONF_REG (DR_REG_SYSTEM_BASE + 0x70) 962 /* SYSTEM_COMB_PVT_MONITOR_EN_HVT : R/W ;bitpos:[6] ;default: 1'b0 ; */ 963 /*description: .*/ 964 #define SYSTEM_COMB_PVT_MONITOR_EN_HVT (BIT(6)) 965 #define SYSTEM_COMB_PVT_MONITOR_EN_HVT_M (BIT(6)) 966 #define SYSTEM_COMB_PVT_MONITOR_EN_HVT_V 0x1 967 #define SYSTEM_COMB_PVT_MONITOR_EN_HVT_S 6 968 /* SYSTEM_COMB_ERR_CNT_CLR_HVT : WO ;bitpos:[5] ;default: 1'b0 ; */ 969 /*description: .*/ 970 #define SYSTEM_COMB_ERR_CNT_CLR_HVT (BIT(5)) 971 #define SYSTEM_COMB_ERR_CNT_CLR_HVT_M (BIT(5)) 972 #define SYSTEM_COMB_ERR_CNT_CLR_HVT_V 0x1 973 #define SYSTEM_COMB_ERR_CNT_CLR_HVT_S 5 974 /* SYSTEM_COMB_PATH_LEN_HVT : R/W ;bitpos:[4:0] ;default: 5'h3 ; */ 975 /*description: .*/ 976 #define SYSTEM_COMB_PATH_LEN_HVT 0x0000001F 977 #define SYSTEM_COMB_PATH_LEN_HVT_M ((SYSTEM_COMB_PATH_LEN_HVT_V)<<(SYSTEM_COMB_PATH_LEN_HVT_S)) 978 #define SYSTEM_COMB_PATH_LEN_HVT_V 0x1F 979 #define SYSTEM_COMB_PATH_LEN_HVT_S 0 980 981 #define SYSTEM_COMB_PVT_ERR_LVT_SITE0_REG (DR_REG_SYSTEM_BASE + 0x74) 982 /* SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ 983 /*description: .*/ 984 #define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0 0x0000FFFF 985 #define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0_M ((SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0_S)) 986 #define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0_V 0xFFFF 987 #define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0_S 0 988 989 #define SYSTEM_COMB_PVT_ERR_NVT_SITE0_REG (DR_REG_SYSTEM_BASE + 0x78) 990 /* SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ 991 /*description: .*/ 992 #define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0 0x0000FFFF 993 #define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0_M ((SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0_S)) 994 #define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0_V 0xFFFF 995 #define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0_S 0 996 997 #define SYSTEM_COMB_PVT_ERR_HVT_SITE0_REG (DR_REG_SYSTEM_BASE + 0x7C) 998 /* SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ 999 /*description: .*/ 1000 #define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0 0x0000FFFF 1001 #define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0_M ((SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0_S)) 1002 #define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0_V 0xFFFF 1003 #define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0_S 0 1004 1005 #define SYSTEM_COMB_PVT_ERR_LVT_SITE1_REG (DR_REG_SYSTEM_BASE + 0x80) 1006 /* SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ 1007 /*description: .*/ 1008 #define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1 0x0000FFFF 1009 #define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1_M ((SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1_S)) 1010 #define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1_V 0xFFFF 1011 #define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1_S 0 1012 1013 #define SYSTEM_COMB_PVT_ERR_NVT_SITE1_REG (DR_REG_SYSTEM_BASE + 0x84) 1014 /* SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ 1015 /*description: .*/ 1016 #define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1 0x0000FFFF 1017 #define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1_M ((SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1_S)) 1018 #define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1_V 0xFFFF 1019 #define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1_S 0 1020 1021 #define SYSTEM_COMB_PVT_ERR_HVT_SITE1_REG (DR_REG_SYSTEM_BASE + 0x88) 1022 /* SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ 1023 /*description: .*/ 1024 #define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1 0x0000FFFF 1025 #define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1_M ((SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1_S)) 1026 #define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1_V 0xFFFF 1027 #define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1_S 0 1028 1029 #define SYSTEM_COMB_PVT_ERR_LVT_SITE2_REG (DR_REG_SYSTEM_BASE + 0x8C) 1030 /* SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ 1031 /*description: .*/ 1032 #define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2 0x0000FFFF 1033 #define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2_M ((SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2_S)) 1034 #define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2_V 0xFFFF 1035 #define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2_S 0 1036 1037 #define SYSTEM_COMB_PVT_ERR_NVT_SITE2_REG (DR_REG_SYSTEM_BASE + 0x90) 1038 /* SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ 1039 /*description: .*/ 1040 #define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2 0x0000FFFF 1041 #define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2_M ((SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2_S)) 1042 #define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2_V 0xFFFF 1043 #define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2_S 0 1044 1045 #define SYSTEM_COMB_PVT_ERR_HVT_SITE2_REG (DR_REG_SYSTEM_BASE + 0x94) 1046 /* SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ 1047 /*description: .*/ 1048 #define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2 0x0000FFFF 1049 #define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2_M ((SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2_S)) 1050 #define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2_V 0xFFFF 1051 #define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2_S 0 1052 1053 #define SYSTEM_COMB_PVT_ERR_LVT_SITE3_REG (DR_REG_SYSTEM_BASE + 0x98) 1054 /* SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ 1055 /*description: .*/ 1056 #define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3 0x0000FFFF 1057 #define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3_M ((SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3_S)) 1058 #define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3_V 0xFFFF 1059 #define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3_S 0 1060 1061 #define SYSTEM_COMB_PVT_ERR_NVT_SITE3_REG (DR_REG_SYSTEM_BASE + 0x9C) 1062 /* SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ 1063 /*description: .*/ 1064 #define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3 0x0000FFFF 1065 #define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3_M ((SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3_S)) 1066 #define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3_V 0xFFFF 1067 #define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3_S 0 1068 1069 #define SYSTEM_COMB_PVT_ERR_HVT_SITE3_REG (DR_REG_SYSTEM_BASE + 0xA0) 1070 /* SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ 1071 /*description: .*/ 1072 #define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3 0x0000FFFF 1073 #define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3_M ((SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3_S)) 1074 #define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3_V 0xFFFF 1075 #define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3_S 0 1076 1077 #define SYSTEM_DATE_REG (DR_REG_SYSTEM_BASE + 0xFFC) 1078 /* SYSTEM_DATE : R/W ;bitpos:[27:0] ;default: 28'h2101220 ; */ 1079 /*description: .*/ 1080 #define SYSTEM_DATE 0x0FFFFFFF 1081 #define SYSTEM_DATE_M ((SYSTEM_DATE_V)<<(SYSTEM_DATE_S)) 1082 #define SYSTEM_DATE_V 0xFFFFFFF 1083 #define SYSTEM_DATE_S 0 1084 1085 1086 #ifdef __cplusplus 1087 } 1088 #endif 1089 1090 1091 1092 #endif /*_SOC_SYSTEM_REG_H_ */ 1093
