1 // Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 // 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 #ifndef _SOC_CLKRST_REG_H_ 15 #define _SOC_CLKRST_REG_H_ 16 17 18 #ifdef __cplusplus 19 extern "C" { 20 #endif 21 #include "soc.h" 22 #define SYSTEM_SYSCLK_CONF_REG (DR_REG_CLKRST_BASE + 0x0000) 23 /* SYSTEM_SOC_CLK_SEL : R/W ;bitpos:[17:16] ;default: 2'h3 ; */ 24 /*description: */ 25 #define SYSTEM_SOC_CLK_SEL 0x00000003 26 #define SYSTEM_SOC_CLK_SEL_M ((SYSTEM_SOC_CLK_SEL_V)<<(SYSTEM_SOC_CLK_SEL_S)) 27 #define SYSTEM_SOC_CLK_SEL_V 0x3 28 #define SYSTEM_SOC_CLK_SEL_S 16 29 /* SYSTEM_SPLL_FREQ : RO ;bitpos:[15:8] ;default: 8'h0 ; */ 30 /*description: */ 31 #define SYSTEM_SPLL_FREQ 0x000000FF 32 #define SYSTEM_SPLL_FREQ_M ((SYSTEM_SPLL_FREQ_V)<<(SYSTEM_SPLL_FREQ_S)) 33 #define SYSTEM_SPLL_FREQ_V 0xFF 34 #define SYSTEM_SPLL_FREQ_S 8 35 /* SYSTEM_XTAL_FREQ : RO ;bitpos:[7:0] ;default: 8'h0 ; */ 36 /*description: */ 37 #define SYSTEM_CLK_XTAL_FREQ 0x000000FF 38 #define SYSTEM_CLK_XTAL_FREQ_M ((SYSTEM_XTAL_FREQ_V)<<(SYSTEM_XTAL_FREQ_S)) 39 #define SYSTEM_CLK_XTAL_FREQ_V 0xFF 40 #define SYSTEM_CLK_XTAL_FREQ_S 0 41 42 #define SYSTEM_CPUCLK_CONF_REG (DR_REG_CLKRST_BASE + 0x0004) 43 /* SYSTEM_CPU_DIV_DENOMINATOR : R/W ;bitpos:[21:16] ;default: 6'h0 ; */ 44 /*description: */ 45 #define SYSTEM_CPU_DIV_DENOMINATOR 0x0000003F 46 #define SYSTEM_CPU_DIV_DENOMINATOR_M ((SYSTEM_CPU_DIV_DENOMINATOR_V)<<(SYSTEM_CPU_DIV_DENOMINATOR_S)) 47 #define SYSTEM_CPU_DIV_DENOMINATOR_V 0x3F 48 #define SYSTEM_CPU_DIV_DENOMINATOR_S 16 49 /* SYSTEM_CPU_DIV_NUMERATOR : R/W ;bitpos:[13:8] ;default: 6'h0 ; */ 50 /*description: */ 51 #define SYSTEM_CPU_DIV_NUMERATOR 0x0000003F 52 #define SYSTEM_CPU_DIV_NUMERATOR_M ((SYSTEM_CPU_DIV_NUMERATOR_V)<<(SYSTEM_CPU_DIV_NUMERATOR_S)) 53 #define SYSTEM_CPU_DIV_NUMERATOR_V 0x3F 54 #define SYSTEM_CPU_DIV_NUMERATOR_S 8 55 /* SYSTEM_CPU_DIV_NUM : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ 56 /*description: */ 57 #define SYSTEM_CPU_DIV_NUM 0x000000FF 58 #define SYSTEM_CPU_DIV_NUM_M ((SYSTEM_CPU_DIV_NUM_V)<<(SYSTEM_CPU_DIV_NUM_S)) 59 #define SYSTEM_CPU_DIV_NUM_V 0xFF 60 #define SYSTEM_CPU_DIV_NUM_S 0 61 62 #define SYSTEM_PRE_DIV_CNT SYSTEM_CPU_DIV_NUM 63 #define SYSTEM_PRE_DIV_CNT_M SYSTEM_CPU_DIV_NUM_M 64 #define SYSTEM_PRE_DIV_CNT_V SYSTEM_CPU_DIV_NUM_V 65 #define SYSTEM_PRE_DIV_CNT_S SYSTEM_CPU_DIV_NUM_S 66 67 #define SYSTEM_BUSCLK_CONF_REG (DR_REG_CLKRST_BASE + 0x0008) 68 /* SYSTEM_AHB_DIV_NUM : R/W ;bitpos:[15:8] ;default: 8'h0 ; */ 69 /*description: */ 70 #define SYSTEM_AHB_DIV_NUM 0x000000FF 71 #define SYSTEM_AHB_DIV_NUM_M ((SYSTEM_AHB_DIV_NUM_V)<<(SYSTEM_AHB_DIV_NUM_S)) 72 #define SYSTEM_AHB_DIV_NUM_V 0xFF 73 #define SYSTEM_AHB_DIV_NUM_S 8 74 /* SYSTEM_APB_DIV_NUM : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ 75 /*description: */ 76 #define SYSTEM_APB_DIV_NUM 0x000000FF 77 #define SYSTEM_APB_DIV_NUM_M ((SYSTEM_APB_DIV_NUM_V)<<(SYSTEM_APB_DIV_NUM_S)) 78 #define SYSTEM_APB_DIV_NUM_V 0xFF 79 #define SYSTEM_APB_DIV_NUM_S 0 80 81 #define SYSTEM_MODCLK_CONF_REG (DR_REG_CLKRST_BASE + 0x000C) 82 /* SYSTEM_MODEM_CLK_SEL : R/W ;bitpos:[1:0] ;default: 1'h1 ; */ 83 /*description: */ 84 #define SYSTEM_MODEM_CLK_SEL 0x00000003 85 #define SYSTEM_MODEM_CLK_SEL_M ((SYSTEM_MODEM_CLK_SEL_V)<<(SYSTEM_MODEM_CLK_SEL_S)) 86 #define SYSTEM_MODEM_CLK_SEL_V 0x3 87 #define SYSTEM_MODEM_CLK_SEL_S 0 88 89 #define SYSTEM_CLK_OUT_EN_REG (DR_REG_CLKRST_BASE + 0x0010) 90 /* SYSTEM_CLK_RFADC_OEN : R/W ;bitpos:[12] ;default: 1'b1 ; */ 91 /*description: */ 92 #define SYSTEM_CLK_RFADC_OEN (BIT(12)) 93 #define SYSTEM_CLK_RFADC_OEN_M (BIT(12)) 94 #define SYSTEM_CLK_RFADC_OEN_V 0x1 95 #define SYSTEM_CLK_RFADC_OEN_S 12 96 /* SYSTEM_CLK_RFDAC_OEN : R/W ;bitpos:[11] ;default: 1'b1 ; */ 97 /*description: */ 98 #define SYSTEM_CLK_RFDAC_OEN (BIT(11)) 99 #define SYSTEM_CLK_RFDAC_OEN_M (BIT(11)) 100 #define SYSTEM_CLK_RFDAC_OEN_V 0x1 101 #define SYSTEM_CLK_RFDAC_OEN_S 11 102 /* SYSTEM_CLK_XTAL_OEN : R/W ;bitpos:[10] ;default: 1'b1 ; */ 103 /*description: */ 104 #define SYSTEM_CLK_XTAL_OEN (BIT(10)) 105 #define SYSTEM_CLK_XTAL_OEN_M (BIT(10)) 106 #define SYSTEM_CLK_XTAL_OEN_V 0x1 107 #define SYSTEM_CLK_XTAL_OEN_S 10 108 /* SYSTEM_CLK_SPLL_OEN : R/W ;bitpos:[9] ;default: 1'b1 ; */ 109 /*description: */ 110 #define SYSTEM_CLK_SPLL_OEN (BIT(9)) 111 #define SYSTEM_CLK_SPLL_OEN_M (BIT(9)) 112 #define SYSTEM_CLK_SPLL_OEN_V 0x1 113 #define SYSTEM_CLK_SPLL_OEN_S 9 114 /* SYSTEM_CLK_CPU_OEN : R/W ;bitpos:[8] ;default: 1'b1 ; */ 115 /*description: */ 116 #define SYSTEM_CLK_CPU_OEN (BIT(8)) 117 #define SYSTEM_CLK_CPU_OEN_M (BIT(8)) 118 #define SYSTEM_CLK_CPU_OEN_V 0x1 119 #define SYSTEM_CLK_CPU_OEN_S 8 120 /* SYSTEM_CLK_AHB_OEN : R/W ;bitpos:[7] ;default: 1'b1 ; */ 121 /*description: */ 122 #define SYSTEM_CLK_AHB_OEN (BIT(7)) 123 #define SYSTEM_CLK_AHB_OEN_M (BIT(7)) 124 #define SYSTEM_CLK_AHB_OEN_V 0x1 125 #define SYSTEM_CLK_AHB_OEN_S 7 126 /* SYSTEM_CLK_APB_OEN : R/W ;bitpos:[6] ;default: 1'b1 ; */ 127 /*description: */ 128 #define SYSTEM_CLK_APB_OEN (BIT(6)) 129 #define SYSTEM_CLK_APB_OEN_M (BIT(6)) 130 #define SYSTEM_CLK_APB_OEN_V 0x1 131 #define SYSTEM_CLK_APB_OEN_S 6 132 /* SYSTEM_CLK_32M_BT_OEN : R/W ;bitpos:[5] ;default: 1'b1 ; */ 133 /*description: */ 134 #define SYSTEM_CLK_32M_BT_OEN (BIT(5)) 135 #define SYSTEM_CLK_32M_BT_OEN_M (BIT(5)) 136 #define SYSTEM_CLK_32M_BT_OEN_V 0x1 137 #define SYSTEM_CLK_32M_BT_OEN_S 5 138 /* SYSTEM_CLK_16M_BT_OEN : R/W ;bitpos:[4] ;default: 1'b1 ; */ 139 /*description: */ 140 #define SYSTEM_CLK_16M_BT_OEN (BIT(4)) 141 #define SYSTEM_CLK_16M_BT_OEN_M (BIT(4)) 142 #define SYSTEM_CLK_16M_BT_OEN_V 0x1 143 #define SYSTEM_CLK_16M_BT_OEN_S 4 144 /* SYSTEM_CLK_8M_BT_OEN : R/W ;bitpos:[3] ;default: 1'b1 ; */ 145 /*description: */ 146 #define SYSTEM_CLK_8M_BT_OEN (BIT(3)) 147 #define SYSTEM_CLK_8M_BT_OEN_M (BIT(3)) 148 #define SYSTEM_CLK_8M_BT_OEN_V 0x1 149 #define SYSTEM_CLK_8M_BT_OEN_S 3 150 151 #define SYSTEM_MODEM_CLK_EN_REG (DR_REG_CLKRST_BASE + 0x0014) 152 /* SYSTEM_DATA_DUMP_CLK_EN : R/W ;bitpos:[21] ;default: 1'b0 ; */ 153 /*description: */ 154 #define SYSTEM_DATA_DUMP_CLK_EN (BIT(21)) 155 #define SYSTEM_DATA_DUMP_CLK_EN_M (BIT(21)) 156 #define SYSTEM_DATA_DUMP_CLK_EN_V 0x1 157 #define SYSTEM_DATA_DUMP_CLK_EN_S 21 158 /* SYSTEM_RFADC_CLK_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */ 159 /*description: */ 160 #define SYSTEM_RFADC_CLK_EN (BIT(20)) 161 #define SYSTEM_RFADC_CLK_EN_M (BIT(20)) 162 #define SYSTEM_RFADC_CLK_EN_V 0x1 163 #define SYSTEM_RFADC_CLK_EN_S 20 164 /* SYSTEM_RFDAC_CLK_EN : R/W ;bitpos:[19] ;default: 1'b0 ; */ 165 /*description: */ 166 #define SYSTEM_RFDAC_CLK_EN (BIT(19)) 167 #define SYSTEM_RFDAC_CLK_EN_M (BIT(19)) 168 #define SYSTEM_RFDAC_CLK_EN_V 0x1 169 #define SYSTEM_RFDAC_CLK_EN_S 19 170 /* SYSTEM_BTLC_CLK_EN : R/W ;bitpos:[18] ;default: 1'b0 ; */ 171 /*description: */ 172 #define SYSTEM_BTLC_CLK_EN (BIT(18)) 173 #define SYSTEM_BTLC_CLK_EN_M (BIT(18)) 174 #define SYSTEM_BTLC_CLK_EN_V 0x1 175 #define SYSTEM_BTLC_CLK_EN_S 18 176 /* SYSTEM_BLE_SEC_CLK_EN : R/W ;bitpos:[17] ;default: 1'b0 ; */ 177 /*description: */ 178 #define SYSTEM_BLE_SEC_CLK_EN (BIT(17)) 179 #define SYSTEM_BLE_SEC_CLK_EN_M (BIT(17)) 180 #define SYSTEM_BLE_SEC_CLK_EN_V 0x1 181 #define SYSTEM_BLE_SEC_CLK_EN_S 17 182 /* SYSTEM_BLE_SEC_AAR_CLK_EN : R/W ;bitpos:[16] ;default: 1'b0 ; */ 183 /*description: */ 184 #define SYSTEM_BLE_SEC_AAR_CLK_EN (BIT(16)) 185 #define SYSTEM_BLE_SEC_AAR_CLK_EN_M (BIT(16)) 186 #define SYSTEM_BLE_SEC_AAR_CLK_EN_V 0x1 187 #define SYSTEM_BLE_SEC_AAR_CLK_EN_S 16 188 /* SYSTEM_BLE_SEC_CCM_CLK_EN : R/W ;bitpos:[15] ;default: 1'b0 ; */ 189 /*description: */ 190 #define SYSTEM_BLE_SEC_CCM_CLK_EN (BIT(15)) 191 #define SYSTEM_BLE_SEC_CCM_CLK_EN_M (BIT(15)) 192 #define SYSTEM_BLE_SEC_CCM_CLK_EN_V 0x1 193 #define SYSTEM_BLE_SEC_CCM_CLK_EN_S 15 194 /* SYSTEM_BLE_SEC_ECB_CLK_EN : R/W ;bitpos:[14] ;default: 1'b0 ; */ 195 /*description: */ 196 #define SYSTEM_BLE_SEC_ECB_CLK_EN (BIT(14)) 197 #define SYSTEM_BLE_SEC_ECB_CLK_EN_M (BIT(14)) 198 #define SYSTEM_BLE_SEC_ECB_CLK_EN_V 0x1 199 #define SYSTEM_BLE_SEC_ECB_CLK_EN_S 14 200 /* SYSTEM_IEEE802154MAC_CLK_EN : R/W ;bitpos:[13] ;default: 1'b0 ; */ 201 /*description: */ 202 #define SYSTEM_IEEE802154MAC_CLK_EN (BIT(13)) 203 #define SYSTEM_IEEE802154MAC_CLK_EN_M (BIT(13)) 204 #define SYSTEM_IEEE802154MAC_CLK_EN_V 0x1 205 #define SYSTEM_IEEE802154MAC_CLK_EN_S 13 206 /* SYSTEM_IEEE802154BB_CLK_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */ 207 /*description: */ 208 #define SYSTEM_IEEE802154BB_CLK_EN (BIT(12)) 209 #define SYSTEM_IEEE802154BB_CLK_EN_M (BIT(12)) 210 #define SYSTEM_IEEE802154BB_CLK_EN_V 0x1 211 #define SYSTEM_IEEE802154BB_CLK_EN_S 12 212 /* SYSTEM_COEX_CLK_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */ 213 /*description: */ 214 #define SYSTEM_COEX_CLK_EN (BIT(11)) 215 #define SYSTEM_COEX_CLK_EN_M (BIT(11)) 216 #define SYSTEM_COEX_CLK_EN_V 0x1 217 #define SYSTEM_COEX_CLK_EN_S 11 218 /* SYSTEM_I2CMST_CLK_EN : R/W ;bitpos:[10] ;default: 1'b1 ; */ 219 /*description: */ 220 #define SYSTEM_I2CMST_CLK_EN (BIT(10)) 221 #define SYSTEM_I2CMST_CLK_EN_M (BIT(10)) 222 #define SYSTEM_I2CMST_CLK_EN_V 0x1 223 #define SYSTEM_I2CMST_CLK_EN_S 10 224 /* SYSTEM_I2C_CLK_EN : R/W ;bitpos:[9] ;default: 1'b1 ; */ 225 /*description: */ 226 #define SYSTEM_I2C_CLK_EN (BIT(9)) 227 #define SYSTEM_I2C_CLK_EN_M (BIT(9)) 228 #define SYSTEM_I2C_CLK_EN_V 0x1 229 #define SYSTEM_I2C_CLK_EN_S 9 230 /* SYSTEM_RW_BTMAC_CLK_EN : R/W ;bitpos:[8] ;default: 2'b0 ; */ 231 /*description: */ 232 #define SYSTEM_RW_BTMAC_CLK_EN (BIT(8)) 233 #define SYSTEM_RW_BTMAC_CLK_EN_M (BIT(8)) 234 #define SYSTEM_RW_BTMAC_CLK_EN_V 0x1 235 #define SYSTEM_RW_BTMAC_CLK_EN_S 8 236 /* SYSTEM_MACPWR_CLK_EN : R/W ;bitpos:[7] ;default: 1'b1 ; */ 237 /*description: */ 238 #define SYSTEM_MACPWR_CLK_EN (BIT(7)) 239 #define SYSTEM_MACPWR_CLK_EN_M (BIT(7)) 240 #define SYSTEM_MACPWR_CLK_EN_V 0x1 241 #define SYSTEM_MACPWR_CLK_EN_S 7 242 /* SYSTEM_EMAC_CLK_EN : R/W ;bitpos:[6] ;default: 1'b1 ; */ 243 /*description: */ 244 #define SYSTEM_EMAC_CLK_EN (BIT(6)) 245 #define SYSTEM_EMAC_CLK_EN_M (BIT(6)) 246 #define SYSTEM_EMAC_CLK_EN_V 0x1 247 #define SYSTEM_EMAC_CLK_EN_S 6 248 /* SYSTEM_SDIO_CLK_EN : R/W ;bitpos:[5] ;default: 1'b1 ; */ 249 /*description: */ 250 #define SYSTEM_SDIO_CLK_EN (BIT(5)) 251 #define SYSTEM_SDIO_CLK_EN_M (BIT(5)) 252 #define SYSTEM_SDIO_CLK_EN_V 0x1 253 #define SYSTEM_SDIO_CLK_EN_S 5 254 /* SYSTEM_BTMAC_CLK_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */ 255 /*description: */ 256 #define SYSTEM_BTMAC_CLK_EN (BIT(4)) 257 #define SYSTEM_BTMAC_CLK_EN_M (BIT(4)) 258 #define SYSTEM_BTMAC_CLK_EN_V 0x1 259 #define SYSTEM_BTMAC_CLK_EN_S 4 260 /* SYSTEM_BT_CLK_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */ 261 /*description: */ 262 #define SYSTEM_BT_CLK_EN (BIT(3)) 263 #define SYSTEM_BT_CLK_EN_M (BIT(3)) 264 #define SYSTEM_BT_CLK_EN_V 0x1 265 #define SYSTEM_BT_CLK_EN_S 3 266 /* SYSTEM_MAC_CLK_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */ 267 /*description: */ 268 #define SYSTEM_MAC_CLK_EN (BIT(2)) 269 #define SYSTEM_MAC_CLK_EN_M (BIT(2)) 270 #define SYSTEM_MAC_CLK_EN_V 0x1 271 #define SYSTEM_MAC_CLK_EN_S 2 272 /* SYSTEM_FE_CLK_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */ 273 /*description: */ 274 #define SYSTEM_FE_CLK_EN (BIT(1)) 275 #define SYSTEM_FE_CLK_EN_M (BIT(1)) 276 #define SYSTEM_FE_CLK_EN_V 0x1 277 #define SYSTEM_FE_CLK_EN_S 1 278 /* SYSTEM_FE_CAL_CLK_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ 279 /*description: */ 280 #define SYSTEM_FE_CAL_CLK_EN (BIT(0)) 281 #define SYSTEM_FE_CAL_CLK_EN_M (BIT(0)) 282 #define SYSTEM_FE_CAL_CLK_EN_V 0x1 283 #define SYSTEM_FE_CAL_CLK_EN_S 0 284 285 #define SYSTEM_MODEM_RST_EN_REG (DR_REG_CLKRST_BASE + 0x0018) 286 /* SYSTEM_DATA_DUMP_RST : R/W ;bitpos:[20] ;default: 1'b0 ; */ 287 /*description: */ 288 #define SYSTEM_DATA_DUMP_RST (BIT(20)) 289 #define SYSTEM_DATA_DUMP_RST_M (BIT(20)) 290 #define SYSTEM_DATA_DUMP_RST_V 0x1 291 #define SYSTEM_DATA_DUMP_RST_S 20 292 /* SYSTEM_APB_RET_RST : R/W ;bitpos:[19] ;default: 1'b0 ; */ 293 /*description: */ 294 #define SYSTEM_APB_RET_RST (BIT(19)) 295 #define SYSTEM_APB_RET_RST_M (BIT(19)) 296 #define SYSTEM_APB_RET_RST_V 0x1 297 #define SYSTEM_APB_RET_RST_S 19 298 /* SYSTEM_BLE_SEC_RST : R/W ;bitpos:[18] ;default: 1'b0 ; */ 299 /*description: */ 300 #define SYSTEM_BLE_SEC_RST (BIT(18)) 301 #define SYSTEM_BLE_SEC_RST_M (BIT(18)) 302 #define SYSTEM_BLE_SEC_RST_V 0x1 303 #define SYSTEM_BLE_SEC_RST_S 18 304 /* SYSTEM_BLE_SEC_AAR_RST : R/W ;bitpos:[17] ;default: 1'b0 ; */ 305 /*description: */ 306 #define SYSTEM_BLE_SEC_AAR_RST (BIT(17)) 307 #define SYSTEM_BLE_SEC_AAR_RST_M (BIT(17)) 308 #define SYSTEM_BLE_SEC_AAR_RST_V 0x1 309 #define SYSTEM_BLE_SEC_AAR_RST_S 17 310 /* SYSTEM_BLE_SEC_CCM_RST : R/W ;bitpos:[16] ;default: 1'b0 ; */ 311 /*description: */ 312 #define SYSTEM_BLE_SEC_CCM_RST (BIT(16)) 313 #define SYSTEM_BLE_SEC_CCM_RST_M (BIT(16)) 314 #define SYSTEM_BLE_SEC_CCM_RST_V 0x1 315 #define SYSTEM_BLE_SEC_CCM_RST_S 16 316 /* SYSTEM_BLE_SEC_ECB_RST : R/W ;bitpos:[15] ;default: 1'b0 ; */ 317 /*description: */ 318 #define SYSTEM_BLE_SEC_ECB_RST (BIT(15)) 319 #define SYSTEM_BLE_SEC_ECB_RST_M (BIT(15)) 320 #define SYSTEM_BLE_SEC_ECB_RST_V 0x1 321 #define SYSTEM_BLE_SEC_ECB_RST_S 15 322 /* SYSTEM_IEEE802154MAC_RST : R/W ;bitpos:[14] ;default: 1'b0 ; */ 323 /*description: */ 324 #define SYSTEM_IEEE802154MAC_RST (BIT(14)) 325 #define SYSTEM_IEEE802154MAC_RST_M (BIT(14)) 326 #define SYSTEM_IEEE802154MAC_RST_V 0x1 327 #define SYSTEM_IEEE802154MAC_RST_S 14 328 /* SYSTEM_IEEE802154BB_RST : R/W ;bitpos:[13] ;default: 1'b0 ; */ 329 /*description: */ 330 #define SYSTEM_IEEE802154BB_RST (BIT(13)) 331 #define SYSTEM_IEEE802154BB_RST_M (BIT(13)) 332 #define SYSTEM_IEEE802154BB_RST_V 0x1 333 #define SYSTEM_IEEE802154BB_RST_S 13 334 /* SYSTEM_COEX_RST : R/W ;bitpos:[12] ;default: 1'b0 ; */ 335 /*description: */ 336 #define SYSTEM_COEX_RST (BIT(12)) 337 #define SYSTEM_COEX_RST_M (BIT(12)) 338 #define SYSTEM_COEX_RST_V 0x1 339 #define SYSTEM_COEX_RST_S 12 340 /* SYSTEM_BT_RST : R/W ;bitpos:[11] ;default: 1'b0 ; */ 341 /*description: */ 342 #define SYSTEM_BT_REG_RST (BIT(11)) 343 #define SYSTEM_BT_REG_RST_M (BIT(11)) 344 #define SYSTEM_BT_REG_RST_V 0x1 345 #define SYSTEM_BT_REG_RST_S 11 346 /* SYSTEM_RW_BTLPRST : R/W ;bitpos:[10] ;default: 1'b0 ; */ 347 /*description: */ 348 #define SYSTEM_RW_BTLPRST (BIT(10)) 349 #define SYSTEM_RW_BTLPRST_M (BIT(10)) 350 #define SYSTEM_RW_BTLPRST_V 0x1 351 #define SYSTEM_RW_BTLPRST_S 10 352 /* SYSTEM_RW_BTRST : R/W ;bitpos:[9] ;default: 1'b0 ; */ 353 /*description: */ 354 #define SYSTEM_RW_BTRST (BIT(9)) 355 #define SYSTEM_RW_BTRST_M (BIT(9)) 356 #define SYSTEM_RW_BTRST_V 0x1 357 #define SYSTEM_RW_BTRST_S 9 358 /* SYSTEM_RW_BTLP_RST : R/W ;bitpos:[8] ;default: 1'b0 ; */ 359 /*description: */ 360 #define SYSTEM_RW_BTLP_RST (BIT(8)) 361 #define SYSTEM_RW_BTLP_RST_M (BIT(8)) 362 #define SYSTEM_RW_BTLP_RST_V 0x1 363 #define SYSTEM_RW_BTLP_RST_S 8 364 /* SYSTEM_RW_BTMAC_RST : R/W ;bitpos:[7] ;default: 1'b0 ; */ 365 /*description: */ 366 #define SYSTEM_RW_BTMAC_RST (BIT(7)) 367 #define SYSTEM_RW_BTMAC_RST_M (BIT(7)) 368 #define SYSTEM_RW_BTMAC_RST_V 0x1 369 #define SYSTEM_RW_BTMAC_RST_S 7 370 /* SYSTEM_MACPWR_RST : R/W ;bitpos:[6] ;default: 1'b0 ; */ 371 /*description: */ 372 #define SYSTEM_MACPWR_RST (BIT(6)) 373 #define SYSTEM_MACPWR_RST_M (BIT(6)) 374 #define SYSTEM_MACPWR_RST_V 0x1 375 #define SYSTEM_MACPWR_RST_S 6 376 /* SYSTEM_EMAC_RST : R/W ;bitpos:[5] ;default: 1'b0 ; */ 377 /*description: */ 378 #define SYSTEM_EMAC_RST (BIT(5)) 379 #define SYSTEM_EMAC_RST_M (BIT(5)) 380 #define SYSTEM_EMAC_RST_V 0x1 381 #define SYSTEM_EMAC_RST_S 5 382 /* SYSTEM_SDIO_RST : R/W ;bitpos:[4] ;default: 1'b0 ; */ 383 /*description: */ 384 #define SYSTEM_SDIO_RST (BIT(4)) 385 #define SYSTEM_SDIO_RST_M (BIT(4)) 386 #define SYSTEM_SDIO_RST_V 0x1 387 #define SYSTEM_SDIO_RST_S 4 388 /* SYSTEM_BTMAC_RST : R/W ;bitpos:[3] ;default: 1'b0 ; */ 389 /*description: */ 390 #define SYSTEM_BTMAC_RST (BIT(3)) 391 #define SYSTEM_BTMAC_RST_M (BIT(3)) 392 #define SYSTEM_BTMAC_RST_V 0x1 393 #define SYSTEM_BTMAC_RST_S 3 394 /* SYSTEM_BT_RST : R/W ;bitpos:[2] ;default: 1'b0 ; */ 395 /*description: */ 396 #define SYSTEM_BT_RST (BIT(2)) 397 #define SYSTEM_BT_RST_M (BIT(2)) 398 #define SYSTEM_BT_RST_V 0x1 399 #define SYSTEM_BT_RST_S 2 400 /* SYSTEM_MAC_RST : R/W ;bitpos:[1] ;default: 1'b0 ; */ 401 /*description: */ 402 #define SYSTEM_MAC_RST (BIT(1)) 403 #define SYSTEM_MAC_RST_M (BIT(1)) 404 #define SYSTEM_MAC_RST_V 0x1 405 #define SYSTEM_MAC_RST_S 1 406 /* SYSTEM_FE_RST : R/W ;bitpos:[0] ;default: 1'b0 ; */ 407 /*description: */ 408 #define SYSTEM_FE_RST (BIT(0)) 409 #define SYSTEM_FE_RST_M (BIT(0)) 410 #define SYSTEM_FE_RST_V 0x1 411 #define SYSTEM_FE_RST_S 0 412 413 #define SYSTEM_PERIP_CLK_CONF_REG (DR_REG_CLKRST_BASE + 0x001C) 414 /* SYSTEM_MSPI_DIV_NUM : R/W ;bitpos:[31:24] ;default: 8'h1 ; */ 415 /*description: */ 416 #define SYSTEM_MSPI_DIV_NUM 0x000000FF 417 #define SYSTEM_MSPI_DIV_NUM_M ((SYSTEM_MSPI_DIV_NUM_V)<<(SYSTEM_MSPI_DIV_NUM_S)) 418 #define SYSTEM_MSPI_DIV_NUM_V 0xFF 419 #define SYSTEM_MSPI_DIV_NUM_S 24 420 /* SYSTEM_CAN_DIV_NUM : R/W ;bitpos:[23:16] ;default: 8'h1 ; */ 421 /*description: */ 422 #define SYSTEM_CAN_DIV_NUM 0x000000FF 423 #define SYSTEM_CAN_DIV_NUM_M ((SYSTEM_CAN_DIV_NUM_V)<<(SYSTEM_CAN_DIV_NUM_S)) 424 #define SYSTEM_CAN_DIV_NUM_V 0xFF 425 #define SYSTEM_CAN_DIV_NUM_S 16 426 /* SYSTEM_USB_DEVICE_DIV_NUM : R/W ;bitpos:[15:8] ;default: 8'h1 ; */ 427 /*description: */ 428 #define SYSTEM_USB_DEVICE_DIV_NUM 0x000000FF 429 #define SYSTEM_USB_DEVICE_DIV_NUM_M ((SYSTEM_USB_DEVICE_DIV_NUM_V)<<(SYSTEM_USB_DEVICE_DIV_NUM_S)) 430 #define SYSTEM_USB_DEVICE_DIV_NUM_V 0xFF 431 #define SYSTEM_USB_DEVICE_DIV_NUM_S 8 432 /* SYSTEM_SEC_DIV_NUM : R/W ;bitpos:[7:0] ;default: 8'h1 ; */ 433 /*description: */ 434 #define SYSTEM_SEC_DIV_NUM 0x000000FF 435 #define SYSTEM_SEC_DIV_NUM_M ((SYSTEM_SEC_DIV_NUM_V)<<(SYSTEM_SEC_DIV_NUM_S)) 436 #define SYSTEM_SEC_DIV_NUM_V 0xFF 437 #define SYSTEM_SEC_DIV_NUM_S 0 438 439 #define SYSTEM_PERIP_CLK_EN0_REG (DR_REG_CLKRST_BASE + 0x0020) 440 /* SYSTEM_SPI4_CLK_EN : R/W ;bitpos:[31] ;default: 1'h1 ; */ 441 /*description: */ 442 #define SYSTEM_SPI4_CLK_EN (BIT(31)) 443 #define SYSTEM_SPI4_CLK_EN_M (BIT(31)) 444 #define SYSTEM_SPI4_CLK_EN_V 0x1 445 #define SYSTEM_SPI4_CLK_EN_S 31 446 /* SYSTEM_ADC2_ARB_CLK_EN : R/W ;bitpos:[30] ;default: 1'b1 ; */ 447 /*description: */ 448 #define SYSTEM_ADC2_ARB_CLK_EN (BIT(30)) 449 #define SYSTEM_ADC2_ARB_CLK_EN_M (BIT(30)) 450 #define SYSTEM_ADC2_ARB_CLK_EN_V 0x1 451 #define SYSTEM_ADC2_ARB_CLK_EN_S 30 452 /* SYSTEM_SYSTIMER_CLK_EN : R/W ;bitpos:[29] ;default: 1'b1 ; */ 453 /*description: */ 454 #define SYSTEM_SYSTIMER_CLK_EN (BIT(29)) 455 #define SYSTEM_SYSTIMER_CLK_EN_M (BIT(29)) 456 #define SYSTEM_SYSTIMER_CLK_EN_V 0x1 457 #define SYSTEM_SYSTIMER_CLK_EN_S 29 458 /* SYSTEM_APB_SARADC_CLK_EN : R/W ;bitpos:[28] ;default: 1'b1 ; */ 459 /*description: */ 460 #define SYSTEM_APB_SARADC_CLK_EN (BIT(28)) 461 #define SYSTEM_APB_SARADC_CLK_EN_M (BIT(28)) 462 #define SYSTEM_APB_SARADC_CLK_EN_V 0x1 463 #define SYSTEM_APB_SARADC_CLK_EN_S 28 464 /* SYSTEM_SPI3_DMA_CLK_EN : R/W ;bitpos:[27] ;default: 1'b1 ; */ 465 /*description: */ 466 #define SYSTEM_SPI3_DMA_CLK_EN (BIT(27)) 467 #define SYSTEM_SPI3_DMA_CLK_EN_M (BIT(27)) 468 #define SYSTEM_SPI3_DMA_CLK_EN_V 0x1 469 #define SYSTEM_SPI3_DMA_CLK_EN_S 27 470 /* SYSTEM_PWM3_CLK_EN : R/W ;bitpos:[26] ;default: 1'b0 ; */ 471 /*description: */ 472 #define SYSTEM_PWM3_CLK_EN (BIT(26)) 473 #define SYSTEM_PWM3_CLK_EN_M (BIT(26)) 474 #define SYSTEM_PWM3_CLK_EN_V 0x1 475 #define SYSTEM_PWM3_CLK_EN_S 26 476 /* SYSTEM_PWM2_CLK_EN : R/W ;bitpos:[25] ;default: 1'b0 ; */ 477 /*description: */ 478 #define SYSTEM_PWM2_CLK_EN (BIT(25)) 479 #define SYSTEM_PWM2_CLK_EN_M (BIT(25)) 480 #define SYSTEM_PWM2_CLK_EN_V 0x1 481 #define SYSTEM_PWM2_CLK_EN_S 25 482 /* SYSTEM_UART_MEM_CLK_EN : R/W ;bitpos:[24] ;default: 1'b1 ; */ 483 /*description: */ 484 #define SYSTEM_UART_MEM_CLK_EN (BIT(24)) 485 #define SYSTEM_UART_MEM_CLK_EN_M (BIT(24)) 486 #define SYSTEM_UART_MEM_CLK_EN_V 0x1 487 #define SYSTEM_UART_MEM_CLK_EN_S 24 488 /* SYSTEM_USB_DEVICE_CLK_EN : R/W ;bitpos:[23] ;default: 1'b1 ; */ 489 /*description: */ 490 #define SYSTEM_USB_DEVICE_CLK_EN (BIT(23)) 491 #define SYSTEM_USB_DEVICE_CLK_EN_M (BIT(23)) 492 #define SYSTEM_USB_DEVICE_CLK_EN_V 0x1 493 #define SYSTEM_USB_DEVICE_CLK_EN_S 23 494 /* SYSTEM_SPI2_DMA_CLK_EN : R/W ;bitpos:[22] ;default: 1'b1 ; */ 495 /*description: */ 496 #define SYSTEM_SPI2_DMA_CLK_EN (BIT(22)) 497 #define SYSTEM_SPI2_DMA_CLK_EN_M (BIT(22)) 498 #define SYSTEM_SPI2_DMA_CLK_EN_V 0x1 499 #define SYSTEM_SPI2_DMA_CLK_EN_S 22 500 /* SYSTEM_I2S1_CLK_EN : R/W ;bitpos:[21] ;default: 1'b0 ; */ 501 /*description: */ 502 #define SYSTEM_I2S1_CLK_EN (BIT(21)) 503 #define SYSTEM_I2S1_CLK_EN_M (BIT(21)) 504 #define SYSTEM_I2S1_CLK_EN_V 0x1 505 #define SYSTEM_I2S1_CLK_EN_S 21 506 /* SYSTEM_PWM1_CLK_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */ 507 /*description: */ 508 #define SYSTEM_PWM1_CLK_EN (BIT(20)) 509 #define SYSTEM_PWM1_CLK_EN_M (BIT(20)) 510 #define SYSTEM_PWM1_CLK_EN_V 0x1 511 #define SYSTEM_PWM1_CLK_EN_S 20 512 /* SYSTEM_TWAI_CLK_EN : R/W ;bitpos:[19] ;default: 1'b0 ; */ 513 /*description: */ 514 #define SYSTEM_TWAI_CLK_EN (BIT(19)) 515 #define SYSTEM_TWAI_CLK_EN_M (BIT(19)) 516 #define SYSTEM_TWAI_CLK_EN_V 0x1 517 #define SYSTEM_TWAI_CLK_EN_S 19 518 /* SYSTEM_I2C_EXT1_CLK_EN : R/W ;bitpos:[18] ;default: 1'b0 ; */ 519 /*description: */ 520 #define SYSTEM_I2C_EXT1_CLK_EN (BIT(18)) 521 #define SYSTEM_I2C_EXT1_CLK_EN_M (BIT(18)) 522 #define SYSTEM_I2C_EXT1_CLK_EN_V 0x1 523 #define SYSTEM_I2C_EXT1_CLK_EN_S 18 524 /* SYSTEM_PWM0_CLK_EN : R/W ;bitpos:[17] ;default: 1'b0 ; */ 525 /*description: */ 526 #define SYSTEM_PWM0_CLK_EN (BIT(17)) 527 #define SYSTEM_PWM0_CLK_EN_M (BIT(17)) 528 #define SYSTEM_PWM0_CLK_EN_V 0x1 529 #define SYSTEM_PWM0_CLK_EN_S 17 530 /* SYSTEM_SPI3_CLK_EN : R/W ;bitpos:[16] ;default: 1'b1 ; */ 531 /*description: */ 532 #define SYSTEM_SPI3_CLK_EN (BIT(16)) 533 #define SYSTEM_SPI3_CLK_EN_M (BIT(16)) 534 #define SYSTEM_SPI3_CLK_EN_V 0x1 535 #define SYSTEM_SPI3_CLK_EN_S 16 536 /* SYSTEM_TIMERGROUP1_CLK_EN : R/W ;bitpos:[15] ;default: 1'b1 ; */ 537 /*description: */ 538 #define SYSTEM_TIMERGROUP1_CLK_EN (BIT(15)) 539 #define SYSTEM_TIMERGROUP1_CLK_EN_M (BIT(15)) 540 #define SYSTEM_TIMERGROUP1_CLK_EN_V 0x1 541 #define SYSTEM_TIMERGROUP1_CLK_EN_S 15 542 /* SYSTEM_EFUSE_CLK_EN : R/W ;bitpos:[14] ;default: 1'b1 ; */ 543 /*description: */ 544 #define SYSTEM_EFUSE_CLK_EN (BIT(14)) 545 #define SYSTEM_EFUSE_CLK_EN_M (BIT(14)) 546 #define SYSTEM_EFUSE_CLK_EN_V 0x1 547 #define SYSTEM_EFUSE_CLK_EN_S 14 548 /* SYSTEM_TIMERGROUP_CLK_EN : R/W ;bitpos:[13] ;default: 1'b1 ; */ 549 /*description: */ 550 #define SYSTEM_TIMERGROUP_CLK_EN (BIT(13)) 551 #define SYSTEM_TIMERGROUP_CLK_EN_M (BIT(13)) 552 #define SYSTEM_TIMERGROUP_CLK_EN_V 0x1 553 #define SYSTEM_TIMERGROUP_CLK_EN_S 13 554 /* SYSTEM_UHCI1_CLK_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */ 555 /*description: */ 556 #define SYSTEM_UHCI1_CLK_EN (BIT(12)) 557 #define SYSTEM_UHCI1_CLK_EN_M (BIT(12)) 558 #define SYSTEM_UHCI1_CLK_EN_V 0x1 559 #define SYSTEM_UHCI1_CLK_EN_S 12 560 /* SYSTEM_LEDC_CLK_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */ 561 /*description: */ 562 #define SYSTEM_LEDC_CLK_EN (BIT(11)) 563 #define SYSTEM_LEDC_CLK_EN_M (BIT(11)) 564 #define SYSTEM_LEDC_CLK_EN_V 0x1 565 #define SYSTEM_LEDC_CLK_EN_S 11 566 /* SYSTEM_PCNT_CLK_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ 567 /*description: */ 568 #define SYSTEM_PCNT_CLK_EN (BIT(10)) 569 #define SYSTEM_PCNT_CLK_EN_M (BIT(10)) 570 #define SYSTEM_PCNT_CLK_EN_V 0x1 571 #define SYSTEM_PCNT_CLK_EN_S 10 572 /* SYSTEM_RMT_CLK_EN : R/W ;bitpos:[9] ;default: 1'b0 ; */ 573 /*description: */ 574 #define SYSTEM_RMT_CLK_EN (BIT(9)) 575 #define SYSTEM_RMT_CLK_EN_M (BIT(9)) 576 #define SYSTEM_RMT_CLK_EN_V 0x1 577 #define SYSTEM_RMT_CLK_EN_S 9 578 /* SYSTEM_UHCI0_CLK_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */ 579 /*description: */ 580 #define SYSTEM_UHCI0_CLK_EN (BIT(8)) 581 #define SYSTEM_UHCI0_CLK_EN_M (BIT(8)) 582 #define SYSTEM_UHCI0_CLK_EN_V 0x1 583 #define SYSTEM_UHCI0_CLK_EN_S 8 584 /* SYSTEM_I2C_EXT0_CLK_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */ 585 /*description: */ 586 #define SYSTEM_I2C_EXT0_CLK_EN (BIT(7)) 587 #define SYSTEM_I2C_EXT0_CLK_EN_M (BIT(7)) 588 #define SYSTEM_I2C_EXT0_CLK_EN_V 0x1 589 #define SYSTEM_I2C_EXT0_CLK_EN_S 7 590 /* SYSTEM_SPI2_CLK_EN : R/W ;bitpos:[6] ;default: 1'b1 ; */ 591 /*description: */ 592 #define SYSTEM_SPI2_CLK_EN (BIT(6)) 593 #define SYSTEM_SPI2_CLK_EN_M (BIT(6)) 594 #define SYSTEM_SPI2_CLK_EN_V 0x1 595 #define SYSTEM_SPI2_CLK_EN_S 6 596 /* SYSTEM_UART1_CLK_EN : R/W ;bitpos:[5] ;default: 1'b1 ; */ 597 /*description: */ 598 #define SYSTEM_UART1_CLK_EN (BIT(5)) 599 #define SYSTEM_UART1_CLK_EN_M (BIT(5)) 600 #define SYSTEM_UART1_CLK_EN_V 0x1 601 #define SYSTEM_UART1_CLK_EN_S 5 602 /* SYSTEM_I2S0_CLK_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */ 603 /*description: */ 604 #define SYSTEM_I2S0_CLK_EN (BIT(4)) 605 #define SYSTEM_I2S0_CLK_EN_M (BIT(4)) 606 #define SYSTEM_I2S0_CLK_EN_V 0x1 607 #define SYSTEM_I2S0_CLK_EN_S 4 608 /* SYSTEM_WDG_CLK_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */ 609 /*description: */ 610 #define SYSTEM_WDG_CLK_EN (BIT(3)) 611 #define SYSTEM_WDG_CLK_EN_M (BIT(3)) 612 #define SYSTEM_WDG_CLK_EN_V 0x1 613 #define SYSTEM_WDG_CLK_EN_S 3 614 /* SYSTEM_UART_CLK_EN : R/W ;bitpos:[2] ;default: 1'b1 ; */ 615 /*description: */ 616 #define SYSTEM_UART_CLK_EN (BIT(2)) 617 #define SYSTEM_UART_CLK_EN_M (BIT(2)) 618 #define SYSTEM_UART_CLK_EN_V 0x1 619 #define SYSTEM_UART_CLK_EN_S 2 620 /* SYSTEM_SPI01_CLK_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */ 621 /*description: */ 622 #define SYSTEM_SPI01_CLK_EN (BIT(1)) 623 #define SYSTEM_SPI01_CLK_EN_M (BIT(1)) 624 #define SYSTEM_SPI01_CLK_EN_V 0x1 625 #define SYSTEM_SPI01_CLK_EN_S 1 626 /* SYSTEM_TIMERS_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ 627 /*description: */ 628 #define SYSTEM_TIMERS_CLK_EN (BIT(0)) 629 #define SYSTEM_TIMERS_CLK_EN_M (BIT(0)) 630 #define SYSTEM_TIMERS_CLK_EN_V 0x1 631 #define SYSTEM_TIMERS_CLK_EN_S 0 632 633 #define SYSTEM_PERIP_CLK_EN1_REG (DR_REG_CLKRST_BASE + 0x0024) 634 /* SYSTEM_PVT_CLK_EN : R/W ;bitpos:[15] ;default: 1'b1 ; */ 635 /*description: */ 636 #define SYSTEM_PVT_CLK_EN (BIT(15)) 637 #define SYSTEM_PVT_CLK_EN_M (BIT(15)) 638 #define SYSTEM_PVT_CLK_EN_V 0x1 639 #define SYSTEM_PVT_CLK_EN_S 15 640 /* SYSTEM_REGRET_CLK_EN : R/W ;bitpos:[14] ;default: 1'b0 ; */ 641 /*description: */ 642 #define SYSTEM_REGRET_CLK_EN (BIT(14)) 643 #define SYSTEM_REGRET_CLK_EN_M (BIT(14)) 644 #define SYSTEM_REGRET_CLK_EN_V 0x1 645 #define SYSTEM_REGRET_CLK_EN_S 14 646 /* SYSTEM_TIMERGROUP3_CLK_EN : R/W ;bitpos:[13] ;default: 1'b0 ; */ 647 /*description: */ 648 #define SYSTEM_TIMERGROUP3_CLK_EN (BIT(13)) 649 #define SYSTEM_TIMERGROUP3_CLK_EN_M (BIT(13)) 650 #define SYSTEM_TIMERGROUP3_CLK_EN_V 0x1 651 #define SYSTEM_TIMERGROUP3_CLK_EN_S 13 652 /* SYSTEM_ETM_CLK_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */ 653 /*description: */ 654 #define SYSTEM_ETM_CLK_EN (BIT(12)) 655 #define SYSTEM_ETM_CLK_EN_M (BIT(12)) 656 #define SYSTEM_ETM_CLK_EN_V 0x1 657 #define SYSTEM_ETM_CLK_EN_S 12 658 /* SYSTEM_TSENS_CLK_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */ 659 /*description: */ 660 #define SYSTEM_TSENS_CLK_EN (BIT(11)) 661 #define SYSTEM_TSENS_CLK_EN_M (BIT(11)) 662 #define SYSTEM_TSENS_CLK_EN_V 0x1 663 #define SYSTEM_TSENS_CLK_EN_S 11 664 /* SYSTEM_UART2_CLK_EN : R/W ;bitpos:[10] ;default: 1'b1 ; */ 665 /*description: */ 666 #define SYSTEM_UART2_CLK_EN (BIT(10)) 667 #define SYSTEM_UART2_CLK_EN_M (BIT(10)) 668 #define SYSTEM_UART2_CLK_EN_V 0x1 669 #define SYSTEM_UART2_CLK_EN_S 10 670 /* SYSTEM_LCD_CAM_CLK_EN : R/W ;bitpos:[9] ;default: 1'b0 ; */ 671 /*description: */ 672 #define SYSTEM_LCD_CAM_CLK_EN (BIT(9)) 673 #define SYSTEM_LCD_CAM_CLK_EN_M (BIT(9)) 674 #define SYSTEM_LCD_CAM_CLK_EN_V 0x1 675 #define SYSTEM_LCD_CAM_CLK_EN_S 9 676 /* SYSTEM_SDIO_HOST_CLK_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */ 677 /*description: */ 678 #define SYSTEM_SDIO_HOST_CLK_EN (BIT(8)) 679 #define SYSTEM_SDIO_HOST_CLK_EN_M (BIT(8)) 680 #define SYSTEM_SDIO_HOST_CLK_EN_V 0x1 681 #define SYSTEM_SDIO_HOST_CLK_EN_S 8 682 /* SYSTEM_DMA_CLK_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */ 683 /*description: */ 684 #define SYSTEM_DMA_CLK_EN (BIT(7)) 685 #define SYSTEM_DMA_CLK_EN_M (BIT(7)) 686 #define SYSTEM_DMA_CLK_EN_V 0x1 687 #define SYSTEM_DMA_CLK_EN_S 7 688 /* SYSTEM_CRYPTO_ECC_CLK_EN : R/W ;bitpos:[6] ;default: 1'b0 ; */ 689 /*description: */ 690 #define SYSTEM_CRYPTO_ECC_CLK_EN (BIT(6)) 691 #define SYSTEM_CRYPTO_ECC_CLK_EN_M (BIT(6)) 692 #define SYSTEM_CRYPTO_ECC_CLK_EN_V 0x1 693 #define SYSTEM_CRYPTO_ECC_CLK_EN_S 6 694 /* SYSTEM_CRYPTO_HMAC_CLK_EN : R/W ;bitpos:[5] ;default: 1'b0 ; */ 695 /*description: */ 696 #define SYSTEM_CRYPTO_HMAC_CLK_EN (BIT(5)) 697 #define SYSTEM_CRYPTO_HMAC_CLK_EN_M (BIT(5)) 698 #define SYSTEM_CRYPTO_HMAC_CLK_EN_V 0x1 699 #define SYSTEM_CRYPTO_HMAC_CLK_EN_S 5 700 /* SYSTEM_CRYPTO_DS_CLK_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */ 701 /*description: */ 702 #define SYSTEM_CRYPTO_DS_CLK_EN (BIT(4)) 703 #define SYSTEM_CRYPTO_DS_CLK_EN_M (BIT(4)) 704 #define SYSTEM_CRYPTO_DS_CLK_EN_V 0x1 705 #define SYSTEM_CRYPTO_DS_CLK_EN_S 4 706 /* SYSTEM_CRYPTO_RSA_CLK_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */ 707 /*description: */ 708 #define SYSTEM_CRYPTO_RSA_CLK_EN (BIT(3)) 709 #define SYSTEM_CRYPTO_RSA_CLK_EN_M (BIT(3)) 710 #define SYSTEM_CRYPTO_RSA_CLK_EN_V 0x1 711 #define SYSTEM_CRYPTO_RSA_CLK_EN_S 3 712 /* SYSTEM_CRYPTO_SHA_CLK_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */ 713 /*description: */ 714 #define SYSTEM_CRYPTO_SHA_CLK_EN (BIT(2)) 715 #define SYSTEM_CRYPTO_SHA_CLK_EN_M (BIT(2)) 716 #define SYSTEM_CRYPTO_SHA_CLK_EN_V 0x1 717 #define SYSTEM_CRYPTO_SHA_CLK_EN_S 2 718 /* SYSTEM_CRYPTO_AES_CLK_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */ 719 /*description: */ 720 #define SYSTEM_CRYPTO_AES_CLK_EN (BIT(1)) 721 #define SYSTEM_CRYPTO_AES_CLK_EN_M (BIT(1)) 722 #define SYSTEM_CRYPTO_AES_CLK_EN_V 0x1 723 #define SYSTEM_CRYPTO_AES_CLK_EN_S 1 724 /* SYSTEM_RETENTION_TOP_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ 725 /*description: */ 726 #define SYSTEM_RETENTION_TOP_CLK_EN (BIT(0)) 727 #define SYSTEM_RETENTION_TOP_CLK_EN_M (BIT(0)) 728 #define SYSTEM_RETENTION_TOP_CLK_EN_V 0x1 729 #define SYSTEM_RETENTION_TOP_CLK_EN_S 0 730 731 #define SYSTEM_PERIP_RST_EN0_REG (DR_REG_CLKRST_BASE + 0x0028) 732 /* SYSTEM_SPI4_RST : R/W ;bitpos:[31] ;default: 1'h0 ; */ 733 /*description: */ 734 #define SYSTEM_SPI4_RST (BIT(31)) 735 #define SYSTEM_SPI4_RST_M (BIT(31)) 736 #define SYSTEM_SPI4_RST_V 0x1 737 #define SYSTEM_SPI4_RST_S 31 738 /* SYSTEM_ADC2_ARB_RST : R/W ;bitpos:[30] ;default: 1'b0 ; */ 739 /*description: */ 740 #define SYSTEM_ADC2_ARB_RST (BIT(30)) 741 #define SYSTEM_ADC2_ARB_RST_M (BIT(30)) 742 #define SYSTEM_ADC2_ARB_RST_V 0x1 743 #define SYSTEM_ADC2_ARB_RST_S 30 744 /* SYSTEM_SYSTIMER_RST : R/W ;bitpos:[29] ;default: 1'b0 ; */ 745 /*description: */ 746 #define SYSTEM_SYSTIMER_RST (BIT(29)) 747 #define SYSTEM_SYSTIMER_RST_M (BIT(29)) 748 #define SYSTEM_SYSTIMER_RST_V 0x1 749 #define SYSTEM_SYSTIMER_RST_S 29 750 /* SYSTEM_APB_SARADC_RST : R/W ;bitpos:[28] ;default: 1'b0 ; */ 751 /*description: */ 752 #define SYSTEM_APB_SARADC_RST (BIT(28)) 753 #define SYSTEM_APB_SARADC_RST_M (BIT(28)) 754 #define SYSTEM_APB_SARADC_RST_V 0x1 755 #define SYSTEM_APB_SARADC_RST_S 28 756 /* SYSTEM_SPI3_DMA_RST : R/W ;bitpos:[27] ;default: 1'b0 ; */ 757 /*description: */ 758 #define SYSTEM_SPI3_DMA_RST (BIT(27)) 759 #define SYSTEM_SPI3_DMA_RST_M (BIT(27)) 760 #define SYSTEM_SPI3_DMA_RST_V 0x1 761 #define SYSTEM_SPI3_DMA_RST_S 27 762 /* SYSTEM_PWM3_RST : R/W ;bitpos:[26] ;default: 1'b0 ; */ 763 /*description: */ 764 #define SYSTEM_PWM3_RST (BIT(26)) 765 #define SYSTEM_PWM3_RST_M (BIT(26)) 766 #define SYSTEM_PWM3_RST_V 0x1 767 #define SYSTEM_PWM3_RST_S 26 768 /* SYSTEM_PWM2_RST : R/W ;bitpos:[25] ;default: 1'b0 ; */ 769 /*description: */ 770 #define SYSTEM_PWM2_RST (BIT(25)) 771 #define SYSTEM_PWM2_RST_M (BIT(25)) 772 #define SYSTEM_PWM2_RST_V 0x1 773 #define SYSTEM_PWM2_RST_S 25 774 /* SYSTEM_UART_MEM_RST : R/W ;bitpos:[24] ;default: 1'b0 ; */ 775 /*description: */ 776 #define SYSTEM_UART_MEM_RST (BIT(24)) 777 #define SYSTEM_UART_MEM_RST_M (BIT(24)) 778 #define SYSTEM_UART_MEM_RST_V 0x1 779 #define SYSTEM_UART_MEM_RST_S 24 780 /* SYSTEM_USB_DEVICE_RST : R/W ;bitpos:[23] ;default: 1'b0 ; */ 781 /*description: */ 782 #define SYSTEM_USB_DEVICE_RST (BIT(23)) 783 #define SYSTEM_USB_DEVICE_RST_M (BIT(23)) 784 #define SYSTEM_USB_DEVICE_RST_V 0x1 785 #define SYSTEM_USB_DEVICE_RST_S 23 786 /* SYSTEM_SPI2_DMA_RST : R/W ;bitpos:[22] ;default: 1'b0 ; */ 787 /*description: */ 788 #define SYSTEM_SPI2_DMA_RST (BIT(22)) 789 #define SYSTEM_SPI2_DMA_RST_M (BIT(22)) 790 #define SYSTEM_SPI2_DMA_RST_V 0x1 791 #define SYSTEM_SPI2_DMA_RST_S 22 792 /* SYSTEM_I2S1_RST : R/W ;bitpos:[21] ;default: 1'b0 ; */ 793 /*description: */ 794 #define SYSTEM_I2S1_RST (BIT(21)) 795 #define SYSTEM_I2S1_RST_M (BIT(21)) 796 #define SYSTEM_I2S1_RST_V 0x1 797 #define SYSTEM_I2S1_RST_S 21 798 /* SYSTEM_PWM1_RST : R/W ;bitpos:[20] ;default: 1'b0 ; */ 799 /*description: */ 800 #define SYSTEM_PWM1_RST (BIT(20)) 801 #define SYSTEM_PWM1_RST_M (BIT(20)) 802 #define SYSTEM_PWM1_RST_V 0x1 803 #define SYSTEM_PWM1_RST_S 20 804 /* SYSTEM_TWAI_RST : R/W ;bitpos:[19] ;default: 1'b0 ; */ 805 /*description: */ 806 #define SYSTEM_TWAI_RST (BIT(19)) 807 #define SYSTEM_TWAI_RST_M (BIT(19)) 808 #define SYSTEM_TWAI_RST_V 0x1 809 #define SYSTEM_TWAI_RST_S 19 810 /* SYSTEM_I2C_EXT1_RST : R/W ;bitpos:[18] ;default: 1'b0 ; */ 811 /*description: */ 812 #define SYSTEM_I2C_EXT1_RST (BIT(18)) 813 #define SYSTEM_I2C_EXT1_RST_M (BIT(18)) 814 #define SYSTEM_I2C_EXT1_RST_V 0x1 815 #define SYSTEM_I2C_EXT1_RST_S 18 816 /* SYSTEM_PWM0_RST : R/W ;bitpos:[17] ;default: 1'b0 ; */ 817 /*description: */ 818 #define SYSTEM_PWM0_RST (BIT(17)) 819 #define SYSTEM_PWM0_RST_M (BIT(17)) 820 #define SYSTEM_PWM0_RST_V 0x1 821 #define SYSTEM_PWM0_RST_S 17 822 /* SYSTEM_SPI3_RST : R/W ;bitpos:[16] ;default: 1'b0 ; */ 823 /*description: */ 824 #define SYSTEM_SPI3_RST (BIT(16)) 825 #define SYSTEM_SPI3_RST_M (BIT(16)) 826 #define SYSTEM_SPI3_RST_V 0x1 827 #define SYSTEM_SPI3_RST_S 16 828 /* SYSTEM_TIMERGROUP1_RST : R/W ;bitpos:[15] ;default: 1'b0 ; */ 829 /*description: */ 830 #define SYSTEM_TIMERGROUP1_RST (BIT(15)) 831 #define SYSTEM_TIMERGROUP1_RST_M (BIT(15)) 832 #define SYSTEM_TIMERGROUP1_RST_V 0x1 833 #define SYSTEM_TIMERGROUP1_RST_S 15 834 /* SYSTEM_EFUSE_RST : R/W ;bitpos:[14] ;default: 1'b0 ; */ 835 /*description: */ 836 #define SYSTEM_EFUSE_RST (BIT(14)) 837 #define SYSTEM_EFUSE_RST_M (BIT(14)) 838 #define SYSTEM_EFUSE_RST_V 0x1 839 #define SYSTEM_EFUSE_RST_S 14 840 /* SYSTEM_TIMERGROUP_RST : R/W ;bitpos:[13] ;default: 1'b0 ; */ 841 /*description: */ 842 #define SYSTEM_TIMERGROUP_RST (BIT(13)) 843 #define SYSTEM_TIMERGROUP_RST_M (BIT(13)) 844 #define SYSTEM_TIMERGROUP_RST_V 0x1 845 #define SYSTEM_TIMERGROUP_RST_S 13 846 /* SYSTEM_UHCI1_RST : R/W ;bitpos:[12] ;default: 1'b0 ; */ 847 /*description: */ 848 #define SYSTEM_UHCI1_RST (BIT(12)) 849 #define SYSTEM_UHCI1_RST_M (BIT(12)) 850 #define SYSTEM_UHCI1_RST_V 0x1 851 #define SYSTEM_UHCI1_RST_S 12 852 /* SYSTEM_LEDC_RST : R/W ;bitpos:[11] ;default: 1'b0 ; */ 853 /*description: */ 854 #define SYSTEM_LEDC_RST (BIT(11)) 855 #define SYSTEM_LEDC_RST_M (BIT(11)) 856 #define SYSTEM_LEDC_RST_V 0x1 857 #define SYSTEM_LEDC_RST_S 11 858 /* SYSTEM_PCNT_RST : R/W ;bitpos:[10] ;default: 1'b0 ; */ 859 /*description: */ 860 #define SYSTEM_PCNT_RST (BIT(10)) 861 #define SYSTEM_PCNT_RST_M (BIT(10)) 862 #define SYSTEM_PCNT_RST_V 0x1 863 #define SYSTEM_PCNT_RST_S 10 864 /* SYSTEM_RMT_RST : R/W ;bitpos:[9] ;default: 1'b0 ; */ 865 /*description: */ 866 #define SYSTEM_RMT_RST (BIT(9)) 867 #define SYSTEM_RMT_RST_M (BIT(9)) 868 #define SYSTEM_RMT_RST_V 0x1 869 #define SYSTEM_RMT_RST_S 9 870 /* SYSTEM_UHCI0_RST : R/W ;bitpos:[8] ;default: 1'b0 ; */ 871 /*description: */ 872 #define SYSTEM_UHCI0_RST (BIT(8)) 873 #define SYSTEM_UHCI0_RST_M (BIT(8)) 874 #define SYSTEM_UHCI0_RST_V 0x1 875 #define SYSTEM_UHCI0_RST_S 8 876 /* SYSTEM_I2C_EXT0_RST : R/W ;bitpos:[7] ;default: 1'b0 ; */ 877 /*description: */ 878 #define SYSTEM_I2C_EXT0_RST (BIT(7)) 879 #define SYSTEM_I2C_EXT0_RST_M (BIT(7)) 880 #define SYSTEM_I2C_EXT0_RST_V 0x1 881 #define SYSTEM_I2C_EXT0_RST_S 7 882 /* SYSTEM_SPI2_RST : R/W ;bitpos:[6] ;default: 1'b0 ; */ 883 /*description: */ 884 #define SYSTEM_SPI2_RST (BIT(6)) 885 #define SYSTEM_SPI2_RST_M (BIT(6)) 886 #define SYSTEM_SPI2_RST_V 0x1 887 #define SYSTEM_SPI2_RST_S 6 888 /* SYSTEM_UART1_RST : R/W ;bitpos:[5] ;default: 1'b0 ; */ 889 /*description: */ 890 #define SYSTEM_UART1_RST (BIT(5)) 891 #define SYSTEM_UART1_RST_M (BIT(5)) 892 #define SYSTEM_UART1_RST_V 0x1 893 #define SYSTEM_UART1_RST_S 5 894 /* SYSTEM_I2S0_RST : R/W ;bitpos:[4] ;default: 1'b0 ; */ 895 /*description: */ 896 #define SYSTEM_I2S0_RST (BIT(4)) 897 #define SYSTEM_I2S0_RST_M (BIT(4)) 898 #define SYSTEM_I2S0_RST_V 0x1 899 #define SYSTEM_I2S0_RST_S 4 900 /* SYSTEM_WDG_RST : R/W ;bitpos:[3] ;default: 1'b0 ; */ 901 /*description: */ 902 #define SYSTEM_WDG_RST (BIT(3)) 903 #define SYSTEM_WDG_RST_M (BIT(3)) 904 #define SYSTEM_WDG_RST_V 0x1 905 #define SYSTEM_WDG_RST_S 3 906 /* SYSTEM_UART_RST : R/W ;bitpos:[2] ;default: 1'b0 ; */ 907 /*description: */ 908 #define SYSTEM_UART_RST (BIT(2)) 909 #define SYSTEM_UART_RST_M (BIT(2)) 910 #define SYSTEM_UART_RST_V 0x1 911 #define SYSTEM_UART_RST_S 2 912 /* SYSTEM_SPI01_RST : R/W ;bitpos:[1] ;default: 1'b0 ; */ 913 /*description: */ 914 #define SYSTEM_SPI01_RST (BIT(1)) 915 #define SYSTEM_SPI01_RST_M (BIT(1)) 916 #define SYSTEM_SPI01_RST_V 0x1 917 #define SYSTEM_SPI01_RST_S 1 918 /* SYSTEM_TIMERS_RST : R/W ;bitpos:[0] ;default: 1'b0 ; */ 919 /*description: */ 920 #define SYSTEM_TIMERS_RST (BIT(0)) 921 #define SYSTEM_TIMERS_RST_M (BIT(0)) 922 #define SYSTEM_TIMERS_RST_V 0x1 923 #define SYSTEM_TIMERS_RST_S 0 924 925 #define SYSTEM_PERIP_RST_EN1_REG (DR_REG_CLKRST_BASE + 0x002C) 926 /* SYSTEM_PVT_RST : R/W ;bitpos:[15] ;default: 1'b0 ; */ 927 /*description: */ 928 #define SYSTEM_PVT_RST (BIT(15)) 929 #define SYSTEM_PVT_RST_M (BIT(15)) 930 #define SYSTEM_PVT_RST_V 0x1 931 #define SYSTEM_PVT_RST_S 15 932 /* SYSTEM_REGRET_RST : R/W ;bitpos:[14] ;default: 1'b0 ; */ 933 /*description: */ 934 #define SYSTEM_REGRET_RST (BIT(14)) 935 #define SYSTEM_REGRET_RST_M (BIT(14)) 936 #define SYSTEM_REGRET_RST_V 0x1 937 #define SYSTEM_REGRET_RST_S 14 938 /* SYSTEM_TIMERGROUP3_RST : R/W ;bitpos:[13] ;default: 1'b0 ; */ 939 /*description: */ 940 #define SYSTEM_TIMERGROUP3_RST (BIT(13)) 941 #define SYSTEM_TIMERGROUP3_RST_M (BIT(13)) 942 #define SYSTEM_TIMERGROUP3_RST_V 0x1 943 #define SYSTEM_TIMERGROUP3_RST_S 13 944 /* SYSTEM_ETM_RST : R/W ;bitpos:[12] ;default: 1'b0 ; */ 945 /*description: */ 946 #define SYSTEM_ETM_RST (BIT(12)) 947 #define SYSTEM_ETM_RST_M (BIT(12)) 948 #define SYSTEM_ETM_RST_V 0x1 949 #define SYSTEM_ETM_RST_S 12 950 /* SYSTEM_TSENS_RST : R/W ;bitpos:[11] ;default: 1'b0 ; */ 951 /*description: */ 952 #define SYSTEM_TSENS_RST (BIT(11)) 953 #define SYSTEM_TSENS_RST_M (BIT(11)) 954 #define SYSTEM_TSENS_RST_V 0x1 955 #define SYSTEM_TSENS_RST_S 11 956 /* SYSTEM_UART2_RST : R/W ;bitpos:[10] ;default: 1'b0 ; */ 957 /*description: */ 958 #define SYSTEM_UART2_RST (BIT(10)) 959 #define SYSTEM_UART2_RST_M (BIT(10)) 960 #define SYSTEM_UART2_RST_V 0x1 961 #define SYSTEM_UART2_RST_S 10 962 /* SYSTEM_LCD_CAM_RST : R/W ;bitpos:[9] ;default: 1'b1 ; */ 963 /*description: */ 964 #define SYSTEM_LCD_CAM_RST (BIT(9)) 965 #define SYSTEM_LCD_CAM_RST_M (BIT(9)) 966 #define SYSTEM_LCD_CAM_RST_V 0x1 967 #define SYSTEM_LCD_CAM_RST_S 9 968 /* SYSTEM_SDIO_HOST_RST : R/W ;bitpos:[8] ;default: 1'b1 ; */ 969 /*description: */ 970 #define SYSTEM_SDIO_HOST_RST (BIT(8)) 971 #define SYSTEM_SDIO_HOST_RST_M (BIT(8)) 972 #define SYSTEM_SDIO_HOST_RST_V 0x1 973 #define SYSTEM_SDIO_HOST_RST_S 8 974 /* SYSTEM_DMA_RST : R/W ;bitpos:[7] ;default: 1'b1 ; */ 975 /*description: */ 976 #define SYSTEM_DMA_RST (BIT(7)) 977 #define SYSTEM_DMA_RST_M (BIT(7)) 978 #define SYSTEM_DMA_RST_V 0x1 979 #define SYSTEM_DMA_RST_S 7 980 /* SYSTEM_CRYPTO_ECC_RST : R/W ;bitpos:[6] ;default: 1'b1 ; */ 981 /*description: */ 982 #define SYSTEM_CRYPTO_ECC_RST (BIT(6)) 983 #define SYSTEM_CRYPTO_ECC_RST_M (BIT(6)) 984 #define SYSTEM_CRYPTO_ECC_RST_V 0x1 985 #define SYSTEM_CRYPTO_ECC_RST_S 6 986 /* SYSTEM_CRYPTO_HMAC_RST : R/W ;bitpos:[5] ;default: 1'b1 ; */ 987 /*description: */ 988 #define SYSTEM_CRYPTO_HMAC_RST (BIT(5)) 989 #define SYSTEM_CRYPTO_HMAC_RST_M (BIT(5)) 990 #define SYSTEM_CRYPTO_HMAC_RST_V 0x1 991 #define SYSTEM_CRYPTO_HMAC_RST_S 5 992 /* SYSTEM_CRYPTO_DS_RST : R/W ;bitpos:[4] ;default: 1'b1 ; */ 993 /*description: */ 994 #define SYSTEM_CRYPTO_DS_RST (BIT(4)) 995 #define SYSTEM_CRYPTO_DS_RST_M (BIT(4)) 996 #define SYSTEM_CRYPTO_DS_RST_V 0x1 997 #define SYSTEM_CRYPTO_DS_RST_S 4 998 /* SYSTEM_CRYPTO_RSA_RST : R/W ;bitpos:[3] ;default: 1'b1 ; */ 999 /*description: */ 1000 #define SYSTEM_CRYPTO_RSA_RST (BIT(3)) 1001 #define SYSTEM_CRYPTO_RSA_RST_M (BIT(3)) 1002 #define SYSTEM_CRYPTO_RSA_RST_V 0x1 1003 #define SYSTEM_CRYPTO_RSA_RST_S 3 1004 /* SYSTEM_CRYPTO_SHA_RST : R/W ;bitpos:[2] ;default: 1'b1 ; */ 1005 /*description: */ 1006 #define SYSTEM_CRYPTO_SHA_RST (BIT(2)) 1007 #define SYSTEM_CRYPTO_SHA_RST_M (BIT(2)) 1008 #define SYSTEM_CRYPTO_SHA_RST_V 0x1 1009 #define SYSTEM_CRYPTO_SHA_RST_S 2 1010 /* SYSTEM_CRYPTO_AES_RST : R/W ;bitpos:[1] ;default: 1'b1 ; */ 1011 /*description: */ 1012 #define SYSTEM_CRYPTO_AES_RST (BIT(1)) 1013 #define SYSTEM_CRYPTO_AES_RST_M (BIT(1)) 1014 #define SYSTEM_CRYPTO_AES_RST_V 0x1 1015 #define SYSTEM_CRYPTO_AES_RST_S 1 1016 /* SYSTEM_RETENTION_TOP_RST : R/W ;bitpos:[0] ;default: 1'b0 ; */ 1017 /*description: */ 1018 #define SYSTEM_RETENTION_TOP_RST (BIT(0)) 1019 #define SYSTEM_RETENTION_TOP_RST_M (BIT(0)) 1020 #define SYSTEM_RETENTION_TOP_RST_V 0x1 1021 #define SYSTEM_RETENTION_TOP_RST_S 0 1022 1023 #define SYSTEM_FPGA_DBG_REG (DR_REG_CLKRST_BASE + 0x0030) 1024 /* SYSTEM_FPGA_DEBUG : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */ 1025 /*description: */ 1026 #define SYSTEM_FPGA_DEBUG 0xFFFFFFFF 1027 #define SYSTEM_FPGA_DEBUG_M ((SYSTEM_FPGA_DEBUG_V)<<(SYSTEM_FPGA_DEBUG_S)) 1028 #define SYSTEM_FPGA_DEBUG_V 0xFFFFFFFF 1029 #define SYSTEM_FPGA_DEBUG_S 0 1030 1031 #define SYSTEMCLK_CONF_REG (DR_REG_CLKRST_BASE + 0x0034) 1032 /* SYSTEM_CLK_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ 1033 /*description: */ 1034 #define SYSTEM_CLK_EN (BIT(0)) 1035 #define SYSTEM_CLK_EN_M (BIT(0)) 1036 #define SYSTEM_CLK_EN_V 0x1 1037 #define SYSTEM_CLK_EN_S 0 1038 1039 #define SYSTEM_CLKRST_DATE_REG (DR_REG_CLKRST_BASE + 0x038) 1040 /* SYSTEM_DATE : R/W ;bitpos:[27:0] ;default: 28'h2103191 ; */ 1041 /*description: */ 1042 #define CLKRST_DATE 0x0FFFFFFF 1043 #define CLKRST_DATE_M ((CLKRST_DATE_V)<<(CLKRST_DATE_S)) 1044 #define CLKRST_DATE_V 0xFFFFFFF 1045 #define CLKRST_DATE_S 0 1046 1047 #ifdef __cplusplus 1048 } 1049 #endif 1050 1051 #endif /*_SOC_CLKRST_REG_H_ */ 1052
