1 /*
2 * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 /*
8 Tests for the adc device driver on ESP32-S2 only
9 */
10 #include "sdkconfig.h"
11 #include "unity.h"
12 #include "test_utils.h"
13
14 #if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2) //TODO: IDF-3160
15 #if CONFIG_IDF_TARGET_ESP32S2
16
17
18 #include "esp_system.h"
19 #include "esp_intr_alloc.h"
20 #include "freertos/FreeRTOS.h"
21 #include "freertos/task.h"
22 #include "freertos/queue.h"
23 #include "driver/adc.h"
24 #include "driver/rtc_io.h"
25 #include "driver/gpio.h"
26 #include "unity.h"
27 #include "esp_system.h"
28 #include "esp_event.h"
29 #include "esp_wifi.h"
30 #include "esp_log.h"
31 #include "nvs_flash.h"
32 #include "test_utils.h"
33 #include "soc/adc_periph.h"
34 #include "test/test_common_adc.h"
35 #include "esp_rom_sys.h"
36 #include "driver/dac.h"
37
38 #include "soc/system_reg.h"
39 #include "soc/spi_reg.h"
40 #include "soc/soc.h"
41 #include "soc/lldesc.h"
42 #include "test/test_adc_dac_dma.h"
43
44 #include "driver/adc_deprecated.h"
45 #include "hal/adc_ll.h"
46 #include "esp_pm.h"
47
48 static const char *TAG = "test_adc";
49
50 #define PLATFORM_SELECT (1) //0: pxp; 1: chip
51 #if (PLATFORM_SELECT == 0) //PXP platform
52 #include "soc/syscon_reg.h"
53 #define SET_BREAK_POINT(flag) REG_WRITE(SYSCON_DATE_REG, flag)
54 //PXP clk is slower.
55 #define SYS_DELAY_TIME_MOM (1/40)
56 #define RTC_SLOW_CLK_FLAG 1 // Slow clock is 32KHz.
test_pxp_deinit_io(void)57 static void test_pxp_deinit_io(void)
58 {
59 for (int i = 0; i < 22; i++) {
60 rtc_gpio_init(i);
61 }
62 }
63 #else
64 //PXP clk is slower.
65 #define SET_BREAK_POINT(flag)
66 #define SYS_DELAY_TIME_MOM (1)
67 #define RTC_SLOW_CLK_FLAG 0 // Slow clock is 32KHz.
68 #endif
69
70 #define ADC_REG_BASE_TEST() ({ \
71 TEST_ASSERT_EQUAL_UINT32(REG_GET_FIELD(APB_SARADC_APB_CTRL_DATE_REG, APB_SARADC_APB_CTRL_DATE), APB_SARADC.apb_ctrl_date); \
72 TEST_ASSERT_EQUAL_UINT32(REG_GET_FIELD(SENS_SARDATE_REG, SENS_SAR_DATE), SENS.sardate.sar_date); \
73 TEST_ASSERT_EQUAL_UINT32(REG_GET_FIELD(RTC_IO_DATE_REG, RTC_IO_IO_DATE), RTCIO.date.date); \
74 })
75 /** Sample rate = APB_CLK(80 MHz) / (CLK_DIV + 1) / TRIGGER_INTERVAL / 2. */
76 #define TEST_ADC_TRIGGER_INTERVAL_DEFAULT (40)
77 #define TEST_ADC_DIGI_CLK_DIV_DEFAULT (9)
78 static uint8_t adc_test_num = 9;
79 static adc_channel_t adc_list[SOC_ADC_PATT_LEN_MAX] = {
80 ADC_CHANNEL_0,
81 ADC_CHANNEL_1,
82 ADC_CHANNEL_2,
83 ADC_CHANNEL_3,
84 ADC_CHANNEL_4,
85 ADC_CHANNEL_5,
86 ADC_CHANNEL_6,
87 // ADC_CHANNEL_7, // Workaround: IO18 is pullup outside in ESP32S2-Saola Runner.
88 ADC_CHANNEL_8,
89 ADC_CHANNEL_9,
90 };
91 /* For ESP32S2, it should use same atten, or, it will have error. */
92 #define TEST_ADC_ATTEN_DEFAULT (ADC_ATTEN_11db)
93
94
95 /* Work mode.
96 * single: eof_num;
97 * double: SAR_EOF_NUMBER/2;
98 * alter: eof_num;
99 * */
100 #define SAR_SIMPLE_NUM 512 // Set sample number of enabled unit.
101 /* Use two DMA linker to save ADC data. ADC sample 1 times -> 2 byte data -> 2 DMA link buf. */
102 #define SAR_DMA_DATA_SIZE(unit, sample_num) (SAR_EOF_NUMBER(unit, sample_num))
103 #define SAR_EOF_NUMBER(unit, sample_num) ((sample_num) * (unit))
104 #define SAR_MEAS_LIMIT_NUM(unit, sample_num) (SAR_SIMPLE_NUM)
105 #define SAR_SIMPLE_TIMEOUT_MS 1000
106
107 typedef struct dma_msg {
108 uint32_t int_msk;
109 uint8_t *data;
110 uint32_t data_len;
111 } adc_dma_event_t;
112
113 static uint8_t link_buf[2][SAR_DMA_DATA_SIZE(2, SAR_SIMPLE_NUM)] = {0};
114 static lldesc_t dma1 = {0};
115 static lldesc_t dma2 = {0};
116 static QueueHandle_t que_adc = NULL;
117 static adc_dma_event_t adc_evt;
118
119 /**
120 * @brief Reset FSM of adc digital controller.
121 *
122 * @return
123 * - ESP_OK Success
124 */
adc_digi_reset(void)125 static esp_err_t adc_digi_reset(void)
126 {
127 adc_ll_digi_reset();
128 adc_ll_digi_clear_pattern_table(ADC_NUM_1);
129 adc_ll_digi_clear_pattern_table(ADC_NUM_2);
130 return ESP_OK;
131 }
132
133 /** ADC-DMA ISR handler. */
adc_dma_isr(void * arg)134 static IRAM_ATTR void adc_dma_isr(void *arg)
135 {
136 uint32_t int_st = REG_READ(SPI_DMA_INT_ST_REG(3));
137 int task_awoken = pdFALSE;
138 REG_WRITE(SPI_DMA_INT_CLR_REG(3), int_st);
139 if (int_st & SPI_IN_SUC_EOF_INT_ST_M) {
140 adc_evt.int_msk = int_st;
141 xQueueSendFromISR(que_adc, &adc_evt, &task_awoken);
142 }
143 if (int_st & SPI_IN_DONE_INT_ST) {
144 adc_evt.int_msk = int_st;
145 xQueueSendFromISR(que_adc, &adc_evt, &task_awoken);
146 }
147 ESP_EARLY_LOGV(TAG, "int msk%x\n", int_st);
148 if (task_awoken == pdTRUE) {
149 portYIELD_FROM_ISR();
150 }
151 }
152
153 /**
154 * DMA liner initialization and start.
155 * @param is_loop
156 * - true: The two dma linked lists are connected end to end, with no end mark (eof).
157 * - false: The two dma linked lists are connected end to end, with end mark (eof).
158 */
adc_dma_linker_init(adc_unit_t adc,bool is_loop)159 static uint32_t adc_dma_linker_init(adc_unit_t adc, bool is_loop)
160 {
161 dma1 = (lldesc_t) {
162 .size = SAR_DMA_DATA_SIZE((adc > 2) ? 2 : 1, SAR_SIMPLE_NUM),
163 .owner = 1,
164 .buf = &link_buf[0][0],
165 .qe.stqe_next = &dma2,
166 };
167 dma2 = (lldesc_t) {
168 .size = SAR_DMA_DATA_SIZE((adc > 2) ? 2 : 1, SAR_SIMPLE_NUM),
169 .owner = 1,
170 .buf = &link_buf[1][0],
171 };
172 if (is_loop) {
173 dma2.qe.stqe_next = &dma1;
174 } else {
175 dma2.qe.stqe_next = NULL;
176 }
177 return (uint32_t)&dma1;
178 }
179
180 #define DEBUG_CHECK_ENABLE 1
181 #define DEBUG_PRINT_ENABLE 1
182 #define DEBUG_CHECK_ERROR 10
183
184 /**
185 * Check the ADC-DMA data in linker buffer by input level.
186 * ideal_level
187 * - -1: Don't check data.
188 * - 0: ADC channel voltage is 0v.
189 * - 1: ADC channel voltage is 3.3v.
190 * - 2: ADC channel voltage is 1.4v.
191 */
adc_dma_data_check(adc_unit_t adc,int ideal_level)192 static esp_err_t adc_dma_data_check(adc_unit_t adc, int ideal_level)
193 {
194 int unit_old = 1;
195 int ch_cnt = 0;
196 for (int cnt = 0; cnt < 2; cnt++) {
197 esp_rom_printf("\n[%s] link_buf[%d]: \n", __func__, cnt % 2);
198 for (int i = 0; i < SAR_DMA_DATA_SIZE((adc > 2) ? 2 : 1, SAR_SIMPLE_NUM); i += 2) {
199 uint8_t h = link_buf[cnt % 2][i + 1], l = link_buf[cnt % 2][i];
200 uint16_t temp = (h << 8 | l);
201 adc_digi_output_data_t *data = (adc_digi_output_data_t *)&temp;
202
203 if (adc > ADC_UNIT_2) { //ADC_ENCODE_11BIT
204 #if DEBUG_PRINT_ENABLE
205 if (i % 16 == 0) {
206 esp_rom_printf("\n");
207 }
208 esp_rom_printf("[%d_%d_%04x] ", data->type2.unit, data->type2.channel, data->type2.data);
209 #endif
210 #if DEBUG_CHECK_ENABLE
211 if (ideal_level >= 0) {
212 TEST_ASSERT_NOT_EQUAL(unit_old, data->type2.unit);
213 unit_old = data->type2.unit;
214 if (data->type2.channel > ADC_CHANNEL_MAX) {
215 printf("Data invalid [%d]\n", data->type2.channel);
216 continue;
217 }
218 int cur_ch = ((ch_cnt++ / 2) % adc_test_num);
219 TEST_ASSERT_EQUAL( data->type2.channel, adc_list[cur_ch] );
220 }
221 if (ideal_level == 1) { // high level 3.3v
222 TEST_ASSERT_EQUAL( 0x7FF, data->type2.data );
223 } else if (ideal_level == 0) { // low level 0v
224 TEST_ASSERT_LESS_THAN( 10, data->type2.data );
225 } else if (ideal_level == 2) { // middle level 1.4v
226 TEST_ASSERT_INT_WITHIN( 128, 1100, data->type2.data );
227 } else if (ideal_level == 3) { // normal level
228 } else { // no check
229 }
230 #endif
231 } else { //ADC_ENCODE_12BIT
232 #if DEBUG_PRINT_ENABLE
233 if (i % 16 == 0) {
234 esp_rom_printf("\n");
235 }
236 esp_rom_printf("[%d_%04x] ", data->type1.channel, data->type1.data);
237 #endif
238 #if DEBUG_CHECK_ENABLE
239 if (ideal_level >= 0) {
240 int cur_ch = ((ch_cnt++) % adc_test_num);
241 TEST_ASSERT_EQUAL( adc_list[cur_ch], data->type1.channel );
242 }
243 if (ideal_level == 1) { // high level 3.3v
244 TEST_ASSERT_EQUAL( 0XFFF, data->type1.data );
245 } else if (ideal_level == 0) { // low level 0v
246 TEST_ASSERT_LESS_THAN( 10, data->type1.data );
247 } else if (ideal_level == 2) { // middle level 1.4v
248 TEST_ASSERT_INT_WITHIN( 256, 2200, data->type1.data );
249 } else if (ideal_level == 3) { // normal level
250 } else { // no check
251 }
252 #endif
253 }
254 link_buf[cnt % 2][i] = 0;
255 link_buf[cnt % 2][i + 1] = 0;
256 }
257 esp_rom_printf("\n");
258 }
259 return ESP_OK;
260 }
261
adc_dma_data_multi_st_check(adc_unit_t adc,void * dma_addr,uint32_t int_mask)262 static esp_err_t adc_dma_data_multi_st_check(adc_unit_t adc, void *dma_addr, uint32_t int_mask)
263 {
264 adc_dma_event_t evt;
265
266 ESP_LOGI(TAG, "adc IO normal, test ...");
267 for (int i = 0; i < adc_test_num; i++) {
268 adc_io_normal(adc, adc_list[i]);
269 }
270 TEST_ESP_OK( adc_digi_start() );
271 while (1) {
272 TEST_ASSERT_EQUAL( xQueueReceive(que_adc, &evt, SAR_SIMPLE_TIMEOUT_MS / portTICK_RATE_MS), pdTRUE );
273 if (evt.int_msk & SPI_IN_SUC_EOF_INT_ENA) {
274 break;
275 }
276 }
277 TEST_ESP_OK( adc_digi_stop() );
278 adc_dac_dma_linker_start(DMA_ONLY_ADC_INLINK, (void *)dma_addr, int_mask);
279 adc_digi_reset();
280 TEST_ESP_OK( adc_dma_data_check(adc, -1) ); // Don't check data.
281
282 ESP_LOGI(TAG, "adc IO fake tie high, test ...");
283 for (int i = 0; i < adc_test_num; i++) {
284 adc_fake_tie_high(adc, adc_list[i]);
285 }
286 TEST_ESP_OK( adc_digi_start() );
287 while (1) {
288 TEST_ASSERT_EQUAL( xQueueReceive(que_adc, &evt, SAR_SIMPLE_TIMEOUT_MS / portTICK_RATE_MS), pdTRUE );
289 if (evt.int_msk & SPI_IN_SUC_EOF_INT_ENA) {
290 break;
291 }
292 }
293 TEST_ESP_OK( adc_digi_stop() );
294 adc_dac_dma_linker_start(DMA_ONLY_ADC_INLINK, (void *)dma_addr, int_mask);
295 adc_digi_reset();
296 TEST_ESP_OK( adc_dma_data_check(adc, 1) );
297
298 ESP_LOGI(TAG, "adc IO fake tie low, test ...");
299 for (int i = 0; i < adc_test_num; i++) {
300 adc_fake_tie_low(adc, adc_list[i]);
301 }
302 TEST_ESP_OK( adc_digi_start() );
303 while (1) {
304 TEST_ASSERT_EQUAL( xQueueReceive(que_adc, &evt, SAR_SIMPLE_TIMEOUT_MS / portTICK_RATE_MS), pdTRUE );
305 if (evt.int_msk & SPI_IN_SUC_EOF_INT_ENA) {
306 break;
307 }
308 }
309 TEST_ESP_OK( adc_digi_stop() );
310 adc_dac_dma_linker_start(DMA_ONLY_ADC_INLINK, (void *)dma_addr, int_mask);
311 adc_digi_reset();
312 TEST_ESP_OK( adc_dma_data_check(adc, 0) );
313
314 ESP_LOGI(TAG, "adc IO fake tie middle, test ...");
315 for (int i = 0; i < adc_test_num; i++) {
316 adc_fake_tie_middle(adc, adc_list[i]);
317 }
318 TEST_ESP_OK( adc_digi_start() );
319 while (1) {
320 TEST_ASSERT_EQUAL( xQueueReceive(que_adc, &evt, SAR_SIMPLE_TIMEOUT_MS / portTICK_RATE_MS), pdTRUE );
321 if (evt.int_msk & SPI_IN_SUC_EOF_INT_ENA) {
322 break;
323 }
324 }
325 TEST_ESP_OK( adc_digi_stop() );
326 adc_dac_dma_linker_start(DMA_ONLY_ADC_INLINK, (void *)dma_addr, int_mask);
327 adc_digi_reset();
328 TEST_ESP_OK( adc_dma_data_check(adc, 2) );
329
330 return ESP_OK;
331 }
332
333 #include "soc/apb_saradc_struct.h"
334 /**
335 * Test the partten table setting. It's easy wrong.
336 *
337 * @param adc_n ADC unit.
338 * @param in_partten_len The length of partten be set.
339 * @param in_last_ch The channel number of the last message.
340 */
adc_check_patt_table(adc_unit_t adc,uint32_t in_partten_len,adc_channel_t in_last_ch)341 static esp_err_t adc_check_patt_table(adc_unit_t adc, uint32_t in_partten_len, adc_channel_t in_last_ch)
342 {
343 esp_err_t ret = ESP_FAIL;
344 uint8_t index = (in_partten_len - 1) / 4;
345 uint8_t offset = 24 - ((in_partten_len - 1) % 4) * 8;
346 uint32_t temp = 0, len;
347
348 if (adc & ADC_UNIT_1) {
349 len = APB_SARADC.ctrl.sar1_patt_len + 1;
350 temp = APB_SARADC.sar1_patt_tab[index];
351 printf("patt1 len %d\n", len);
352 printf("patt1 0x%08x\n", APB_SARADC.sar1_patt_tab[0]);
353 printf("patt1 0x%08x\n", APB_SARADC.sar1_patt_tab[1]);
354 printf("patt1 0x%08x\n", APB_SARADC.sar1_patt_tab[2]);
355 printf("patt1 0x%08x\n", APB_SARADC.sar1_patt_tab[3]);
356 if (in_partten_len == len) {
357 if (in_last_ch == (((temp >> (offset + 4))) & 0xf)) {
358 ret = ESP_OK;
359 }
360 }
361 }
362 if (adc & ADC_UNIT_2) {
363 len = APB_SARADC.ctrl.sar2_patt_len + 1;
364 temp = APB_SARADC.sar2_patt_tab[index];
365 printf("patt2 len %d\n", len);
366 printf("patt2 0x%08x\n", APB_SARADC.sar2_patt_tab[0]);
367 printf("patt2 0x%08x\n", APB_SARADC.sar2_patt_tab[1]);
368 printf("patt2 0x%08x\n", APB_SARADC.sar2_patt_tab[2]);
369 printf("patt2 0x%08x\n", APB_SARADC.sar2_patt_tab[3]);
370 if (in_partten_len == len) {
371 if (in_last_ch == (((temp >> (offset + 4))) & 0xf)) {
372 ret = ESP_OK;
373 }
374 }
375 }
376 return ret;
377 }
378
379 /**
380 * Testcase: Check the base function of ADC-DMA. Include:
381 * - Various conversion modes.
382 * - Whether the channel and data are lost.
383 * - Whether the data is the same as the channel voltage.
384 */
test_adc_dig_dma_single_unit(adc_unit_t adc)385 int test_adc_dig_dma_single_unit(adc_unit_t adc)
386 {
387 ESP_LOGI(TAG, " >> %s << ", __func__);
388 ESP_LOGI(TAG, " >> adc unit: %x << ", adc);
389
390 TEST_ESP_OK( adc_digi_init() );
391 /* arbiter config */
392 adc_arbiter_t arb_cfg = {
393 .mode = ADC_ARB_MODE_FIX,
394 .dig_pri = 0,
395 .pwdet_pri = 2,
396 .rtc_pri = 1,
397 };
398 TEST_ESP_OK( adc_arbiter_config(ADC_UNIT_2, &arb_cfg) ); // If you want use force
399
400 adc_digi_config_t config = {
401 .conv_limit_en = false,
402 .conv_limit_num = 0,
403 .interval = TEST_ADC_TRIGGER_INTERVAL_DEFAULT,
404 .dig_clk.use_apll = 0, // APB clk
405 .dig_clk.div_num = TEST_ADC_DIGI_CLK_DIV_DEFAULT,
406 .dig_clk.div_b = 0,
407 .dig_clk.div_a = 0,
408 .dma_eof_num = SAR_EOF_NUMBER((adc > 2) ? 2 : 1, SAR_SIMPLE_NUM),
409 };
410 /* Config pattern table */
411 adc_digi_pattern_table_t adc1_patt[SOC_ADC_PATT_LEN_MAX] = {0};
412 adc_digi_pattern_table_t adc2_patt[SOC_ADC_PATT_LEN_MAX] = {0};
413 if (adc & ADC_UNIT_1) {
414 config.adc1_pattern_len = adc_test_num;
415 config.adc1_pattern = adc1_patt;
416 for (int i = 0; i < adc_test_num; i++) {
417 adc1_patt[i].atten = TEST_ADC_ATTEN_DEFAULT;
418 adc1_patt[i].channel = adc_list[i];
419 adc_gpio_init(ADC_UNIT_1, adc_list[i]);
420 }
421 }
422 if (adc & ADC_UNIT_2) {
423 config.adc2_pattern_len = adc_test_num;
424 config.adc2_pattern = adc2_patt;
425 for (int i = 0; i < adc_test_num; i++) {
426 adc2_patt[i].atten = TEST_ADC_ATTEN_DEFAULT;
427 adc2_patt[i].channel = adc_list[i];
428 adc_gpio_init(ADC_UNIT_2, adc_list[i]);
429 }
430 }
431 if (adc == ADC_UNIT_1) {
432 config.conv_mode = ADC_CONV_SINGLE_UNIT_1;
433 config.format = ADC_DIGI_FORMAT_12BIT;
434 } else if (adc == ADC_UNIT_2) {
435 config.conv_mode = ADC_CONV_SINGLE_UNIT_2;
436 config.format = ADC_DIGI_FORMAT_12BIT;
437 } else if (adc == ADC_UNIT_BOTH) {
438 config.conv_mode = ADC_CONV_BOTH_UNIT;
439 config.format = ADC_DIGI_FORMAT_11BIT;
440 } else if (adc == ADC_UNIT_ALTER) {
441 config.conv_mode = ADC_CONV_ALTER_UNIT;
442 config.format = ADC_DIGI_FORMAT_11BIT;
443 }
444 TEST_ESP_OK( adc_digi_controller_config(&config) );
445
446 /* ADC-DMA linker init */
447 if (que_adc == NULL) {
448 que_adc = xQueueCreate(5, sizeof(adc_dma_event_t));
449 } else {
450 xQueueReset(que_adc);
451 }
452 uint32_t int_mask = SPI_IN_SUC_EOF_INT_ENA;
453 uint32_t dma_addr = adc_dma_linker_init(adc, false);
454 adc_dac_dma_isr_register(adc_dma_isr, NULL, int_mask);
455 adc_dac_dma_linker_start(DMA_ONLY_ADC_INLINK, (void *)dma_addr, int_mask);
456
457 TEST_ESP_OK( adc_check_patt_table(adc, adc_test_num, adc_list[adc_test_num - 1]) );
458 adc_dma_data_multi_st_check(adc, (void *)dma_addr, int_mask);
459
460 adc_dac_dma_linker_deinit();
461 adc_dac_dma_isr_deregister(adc_dma_isr, NULL);
462 TEST_ESP_OK( adc_digi_deinit() );
463 vTaskDelay(10 / portTICK_RATE_MS);
464
465 return 0;
466 }
467
468 TEST_CASE("ADC DMA single read", "[ADC]")
469 {
470 test_adc_dig_dma_single_unit(ADC_UNIT_BOTH);
471
472 test_adc_dig_dma_single_unit(ADC_UNIT_ALTER);
473
474 test_adc_dig_dma_single_unit(ADC_UNIT_1);
475
476 test_adc_dig_dma_single_unit(ADC_UNIT_2);
477 }
478
479 #include "touch_scope.h"
480 /**
481 * 0: ADC1 channels raw data debug.
482 * 1: ADC2 channels raw data debug.
483 * 2: ADC1 one channel raw data debug.
484 */
485 #define SCOPE_DEBUG_TYPE 0
486 #define SCOPE_DEBUG_CHANNEL_MAX (10)
487 #define SCOPE_DEBUG_ENABLE (0)
488 #define SCOPE_UART_BUADRATE (256000)
489 #define SCOPE_DEBUG_FREQ_MS (50)
490 #define SCOPE_OUTPUT_UART (0)
491 static float scope_temp[SCOPE_DEBUG_CHANNEL_MAX] = {0}; // max scope channel is 10.
492
test_adc_dig_scope_debug_unit(adc_unit_t adc)493 int test_adc_dig_scope_debug_unit(adc_unit_t adc)
494 {
495 ESP_LOGI(TAG, " >> %s << ", __func__);
496 ESP_LOGI(TAG, " >> adc unit: %x << ", adc);
497
498 TEST_ESP_OK( adc_digi_init() );
499 if (adc & ADC_UNIT_2) {
500 /* arbiter config */
501 adc_arbiter_t arb_cfg = {
502 .mode = ADC_ARB_MODE_FIX,
503 .dig_pri = 0,
504 .pwdet_pri = 2,
505 .rtc_pri = 1,
506 };
507 TEST_ESP_OK( adc_arbiter_config(ADC_UNIT_2, &arb_cfg) ); // If you want use force
508 }
509 adc_digi_config_t config = {
510 .conv_limit_en = false,
511 .conv_limit_num = 0,
512 .interval = TEST_ADC_TRIGGER_INTERVAL_DEFAULT,
513 .dig_clk.use_apll = 0, // APB clk
514 .dig_clk.div_num = TEST_ADC_DIGI_CLK_DIV_DEFAULT,
515 .dig_clk.div_a = 0,
516 .dig_clk.div_b = 0,
517 .dma_eof_num = SAR_EOF_NUMBER((adc > 2) ? 2 : 1, SAR_SIMPLE_NUM),
518 };
519 /* Config pattern table */
520 adc_digi_pattern_table_t adc1_patt[SOC_ADC_PATT_LEN_MAX] = {0};
521 adc_digi_pattern_table_t adc2_patt[SOC_ADC_PATT_LEN_MAX] = {0};
522 if (adc & ADC_UNIT_1) {
523 config.adc1_pattern_len = adc_test_num;
524 config.adc1_pattern = adc1_patt;
525 for (int i = 0; i < adc_test_num; i++) {
526 adc1_patt[i].atten = TEST_ADC_ATTEN_DEFAULT;
527 adc1_patt[i].channel = adc_list[i];
528 adc_gpio_init(ADC_UNIT_1, adc_list[i]);
529 }
530 }
531 if (adc & ADC_UNIT_2) {
532 config.adc2_pattern_len = adc_test_num;
533 config.adc2_pattern = adc2_patt;
534 for (int i = 0; i < adc_test_num; i++) {
535 adc2_patt[i].atten = TEST_ADC_ATTEN_DEFAULT;
536 adc2_patt[i].channel = adc_list[i];
537 adc_gpio_init(ADC_UNIT_2, adc_list[i]);
538 }
539 }
540 if (adc == ADC_UNIT_1) {
541 config.conv_mode = ADC_CONV_SINGLE_UNIT_1;
542 config.format = ADC_DIGI_FORMAT_12BIT;
543 } else if (adc == ADC_UNIT_2) {
544 config.conv_mode = ADC_CONV_SINGLE_UNIT_2;
545 config.format = ADC_DIGI_FORMAT_12BIT;
546 } else if (adc == ADC_UNIT_BOTH) {
547 config.conv_mode = ADC_CONV_BOTH_UNIT;
548 config.format = ADC_DIGI_FORMAT_11BIT;
549 } else if (adc == ADC_UNIT_ALTER) {
550 config.conv_mode = ADC_CONV_ALTER_UNIT;
551 config.format = ADC_DIGI_FORMAT_11BIT;
552 }
553 TEST_ESP_OK( adc_digi_controller_config(&config) );
554
555 /* ADC-DMA linker init */
556 if (que_adc == NULL) {
557 que_adc = xQueueCreate(5, sizeof(adc_dma_event_t));
558 } else {
559 xQueueReset(que_adc);
560 }
561 uint32_t int_mask = SPI_IN_SUC_EOF_INT_ENA;
562 uint32_t dma_addr = adc_dma_linker_init(adc, false);
563 adc_dac_dma_isr_register(adc_dma_isr, NULL, int_mask);
564 adc_dac_dma_linker_start(DMA_ONLY_ADC_INLINK, (void *)dma_addr, int_mask);
565
566 ESP_LOGI(TAG, "adc IO fake tie middle, test ...");
567 for (int i = 0; i < adc_test_num; i++) {
568 adc_fake_tie_middle(adc, adc_list[i]);
569 }
570
571 return 0;
572 }
573
scope_output(int adc_num,int channel,int data)574 static void scope_output(int adc_num, int channel, int data)
575 {
576 /** can replace by uart log.*/
577 #if SCOPE_OUTPUT_UART
578 static int icnt = 0;
579 if (icnt++ % 8 == 0) {
580 esp_rom_printf("\n");
581 }
582 esp_rom_printf("[%d_%d_%04x] ", adc_num, channel, data);
583 return;
584 #endif
585 #if SCOPE_DEBUG_TYPE == 0
586 if (adc_num != 0) {
587 return;
588 }
589 #elif SCOPE_DEBUG_TYPE == 1
590 if (adc_num != 1) {
591 return;
592 }
593 #endif
594 int i;
595 /* adc Read */
596 for (i = 0; i < adc_test_num; i++) {
597 if (adc_list[i] == channel && scope_temp[i] == 0) {
598 scope_temp[i] = data;
599 break;
600 }
601 }
602 if (i == adc_test_num) {
603 test_tp_print_to_scope(scope_temp, adc_test_num);
604 vTaskDelay(SCOPE_DEBUG_FREQ_MS / portTICK_RATE_MS);
605 for (int i = 0; i < adc_test_num; i++) {
606 scope_temp[i] = 0;
607 }
608 }
609 }
610
611 /**
612 * Manual test: Capture ADC-DMA data and display it on the serial oscilloscope. Used to observe the stability of the data.
613 * Use step:
614 * 1. Run this test from the unit test app.
615 * 2. Use `ESP-Tuning Tool`(download from `www.espressif.com`) to capture.
616 * 3. The readings of multiple channels will be displayed on the tool.
617 */
618 TEST_CASE("test_adc_digi_slope_debug", "[adc_dma][ignore]")
619 {
620 adc_dma_event_t evt;
621 test_tp_scope_debug_init(0, -1, -1, SCOPE_UART_BUADRATE);
622 adc_unit_t adc = ADC_CONV_BOTH_UNIT;
623 test_adc_dig_scope_debug_unit(adc);
624 while (1) {
625 TEST_ESP_OK( adc_digi_start() );
626 TEST_ASSERT_EQUAL( xQueueReceive(que_adc, &evt, portMAX_DELAY), pdTRUE );
627 if (evt.int_msk & SPI_IN_SUC_EOF_INT_ST) {
628 TEST_ESP_OK( adc_digi_stop() );
629 adc_digi_reset();
630 for (int cnt = 0; cnt < 2; cnt++) {
631 esp_rom_printf("cnt%d\n", cnt);
632 for (int i = 0; i < SAR_DMA_DATA_SIZE((adc > 2) ? 2 : 1, SAR_SIMPLE_NUM); i += 2) {
633 uint8_t h = link_buf[cnt % 2][i + 1], l = link_buf[cnt % 2][i];
634 uint16_t temp = (h << 8 | l);
635 adc_digi_output_data_t *data = (adc_digi_output_data_t *)&temp;
636 if (adc > ADC_UNIT_2) { //ADC_ENCODE_11BIT
637 scope_output(data->type2.unit, data->type2.channel, data->type2.data);
638 } else { //ADC_ENCODE_12BIT
639 if (adc == ADC_UNIT_1) {
640 scope_output(0, data->type1.channel, data->type1.data);
641 } else if (adc == ADC_UNIT_2) {
642 scope_output(1, data->type1.channel, data->type1.data);
643 }
644 }
645 link_buf[cnt % 2][i] = 0;
646 link_buf[cnt % 2][i + 1] = 0;
647 }
648 }
649 }
650 }
651 }
652
653 #endif // CONFIG_IDF_TARGET_ESP32S2
654 #endif //#if !DISABLED_FOR_TARGETS(ESP32S2)
655
