1 /*
2 * SPDX-FileCopyrightText: 2019-2021 Espressif Systems (Shanghai) CO LTD
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #include <string.h>
8 #include <stdlib.h>
9 #include <sys/cdefs.h>
10 #include "esp_log.h"
11 #include "esp_check.h"
12 #include "esp_eth.h"
13 #include "eth_phy_regs_struct.h"
14 #include "freertos/FreeRTOS.h"
15 #include "freertos/task.h"
16 #include "driver/gpio.h"
17 #include "esp_rom_gpio.h"
18 #include "esp_rom_sys.h"
19
20 static const char *TAG = "lan87xx";
21
22 /***************List of Supported Models***************/
23
24 // See Microchip's Application Note AN25.3 summarizing differences among below models
25 #define LAN8710A_MODEL_NUM 0x0F
26 #define LAN8720A_MODEL_NUM 0x0F
27 #define LAN8740A_MODEL_NUM 0x11
28 #define LAN8741A_MODEL_NUM 0x12
29 #define LAN8742A_MODEL_NUM 0x13
30
31 static const uint8_t supported_models[] = {
32 LAN8710A_MODEL_NUM,
33 #if (LAN8710A_MODEL_NUM != LAN8720A_MODEL_NUM)
34 LAN8720A_MODEL_NUM,
35 #endif
36 LAN8740A_MODEL_NUM,
37 LAN8741A_MODEL_NUM,
38 LAN8742A_MODEL_NUM
39 };
40
41 /***************Vendor Specific Register***************/
42
43 /**
44 * @brief MCSR(Mode Control Status Register)
45 *
46 */
47 typedef union {
48 struct {
49 uint32_t reserved1 : 1; /* Reserved */
50 uint32_t energy_is_on : 1; /* Energy is On */
51 uint32_t reserved2 : 4; /* Reserved */
52 uint32_t en_alternate_interrupt : 1; /* Enable Alternate Interrupt Mode */
53 uint32_t reserved3 : 2; /* Reserved */
54 uint32_t en_far_loopback : 1; /* Enable Far Loopback Mode */
55 uint32_t reserved4 : 3; /* Reserved */
56 uint32_t en_energy_detect_powerdown : 1; /* Enable Energy Detect Power Down */
57 uint32_t reserved5 : 2; /* Reserved */
58 };
59 uint32_t val;
60 } mcsr_reg_t;
61 #define ETH_PHY_MCSR_REG_ADDR (0x11)
62
63 /**
64 * @brief SMR(Special Modes Register)
65 *
66 */
67 typedef union {
68 struct {
69 uint32_t phy_addr : 5; /* PHY Address */
70 uint32_t mode : 3; /* Transceiver Mode of Operation */
71 uint32_t reserved_1 : 6; /* Reserved */
72 uint32_t mii_mode : 1; /* Mode of the digital interface (only LAN8710A/LAN8740A/LAN8741A) */
73 uint32_t reserved_2 : 1; /* Reserved */
74 };
75 uint32_t val;
76 } smr_reg_t;
77 #define ETH_PHY_SMR_REG_ADDR (0x12)
78
79 /**
80 * @brief Time Domain Reflectometry Patterns/Delay Control Register
81 * Only available in LAN8740A/LAN8742A
82 */
83 typedef union {
84 struct {
85 uint32_t tdr_pattern_low : 6; /* Data pattern sent in TDR mode for the low cycle */
86 uint32_t tdr_pattern_high : 6; /* Data pattern sent in TDR mode for the high cycle */
87 uint32_t tdr_line_break_counter : 3; /* Increments of 256ms of break time */
88 uint32_t tdr_delay_in : 1; /* Line break counter used */
89 };
90 uint32_t val;
91 } tdr_pattern_reg_t;
92 #define EHT_PHY_TDRPD_REG_ADDR (0x18)
93
94 /**
95 * @brief Time Domain Reflectometry Control/Status Register)
96 * Only available in LAN8740A/LAN8742A
97 */
98 typedef union {
99 struct {
100 uint32_t tdr_channel_length : 8; /* TDR channel length */
101 uint32_t tdr_channel_status : 1; /* TDR channel status */
102 uint32_t tdr_channel_cable_type : 2; /* TDR channel cable type */
103 uint32_t reserved : 3; /* Reserved */
104 uint32_t tdr_a2d_filter_enable: 1; /* Analog to Digital Filter Enabled */
105 uint32_t tdr_enable : 1; /* Enable TDR */
106 };
107 uint32_t val;
108 } tdr_control_reg_t;
109 #define EHT_PHY_TDRC_REG_ADDR (0x19)
110
111 /**
112 * @brief SECR(Symbol Error Counter Register)
113 *
114 */
115 typedef union {
116 struct {
117 uint32_t symbol_err_count : 16; /* Symbol Error Counter */
118 };
119 uint32_t val;
120 } secr_reg_t;
121 #define EHT_PHY_SECR_REG_ADDR (0x1A)
122
123 /**
124 * @brief CSIR(Control Status Indications Register)
125 *
126 */
127 typedef union {
128 struct {
129 uint32_t reserved1 : 4; /* Reserved */
130 uint32_t base10_t_polarity : 1; /* Polarity State of 10Base-T */
131 uint32_t reserved2 : 6; /* Reserved */
132 uint32_t dis_sqe : 1; /* Disable SQE test(Heartbeat) */
133 uint32_t reserved3 : 1; /* Reserved */
134 uint32_t select_channel : 1; /* Manual channel select:MDI(0) or MDIX(1) */
135 uint32_t reserved4 : 1; /* Reserved */
136 uint32_t auto_mdix_ctrl : 1; /* Auto-MDIX Control: EN(0) or DE(1) */
137 };
138 uint32_t val;
139 } scsir_reg_t;
140 #define ETH_PHY_CSIR_REG_ADDR (0x1B)
141
142 /**
143 * @brief Cable Length Register
144 * Only available in LAN8740A/LAN8742A
145 */
146 typedef union {
147 struct {
148 uint32_t reserved : 12; /* Reserved */
149 uint32_t cable_length : 4; /* Cable length */
150 };
151 uint32_t val;
152 } cbln_reg_t;
153 #define EHT_PHY_CBLN_REG_ADDR (0x1C)
154
155 /**
156 * @brief ISR(Interrupt Source Register)
157 *
158 */
159 typedef union {
160 struct {
161 uint32_t reserved1 : 1; /* Reserved */
162 uint32_t auto_nego_page_received : 1; /* Auto-Negotiation Page Received */
163 uint32_t parallel_detect_fault : 1; /* Parallel Detection Fault */
164 uint32_t auto_nego_lp_acknowledge : 1; /* Auto-Negotiation LP Acknowledge */
165 uint32_t link_down : 1; /* Link Down */
166 uint32_t remote_fault_detect : 1; /* Remote Fault Detect */
167 uint32_t auto_nego_complete : 1; /* Auto-Negotiation Complete */
168 uint32_t energy_on_generate : 1; /* ENERGY ON generated */
169 uint32_t wake_on_lan : 1; /* Wake on Lan (WOL) event detected (only LAN8740A/LAN8742A) */
170 uint32_t reserved2 : 7; /* Reserved */
171 };
172 uint32_t val;
173 } isfr_reg_t;
174 #define ETH_PHY_ISR_REG_ADDR (0x1D)
175
176 /**
177 * @brief IMR(Interrupt Mask Register)
178 *
179 */
180 typedef union {
181 struct {
182 uint32_t reserved1 : 1; /* Reserved */
183 uint32_t auto_nego_page_received : 1; /* Auto-Negotiation Page Received */
184 uint32_t parallel_detect_fault : 1; /* Parallel Detection Fault */
185 uint32_t auto_nego_lp_acknowledge : 1; /* Auto-Negotiation LP Acknowledge */
186 uint32_t link_down : 1; /* Link Down */
187 uint32_t remote_fault_detect : 1; /* Remote Fault Detect */
188 uint32_t auto_nego_complete : 1; /* Auto-Negotiation Complete */
189 uint32_t energy_on_generate : 1; /* ENERGY ON generated */
190 uint32_t wake_on_lan : 1; /* Wake on Lan (WOL) event detected (only LAN8740A/LAN8742A) */
191 uint32_t reserved2 : 7; /* Reserved */
192 };
193 uint32_t val;
194 } imr_reg_t;
195 #define ETH_PHY_IMR_REG_ADDR (0x1E)
196
197 /**
198 * @brief PSCSR(PHY Special Control Status Register)
199 *
200 */
201 typedef union {
202 struct {
203 uint32_t reserved1 : 2; /* Reserved */
204 uint32_t speed_indication : 3; /* Speed Indication */
205 uint32_t reserved2 : 1; /* Reserved */
206 uint32_t enable_4b5b : 1; /* Enable 4B5B encoder (only LAN8740A/LAN8741A) */
207 uint32_t reserved3 : 5; /* Reserved */
208 uint32_t auto_nego_done : 1; /* Auto Negotiation Done */
209 uint32_t reserved4 : 3; /* Reserved */
210 };
211 uint32_t val;
212 } pscsr_reg_t;
213 #define ETH_PHY_PSCSR_REG_ADDR (0x1F)
214
215 typedef struct {
216 esp_eth_phy_t parent;
217 esp_eth_mediator_t *eth;
218 int addr;
219 uint32_t reset_timeout_ms;
220 uint32_t autonego_timeout_ms;
221 eth_link_t link_status;
222 int reset_gpio_num;
223 } phy_lan87xx_t;
224
lan87xx_update_link_duplex_speed(phy_lan87xx_t * lan87xx)225 static esp_err_t lan87xx_update_link_duplex_speed(phy_lan87xx_t *lan87xx)
226 {
227 esp_err_t ret = ESP_OK;
228 esp_eth_mediator_t *eth = lan87xx->eth;
229 eth_speed_t speed = ETH_SPEED_10M;
230 eth_duplex_t duplex = ETH_DUPLEX_HALF;
231 bmsr_reg_t bmsr;
232 pscsr_reg_t pscsr;
233 uint32_t peer_pause_ability = false;
234 anlpar_reg_t anlpar;
235 ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, lan87xx->addr, ETH_PHY_ANLPAR_REG_ADDR, &(anlpar.val)), err, TAG, "read ANLPAR failed");
236 ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, lan87xx->addr, ETH_PHY_BMSR_REG_ADDR, &(bmsr.val)), err, TAG, "read BMSR failed");
237 eth_link_t link = bmsr.link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
238 /* check if link status changed */
239 if (lan87xx->link_status != link) {
240 /* when link up, read negotiation result */
241 if (link == ETH_LINK_UP) {
242 ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, lan87xx->addr, ETH_PHY_PSCSR_REG_ADDR, &(pscsr.val)), err, TAG, "read PSCSR failed");
243 switch (pscsr.speed_indication) {
244 case 1: //10Base-T half-duplex
245 speed = ETH_SPEED_10M;
246 duplex = ETH_DUPLEX_HALF;
247 break;
248 case 2: //100Base-TX half-duplex
249 speed = ETH_SPEED_100M;
250 duplex = ETH_DUPLEX_HALF;
251 break;
252 case 5: //10Base-T full-duplex
253 speed = ETH_SPEED_10M;
254 duplex = ETH_DUPLEX_FULL;
255 break;
256 case 6: //100Base-TX full-duplex
257 speed = ETH_SPEED_100M;
258 duplex = ETH_DUPLEX_FULL;
259 break;
260 default:
261 break;
262 }
263 ESP_GOTO_ON_ERROR(eth->on_state_changed(eth, ETH_STATE_SPEED, (void *)speed), err, TAG, "change speed failed");
264 ESP_GOTO_ON_ERROR(eth->on_state_changed(eth, ETH_STATE_DUPLEX, (void *)duplex), err, TAG, "change duplex failed");
265 /* if we're in duplex mode, and peer has the flow control ability */
266 if (duplex == ETH_DUPLEX_FULL && anlpar.symmetric_pause) {
267 peer_pause_ability = 1;
268 } else {
269 peer_pause_ability = 0;
270 }
271 ESP_GOTO_ON_ERROR(eth->on_state_changed(eth, ETH_STATE_PAUSE, (void *)peer_pause_ability), err, TAG, "change pause ability failed");
272 }
273 ESP_GOTO_ON_ERROR(eth->on_state_changed(eth, ETH_STATE_LINK, (void *)link), err, TAG, "change link failed");
274 lan87xx->link_status = link;
275 }
276 return ESP_OK;
277 err:
278 return ret;
279 }
280
lan87xx_set_mediator(esp_eth_phy_t * phy,esp_eth_mediator_t * eth)281 static esp_err_t lan87xx_set_mediator(esp_eth_phy_t *phy, esp_eth_mediator_t *eth)
282 {
283 esp_err_t ret = ESP_OK;
284 ESP_GOTO_ON_FALSE(eth, ESP_ERR_INVALID_ARG, err, TAG, "can't set mediator to null");
285 phy_lan87xx_t *lan87xx = __containerof(phy, phy_lan87xx_t, parent);
286 lan87xx->eth = eth;
287 return ESP_OK;
288 err:
289 return ret;
290 }
291
lan87xx_get_link(esp_eth_phy_t * phy)292 static esp_err_t lan87xx_get_link(esp_eth_phy_t *phy)
293 {
294 esp_err_t ret = ESP_OK;
295 phy_lan87xx_t *lan87xx = __containerof(phy, phy_lan87xx_t, parent);
296 /* Updata information about link, speed, duplex */
297 ESP_GOTO_ON_ERROR(lan87xx_update_link_duplex_speed(lan87xx), err, TAG, "update link duplex speed failed");
298 return ESP_OK;
299 err:
300 return ret;
301 }
302
lan87xx_reset(esp_eth_phy_t * phy)303 static esp_err_t lan87xx_reset(esp_eth_phy_t *phy)
304 {
305 esp_err_t ret = ESP_OK;
306 phy_lan87xx_t *lan87xx = __containerof(phy, phy_lan87xx_t, parent);
307 lan87xx->link_status = ETH_LINK_DOWN;
308 esp_eth_mediator_t *eth = lan87xx->eth;
309 bmcr_reg_t bmcr = {.reset = 1};
310 ESP_GOTO_ON_ERROR(eth->phy_reg_write(eth, lan87xx->addr, ETH_PHY_BMCR_REG_ADDR, bmcr.val), err, TAG, "write BMCR failed");
311 /* wait for reset complete */
312 uint32_t to = 0;
313 for (to = 0; to < lan87xx->reset_timeout_ms / 10; to++) {
314 vTaskDelay(pdMS_TO_TICKS(10));
315 ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, lan87xx->addr, ETH_PHY_BMCR_REG_ADDR, &(bmcr.val)), err, TAG, "read BMCR failed");
316 if (!bmcr.reset) {
317 break;
318 }
319 }
320 ESP_GOTO_ON_FALSE(to < lan87xx->reset_timeout_ms / 10, ESP_FAIL, err, TAG, "reset timeout");
321 return ESP_OK;
322 err:
323 return ret;
324 }
325
lan87xx_reset_hw(esp_eth_phy_t * phy)326 static esp_err_t lan87xx_reset_hw(esp_eth_phy_t *phy)
327 {
328 phy_lan87xx_t *lan87xx = __containerof(phy, phy_lan87xx_t, parent);
329 if (lan87xx->reset_gpio_num >= 0) {
330 esp_rom_gpio_pad_select_gpio(lan87xx->reset_gpio_num);
331 gpio_set_direction(lan87xx->reset_gpio_num, GPIO_MODE_OUTPUT);
332 gpio_set_level(lan87xx->reset_gpio_num, 0);
333 /* assert nRST signal on LAN87xx a little longer than the minimum specified in datasheet */
334 esp_rom_delay_us(150);
335 gpio_set_level(lan87xx->reset_gpio_num, 1);
336 }
337 return ESP_OK;
338 }
339
340 /**
341 * @note This function is responsible for restarting a new auto-negotiation,
342 * the result of negotiation won't be relected to uppler layers.
343 * Instead, the negotiation result is fetched by linker timer, see `lan87xx_get_link()`
344 */
lan87xx_negotiate(esp_eth_phy_t * phy)345 static esp_err_t lan87xx_negotiate(esp_eth_phy_t *phy)
346 {
347 esp_err_t ret = ESP_OK;
348 phy_lan87xx_t *lan87xx = __containerof(phy, phy_lan87xx_t, parent);
349 esp_eth_mediator_t *eth = lan87xx->eth;
350 /* in case any link status has changed, let's assume we're in link down status */
351 lan87xx->link_status = ETH_LINK_DOWN;
352 /* Restart auto negotiation */
353 bmcr_reg_t bmcr = {
354 .speed_select = 1, /* 100Mbps */
355 .duplex_mode = 1, /* Full Duplex */
356 .en_auto_nego = 1, /* Auto Negotiation */
357 .restart_auto_nego = 1 /* Restart Auto Negotiation */
358 };
359 ESP_GOTO_ON_ERROR(eth->phy_reg_write(eth, lan87xx->addr, ETH_PHY_BMCR_REG_ADDR, bmcr.val), err, TAG, "write BMCR failed");
360 /* Wait for auto negotiation complete */
361 bmsr_reg_t bmsr;
362 pscsr_reg_t pscsr;
363 uint32_t to = 0;
364 for (to = 0; to < lan87xx->autonego_timeout_ms / 100; to++) {
365 vTaskDelay(pdMS_TO_TICKS(100));
366 ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, lan87xx->addr, ETH_PHY_BMSR_REG_ADDR, &(bmsr.val)), err, TAG, "read BMSR failed");
367 ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, lan87xx->addr, ETH_PHY_PSCSR_REG_ADDR, &(pscsr.val)), err, TAG, "read PSCSR failed");
368 if (bmsr.auto_nego_complete && pscsr.auto_nego_done) {
369 break;
370 }
371 }
372 /* Auto negotiation failed, maybe no network cable plugged in, so output a warning */
373 if (to >= lan87xx->autonego_timeout_ms / 100 && (lan87xx->link_status == ETH_LINK_UP)) {
374 ESP_LOGW(TAG, "auto negotiation timeout");
375 }
376 return ESP_OK;
377 err:
378 return ret;
379 }
380
lan87xx_pwrctl(esp_eth_phy_t * phy,bool enable)381 static esp_err_t lan87xx_pwrctl(esp_eth_phy_t *phy, bool enable)
382 {
383 esp_err_t ret = ESP_OK;
384 phy_lan87xx_t *lan87xx = __containerof(phy, phy_lan87xx_t, parent);
385 esp_eth_mediator_t *eth = lan87xx->eth;
386 bmcr_reg_t bmcr;
387 ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, lan87xx->addr, ETH_PHY_BMCR_REG_ADDR, &(bmcr.val)), err, TAG, "read BMCR failed");
388 if (!enable) {
389 /* General Power Down Mode */
390 bmcr.power_down = 1;
391 } else {
392 /* Normal operation Mode */
393 bmcr.power_down = 0;
394 }
395 ESP_GOTO_ON_ERROR(eth->phy_reg_write(eth, lan87xx->addr, ETH_PHY_BMCR_REG_ADDR, bmcr.val), err, TAG, "write BMCR failed");
396 if (!enable) {
397 ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, lan87xx->addr, ETH_PHY_BMCR_REG_ADDR, &(bmcr.val)), err, TAG, "read BMCR failed");
398 ESP_GOTO_ON_FALSE(bmcr.power_down == 1, ESP_FAIL, err, TAG, "power down failed");
399 } else {
400 /* wait for power up complete */
401 uint32_t to = 0;
402 for (to = 0; to < lan87xx->reset_timeout_ms / 10; to++) {
403 vTaskDelay(pdMS_TO_TICKS(10));
404 ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, lan87xx->addr, ETH_PHY_BMCR_REG_ADDR, &(bmcr.val)), err, TAG, "read BMCR failed");
405 if (bmcr.power_down == 0) {
406 break;
407 }
408 }
409 ESP_GOTO_ON_FALSE(to < lan87xx->reset_timeout_ms / 10, ESP_FAIL, err, TAG, "power up timeout");
410 }
411 return ESP_OK;
412 err:
413 return ret;
414 }
415
lan87xx_set_addr(esp_eth_phy_t * phy,uint32_t addr)416 static esp_err_t lan87xx_set_addr(esp_eth_phy_t *phy, uint32_t addr)
417 {
418 phy_lan87xx_t *lan87xx = __containerof(phy, phy_lan87xx_t, parent);
419 lan87xx->addr = addr;
420 return ESP_OK;
421 }
422
lan87xx_get_addr(esp_eth_phy_t * phy,uint32_t * addr)423 static esp_err_t lan87xx_get_addr(esp_eth_phy_t *phy, uint32_t *addr)
424 {
425 esp_err_t ret = ESP_OK;
426 ESP_GOTO_ON_FALSE(addr, ESP_ERR_INVALID_ARG, err, TAG, "addr can't be null");
427 phy_lan87xx_t *lan87xx = __containerof(phy, phy_lan87xx_t, parent);
428 *addr = lan87xx->addr;
429 return ESP_OK;
430 err:
431 return ret;
432 }
433
lan87xx_del(esp_eth_phy_t * phy)434 static esp_err_t lan87xx_del(esp_eth_phy_t *phy)
435 {
436 phy_lan87xx_t *lan87xx = __containerof(phy, phy_lan87xx_t, parent);
437 free(lan87xx);
438 return ESP_OK;
439 }
440
lan87xx_advertise_pause_ability(esp_eth_phy_t * phy,uint32_t ability)441 static esp_err_t lan87xx_advertise_pause_ability(esp_eth_phy_t *phy, uint32_t ability)
442 {
443 esp_err_t ret = ESP_OK;
444 phy_lan87xx_t *lan87xx = __containerof(phy, phy_lan87xx_t, parent);
445 esp_eth_mediator_t *eth = lan87xx->eth;
446 /* Set PAUSE function ability */
447 anar_reg_t anar;
448 ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, lan87xx->addr, ETH_PHY_ANAR_REG_ADDR, &(anar.val)), err, TAG, "read ANAR failed");
449 if (ability) {
450 anar.asymmetric_pause = 1;
451 anar.symmetric_pause = 1;
452 } else {
453 anar.asymmetric_pause = 0;
454 anar.symmetric_pause = 0;
455 }
456 ESP_GOTO_ON_ERROR(eth->phy_reg_write(eth, lan87xx->addr, ETH_PHY_ANAR_REG_ADDR, anar.val), err, TAG, "write ANAR failed");
457 return ESP_OK;
458 err:
459 return ret;
460 }
461
lan87xx_loopback(esp_eth_phy_t * phy,bool enable)462 static esp_err_t lan87xx_loopback(esp_eth_phy_t *phy, bool enable)
463 {
464 esp_err_t ret = ESP_OK;
465 phy_lan87xx_t *lan87xx = __containerof(phy, phy_lan87xx_t, parent);
466 esp_eth_mediator_t *eth = lan87xx->eth;
467 /* Set Loopback function */
468 bmcr_reg_t bmcr;
469 ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, lan87xx->addr, ETH_PHY_BMCR_REG_ADDR, &(bmcr.val)), err, TAG, "read BMCR failed");
470 if (enable) {
471 bmcr.en_loopback = 1;
472 } else {
473 bmcr.en_loopback = 0;
474 }
475 ESP_GOTO_ON_ERROR(eth->phy_reg_write(eth, lan87xx->addr, ETH_PHY_BMCR_REG_ADDR, bmcr.val), err, TAG, "write BMCR failed");
476 return ESP_OK;
477 err:
478 return ret;
479 }
480
lan87xx_init(esp_eth_phy_t * phy)481 static esp_err_t lan87xx_init(esp_eth_phy_t *phy)
482 {
483 esp_err_t ret = ESP_OK;
484 phy_lan87xx_t *lan87xx = __containerof(phy, phy_lan87xx_t, parent);
485 esp_eth_mediator_t *eth = lan87xx->eth;
486 // Detect PHY address
487 if (lan87xx->addr == ESP_ETH_PHY_ADDR_AUTO) {
488 ESP_GOTO_ON_ERROR(esp_eth_detect_phy_addr(eth, &lan87xx->addr), err, TAG, "Detect PHY address failed");
489 }
490 /* Power on Ethernet PHY */
491 ESP_GOTO_ON_ERROR(lan87xx_pwrctl(phy, true), err, TAG, "power control failed");
492 /* Reset Ethernet PHY */
493 ESP_GOTO_ON_ERROR(lan87xx_reset(phy), err, TAG, "reset failed");
494 /* Check PHY ID */
495 phyidr1_reg_t id1;
496 phyidr2_reg_t id2;
497 ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, lan87xx->addr, ETH_PHY_IDR1_REG_ADDR, &(id1.val)), err, TAG, "read ID1 failed");
498 ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, lan87xx->addr, ETH_PHY_IDR2_REG_ADDR, &(id2.val)), err, TAG, "read ID2 failed");
499 ESP_GOTO_ON_FALSE(id1.oui_msb == 0x7 && id2.oui_lsb == 0x30, ESP_FAIL, err, TAG, "wrong chip ID");
500 bool supported_model = false;
501 for (unsigned int i = 0; i < sizeof(supported_models); i++) {
502 if (id2.vendor_model == supported_models[i]) {
503 supported_model = true;
504 break;
505 }
506 }
507 ESP_GOTO_ON_FALSE(supported_model, ESP_FAIL, err, TAG, "unsupported chip model");
508 return ESP_OK;
509 err:
510 return ret;
511 }
512
lan87xx_deinit(esp_eth_phy_t * phy)513 static esp_err_t lan87xx_deinit(esp_eth_phy_t *phy)
514 {
515 esp_err_t ret = ESP_OK;
516 /* Power off Ethernet PHY */
517 ESP_GOTO_ON_ERROR(lan87xx_pwrctl(phy, false), err, TAG, "power control failed");
518 return ESP_OK;
519 err:
520 return ret;
521 }
522
esp_eth_phy_new_lan87xx(const eth_phy_config_t * config)523 esp_eth_phy_t *esp_eth_phy_new_lan87xx(const eth_phy_config_t *config)
524 {
525 esp_eth_phy_t *ret = NULL;
526 ESP_GOTO_ON_FALSE(config, NULL, err, TAG, "can't set phy config to null");
527 phy_lan87xx_t *lan87xx = calloc(1, sizeof(phy_lan87xx_t));
528 ESP_GOTO_ON_FALSE(lan87xx, NULL, err, TAG, "calloc lan87xx failed");
529 lan87xx->addr = config->phy_addr;
530 lan87xx->reset_gpio_num = config->reset_gpio_num;
531 lan87xx->reset_timeout_ms = config->reset_timeout_ms;
532 lan87xx->link_status = ETH_LINK_DOWN;
533 lan87xx->autonego_timeout_ms = config->autonego_timeout_ms;
534 lan87xx->parent.reset = lan87xx_reset;
535 lan87xx->parent.reset_hw = lan87xx_reset_hw;
536 lan87xx->parent.init = lan87xx_init;
537 lan87xx->parent.deinit = lan87xx_deinit;
538 lan87xx->parent.set_mediator = lan87xx_set_mediator;
539 lan87xx->parent.negotiate = lan87xx_negotiate;
540 lan87xx->parent.get_link = lan87xx_get_link;
541 lan87xx->parent.pwrctl = lan87xx_pwrctl;
542 lan87xx->parent.get_addr = lan87xx_get_addr;
543 lan87xx->parent.set_addr = lan87xx_set_addr;
544 lan87xx->parent.loopback = lan87xx_loopback;
545 lan87xx->parent.advertise_pause_ability = lan87xx_advertise_pause_ability;
546 lan87xx->parent.del = lan87xx_del;
547
548 return &(lan87xx->parent);
549 err:
550 return ret;
551 }
552
