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Searched refs:DR_REG_SLC_BASE (Results 1 – 6 of 6) sorted by relevance

/hal_espressif-3.4.0/components/soc/esp32/include/soc/
Dslc_reg.h19 #define SLC_CONF0_REG (DR_REG_SLC_BASE + 0x0)
213 #define SLC_0INT_RAW_REG (DR_REG_SLC_BASE + 0x4)
377 #define SLC_0INT_ST_REG (DR_REG_SLC_BASE + 0x8)
541 #define SLC_0INT_ENA_REG (DR_REG_SLC_BASE + 0xC)
705 #define SLC_0INT_CLR_REG (DR_REG_SLC_BASE + 0x10)
869 #define SLC_1INT_RAW_REG (DR_REG_SLC_BASE + 0x14)
1021 #define SLC_1INT_ST_REG (DR_REG_SLC_BASE + 0x18)
1173 #define SLC_1INT_ENA_REG (DR_REG_SLC_BASE + 0x1C)
1325 #define SLC_1INT_CLR_REG (DR_REG_SLC_BASE + 0x20)
1477 #define SLC_RX_STATUS_REG (DR_REG_SLC_BASE + 0x24)
[all …]
Dsoc.h61 #define DR_REG_SLC_BASE 0x3ff58000 macro
/hal_espressif-3.4.0/components/sdmmc/test/
Dtest_sdio.c48 #define SLCCONF1 (DR_REG_SLC_BASE + 0x60)
52 #define SLC0TX_LINK (DR_REG_SLC_BASE + 0x40)
91 if ((addr & DR_REG_SLC_MASK) != DR_REG_SLC_BASE) { in slave_slc_reg_read()
95 uint32_t word = (addr - DR_REG_SLC_BASE) / 4; in slave_slc_reg_read()
111 if ((addr & DR_REG_SLC_MASK) != DR_REG_SLC_BASE) { in slave_slc_reg_write()
115 uint32_t word = (addr - DR_REG_SLC_BASE) / 4; in slave_slc_reg_write()
/hal_espressif-3.4.0/components/soc/esp32h2/include/soc/
Dsoc.h69 #define DR_REG_SLC_BASE 0x6002D000 macro
/hal_espressif-3.4.0/components/soc/esp32s3/include/soc/
Dsoc.h61 #define DR_REG_SLC_BASE 0x60018000 macro
/hal_espressif-3.4.0/components/soc/esp32s2/include/soc/
Dsoc.h66 #define DR_REG_SLC_BASE 0x3f418000 macro