1 // Copyright 2020 Espressif Systems (Shanghai) PTE LTD 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 // 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 15 #pragma once 16 17 #ifndef __ASSEMBLER__ 18 #include <stdint.h> 19 #include "esp_assert.h" 20 #include "esp_bit_defs.h" 21 #endif 22 23 #include "sdkconfig.h" 24 25 #define PRO_CPU_NUM (0) 26 27 #define DR_REG_SYSTEM_BASE 0x600c0000 28 #define DR_REG_SENSITIVE_BASE 0x600c1000 29 #define DR_REG_INTERRUPT_BASE 0x600c2000 30 #define DR_REG_EXTMEM_BASE 0x600c4000 31 #define DR_REG_MMU_TABLE 0x600c5000 32 33 #define DR_REG_ITAG_TABLE 0x600c6000 34 #define DR_REG_DTAG_TABLE 0x600c8000 35 #define DR_REG_ECC_MULT_BASE 0x60039000 36 #define DR_REG_AES_BASE 0x6003a000 37 #define DR_REG_SHA_BASE 0x6003b000 38 #define DR_REG_RSA_BASE 0x6003c000 39 #define DR_REG_DIGITAL_SIGNATURE_BASE 0x6003d000 40 #define DR_REG_HMAC_BASE 0x6003e000 41 #define DR_REG_GDMA_BASE 0x6003f000 42 43 #define DR_REG_ASSIST_DEBUG_BASE 0x600ce000 44 #define DR_REG_DEDICATED_GPIO_BASE 0x600cf000 45 #define DR_REG_WORLD_CNTL_BASE 0x600d0000 46 // #define DR_REG_DPORT_END 0x600d3FFC 47 #define DR_REG_UART_BASE 0x60000000 48 #define DR_REG_SPI1_BASE 0x60002000 49 #define DR_REG_SPI0_BASE 0x60003000 50 #define DR_REG_GPIO_BASE 0x60004000 51 #define DR_REG_GPIO_SD_BASE 0x60004f00 52 #define DR_REG_FE2_BASE 0x60005000 53 #define DR_REG_FE_BASE 0x60006000 54 #define DR_REG_FRC_TIMER_BASE 0x60007000 55 #define DR_REG_RTCCNTL_BASE 0x60008000 56 #define DR_REG_RTCIO_BASE 0x60008400 57 #define DR_REG_SENS_BASE 0x60008800 58 #define DR_REG_RTC_I2C_BASE 0x60008C00 59 #define DR_REG_IO_MUX_BASE 0x60009000 60 #define DR_REG_HINF_BASE 0x6002B000 61 #define DR_REG_UHCI1_BASE 0x6000C000 62 #define DR_REG_I2S_BASE 0x6000F000 63 #define DR_REG_UART1_BASE 0x60010000 64 #define DR_REG_BT_BASE 0x60011000 65 #define DR_REG_I2C_EXT_BASE 0x60013000 66 #define DR_REG_UHCI0_BASE 0x60014000 67 #define DR_REG_SLCHOST_BASE 0x60019000 68 #define DR_REG_RMT_BASE 0x60016000 69 #define DR_REG_SLC_BASE 0x6002D000 70 #define DR_REG_LEDC_BASE 0x60019000 71 #define DR_REG_EFUSE_BASE 0x6001A000 72 #define DR_REG_NRX_BASE 0x6001CC00 73 #define DR_REG_BB_BASE 0x6001D000 74 #define DR_REG_PWM_BASE 0x6001E000 75 #define DR_REG_TIMERGROUP0_BASE 0x6001F000 76 #define DR_REG_TIMERGROUP1_BASE 0x60020000 77 #define DR_REG_RTC_SLOWMEM_BASE 0x60021000 78 #define DR_REG_SYS_TIMER_BASE 0x60023000 79 #define DR_REG_SPI2_BASE 0x60024000 80 #define DR_REG_SPI3_BASE 0x60025000 81 #define DR_REG_SYSCON_BASE 0x60026000 82 #define DR_REG_I2C1_EXT_BASE 0x60027000 83 #define DR_REG_SDMMC_BASE 0x60028000 84 #define DR_REG_CAN_BASE 0x6002B000 85 #define DR_REG_PWM1_BASE 0x6002C000 86 #define DR_REG_I2S1_BASE 0x6002D000 87 #define DR_REG_UART2_BASE 0x6002E000 88 #define DR_REG_PWM2_BASE 0x6002F000 89 #define DR_REG_PWM3_BASE 0x60030000 90 #define DR_REG_SPI4_BASE 0x60037000 91 #define DR_REG_USB_WRAP_BASE 0x60039000 92 #define DR_REG_APB_SARADC_BASE 0x60040000 93 #define DR_REG_LCD_CAM_BASE 0x60041000 94 #define DR_REG_AES_XTS_BASE 0x600CC000 95 #define DR_REG_USB_DEVICE_BASE 0x60043000 96 #define DR_REG_CLKRST_BASE 0x6004B000 97 98 99 #define REG_UHCI_BASE(i) (DR_REG_UHCI0_BASE - (i) * 0x8000) 100 #define REG_UART_BASE( i ) (DR_REG_UART_BASE + (i) * 0x10000 + ( (i) > 1 ? 0xe000 : 0 ) ) 101 #define REG_UART_AHB_BASE(i) (0x60000000 + (i) * 0x10000 + ( (i) > 1 ? 0xe000 : 0 ) ) 102 #define UART_FIFO_AHB_REG(i) (REG_UART_AHB_BASE(i) + 0x0) 103 #define REG_I2S_BASE( i ) (DR_REG_I2S_BASE + (i) * 0x1E000) 104 #define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i)*0x1000) 105 #define REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE - (i) * 0x1000) 106 #define REG_I2C_BASE(i) (DR_REG_I2C_EXT_BASE + (i) * 0x14000 ) 107 108 //Registers Operation {{ 109 #define ETS_UNCACHED_ADDR(addr) (addr) 110 #define ETS_CACHED_ADDR(addr) (addr) 111 112 #ifndef __ASSEMBLER__ 113 #define BIT(nr) (1UL << (nr)) 114 #else 115 #define BIT(nr) (1 << (nr)) 116 #endif 117 118 #ifndef __ASSEMBLER__ 119 120 //write value to register 121 #define REG_WRITE(_r, _v) ({ \ 122 (*(volatile uint32_t *)(_r)) = (_v); \ 123 }) 124 125 //read value from register 126 #define REG_READ(_r) ({ \ 127 (*(volatile uint32_t *)(_r)); \ 128 }) 129 130 //get bit or get bits from register 131 #define REG_GET_BIT(_r, _b) ({ \ 132 (*(volatile uint32_t*)(_r) & (_b)); \ 133 }) 134 135 //set bit or set bits to register 136 #define REG_SET_BIT(_r, _b) ({ \ 137 (*(volatile uint32_t*)(_r) |= (_b)); \ 138 }) 139 140 //clear bit or clear bits of register 141 #define REG_CLR_BIT(_r, _b) ({ \ 142 (*(volatile uint32_t*)(_r) &= ~(_b)); \ 143 }) 144 145 //set bits of register controlled by mask 146 #define REG_SET_BITS(_r, _b, _m) ({ \ 147 (*(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r) & ~(_m)) | ((_b) & (_m))); \ 148 }) 149 150 //get field from register, uses field _S & _V to determine mask 151 #define REG_GET_FIELD(_r, _f) ({ \ 152 ((REG_READ(_r) >> (_f##_S)) & (_f##_V)); \ 153 }) 154 155 //set field of a register from variable, uses field _S & _V to determine mask 156 #define REG_SET_FIELD(_r, _f, _v) ({ \ 157 (REG_WRITE((_r),((REG_READ(_r) & ~((_f##_V) << (_f##_S)))|(((_v) & (_f##_V))<<(_f##_S))))); \ 158 }) 159 160 //get field value from a variable, used when _f is not left shifted by _f##_S 161 #define VALUE_GET_FIELD(_r, _f) (((_r) >> (_f##_S)) & (_f)) 162 163 //get field value from a variable, used when _f is left shifted by _f##_S 164 #define VALUE_GET_FIELD2(_r, _f) (((_r) & (_f))>> (_f##_S)) 165 166 //set field value to a variable, used when _f is not left shifted by _f##_S 167 #define VALUE_SET_FIELD(_r, _f, _v) ((_r)=(((_r) & ~((_f) << (_f##_S)))|((_v)<<(_f##_S)))) 168 169 //set field value to a variable, used when _f is left shifted by _f##_S 170 #define VALUE_SET_FIELD2(_r, _f, _v) ((_r)=(((_r) & ~(_f))|((_v)<<(_f##_S)))) 171 172 //generate a value from a field value, used when _f is not left shifted by _f##_S 173 #define FIELD_TO_VALUE(_f, _v) (((_v)&(_f))<<_f##_S) 174 175 //generate a value from a field value, used when _f is left shifted by _f##_S 176 #define FIELD_TO_VALUE2(_f, _v) (((_v)<<_f##_S) & (_f)) 177 178 //read value from register 179 #define READ_PERI_REG(addr) ({ \ 180 (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))); \ 181 }) 182 183 //write value to register 184 #define WRITE_PERI_REG(addr, val) ({ \ 185 (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))) = (uint32_t)(val); \ 186 }) 187 188 //clear bits of register controlled by mask 189 #define CLEAR_PERI_REG_MASK(reg, mask) ({ \ 190 WRITE_PERI_REG((reg), (READ_PERI_REG(reg)&(~(mask)))); \ 191 }) 192 193 //set bits of register controlled by mask 194 #define SET_PERI_REG_MASK(reg, mask) ({ \ 195 WRITE_PERI_REG((reg), (READ_PERI_REG(reg)|(mask))); \ 196 }) 197 198 //get bits of register controlled by mask 199 #define GET_PERI_REG_MASK(reg, mask) ({ \ 200 (READ_PERI_REG(reg) & (mask)); \ 201 }) 202 203 //get bits of register controlled by highest bit and lowest bit 204 #define GET_PERI_REG_BITS(reg, hipos,lowpos) ({ \ 205 ((READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1)); \ 206 }) 207 208 //set bits of register controlled by mask and shift 209 #define SET_PERI_REG_BITS(reg,bit_map,value,shift) ({ \ 210 (WRITE_PERI_REG((reg),(READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & bit_map)<<(shift)) )); \ 211 }) 212 213 //get field of register 214 #define GET_PERI_REG_BITS2(reg, mask,shift) ({ \ 215 ((READ_PERI_REG(reg)>>(shift))&(mask)); \ 216 }) 217 218 #endif /* !__ASSEMBLER__ */ 219 //}} 220 221 //Periheral Clock {{ 222 #define APB_CLK_FREQ_ROM ( 32*1000000 ) 223 #define CPU_CLK_FREQ_ROM APB_CLK_FREQ_ROM 224 #define UART_CLK_FREQ_ROM ( 32*1000000) 225 #define EFUSE_CLK_FREQ_ROM ( 20*1000000) 226 #define CPU_CLK_FREQ APB_CLK_FREQ 227 #if CONFIG_IDF_ENV_FPGA 228 #define APB_CLK_FREQ ( 32*1000000 ) 229 #else 230 #define APB_CLK_FREQ ( 48*1000000 ) //ESP32H2-TODO: IDF-3786 231 #endif 232 #define REF_CLK_FREQ ( 1000000 ) 233 #define RTC_CLK_FREQ (17.5*1000000) 234 #define XTAL_CLK_FREQ (32*1000000) 235 #define UART_CLK_FREQ APB_CLK_FREQ 236 #define WDT_CLK_FREQ APB_CLK_FREQ 237 #define TIMER_CLK_FREQ (80000000>>4) //80MHz divided by 16 238 #define SPI_CLK_DIV 4 239 #define TICKS_PER_US_ROM 40 // CPU is 80MHz 240 #define GPIO_MATRIX_DELAY_NS 0 241 //}} 242 243 /* Overall memory map */ 244 #define SOC_DROM_LOW 0x3C000000 245 #define SOC_DROM_HIGH 0x3C800000 246 #define SOC_IROM_LOW 0x42000000 247 #define SOC_IROM_HIGH 0x42800000 248 #define SOC_IROM_MASK_LOW 0x40000000 249 #define SOC_IROM_MASK_HIGH 0x40060000 250 #define SOC_DROM_MASK_LOW 0x3FF00000 251 #define SOC_DROM_MASK_HIGH 0x3FF20000 252 #define SOC_IRAM_LOW 0x4037C000 253 #define SOC_IRAM_HIGH 0x403E0000 254 #define SOC_DRAM_LOW 0x3FC80000 255 #define SOC_DRAM_HIGH 0x3FCE0000 256 #define SOC_RTC_IRAM_LOW 0x50000000 // ESP32-H2 only has RTC slow memory 257 #define SOC_RTC_IRAM_HIGH 0x50002000 258 #define SOC_RTC_DRAM_LOW 0x50000000 259 #define SOC_RTC_DRAM_HIGH 0x50002000 260 #define SOC_RTC_DATA_LOW 0x50000000 261 #define SOC_RTC_DATA_HIGH 0x50002000 262 263 //First and last words of the D/IRAM region, for both the DRAM address as well as the IRAM alias. 264 #define SOC_DIRAM_IRAM_LOW 0x40380000 265 #define SOC_DIRAM_IRAM_HIGH 0x403E0000 266 #define SOC_DIRAM_DRAM_LOW 0x3FC80000 267 #define SOC_DIRAM_DRAM_HIGH 0x3FCE0000 268 269 // Region of memory accessible via DMA. See esp_ptr_dma_capable(). 270 #define SOC_DMA_LOW 0x3FC88000 271 #define SOC_DMA_HIGH 0x3FD00000 272 273 // Region of RAM that is byte-accessible. See esp_ptr_byte_accessible(). 274 #define SOC_BYTE_ACCESSIBLE_LOW 0x3FC88000 275 #define SOC_BYTE_ACCESSIBLE_HIGH 0x3FD00000 276 277 //Region of memory that is internal, as in on the same silicon die as the ESP32 CPUs 278 //(excluding RTC data region, that's checked separately.) See esp_ptr_internal(). 279 #define SOC_MEM_INTERNAL_LOW 0x3FC80000 280 #define SOC_MEM_INTERNAL_HIGH 0x3FCE0000 281 #define SOC_MEM_INTERNAL_LOW1 0x40370000 282 #define SOC_MEM_INTERNAL_HIGH1 0x403E0000 283 #define SOC_MEM_INTERNAL_LOW2 0x600FE000 284 #define SOC_MEM_INTERNAL_HIGH2 0x60100000 285 286 #define SOC_MAX_CONTIGUOUS_RAM_SIZE (SOC_IRAM_HIGH - SOC_IRAM_LOW) ///< Largest span of contiguous memory (DRAM or IRAM) in the address space 287 288 // Region of address space that holds peripherals 289 #define SOC_PERIPHERAL_LOW 0x60000000 290 #define SOC_PERIPHERAL_HIGH 0x60100000 291 292 // Debug region, not used by software 293 #define SOC_DEBUG_LOW 0x20000000 294 #define SOC_DEBUG_HIGH 0x28000000 295 296 // Start (highest address) of ROM boot stack, only relevant during early boot 297 #define SOC_ROM_STACK_START 0x3fcebf10 298 299 //On RISC-V CPUs, the interrupt sources are all external interrupts, whose type, source and priority are configured by SW. 300 //There is no HW NMI conception. SW should controlled the masked levels through INT_THRESH_REG. 301 302 //CPU0 Interrupt number reserved in riscv/vector.S, not touch this. 303 #define ETS_T1_WDT_INUM 24 304 #define ETS_CACHEERR_INUM 25 305 #define ETS_MEMPROT_ERR_INUM 26 306 //CPU0 Max valid interrupt number 307 #define ETS_MAX_INUM 31 308 309 //CPU0 Interrupt number used in ROM, should be cancelled in SDK 310 #define ETS_SLC_INUM 1 311 #define ETS_UART0_INUM 5 312 #define ETS_UART1_INUM 5 313 #define ETS_SPI2_INUM 1 314 //CPU0 Interrupt number used in ROM code only when module init function called, should pay attention here. 315 #define ETS_GPIO_INUM 4 316 317 //Other interrupt number should be managed by the user 318 319 //Invalid interrupt for number interrupt matrix 320 #define ETS_INVALID_INUM 0 321 322 //Interrupt medium level, used for INT WDT for example 323 #define SOC_INTERRUPT_LEVEL_MEDIUM 4 324
