1 // Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
2 //
3 // Licensed under the Apache License, Version 2.0 (the "License");
4 // you may not use this file except in compliance with the License.
5 // You may obtain a copy of the License at
6 
7 //     http://www.apache.org/licenses/LICENSE-2.0
8 //
9 // Unless required by applicable law or agreed to in writing, software
10 // distributed under the License is distributed on an "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 // See the License for the specific language governing permissions and
13 // limitations under the License.
14 #ifndef _SOC_DPORT_REG_H_
15 #define _SOC_DPORT_REG_H_
16 
17 #include "soc.h"
18 
19 #ifndef __ASSEMBLER__
20 #include "dport_access.h"
21 #endif
22 
23 /* Registers defined in this header file must be accessed using special macros,
24  * prefixed with DPORT_. See soc/dport_access.h file for details.
25  */
26 
27 #define DPORT_PRO_BOOT_REMAP_CTRL_REG          (DR_REG_DPORT_BASE + 0x000)
28 /* DPORT_PRO_BOOT_REMAP : R/W ;bitpos:[0] ;default: 1'b0 ; */
29 /*description: */
30 #define DPORT_PRO_BOOT_REMAP  (BIT(0))
31 #define DPORT_PRO_BOOT_REMAP_M  (BIT(0))
32 #define DPORT_PRO_BOOT_REMAP_V  0x1
33 #define DPORT_PRO_BOOT_REMAP_S  0
34 
35 #define DPORT_APP_BOOT_REMAP_CTRL_REG          (DR_REG_DPORT_BASE + 0x004)
36 /* DPORT_APP_BOOT_REMAP : R/W ;bitpos:[0] ;default: 1'b0 ; */
37 /*description: */
38 #define DPORT_APP_BOOT_REMAP  (BIT(0))
39 #define DPORT_APP_BOOT_REMAP_M  (BIT(0))
40 #define DPORT_APP_BOOT_REMAP_V  0x1
41 #define DPORT_APP_BOOT_REMAP_S  0
42 
43 #define DPORT_ACCESS_CHECK_REG          (DR_REG_DPORT_BASE + 0x008)
44 /* DPORT_ACCESS_CHECK_APP : RO ;bitpos:[8] ;default: 1'b0 ; */
45 /*description: */
46 #define DPORT_ACCESS_CHECK_APP  (BIT(8))
47 #define DPORT_ACCESS_CHECK_APP_M  (BIT(8))
48 #define DPORT_ACCESS_CHECK_APP_V  0x1
49 #define DPORT_ACCESS_CHECK_APP_S  8
50 /* DPORT_ACCESS_CHECK_PRO : RO ;bitpos:[0] ;default: 1'b0 ; */
51 /*description: */
52 #define DPORT_ACCESS_CHECK_PRO  (BIT(0))
53 #define DPORT_ACCESS_CHECK_PRO_M  (BIT(0))
54 #define DPORT_ACCESS_CHECK_PRO_V  0x1
55 #define DPORT_ACCESS_CHECK_PRO_S  0
56 
57 #define DPORT_PRO_DPORT_APB_MASK0_REG          (DR_REG_DPORT_BASE + 0x00C)
58 /* DPORT_PRODPORT_APB_MASK0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
59 /*description: */
60 #define DPORT_PRODPORT_APB_MASK0  0xFFFFFFFF
61 #define DPORT_PRODPORT_APB_MASK0_M  ((DPORT_PRODPORT_APB_MASK0_V)<<(DPORT_PRODPORT_APB_MASK0_S))
62 #define DPORT_PRODPORT_APB_MASK0_V  0xFFFFFFFF
63 #define DPORT_PRODPORT_APB_MASK0_S  0
64 
65 #define DPORT_PRO_DPORT_APB_MASK1_REG          (DR_REG_DPORT_BASE + 0x010)
66 /* DPORT_PRODPORT_APB_MASK1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
67 /*description: */
68 #define DPORT_PRODPORT_APB_MASK1  0xFFFFFFFF
69 #define DPORT_PRODPORT_APB_MASK1_M  ((DPORT_PRODPORT_APB_MASK1_V)<<(DPORT_PRODPORT_APB_MASK1_S))
70 #define DPORT_PRODPORT_APB_MASK1_V  0xFFFFFFFF
71 #define DPORT_PRODPORT_APB_MASK1_S  0
72 
73 #define DPORT_APP_DPORT_APB_MASK0_REG          (DR_REG_DPORT_BASE + 0x014)
74 /* DPORT_APPDPORT_APB_MASK0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
75 /*description: */
76 #define DPORT_APPDPORT_APB_MASK0  0xFFFFFFFF
77 #define DPORT_APPDPORT_APB_MASK0_M  ((DPORT_APPDPORT_APB_MASK0_V)<<(DPORT_APPDPORT_APB_MASK0_S))
78 #define DPORT_APPDPORT_APB_MASK0_V  0xFFFFFFFF
79 #define DPORT_APPDPORT_APB_MASK0_S  0
80 
81 #define DPORT_APP_DPORT_APB_MASK1_REG          (DR_REG_DPORT_BASE + 0x018)
82 /* DPORT_APPDPORT_APB_MASK1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
83 /*description: */
84 #define DPORT_APPDPORT_APB_MASK1  0xFFFFFFFF
85 #define DPORT_APPDPORT_APB_MASK1_M  ((DPORT_APPDPORT_APB_MASK1_V)<<(DPORT_APPDPORT_APB_MASK1_S))
86 #define DPORT_APPDPORT_APB_MASK1_V  0xFFFFFFFF
87 #define DPORT_APPDPORT_APB_MASK1_S  0
88 
89 #define DPORT_PERI_CLK_EN_REG          (DR_REG_DPORT_BASE + 0x01C)
90 /* DPORT_PERI_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
91 /*description: */
92 #define DPORT_PERI_CLK_EN  0xFFFFFFFF
93 #define DPORT_PERI_CLK_EN_M  ((DPORT_PERI_CLK_EN_V)<<(DPORT_PERI_CLK_EN_S))
94 #define DPORT_PERI_CLK_EN_V  0xFFFFFFFF
95 #define DPORT_PERI_CLK_EN_S  0
96 
97 #define DPORT_PERI_RST_EN_REG          (DR_REG_DPORT_BASE + 0x020)
98 /* DPORT_PERI_RST_EN : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
99 /*description: */
100 #define DPORT_PERI_RST_EN  0xFFFFFFFF
101 #define DPORT_PERI_RST_EN_M  ((DPORT_PERI_RST_EN_V)<<(DPORT_PERI_RST_EN_S))
102 #define DPORT_PERI_RST_EN_V  0xFFFFFFFF
103 #define DPORT_PERI_RST_EN_S  0
104 
105 /* The following bits apply to DPORT_PERI_CLK_EN_REG, DPORT_PERI_RST_EN_REG
106  */
107 #define DPORT_PERI_EN_AES (1<<0)
108 #define DPORT_PERI_EN_SHA (1<<1)
109 #define DPORT_PERI_EN_RSA (1<<2)
110 /* NB: Secure boot reset will hold SHA & AES in reset */
111 #define DPORT_PERI_EN_SECUREBOOT (1<<3)
112 /* NB: Digital signature reset will hold AES & RSA in reset */
113 #define DPORT_PERI_EN_DIGITAL_SIGNATURE (1<<4)
114 
115 #define DPORT_WIFI_BB_CFG_REG          (DR_REG_DPORT_BASE + 0x024)
116 /* DPORT_WIFI_BB_CFG : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
117 /*description: */
118 #define DPORT_WIFI_BB_CFG  0xFFFFFFFF
119 #define DPORT_WIFI_BB_CFG_M  ((DPORT_WIFI_BB_CFG_V)<<(DPORT_WIFI_BB_CFG_S))
120 #define DPORT_WIFI_BB_CFG_V  0xFFFFFFFF
121 #define DPORT_WIFI_BB_CFG_S  0
122 
123 #define DPORT_WIFI_BB_CFG_2_REG          (DR_REG_DPORT_BASE + 0x028)
124 /* DPORT_WIFI_BB_CFG_2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
125 /*description: */
126 #define DPORT_WIFI_BB_CFG_2  0xFFFFFFFF
127 #define DPORT_WIFI_BB_CFG_2_M  ((DPORT_WIFI_BB_CFG_2_V)<<(DPORT_WIFI_BB_CFG_2_S))
128 #define DPORT_WIFI_BB_CFG_2_V  0xFFFFFFFF
129 #define DPORT_WIFI_BB_CFG_2_S  0
130 
131 #define DPORT_APPCPU_CTRL_A_REG          (DR_REG_DPORT_BASE + 0x02C)
132 /* DPORT_APPCPU_RESETTING : R/W ;bitpos:[0] ;default: 1'b1 ; */
133 /*description: */
134 #define DPORT_APPCPU_RESETTING  (BIT(0))
135 #define DPORT_APPCPU_RESETTING_M  (BIT(0))
136 #define DPORT_APPCPU_RESETTING_V  0x1
137 #define DPORT_APPCPU_RESETTING_S  0
138 
139 #define DPORT_APPCPU_CTRL_B_REG          (DR_REG_DPORT_BASE + 0x030)
140 /* DPORT_APPCPU_CLKGATE_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
141 /*description: */
142 #define DPORT_APPCPU_CLKGATE_EN  (BIT(0))
143 #define DPORT_APPCPU_CLKGATE_EN_M  (BIT(0))
144 #define DPORT_APPCPU_CLKGATE_EN_V  0x1
145 #define DPORT_APPCPU_CLKGATE_EN_S  0
146 
147 #define DPORT_APPCPU_CTRL_C_REG          (DR_REG_DPORT_BASE + 0x034)
148 /* DPORT_APPCPU_RUNSTALL : R/W ;bitpos:[0] ;default: 1'b0 ; */
149 /*description: */
150 #define DPORT_APPCPU_RUNSTALL  (BIT(0))
151 #define DPORT_APPCPU_RUNSTALL_M  (BIT(0))
152 #define DPORT_APPCPU_RUNSTALL_V  0x1
153 #define DPORT_APPCPU_RUNSTALL_S  0
154 
155 #define DPORT_APPCPU_CTRL_D_REG          (DR_REG_DPORT_BASE + 0x038)
156 /* DPORT_APPCPU_BOOT_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
157 /*description: */
158 #define DPORT_APPCPU_BOOT_ADDR  0xFFFFFFFF
159 #define DPORT_APPCPU_BOOT_ADDR_M  ((DPORT_APPCPU_BOOT_ADDR_V)<<(DPORT_APPCPU_BOOT_ADDR_S))
160 #define DPORT_APPCPU_BOOT_ADDR_V  0xFFFFFFFF
161 #define DPORT_APPCPU_BOOT_ADDR_S  0
162 
163 #define DPORT_CPU_PER_CONF_REG          (DR_REG_DPORT_BASE + 0x03C)
164 /* DPORT_FAST_CLK_RTC_SEL : R/W ;bitpos:[3] ;default: 1'b0 ; */
165 /*description: */
166 #define DPORT_FAST_CLK_RTC_SEL  (BIT(3))
167 #define DPORT_FAST_CLK_RTC_SEL_M  (BIT(3))
168 #define DPORT_FAST_CLK_RTC_SEL_V  0x1
169 #define DPORT_FAST_CLK_RTC_SEL_S  3
170 /* DPORT_LOWSPEED_CLK_SEL : R/W ;bitpos:[2] ;default: 1'b0 ; */
171 /*description: */
172 #define DPORT_LOWSPEED_CLK_SEL  (BIT(2))
173 #define DPORT_LOWSPEED_CLK_SEL_M  (BIT(2))
174 #define DPORT_LOWSPEED_CLK_SEL_V  0x1
175 #define DPORT_LOWSPEED_CLK_SEL_S  2
176 /* DPORT_CPUPERIOD_SEL : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
177 /*description: */
178 #define DPORT_CPUPERIOD_SEL  0x00000003
179 #define DPORT_CPUPERIOD_SEL_M  ((DPORT_CPUPERIOD_SEL_V)<<(DPORT_CPUPERIOD_SEL_S))
180 #define DPORT_CPUPERIOD_SEL_V  0x3
181 #define DPORT_CPUPERIOD_SEL_S  0
182 #define DPORT_CPUPERIOD_SEL_80		0
183 #define DPORT_CPUPERIOD_SEL_160		1
184 #define DPORT_CPUPERIOD_SEL_240		2
185 
186 #define DPORT_PRO_CACHE_CTRL_REG          (DR_REG_DPORT_BASE + 0x040)
187 /* DPORT_PRO_DRAM_HL : R/W ;bitpos:[16] ;default: 1'b0 ; */
188 /*description: */
189 #define DPORT_PRO_DRAM_HL  (BIT(16))
190 #define DPORT_PRO_DRAM_HL_M  (BIT(16))
191 #define DPORT_PRO_DRAM_HL_V  0x1
192 #define DPORT_PRO_DRAM_HL_S  16
193 /* DPORT_SLAVE_REQ : RO ;bitpos:[15] ;default: 1'b0 ; */
194 /*description: */
195 #define DPORT_SLAVE_REQ  (BIT(15))
196 #define DPORT_SLAVE_REQ_M  (BIT(15))
197 #define DPORT_SLAVE_REQ_V  0x1
198 #define DPORT_SLAVE_REQ_S  15
199 /* DPORT_AHB_SPI_REQ : RO ;bitpos:[14] ;default: 1'b0 ; */
200 /*description: */
201 #define DPORT_AHB_SPI_REQ  (BIT(14))
202 #define DPORT_AHB_SPI_REQ_M  (BIT(14))
203 #define DPORT_AHB_SPI_REQ_V  0x1
204 #define DPORT_AHB_SPI_REQ_S  14
205 /* DPORT_PRO_SLAVE_REQ : RO ;bitpos:[13] ;default: 1'b0 ; */
206 /*description: */
207 #define DPORT_PRO_SLAVE_REQ  (BIT(13))
208 #define DPORT_PRO_SLAVE_REQ_M  (BIT(13))
209 #define DPORT_PRO_SLAVE_REQ_V  0x1
210 #define DPORT_PRO_SLAVE_REQ_S  13
211 /* DPORT_PRO_AHB_SPI_REQ : RO ;bitpos:[12] ;default: 1'b0 ; */
212 /*description: */
213 #define DPORT_PRO_AHB_SPI_REQ  (BIT(12))
214 #define DPORT_PRO_AHB_SPI_REQ_M  (BIT(12))
215 #define DPORT_PRO_AHB_SPI_REQ_V  0x1
216 #define DPORT_PRO_AHB_SPI_REQ_S  12
217 /* DPORT_PRO_DRAM_SPLIT : R/W ;bitpos:[11] ;default: 1'b0 ; */
218 /*description: */
219 #define DPORT_PRO_DRAM_SPLIT  (BIT(11))
220 #define DPORT_PRO_DRAM_SPLIT_M  (BIT(11))
221 #define DPORT_PRO_DRAM_SPLIT_V  0x1
222 #define DPORT_PRO_DRAM_SPLIT_S  11
223 /* DPORT_PRO_SINGLE_IRAM_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
224 /*description: */
225 #define DPORT_PRO_SINGLE_IRAM_ENA  (BIT(10))
226 #define DPORT_PRO_SINGLE_IRAM_ENA_M  (BIT(10))
227 #define DPORT_PRO_SINGLE_IRAM_ENA_V  0x1
228 #define DPORT_PRO_SINGLE_IRAM_ENA_S  10
229 /* DPORT_PRO_CACHE_LOCK_3_EN : R/W ;bitpos:[9] ;default: 1'b0 ; */
230 /*description: */
231 #define DPORT_PRO_CACHE_LOCK_3_EN  (BIT(9))
232 #define DPORT_PRO_CACHE_LOCK_3_EN_M  (BIT(9))
233 #define DPORT_PRO_CACHE_LOCK_3_EN_V  0x1
234 #define DPORT_PRO_CACHE_LOCK_3_EN_S  9
235 /* DPORT_PRO_CACHE_LOCK_2_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */
236 /*description: */
237 #define DPORT_PRO_CACHE_LOCK_2_EN  (BIT(8))
238 #define DPORT_PRO_CACHE_LOCK_2_EN_M  (BIT(8))
239 #define DPORT_PRO_CACHE_LOCK_2_EN_V  0x1
240 #define DPORT_PRO_CACHE_LOCK_2_EN_S  8
241 /* DPORT_PRO_CACHE_LOCK_1_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */
242 /*description: */
243 #define DPORT_PRO_CACHE_LOCK_1_EN  (BIT(7))
244 #define DPORT_PRO_CACHE_LOCK_1_EN_M  (BIT(7))
245 #define DPORT_PRO_CACHE_LOCK_1_EN_V  0x1
246 #define DPORT_PRO_CACHE_LOCK_1_EN_S  7
247 /* DPORT_PRO_CACHE_LOCK_0_EN : R/W ;bitpos:[6] ;default: 1'b0 ; */
248 /*description: */
249 #define DPORT_PRO_CACHE_LOCK_0_EN  (BIT(6))
250 #define DPORT_PRO_CACHE_LOCK_0_EN_M  (BIT(6))
251 #define DPORT_PRO_CACHE_LOCK_0_EN_V  0x1
252 #define DPORT_PRO_CACHE_LOCK_0_EN_S  6
253 /* DPORT_PRO_CACHE_FLUSH_DONE : RO ;bitpos:[5] ;default: 1'b0 ; */
254 /*description: */
255 #define DPORT_PRO_CACHE_FLUSH_DONE  (BIT(5))
256 #define DPORT_PRO_CACHE_FLUSH_DONE_M  (BIT(5))
257 #define DPORT_PRO_CACHE_FLUSH_DONE_V  0x1
258 #define DPORT_PRO_CACHE_FLUSH_DONE_S  5
259 /* DPORT_PRO_CACHE_FLUSH_ENA : R/W ;bitpos:[4] ;default: 1'b1 ; */
260 /*description: */
261 #define DPORT_PRO_CACHE_FLUSH_ENA  (BIT(4))
262 #define DPORT_PRO_CACHE_FLUSH_ENA_M  (BIT(4))
263 #define DPORT_PRO_CACHE_FLUSH_ENA_V  0x1
264 #define DPORT_PRO_CACHE_FLUSH_ENA_S  4
265 /* DPORT_PRO_CACHE_ENABLE : R/W ;bitpos:[3] ;default: 1'b0 ; */
266 /*description: */
267 #define DPORT_PRO_CACHE_ENABLE  (BIT(3))
268 #define DPORT_PRO_CACHE_ENABLE_M  (BIT(3))
269 #define DPORT_PRO_CACHE_ENABLE_V  0x1
270 #define DPORT_PRO_CACHE_ENABLE_S  3
271 /* DPORT_PRO_CACHE_MODE : R/W ;bitpos:[2] ;default: 1'b0 ; */
272 /*description: */
273 #define DPORT_PRO_CACHE_MODE  (BIT(2))
274 #define DPORT_PRO_CACHE_MODE_M  (BIT(2))
275 #define DPORT_PRO_CACHE_MODE_V  0x1
276 #define DPORT_PRO_CACHE_MODE_S  2
277 
278 #define DPORT_PRO_CACHE_CTRL1_REG          (DR_REG_DPORT_BASE + 0x044)
279 /* DPORT_PRO_CACHE_MMU_IA_CLR : R/W ;bitpos:[13] ;default: 1'b0 ; */
280 /*description: */
281 #define DPORT_PRO_CACHE_MMU_IA_CLR  (BIT(13))
282 #define DPORT_PRO_CACHE_MMU_IA_CLR_M  (BIT(13))
283 #define DPORT_PRO_CACHE_MMU_IA_CLR_V  0x1
284 #define DPORT_PRO_CACHE_MMU_IA_CLR_S  13
285 /* DPORT_PRO_CMMU_PD : R/W ;bitpos:[12] ;default: 1'b0 ; */
286 /*description: */
287 #define DPORT_PRO_CMMU_PD  (BIT(12))
288 #define DPORT_PRO_CMMU_PD_M  (BIT(12))
289 #define DPORT_PRO_CMMU_PD_V  0x1
290 #define DPORT_PRO_CMMU_PD_S  12
291 /* DPORT_PRO_CMMU_FORCE_ON : R/W ;bitpos:[11] ;default: 1'b1 ; */
292 /*description: */
293 #define DPORT_PRO_CMMU_FORCE_ON  (BIT(11))
294 #define DPORT_PRO_CMMU_FORCE_ON_M  (BIT(11))
295 #define DPORT_PRO_CMMU_FORCE_ON_V  0x1
296 #define DPORT_PRO_CMMU_FORCE_ON_S  11
297 /* DPORT_PRO_CMMU_FLASH_PAGE_MODE : R/W ;bitpos:[10:9] ;default: 2'b0 ; */
298 /*description: */
299 #define DPORT_PRO_CMMU_FLASH_PAGE_MODE  0x00000003
300 #define DPORT_PRO_CMMU_FLASH_PAGE_MODE_M  ((DPORT_PRO_CMMU_FLASH_PAGE_MODE_V)<<(DPORT_PRO_CMMU_FLASH_PAGE_MODE_S))
301 #define DPORT_PRO_CMMU_FLASH_PAGE_MODE_V  0x3
302 #define DPORT_PRO_CMMU_FLASH_PAGE_MODE_S  9
303 /* DPORT_PRO_CMMU_SRAM_PAGE_MODE : R/W ;bitpos:[8:6] ;default: 3'd3 ; */
304 /*description: */
305 #define DPORT_PRO_CMMU_SRAM_PAGE_MODE  0x00000007
306 #define DPORT_PRO_CMMU_SRAM_PAGE_MODE_M  ((DPORT_PRO_CMMU_SRAM_PAGE_MODE_V)<<(DPORT_PRO_CMMU_SRAM_PAGE_MODE_S))
307 #define DPORT_PRO_CMMU_SRAM_PAGE_MODE_V  0x7
308 #define DPORT_PRO_CMMU_SRAM_PAGE_MODE_S  6
309 /* DPORT_PRO_CACHE_MASK_OPSDRAM : R/W ;bitpos:[5] ;default: 1'b1 ; */
310 /*description: */
311 #define DPORT_PRO_CACHE_MASK_OPSDRAM  (BIT(5))
312 #define DPORT_PRO_CACHE_MASK_OPSDRAM_M  (BIT(5))
313 #define DPORT_PRO_CACHE_MASK_OPSDRAM_V  0x1
314 #define DPORT_PRO_CACHE_MASK_OPSDRAM_S  5
315 /* DPORT_PRO_CACHE_MASK_DROM0 : R/W ;bitpos:[4] ;default: 1'b1 ; */
316 /*description: */
317 #define DPORT_PRO_CACHE_MASK_DROM0  (BIT(4))
318 #define DPORT_PRO_CACHE_MASK_DROM0_M  (BIT(4))
319 #define DPORT_PRO_CACHE_MASK_DROM0_V  0x1
320 #define DPORT_PRO_CACHE_MASK_DROM0_S  4
321 /* DPORT_PRO_CACHE_MASK_DRAM1 : R/W ;bitpos:[3] ;default: 1'b1 ; */
322 /*description: */
323 #define DPORT_PRO_CACHE_MASK_DRAM1  (BIT(3))
324 #define DPORT_PRO_CACHE_MASK_DRAM1_M  (BIT(3))
325 #define DPORT_PRO_CACHE_MASK_DRAM1_V  0x1
326 #define DPORT_PRO_CACHE_MASK_DRAM1_S  3
327 /* DPORT_PRO_CACHE_MASK_IROM0 : R/W ;bitpos:[2] ;default: 1'b1 ; */
328 /*description: */
329 #define DPORT_PRO_CACHE_MASK_IROM0  (BIT(2))
330 #define DPORT_PRO_CACHE_MASK_IROM0_M  (BIT(2))
331 #define DPORT_PRO_CACHE_MASK_IROM0_V  0x1
332 #define DPORT_PRO_CACHE_MASK_IROM0_S  2
333 /* DPORT_PRO_CACHE_MASK_IRAM1 : R/W ;bitpos:[1] ;default: 1'b1 ; */
334 /*description: */
335 #define DPORT_PRO_CACHE_MASK_IRAM1  (BIT(1))
336 #define DPORT_PRO_CACHE_MASK_IRAM1_M  (BIT(1))
337 #define DPORT_PRO_CACHE_MASK_IRAM1_V  0x1
338 #define DPORT_PRO_CACHE_MASK_IRAM1_S  1
339 /* DPORT_PRO_CACHE_MASK_IRAM0 : R/W ;bitpos:[0] ;default: 1'b1 ; */
340 /*description: */
341 #define DPORT_PRO_CACHE_MASK_IRAM0  (BIT(0))
342 #define DPORT_PRO_CACHE_MASK_IRAM0_M  (BIT(0))
343 #define DPORT_PRO_CACHE_MASK_IRAM0_V  0x1
344 #define DPORT_PRO_CACHE_MASK_IRAM0_S  0
345 
346 #define DPORT_PRO_CACHE_LOCK_0_ADDR_REG          (DR_REG_DPORT_BASE + 0x048)
347 /* DPORT_PRO_CACHE_LOCK_0_ADDR_MAX : R/W ;bitpos:[21:18] ;default: 4'h0 ; */
348 /*description: */
349 #define DPORT_PRO_CACHE_LOCK_0_ADDR_MAX  0x0000000F
350 #define DPORT_PRO_CACHE_LOCK_0_ADDR_MAX_M  ((DPORT_PRO_CACHE_LOCK_0_ADDR_MAX_V)<<(DPORT_PRO_CACHE_LOCK_0_ADDR_MAX_S))
351 #define DPORT_PRO_CACHE_LOCK_0_ADDR_MAX_V  0xF
352 #define DPORT_PRO_CACHE_LOCK_0_ADDR_MAX_S  18
353 /* DPORT_PRO_CACHE_LOCK_0_ADDR_MIN : R/W ;bitpos:[17:14] ;default: 4'h0 ; */
354 /*description: */
355 #define DPORT_PRO_CACHE_LOCK_0_ADDR_MIN  0x0000000F
356 #define DPORT_PRO_CACHE_LOCK_0_ADDR_MIN_M  ((DPORT_PRO_CACHE_LOCK_0_ADDR_MIN_V)<<(DPORT_PRO_CACHE_LOCK_0_ADDR_MIN_S))
357 #define DPORT_PRO_CACHE_LOCK_0_ADDR_MIN_V  0xF
358 #define DPORT_PRO_CACHE_LOCK_0_ADDR_MIN_S  14
359 /* DPORT_PRO_CACHE_LOCK_0_ADDR_PRE : R/W ;bitpos:[13:0] ;default: 14'h0 ; */
360 /*description: */
361 #define DPORT_PRO_CACHE_LOCK_0_ADDR_PRE  0x00003FFF
362 #define DPORT_PRO_CACHE_LOCK_0_ADDR_PRE_M  ((DPORT_PRO_CACHE_LOCK_0_ADDR_PRE_V)<<(DPORT_PRO_CACHE_LOCK_0_ADDR_PRE_S))
363 #define DPORT_PRO_CACHE_LOCK_0_ADDR_PRE_V  0x3FFF
364 #define DPORT_PRO_CACHE_LOCK_0_ADDR_PRE_S  0
365 
366 #define DPORT_PRO_CACHE_LOCK_1_ADDR_REG          (DR_REG_DPORT_BASE + 0x04C)
367 /* DPORT_PRO_CACHE_LOCK_1_ADDR_MAX : R/W ;bitpos:[21:18] ;default: 4'h0 ; */
368 /*description: */
369 #define DPORT_PRO_CACHE_LOCK_1_ADDR_MAX  0x0000000F
370 #define DPORT_PRO_CACHE_LOCK_1_ADDR_MAX_M  ((DPORT_PRO_CACHE_LOCK_1_ADDR_MAX_V)<<(DPORT_PRO_CACHE_LOCK_1_ADDR_MAX_S))
371 #define DPORT_PRO_CACHE_LOCK_1_ADDR_MAX_V  0xF
372 #define DPORT_PRO_CACHE_LOCK_1_ADDR_MAX_S  18
373 /* DPORT_PRO_CACHE_LOCK_1_ADDR_MIN : R/W ;bitpos:[17:14] ;default: 4'h0 ; */
374 /*description: */
375 #define DPORT_PRO_CACHE_LOCK_1_ADDR_MIN  0x0000000F
376 #define DPORT_PRO_CACHE_LOCK_1_ADDR_MIN_M  ((DPORT_PRO_CACHE_LOCK_1_ADDR_MIN_V)<<(DPORT_PRO_CACHE_LOCK_1_ADDR_MIN_S))
377 #define DPORT_PRO_CACHE_LOCK_1_ADDR_MIN_V  0xF
378 #define DPORT_PRO_CACHE_LOCK_1_ADDR_MIN_S  14
379 /* DPORT_PRO_CACHE_LOCK_1_ADDR_PRE : R/W ;bitpos:[13:0] ;default: 14'h0 ; */
380 /*description: */
381 #define DPORT_PRO_CACHE_LOCK_1_ADDR_PRE  0x00003FFF
382 #define DPORT_PRO_CACHE_LOCK_1_ADDR_PRE_M  ((DPORT_PRO_CACHE_LOCK_1_ADDR_PRE_V)<<(DPORT_PRO_CACHE_LOCK_1_ADDR_PRE_S))
383 #define DPORT_PRO_CACHE_LOCK_1_ADDR_PRE_V  0x3FFF
384 #define DPORT_PRO_CACHE_LOCK_1_ADDR_PRE_S  0
385 
386 #define DPORT_PRO_CACHE_LOCK_2_ADDR_REG          (DR_REG_DPORT_BASE + 0x050)
387 /* DPORT_PRO_CACHE_LOCK_2_ADDR_MAX : R/W ;bitpos:[21:18] ;default: 4'h0 ; */
388 /*description: */
389 #define DPORT_PRO_CACHE_LOCK_2_ADDR_MAX  0x0000000F
390 #define DPORT_PRO_CACHE_LOCK_2_ADDR_MAX_M  ((DPORT_PRO_CACHE_LOCK_2_ADDR_MAX_V)<<(DPORT_PRO_CACHE_LOCK_2_ADDR_MAX_S))
391 #define DPORT_PRO_CACHE_LOCK_2_ADDR_MAX_V  0xF
392 #define DPORT_PRO_CACHE_LOCK_2_ADDR_MAX_S  18
393 /* DPORT_PRO_CACHE_LOCK_2_ADDR_MIN : R/W ;bitpos:[17:14] ;default: 4'h0 ; */
394 /*description: */
395 #define DPORT_PRO_CACHE_LOCK_2_ADDR_MIN  0x0000000F
396 #define DPORT_PRO_CACHE_LOCK_2_ADDR_MIN_M  ((DPORT_PRO_CACHE_LOCK_2_ADDR_MIN_V)<<(DPORT_PRO_CACHE_LOCK_2_ADDR_MIN_S))
397 #define DPORT_PRO_CACHE_LOCK_2_ADDR_MIN_V  0xF
398 #define DPORT_PRO_CACHE_LOCK_2_ADDR_MIN_S  14
399 /* DPORT_PRO_CACHE_LOCK_2_ADDR_PRE : R/W ;bitpos:[13:0] ;default: 14'h0 ; */
400 /*description: */
401 #define DPORT_PRO_CACHE_LOCK_2_ADDR_PRE  0x00003FFF
402 #define DPORT_PRO_CACHE_LOCK_2_ADDR_PRE_M  ((DPORT_PRO_CACHE_LOCK_2_ADDR_PRE_V)<<(DPORT_PRO_CACHE_LOCK_2_ADDR_PRE_S))
403 #define DPORT_PRO_CACHE_LOCK_2_ADDR_PRE_V  0x3FFF
404 #define DPORT_PRO_CACHE_LOCK_2_ADDR_PRE_S  0
405 
406 #define DPORT_PRO_CACHE_LOCK_3_ADDR_REG          (DR_REG_DPORT_BASE + 0x054)
407 /* DPORT_PRO_CACHE_LOCK_3_ADDR_MAX : R/W ;bitpos:[21:18] ;default: 4'h0 ; */
408 /*description: */
409 #define DPORT_PRO_CACHE_LOCK_3_ADDR_MAX  0x0000000F
410 #define DPORT_PRO_CACHE_LOCK_3_ADDR_MAX_M  ((DPORT_PRO_CACHE_LOCK_3_ADDR_MAX_V)<<(DPORT_PRO_CACHE_LOCK_3_ADDR_MAX_S))
411 #define DPORT_PRO_CACHE_LOCK_3_ADDR_MAX_V  0xF
412 #define DPORT_PRO_CACHE_LOCK_3_ADDR_MAX_S  18
413 /* DPORT_PRO_CACHE_LOCK_3_ADDR_MIN : R/W ;bitpos:[17:14] ;default: 4'h0 ; */
414 /*description: */
415 #define DPORT_PRO_CACHE_LOCK_3_ADDR_MIN  0x0000000F
416 #define DPORT_PRO_CACHE_LOCK_3_ADDR_MIN_M  ((DPORT_PRO_CACHE_LOCK_3_ADDR_MIN_V)<<(DPORT_PRO_CACHE_LOCK_3_ADDR_MIN_S))
417 #define DPORT_PRO_CACHE_LOCK_3_ADDR_MIN_V  0xF
418 #define DPORT_PRO_CACHE_LOCK_3_ADDR_MIN_S  14
419 /* DPORT_PRO_CACHE_LOCK_3_ADDR_PRE : R/W ;bitpos:[13:0] ;default: 14'h0 ; */
420 /*description: */
421 #define DPORT_PRO_CACHE_LOCK_3_ADDR_PRE  0x00003FFF
422 #define DPORT_PRO_CACHE_LOCK_3_ADDR_PRE_M  ((DPORT_PRO_CACHE_LOCK_3_ADDR_PRE_V)<<(DPORT_PRO_CACHE_LOCK_3_ADDR_PRE_S))
423 #define DPORT_PRO_CACHE_LOCK_3_ADDR_PRE_V  0x3FFF
424 #define DPORT_PRO_CACHE_LOCK_3_ADDR_PRE_S  0
425 
426 #define DPORT_APP_CACHE_CTRL_REG          (DR_REG_DPORT_BASE + 0x058)
427 /* DPORT_APP_DRAM_HL : R/W ;bitpos:[14] ;default: 1'b0 ; */
428 /*description: */
429 #define DPORT_APP_DRAM_HL  (BIT(14))
430 #define DPORT_APP_DRAM_HL_M  (BIT(14))
431 #define DPORT_APP_DRAM_HL_V  0x1
432 #define DPORT_APP_DRAM_HL_S  14
433 /* DPORT_APP_SLAVE_REQ : RO ;bitpos:[13] ;default: 1'b0 ; */
434 /*description: */
435 #define DPORT_APP_SLAVE_REQ  (BIT(13))
436 #define DPORT_APP_SLAVE_REQ_M  (BIT(13))
437 #define DPORT_APP_SLAVE_REQ_V  0x1
438 #define DPORT_APP_SLAVE_REQ_S  13
439 /* DPORT_APP_AHB_SPI_REQ : RO ;bitpos:[12] ;default: 1'b0 ; */
440 /*description: */
441 #define DPORT_APP_AHB_SPI_REQ  (BIT(12))
442 #define DPORT_APP_AHB_SPI_REQ_M  (BIT(12))
443 #define DPORT_APP_AHB_SPI_REQ_V  0x1
444 #define DPORT_APP_AHB_SPI_REQ_S  12
445 /* DPORT_APP_DRAM_SPLIT : R/W ;bitpos:[11] ;default: 1'b0 ; */
446 /*description: */
447 #define DPORT_APP_DRAM_SPLIT  (BIT(11))
448 #define DPORT_APP_DRAM_SPLIT_M  (BIT(11))
449 #define DPORT_APP_DRAM_SPLIT_V  0x1
450 #define DPORT_APP_DRAM_SPLIT_S  11
451 /* DPORT_APP_SINGLE_IRAM_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
452 /*description: */
453 #define DPORT_APP_SINGLE_IRAM_ENA  (BIT(10))
454 #define DPORT_APP_SINGLE_IRAM_ENA_M  (BIT(10))
455 #define DPORT_APP_SINGLE_IRAM_ENA_V  0x1
456 #define DPORT_APP_SINGLE_IRAM_ENA_S  10
457 /* DPORT_APP_CACHE_LOCK_3_EN : R/W ;bitpos:[9] ;default: 1'b0 ; */
458 /*description: */
459 #define DPORT_APP_CACHE_LOCK_3_EN  (BIT(9))
460 #define DPORT_APP_CACHE_LOCK_3_EN_M  (BIT(9))
461 #define DPORT_APP_CACHE_LOCK_3_EN_V  0x1
462 #define DPORT_APP_CACHE_LOCK_3_EN_S  9
463 /* DPORT_APP_CACHE_LOCK_2_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */
464 /*description: */
465 #define DPORT_APP_CACHE_LOCK_2_EN  (BIT(8))
466 #define DPORT_APP_CACHE_LOCK_2_EN_M  (BIT(8))
467 #define DPORT_APP_CACHE_LOCK_2_EN_V  0x1
468 #define DPORT_APP_CACHE_LOCK_2_EN_S  8
469 /* DPORT_APP_CACHE_LOCK_1_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */
470 /*description: */
471 #define DPORT_APP_CACHE_LOCK_1_EN  (BIT(7))
472 #define DPORT_APP_CACHE_LOCK_1_EN_M  (BIT(7))
473 #define DPORT_APP_CACHE_LOCK_1_EN_V  0x1
474 #define DPORT_APP_CACHE_LOCK_1_EN_S  7
475 /* DPORT_APP_CACHE_LOCK_0_EN : R/W ;bitpos:[6] ;default: 1'b0 ; */
476 /*description: */
477 #define DPORT_APP_CACHE_LOCK_0_EN  (BIT(6))
478 #define DPORT_APP_CACHE_LOCK_0_EN_M  (BIT(6))
479 #define DPORT_APP_CACHE_LOCK_0_EN_V  0x1
480 #define DPORT_APP_CACHE_LOCK_0_EN_S  6
481 /* DPORT_APP_CACHE_FLUSH_DONE : RO ;bitpos:[5] ;default: 1'b0 ; */
482 /*description: */
483 #define DPORT_APP_CACHE_FLUSH_DONE  (BIT(5))
484 #define DPORT_APP_CACHE_FLUSH_DONE_M  (BIT(5))
485 #define DPORT_APP_CACHE_FLUSH_DONE_V  0x1
486 #define DPORT_APP_CACHE_FLUSH_DONE_S  5
487 /* DPORT_APP_CACHE_FLUSH_ENA : R/W ;bitpos:[4] ;default: 1'b1 ; */
488 /*description: */
489 #define DPORT_APP_CACHE_FLUSH_ENA  (BIT(4))
490 #define DPORT_APP_CACHE_FLUSH_ENA_M  (BIT(4))
491 #define DPORT_APP_CACHE_FLUSH_ENA_V  0x1
492 #define DPORT_APP_CACHE_FLUSH_ENA_S  4
493 /* DPORT_APP_CACHE_ENABLE : R/W ;bitpos:[3] ;default: 1'b0 ; */
494 /*description: */
495 #define DPORT_APP_CACHE_ENABLE  (BIT(3))
496 #define DPORT_APP_CACHE_ENABLE_M  (BIT(3))
497 #define DPORT_APP_CACHE_ENABLE_V  0x1
498 #define DPORT_APP_CACHE_ENABLE_S  3
499 /* DPORT_APP_CACHE_MODE : R/W ;bitpos:[2] ;default: 1'b0 ; */
500 /*description: */
501 #define DPORT_APP_CACHE_MODE  (BIT(2))
502 #define DPORT_APP_CACHE_MODE_M  (BIT(2))
503 #define DPORT_APP_CACHE_MODE_V  0x1
504 #define DPORT_APP_CACHE_MODE_S  2
505 
506 #define DPORT_APP_CACHE_CTRL1_REG          (DR_REG_DPORT_BASE + 0x05C)
507 /* DPORT_APP_CACHE_MMU_IA_CLR : R/W ;bitpos:[13] ;default: 1'b0 ; */
508 /*description: */
509 #define DPORT_APP_CACHE_MMU_IA_CLR  (BIT(13))
510 #define DPORT_APP_CACHE_MMU_IA_CLR_M  (BIT(13))
511 #define DPORT_APP_CACHE_MMU_IA_CLR_V  0x1
512 #define DPORT_APP_CACHE_MMU_IA_CLR_S  13
513 /* DPORT_APP_CMMU_PD : R/W ;bitpos:[12] ;default: 1'b0 ; */
514 /*description: */
515 #define DPORT_APP_CMMU_PD  (BIT(12))
516 #define DPORT_APP_CMMU_PD_M  (BIT(12))
517 #define DPORT_APP_CMMU_PD_V  0x1
518 #define DPORT_APP_CMMU_PD_S  12
519 /* DPORT_APP_CMMU_FORCE_ON : R/W ;bitpos:[11] ;default: 1'b1 ; */
520 /*description: */
521 #define DPORT_APP_CMMU_FORCE_ON  (BIT(11))
522 #define DPORT_APP_CMMU_FORCE_ON_M  (BIT(11))
523 #define DPORT_APP_CMMU_FORCE_ON_V  0x1
524 #define DPORT_APP_CMMU_FORCE_ON_S  11
525 /* DPORT_APP_CMMU_FLASH_PAGE_MODE : R/W ;bitpos:[10:9] ;default: 2'b0 ; */
526 /*description: */
527 #define DPORT_APP_CMMU_FLASH_PAGE_MODE  0x00000003
528 #define DPORT_APP_CMMU_FLASH_PAGE_MODE_M  ((DPORT_APP_CMMU_FLASH_PAGE_MODE_V)<<(DPORT_APP_CMMU_FLASH_PAGE_MODE_S))
529 #define DPORT_APP_CMMU_FLASH_PAGE_MODE_V  0x3
530 #define DPORT_APP_CMMU_FLASH_PAGE_MODE_S  9
531 /* DPORT_APP_CMMU_SRAM_PAGE_MODE : R/W ;bitpos:[8:6] ;default: 3'd3 ; */
532 /*description: */
533 #define DPORT_APP_CMMU_SRAM_PAGE_MODE  0x00000007
534 #define DPORT_APP_CMMU_SRAM_PAGE_MODE_M  ((DPORT_APP_CMMU_SRAM_PAGE_MODE_V)<<(DPORT_APP_CMMU_SRAM_PAGE_MODE_S))
535 #define DPORT_APP_CMMU_SRAM_PAGE_MODE_V  0x7
536 #define DPORT_APP_CMMU_SRAM_PAGE_MODE_S  6
537 /* DPORT_APP_CACHE_MASK_OPSDRAM : R/W ;bitpos:[5] ;default: 1'b1 ; */
538 /*description: */
539 #define DPORT_APP_CACHE_MASK_OPSDRAM  (BIT(5))
540 #define DPORT_APP_CACHE_MASK_OPSDRAM_M  (BIT(5))
541 #define DPORT_APP_CACHE_MASK_OPSDRAM_V  0x1
542 #define DPORT_APP_CACHE_MASK_OPSDRAM_S  5
543 /* DPORT_APP_CACHE_MASK_DROM0 : R/W ;bitpos:[4] ;default: 1'b1 ; */
544 /*description: */
545 #define DPORT_APP_CACHE_MASK_DROM0  (BIT(4))
546 #define DPORT_APP_CACHE_MASK_DROM0_M  (BIT(4))
547 #define DPORT_APP_CACHE_MASK_DROM0_V  0x1
548 #define DPORT_APP_CACHE_MASK_DROM0_S  4
549 /* DPORT_APP_CACHE_MASK_DRAM1 : R/W ;bitpos:[3] ;default: 1'b1 ; */
550 /*description: */
551 #define DPORT_APP_CACHE_MASK_DRAM1  (BIT(3))
552 #define DPORT_APP_CACHE_MASK_DRAM1_M  (BIT(3))
553 #define DPORT_APP_CACHE_MASK_DRAM1_V  0x1
554 #define DPORT_APP_CACHE_MASK_DRAM1_S  3
555 /* DPORT_APP_CACHE_MASK_IROM0 : R/W ;bitpos:[2] ;default: 1'b1 ; */
556 /*description: */
557 #define DPORT_APP_CACHE_MASK_IROM0  (BIT(2))
558 #define DPORT_APP_CACHE_MASK_IROM0_M  (BIT(2))
559 #define DPORT_APP_CACHE_MASK_IROM0_V  0x1
560 #define DPORT_APP_CACHE_MASK_IROM0_S  2
561 /* DPORT_APP_CACHE_MASK_IRAM1 : R/W ;bitpos:[1] ;default: 1'b1 ; */
562 /*description: */
563 #define DPORT_APP_CACHE_MASK_IRAM1  (BIT(1))
564 #define DPORT_APP_CACHE_MASK_IRAM1_M  (BIT(1))
565 #define DPORT_APP_CACHE_MASK_IRAM1_V  0x1
566 #define DPORT_APP_CACHE_MASK_IRAM1_S  1
567 /* DPORT_APP_CACHE_MASK_IRAM0 : R/W ;bitpos:[0] ;default: 1'b1 ; */
568 /*description: */
569 #define DPORT_APP_CACHE_MASK_IRAM0  (BIT(0))
570 #define DPORT_APP_CACHE_MASK_IRAM0_M  (BIT(0))
571 #define DPORT_APP_CACHE_MASK_IRAM0_V  0x1
572 #define DPORT_APP_CACHE_MASK_IRAM0_S  0
573 
574 #define DPORT_APP_CACHE_LOCK_0_ADDR_REG          (DR_REG_DPORT_BASE + 0x060)
575 /* DPORT_APP_CACHE_LOCK_0_ADDR_MAX : R/W ;bitpos:[21:18] ;default: 4'h0 ; */
576 /*description: */
577 #define DPORT_APP_CACHE_LOCK_0_ADDR_MAX  0x0000000F
578 #define DPORT_APP_CACHE_LOCK_0_ADDR_MAX_M  ((DPORT_APP_CACHE_LOCK_0_ADDR_MAX_V)<<(DPORT_APP_CACHE_LOCK_0_ADDR_MAX_S))
579 #define DPORT_APP_CACHE_LOCK_0_ADDR_MAX_V  0xF
580 #define DPORT_APP_CACHE_LOCK_0_ADDR_MAX_S  18
581 /* DPORT_APP_CACHE_LOCK_0_ADDR_MIN : R/W ;bitpos:[17:14] ;default: 4'h0 ; */
582 /*description: */
583 #define DPORT_APP_CACHE_LOCK_0_ADDR_MIN  0x0000000F
584 #define DPORT_APP_CACHE_LOCK_0_ADDR_MIN_M  ((DPORT_APP_CACHE_LOCK_0_ADDR_MIN_V)<<(DPORT_APP_CACHE_LOCK_0_ADDR_MIN_S))
585 #define DPORT_APP_CACHE_LOCK_0_ADDR_MIN_V  0xF
586 #define DPORT_APP_CACHE_LOCK_0_ADDR_MIN_S  14
587 /* DPORT_APP_CACHE_LOCK_0_ADDR_PRE : R/W ;bitpos:[13:0] ;default: 14'h0 ; */
588 /*description: */
589 #define DPORT_APP_CACHE_LOCK_0_ADDR_PRE  0x00003FFF
590 #define DPORT_APP_CACHE_LOCK_0_ADDR_PRE_M  ((DPORT_APP_CACHE_LOCK_0_ADDR_PRE_V)<<(DPORT_APP_CACHE_LOCK_0_ADDR_PRE_S))
591 #define DPORT_APP_CACHE_LOCK_0_ADDR_PRE_V  0x3FFF
592 #define DPORT_APP_CACHE_LOCK_0_ADDR_PRE_S  0
593 
594 #define DPORT_APP_CACHE_LOCK_1_ADDR_REG          (DR_REG_DPORT_BASE + 0x064)
595 /* DPORT_APP_CACHE_LOCK_1_ADDR_MAX : R/W ;bitpos:[21:18] ;default: 4'h0 ; */
596 /*description: */
597 #define DPORT_APP_CACHE_LOCK_1_ADDR_MAX  0x0000000F
598 #define DPORT_APP_CACHE_LOCK_1_ADDR_MAX_M  ((DPORT_APP_CACHE_LOCK_1_ADDR_MAX_V)<<(DPORT_APP_CACHE_LOCK_1_ADDR_MAX_S))
599 #define DPORT_APP_CACHE_LOCK_1_ADDR_MAX_V  0xF
600 #define DPORT_APP_CACHE_LOCK_1_ADDR_MAX_S  18
601 /* DPORT_APP_CACHE_LOCK_1_ADDR_MIN : R/W ;bitpos:[17:14] ;default: 4'h0 ; */
602 /*description: */
603 #define DPORT_APP_CACHE_LOCK_1_ADDR_MIN  0x0000000F
604 #define DPORT_APP_CACHE_LOCK_1_ADDR_MIN_M  ((DPORT_APP_CACHE_LOCK_1_ADDR_MIN_V)<<(DPORT_APP_CACHE_LOCK_1_ADDR_MIN_S))
605 #define DPORT_APP_CACHE_LOCK_1_ADDR_MIN_V  0xF
606 #define DPORT_APP_CACHE_LOCK_1_ADDR_MIN_S  14
607 /* DPORT_APP_CACHE_LOCK_1_ADDR_PRE : R/W ;bitpos:[13:0] ;default: 14'h0 ; */
608 /*description: */
609 #define DPORT_APP_CACHE_LOCK_1_ADDR_PRE  0x00003FFF
610 #define DPORT_APP_CACHE_LOCK_1_ADDR_PRE_M  ((DPORT_APP_CACHE_LOCK_1_ADDR_PRE_V)<<(DPORT_APP_CACHE_LOCK_1_ADDR_PRE_S))
611 #define DPORT_APP_CACHE_LOCK_1_ADDR_PRE_V  0x3FFF
612 #define DPORT_APP_CACHE_LOCK_1_ADDR_PRE_S  0
613 
614 #define DPORT_APP_CACHE_LOCK_2_ADDR_REG          (DR_REG_DPORT_BASE + 0x068)
615 /* DPORT_APP_CACHE_LOCK_2_ADDR_MAX : R/W ;bitpos:[21:18] ;default: 4'h0 ; */
616 /*description: */
617 #define DPORT_APP_CACHE_LOCK_2_ADDR_MAX  0x0000000F
618 #define DPORT_APP_CACHE_LOCK_2_ADDR_MAX_M  ((DPORT_APP_CACHE_LOCK_2_ADDR_MAX_V)<<(DPORT_APP_CACHE_LOCK_2_ADDR_MAX_S))
619 #define DPORT_APP_CACHE_LOCK_2_ADDR_MAX_V  0xF
620 #define DPORT_APP_CACHE_LOCK_2_ADDR_MAX_S  18
621 /* DPORT_APP_CACHE_LOCK_2_ADDR_MIN : R/W ;bitpos:[17:14] ;default: 4'h0 ; */
622 /*description: */
623 #define DPORT_APP_CACHE_LOCK_2_ADDR_MIN  0x0000000F
624 #define DPORT_APP_CACHE_LOCK_2_ADDR_MIN_M  ((DPORT_APP_CACHE_LOCK_2_ADDR_MIN_V)<<(DPORT_APP_CACHE_LOCK_2_ADDR_MIN_S))
625 #define DPORT_APP_CACHE_LOCK_2_ADDR_MIN_V  0xF
626 #define DPORT_APP_CACHE_LOCK_2_ADDR_MIN_S  14
627 /* DPORT_APP_CACHE_LOCK_2_ADDR_PRE : R/W ;bitpos:[13:0] ;default: 14'h0 ; */
628 /*description: */
629 #define DPORT_APP_CACHE_LOCK_2_ADDR_PRE  0x00003FFF
630 #define DPORT_APP_CACHE_LOCK_2_ADDR_PRE_M  ((DPORT_APP_CACHE_LOCK_2_ADDR_PRE_V)<<(DPORT_APP_CACHE_LOCK_2_ADDR_PRE_S))
631 #define DPORT_APP_CACHE_LOCK_2_ADDR_PRE_V  0x3FFF
632 #define DPORT_APP_CACHE_LOCK_2_ADDR_PRE_S  0
633 
634 #define DPORT_APP_CACHE_LOCK_3_ADDR_REG          (DR_REG_DPORT_BASE + 0x06C)
635 /* DPORT_APP_CACHE_LOCK_3_ADDR_MAX : R/W ;bitpos:[21:18] ;default: 4'h0 ; */
636 /*description: */
637 #define DPORT_APP_CACHE_LOCK_3_ADDR_MAX  0x0000000F
638 #define DPORT_APP_CACHE_LOCK_3_ADDR_MAX_M  ((DPORT_APP_CACHE_LOCK_3_ADDR_MAX_V)<<(DPORT_APP_CACHE_LOCK_3_ADDR_MAX_S))
639 #define DPORT_APP_CACHE_LOCK_3_ADDR_MAX_V  0xF
640 #define DPORT_APP_CACHE_LOCK_3_ADDR_MAX_S  18
641 /* DPORT_APP_CACHE_LOCK_3_ADDR_MIN : R/W ;bitpos:[17:14] ;default: 4'h0 ; */
642 /*description: */
643 #define DPORT_APP_CACHE_LOCK_3_ADDR_MIN  0x0000000F
644 #define DPORT_APP_CACHE_LOCK_3_ADDR_MIN_M  ((DPORT_APP_CACHE_LOCK_3_ADDR_MIN_V)<<(DPORT_APP_CACHE_LOCK_3_ADDR_MIN_S))
645 #define DPORT_APP_CACHE_LOCK_3_ADDR_MIN_V  0xF
646 #define DPORT_APP_CACHE_LOCK_3_ADDR_MIN_S  14
647 /* DPORT_APP_CACHE_LOCK_3_ADDR_PRE : R/W ;bitpos:[13:0] ;default: 14'h0 ; */
648 /*description: */
649 #define DPORT_APP_CACHE_LOCK_3_ADDR_PRE  0x00003FFF
650 #define DPORT_APP_CACHE_LOCK_3_ADDR_PRE_M  ((DPORT_APP_CACHE_LOCK_3_ADDR_PRE_V)<<(DPORT_APP_CACHE_LOCK_3_ADDR_PRE_S))
651 #define DPORT_APP_CACHE_LOCK_3_ADDR_PRE_V  0x3FFF
652 #define DPORT_APP_CACHE_LOCK_3_ADDR_PRE_S  0
653 
654 #define DPORT_TRACEMEM_MUX_MODE_REG          (DR_REG_DPORT_BASE + 0x070)
655 /* DPORT_TRACEMEM_MUX_MODE : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
656 /*description: */
657 #define DPORT_TRACEMEM_MUX_MODE  0x00000003
658 #define DPORT_TRACEMEM_MUX_MODE_M  ((DPORT_TRACEMEM_MUX_MODE_V)<<(DPORT_TRACEMEM_MUX_MODE_S))
659 #define DPORT_TRACEMEM_MUX_MODE_V  0x3
660 #define DPORT_TRACEMEM_MUX_MODE_S  0
661 
662 #define DPORT_PRO_TRACEMEM_ENA_REG          (DR_REG_DPORT_BASE + 0x074)
663 /* DPORT_PRO_TRACEMEM_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
664 /*description: */
665 #define DPORT_PRO_TRACEMEM_ENA  (BIT(0))
666 #define DPORT_PRO_TRACEMEM_ENA_M  (BIT(0))
667 #define DPORT_PRO_TRACEMEM_ENA_V  0x1
668 #define DPORT_PRO_TRACEMEM_ENA_S  0
669 
670 #define DPORT_APP_TRACEMEM_ENA_REG          (DR_REG_DPORT_BASE + 0x078)
671 /* DPORT_APP_TRACEMEM_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
672 /*description: */
673 #define DPORT_APP_TRACEMEM_ENA  (BIT(0))
674 #define DPORT_APP_TRACEMEM_ENA_M  (BIT(0))
675 #define DPORT_APP_TRACEMEM_ENA_V  0x1
676 #define DPORT_APP_TRACEMEM_ENA_S  0
677 
678 #define DPORT_CACHE_MUX_MODE_REG          (DR_REG_DPORT_BASE + 0x07C)
679 /* DPORT_CACHE_MUX_MODE : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
680 /*description: */
681 #define DPORT_CACHE_MUX_MODE  0x00000003
682 #define DPORT_CACHE_MUX_MODE_M  ((DPORT_CACHE_MUX_MODE_V)<<(DPORT_CACHE_MUX_MODE_S))
683 #define DPORT_CACHE_MUX_MODE_V  0x3
684 #define DPORT_CACHE_MUX_MODE_S  0
685 
686 #define DPORT_IMMU_PAGE_MODE_REG          (DR_REG_DPORT_BASE + 0x080)
687 /* DPORT_IMMU_PAGE_MODE : R/W ;bitpos:[2:1] ;default: 2'b0 ; */
688 /*description: */
689 #define DPORT_IMMU_PAGE_MODE  0x00000003
690 #define DPORT_IMMU_PAGE_MODE_M  ((DPORT_IMMU_PAGE_MODE_V)<<(DPORT_IMMU_PAGE_MODE_S))
691 #define DPORT_IMMU_PAGE_MODE_V  0x3
692 #define DPORT_IMMU_PAGE_MODE_S  1
693 /* DPORT_INTERNAL_SRAM_IMMU_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
694 /*description: */
695 #define DPORT_INTERNAL_SRAM_IMMU_ENA  (BIT(0))
696 #define DPORT_INTERNAL_SRAM_IMMU_ENA_M  (BIT(0))
697 #define DPORT_INTERNAL_SRAM_IMMU_ENA_V  0x1
698 #define DPORT_INTERNAL_SRAM_IMMU_ENA_S  0
699 
700 #define DPORT_DMMU_PAGE_MODE_REG          (DR_REG_DPORT_BASE + 0x084)
701 /* DPORT_DMMU_PAGE_MODE : R/W ;bitpos:[2:1] ;default: 2'b0 ; */
702 /*description: */
703 #define DPORT_DMMU_PAGE_MODE  0x00000003
704 #define DPORT_DMMU_PAGE_MODE_M  ((DPORT_DMMU_PAGE_MODE_V)<<(DPORT_DMMU_PAGE_MODE_S))
705 #define DPORT_DMMU_PAGE_MODE_V  0x3
706 #define DPORT_DMMU_PAGE_MODE_S  1
707 /* DPORT_INTERNAL_SRAM_DMMU_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
708 /*description: */
709 #define DPORT_INTERNAL_SRAM_DMMU_ENA  (BIT(0))
710 #define DPORT_INTERNAL_SRAM_DMMU_ENA_M  (BIT(0))
711 #define DPORT_INTERNAL_SRAM_DMMU_ENA_V  0x1
712 #define DPORT_INTERNAL_SRAM_DMMU_ENA_S  0
713 
714 #define DPORT_ROM_MPU_ENA_REG          (DR_REG_DPORT_BASE + 0x088)
715 /* DPORT_APP_ROM_MPU_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
716 /*description: */
717 #define DPORT_APP_ROM_MPU_ENA  (BIT(2))
718 #define DPORT_APP_ROM_MPU_ENA_M  (BIT(2))
719 #define DPORT_APP_ROM_MPU_ENA_V  0x1
720 #define DPORT_APP_ROM_MPU_ENA_S  2
721 /* DPORT_PRO_ROM_MPU_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
722 /*description: */
723 #define DPORT_PRO_ROM_MPU_ENA  (BIT(1))
724 #define DPORT_PRO_ROM_MPU_ENA_M  (BIT(1))
725 #define DPORT_PRO_ROM_MPU_ENA_V  0x1
726 #define DPORT_PRO_ROM_MPU_ENA_S  1
727 /* DPORT_SHARE_ROM_MPU_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
728 /*description: */
729 #define DPORT_SHARE_ROM_MPU_ENA  (BIT(0))
730 #define DPORT_SHARE_ROM_MPU_ENA_M  (BIT(0))
731 #define DPORT_SHARE_ROM_MPU_ENA_V  0x1
732 #define DPORT_SHARE_ROM_MPU_ENA_S  0
733 
734 #define DPORT_MEM_PD_MASK_REG          (DR_REG_DPORT_BASE + 0x08C)
735 /* DPORT_LSLP_MEM_PD_MASK : R/W ;bitpos:[0] ;default: 1'b1 ; */
736 /*description: */
737 #define DPORT_LSLP_MEM_PD_MASK  (BIT(0))
738 #define DPORT_LSLP_MEM_PD_MASK_M  (BIT(0))
739 #define DPORT_LSLP_MEM_PD_MASK_V  0x1
740 #define DPORT_LSLP_MEM_PD_MASK_S  0
741 
742 #define DPORT_ROM_PD_CTRL_REG          (DR_REG_DPORT_BASE + 0x090)
743 /* DPORT_SHARE_ROM_PD : R/W ;bitpos:[7:2] ;default: 6'h0 ; */
744 /*description: */
745 #define DPORT_SHARE_ROM_PD  0x0000003F
746 #define DPORT_SHARE_ROM_PD_M  ((DPORT_SHARE_ROM_PD_V)<<(DPORT_SHARE_ROM_PD_S))
747 #define DPORT_SHARE_ROM_PD_V  0x3F
748 #define DPORT_SHARE_ROM_PD_S  2
749 /* DPORT_APP_ROM_PD : R/W ;bitpos:[1] ;default: 1'h0 ; */
750 /*description: */
751 #define DPORT_APP_ROM_PD  (BIT(1))
752 #define DPORT_APP_ROM_PD_M  (BIT(1))
753 #define DPORT_APP_ROM_PD_V  0x1
754 #define DPORT_APP_ROM_PD_S  1
755 /* DPORT_PRO_ROM_PD : R/W ;bitpos:[0] ;default: 1'h0 ; */
756 /*description: */
757 #define DPORT_PRO_ROM_PD  (BIT(0))
758 #define DPORT_PRO_ROM_PD_M  (BIT(0))
759 #define DPORT_PRO_ROM_PD_V  0x1
760 #define DPORT_PRO_ROM_PD_S  0
761 
762 #define DPORT_ROM_FO_CTRL_REG          (DR_REG_DPORT_BASE + 0x094)
763 /* DPORT_SHARE_ROM_FO : R/W ;bitpos:[7:2] ;default: 6'h0 ; */
764 /*description: */
765 #define DPORT_SHARE_ROM_FO  0x0000003F
766 #define DPORT_SHARE_ROM_FO_M  ((DPORT_SHARE_ROM_FO_V)<<(DPORT_SHARE_ROM_FO_S))
767 #define DPORT_SHARE_ROM_FO_V  0x3F
768 #define DPORT_SHARE_ROM_FO_S  2
769 /* DPORT_APP_ROM_FO : R/W ;bitpos:[1] ;default: 1'h1 ; */
770 /*description: */
771 #define DPORT_APP_ROM_FO  (BIT(1))
772 #define DPORT_APP_ROM_FO_M  (BIT(1))
773 #define DPORT_APP_ROM_FO_V  0x1
774 #define DPORT_APP_ROM_FO_S  1
775 /* DPORT_PRO_ROM_FO : R/W ;bitpos:[0] ;default: 1'h1 ; */
776 /*description: */
777 #define DPORT_PRO_ROM_FO  (BIT(0))
778 #define DPORT_PRO_ROM_FO_M  (BIT(0))
779 #define DPORT_PRO_ROM_FO_V  0x1
780 #define DPORT_PRO_ROM_FO_S  0
781 
782 #define DPORT_SRAM_PD_CTRL_0_REG          (DR_REG_DPORT_BASE + 0x098)
783 /* DPORT_SRAM_PD_0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
784 /*description: */
785 #define DPORT_SRAM_PD_0  0xFFFFFFFF
786 #define DPORT_SRAM_PD_0_M  ((DPORT_SRAM_PD_0_V)<<(DPORT_SRAM_PD_0_S))
787 #define DPORT_SRAM_PD_0_V  0xFFFFFFFF
788 #define DPORT_SRAM_PD_0_S  0
789 
790 #define DPORT_SRAM_PD_CTRL_1_REG          (DR_REG_DPORT_BASE + 0x09C)
791 /* DPORT_SRAM_PD_1 : R/W ;bitpos:[0] ;default: 1'h0 ; */
792 /*description: */
793 #define DPORT_SRAM_PD_1  (BIT(0))
794 #define DPORT_SRAM_PD_1_M  (BIT(0))
795 #define DPORT_SRAM_PD_1_V  0x1
796 #define DPORT_SRAM_PD_1_S  0
797 
798 #define DPORT_SRAM_FO_CTRL_0_REG          (DR_REG_DPORT_BASE + 0x0A0)
799 /* DPORT_SRAM_FO_0 : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */
800 /*description: */
801 #define DPORT_SRAM_FO_0  0xFFFFFFFF
802 #define DPORT_SRAM_FO_0_M  ((DPORT_SRAM_FO_0_V)<<(DPORT_SRAM_FO_0_S))
803 #define DPORT_SRAM_FO_0_V  0xFFFFFFFF
804 #define DPORT_SRAM_FO_0_S  0
805 
806 #define DPORT_SRAM_FO_CTRL_1_REG          (DR_REG_DPORT_BASE + 0x0A4)
807 /* DPORT_SRAM_FO_1 : R/W ;bitpos:[0] ;default: 1'h1 ; */
808 /*description: */
809 #define DPORT_SRAM_FO_1  (BIT(0))
810 #define DPORT_SRAM_FO_1_M  (BIT(0))
811 #define DPORT_SRAM_FO_1_V  0x1
812 #define DPORT_SRAM_FO_1_S  0
813 
814 #define DPORT_IRAM_DRAM_AHB_SEL_REG          (DR_REG_DPORT_BASE + 0x0A8)
815 /* DPORT_MAC_DUMP_MODE : R/W ;bitpos:[6:5] ;default: 2'h0 ; */
816 /*description: */
817 #define DPORT_MAC_DUMP_MODE  0x00000003
818 #define DPORT_MAC_DUMP_MODE_M  ((DPORT_MAC_DUMP_MODE_V)<<(DPORT_MAC_DUMP_MODE_S))
819 #define DPORT_MAC_DUMP_MODE_V  0x3
820 #define DPORT_MAC_DUMP_MODE_S  5
821 /* DPORT_MASK_AHB : R/W ;bitpos:[4] ;default: 1'b0 ; */
822 /*description: */
823 #define DPORT_MASK_AHB  (BIT(4))
824 #define DPORT_MASK_AHB_M  (BIT(4))
825 #define DPORT_MASK_AHB_V  0x1
826 #define DPORT_MASK_AHB_S  4
827 /* DPORT_MASK_APP_DRAM : R/W ;bitpos:[3] ;default: 1'b0 ; */
828 /*description: */
829 #define DPORT_MASK_APP_DRAM  (BIT(3))
830 #define DPORT_MASK_APP_DRAM_M  (BIT(3))
831 #define DPORT_MASK_APP_DRAM_V  0x1
832 #define DPORT_MASK_APP_DRAM_S  3
833 /* DPORT_MASK_PRO_DRAM : R/W ;bitpos:[2] ;default: 1'b0 ; */
834 /*description: */
835 #define DPORT_MASK_PRO_DRAM  (BIT(2))
836 #define DPORT_MASK_PRO_DRAM_M  (BIT(2))
837 #define DPORT_MASK_PRO_DRAM_V  0x1
838 #define DPORT_MASK_PRO_DRAM_S  2
839 /* DPORT_MASK_APP_IRAM : R/W ;bitpos:[1] ;default: 1'b0 ; */
840 /*description: */
841 #define DPORT_MASK_APP_IRAM  (BIT(1))
842 #define DPORT_MASK_APP_IRAM_M  (BIT(1))
843 #define DPORT_MASK_APP_IRAM_V  0x1
844 #define DPORT_MASK_APP_IRAM_S  1
845 /* DPORT_MASK_PRO_IRAM : R/W ;bitpos:[0] ;default: 1'b0 ; */
846 /*description: */
847 #define DPORT_MASK_PRO_IRAM  (BIT(0))
848 #define DPORT_MASK_PRO_IRAM_M  (BIT(0))
849 #define DPORT_MASK_PRO_IRAM_V  0x1
850 #define DPORT_MASK_PRO_IRAM_S  0
851 
852 #define DPORT_TAG_FO_CTRL_REG          (DR_REG_DPORT_BASE + 0x0AC)
853 /* DPORT_APP_CACHE_TAG_PD : R/W ;bitpos:[9] ;default: 1'b0 ; */
854 /*description: */
855 #define DPORT_APP_CACHE_TAG_PD  (BIT(9))
856 #define DPORT_APP_CACHE_TAG_PD_M  (BIT(9))
857 #define DPORT_APP_CACHE_TAG_PD_V  0x1
858 #define DPORT_APP_CACHE_TAG_PD_S  9
859 /* DPORT_APP_CACHE_TAG_FORCE_ON : R/W ;bitpos:[8] ;default: 1'b1 ; */
860 /*description: */
861 #define DPORT_APP_CACHE_TAG_FORCE_ON  (BIT(8))
862 #define DPORT_APP_CACHE_TAG_FORCE_ON_M  (BIT(8))
863 #define DPORT_APP_CACHE_TAG_FORCE_ON_V  0x1
864 #define DPORT_APP_CACHE_TAG_FORCE_ON_S  8
865 /* DPORT_PRO_CACHE_TAG_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */
866 /*description: */
867 #define DPORT_PRO_CACHE_TAG_PD  (BIT(1))
868 #define DPORT_PRO_CACHE_TAG_PD_M  (BIT(1))
869 #define DPORT_PRO_CACHE_TAG_PD_V  0x1
870 #define DPORT_PRO_CACHE_TAG_PD_S  1
871 /* DPORT_PRO_CACHE_TAG_FORCE_ON : R/W ;bitpos:[0] ;default: 1'b1 ; */
872 /*description: */
873 #define DPORT_PRO_CACHE_TAG_FORCE_ON  (BIT(0))
874 #define DPORT_PRO_CACHE_TAG_FORCE_ON_M  (BIT(0))
875 #define DPORT_PRO_CACHE_TAG_FORCE_ON_V  0x1
876 #define DPORT_PRO_CACHE_TAG_FORCE_ON_S  0
877 
878 #define DPORT_AHB_LITE_MASK_REG          (DR_REG_DPORT_BASE + 0x0B0)
879 /* DPORT_AHB_LITE_SDHOST_PID_REG : R/W ;bitpos:[13:11] ;default: 3'b0 ; */
880 /*description: */
881 #define DPORT_AHB_LITE_SDHOST_PID_REG  0x00000007
882 #define DPORT_AHB_LITE_SDHOST_PID_REG_M  ((DPORT_AHB_LITE_SDHOST_PID_REG_V)<<(DPORT_AHB_LITE_SDHOST_PID_REG_S))
883 #define DPORT_AHB_LITE_SDHOST_PID_REG_V  0x7
884 #define DPORT_AHB_LITE_SDHOST_PID_REG_S  11
885 /* DPORT_AHB_LITE_MASK_APPDPORT : R/W ;bitpos:[10] ;default: 1'b0 ; */
886 /*description: */
887 #define DPORT_AHB_LITE_MASK_APPDPORT  (BIT(10))
888 #define DPORT_AHB_LITE_MASK_APPDPORT_M  (BIT(10))
889 #define DPORT_AHB_LITE_MASK_APPDPORT_V  0x1
890 #define DPORT_AHB_LITE_MASK_APPDPORT_S  10
891 /* DPORT_AHB_LITE_MASK_PRODPORT : R/W ;bitpos:[9] ;default: 1'b0 ; */
892 /*description: */
893 #define DPORT_AHB_LITE_MASK_PRODPORT  (BIT(9))
894 #define DPORT_AHB_LITE_MASK_PRODPORT_M  (BIT(9))
895 #define DPORT_AHB_LITE_MASK_PRODPORT_V  0x1
896 #define DPORT_AHB_LITE_MASK_PRODPORT_S  9
897 /* DPORT_AHB_LITE_MASK_SDIO : R/W ;bitpos:[8] ;default: 1'b0 ; */
898 /*description: */
899 #define DPORT_AHB_LITE_MASK_SDIO  (BIT(8))
900 #define DPORT_AHB_LITE_MASK_SDIO_M  (BIT(8))
901 #define DPORT_AHB_LITE_MASK_SDIO_V  0x1
902 #define DPORT_AHB_LITE_MASK_SDIO_S  8
903 /* DPORT_AHB_LITE_MASK_APP : R/W ;bitpos:[4] ;default: 1'b0 ; */
904 /*description: */
905 #define DPORT_AHB_LITE_MASK_APP  (BIT(4))
906 #define DPORT_AHB_LITE_MASK_APP_M  (BIT(4))
907 #define DPORT_AHB_LITE_MASK_APP_V  0x1
908 #define DPORT_AHB_LITE_MASK_APP_S  4
909 /* DPORT_AHB_LITE_MASK_PRO : R/W ;bitpos:[0] ;default: 1'b0 ; */
910 /*description: */
911 #define DPORT_AHB_LITE_MASK_PRO  (BIT(0))
912 #define DPORT_AHB_LITE_MASK_PRO_M  (BIT(0))
913 #define DPORT_AHB_LITE_MASK_PRO_V  0x1
914 #define DPORT_AHB_LITE_MASK_PRO_S  0
915 
916 #define DPORT_AHB_MPU_TABLE_0_REG          (DR_REG_DPORT_BASE + 0x0B4)
917 /* DPORT_AHB_ACCESS_GRANT_0 : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */
918 /*description: */
919 #define DPORT_AHB_ACCESS_GRANT_0  0xFFFFFFFF
920 #define DPORT_AHB_ACCESS_GRANT_0_M  ((DPORT_AHB_ACCESS_GRANT_0_V)<<(DPORT_AHB_ACCESS_GRANT_0_S))
921 #define DPORT_AHB_ACCESS_GRANT_0_V  0xFFFFFFFF
922 #define DPORT_AHB_ACCESS_GRANT_0_S  0
923 
924 #define DPORT_AHB_MPU_TABLE_1_REG          (DR_REG_DPORT_BASE + 0x0B8)
925 /* DPORT_AHB_ACCESS_GRANT_1 : R/W ;bitpos:[8:0] ;default: 9'h1ff ; */
926 /*description: */
927 #define DPORT_AHB_ACCESS_GRANT_1  0x000001FF
928 #define DPORT_AHB_ACCESS_GRANT_1_M  ((DPORT_AHB_ACCESS_GRANT_1_V)<<(DPORT_AHB_ACCESS_GRANT_1_S))
929 #define DPORT_AHB_ACCESS_GRANT_1_V  0x1FF
930 #define DPORT_AHB_ACCESS_GRANT_1_S  0
931 
932 #define DPORT_HOST_INF_SEL_REG          (DR_REG_DPORT_BASE + 0x0BC)
933 /* DPORT_LINK_DEVICE_SEL : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
934 /*description: */
935 #define DPORT_LINK_DEVICE_SEL  0x000000FF
936 #define DPORT_LINK_DEVICE_SEL_M  ((DPORT_LINK_DEVICE_SEL_V)<<(DPORT_LINK_DEVICE_SEL_S))
937 #define DPORT_LINK_DEVICE_SEL_V  0xFF
938 #define DPORT_LINK_DEVICE_SEL_S  8
939 /* DPORT_PERI_IO_SWAP : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
940 /*description: */
941 #define DPORT_PERI_IO_SWAP  0x000000FF
942 #define DPORT_PERI_IO_SWAP_M  ((DPORT_PERI_IO_SWAP_V)<<(DPORT_PERI_IO_SWAP_S))
943 #define DPORT_PERI_IO_SWAP_V  0xFF
944 #define DPORT_PERI_IO_SWAP_S  0
945 
946 #define DPORT_PERIP_CLK_EN_REG          (DR_REG_DPORT_BASE + 0x0C0)
947 /* DPORT_PERIP_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'hf9c1e06f ; */
948 /*description: */
949 #define DPORT_PERIP_CLK_EN  0xFFFFFFFF
950 #define DPORT_PERIP_CLK_EN_M  ((DPORT_PERIP_CLK_EN_V)<<(DPORT_PERIP_CLK_EN_S))
951 #define DPORT_PERIP_CLK_EN_V  0xFFFFFFFF
952 #define DPORT_PERIP_CLK_EN_S  0
953 
954 #define DPORT_PWM3_CLK_EN (BIT(26))
955 #define DPORT_PWM2_CLK_EN (BIT(25))
956 #define DPORT_UART_MEM_CLK_EN   (BIT(24))
957 #define DPORT_UART2_CLK_EN   (BIT(23))
958 #define DPORT_SPI_DMA_CLK_EN   (BIT(22))
959 #define DPORT_I2S1_CLK_EN   (BIT(21))
960 #define DPORT_PWM1_CLK_EN   (BIT(20))
961 #define DPORT_TWAI_CLK_EN   (BIT(19))
962 #define DPORT_CAN_CLK_EN    DPORT_TWAI_CLK_EN
963 #define DPORT_I2C_EXT1_CLK_EN   (BIT(18))
964 #define DPORT_PWM0_CLK_EN   (BIT(17))
965 #define DPORT_SPI3_CLK_EN   (BIT(16))
966 #define DPORT_TIMERGROUP1_CLK_EN   (BIT(15))
967 #define DPORT_EFUSE_CLK_EN   (BIT(14))
968 #define DPORT_TIMERGROUP_CLK_EN   (BIT(13))
969 #define DPORT_UHCI1_CLK_EN   (BIT(12))
970 #define DPORT_LEDC_CLK_EN   (BIT(11))
971 #define DPORT_PCNT_CLK_EN   (BIT(10))
972 #define DPORT_RMT_CLK_EN   (BIT(9))
973 #define DPORT_UHCI0_CLK_EN   (BIT(8))
974 #define DPORT_I2C_EXT0_CLK_EN   (BIT(7))
975 #define DPORT_SPI2_CLK_EN   (BIT(6))
976 #define DPORT_UART1_CLK_EN   (BIT(5))
977 #define DPORT_I2S0_CLK_EN   (BIT(4))
978 #define DPORT_WDG_CLK_EN   (BIT(3))
979 #define DPORT_UART_CLK_EN   (BIT(2))
980 #define DPORT_SPI01_CLK_EN   (BIT(1))
981 #define DPORT_TIMERS_CLK_EN   (BIT(0))
982 #define DPORT_PERIP_RST_EN_REG          (DR_REG_DPORT_BASE + 0x0C4)
983 /* DPORT_PERIP_RST : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
984 /*description: */
985 #define DPORT_PERIP_RST  0xFFFFFFFF
986 #define DPORT_PERIP_RST_M  ((DPORT_PERIP_RST_V)<<(DPORT_PERIP_RST_S))
987 #define DPORT_PERIP_RST_V  0xFFFFFFFF
988 #define DPORT_PERIP_RST_S  0
989 #define DPORT_PWM3_RST (BIT(26))
990 #define DPORT_PWM2_RST (BIT(25))
991 #define DPORT_UART_MEM_RST   (BIT(24))
992 #define DPORT_UART2_RST   (BIT(23))
993 #define DPORT_SPI_DMA_RST   (BIT(22))
994 #define DPORT_I2S1_RST   (BIT(21))
995 #define DPORT_PWM1_RST   (BIT(20))
996 #define DPORT_TWAI_RST   (BIT(19))
997 #define DPORT_CAN_RST    DPORT_TWAI_RST
998 #define DPORT_I2C_EXT1_RST   (BIT(18))
999 #define DPORT_PWM0_RST   (BIT(17))
1000 #define DPORT_SPI3_RST   (BIT(16))
1001 #define DPORT_TIMERGROUP1_RST   (BIT(15))
1002 #define DPORT_EFUSE_RST   (BIT(14))
1003 #define DPORT_TIMERGROUP_RST   (BIT(13))
1004 #define DPORT_UHCI1_RST   (BIT(12))
1005 #define DPORT_LEDC_RST   (BIT(11))
1006 #define DPORT_PCNT_RST   (BIT(10))
1007 #define DPORT_RMT_RST   (BIT(9))
1008 #define DPORT_UHCI0_RST   (BIT(8))
1009 #define DPORT_I2C_EXT0_RST   (BIT(7))
1010 #define DPORT_SPI2_RST   (BIT(6))
1011 #define DPORT_UART1_RST   (BIT(5))
1012 #define DPORT_I2S0_RST   (BIT(4))
1013 #define DPORT_WDG_RST   (BIT(3))
1014 #define DPORT_UART_RST   (BIT(2))
1015 #define DPORT_SPI01_RST   (BIT(1))
1016 #define DPORT_TIMERS_RST   (BIT(0))
1017 #define DPORT_SLAVE_SPI_CONFIG_REG          (DR_REG_DPORT_BASE + 0x0C8)
1018 /* DPORT_SPI_DECRYPT_ENABLE : R/W ;bitpos:[12] ;default: 1'b0 ; */
1019 /*description: */
1020 #define DPORT_SPI_DECRYPT_ENABLE  (BIT(12))
1021 #define DPORT_SPI_DECRYPT_ENABLE_M  (BIT(12))
1022 #define DPORT_SPI_DECRYPT_ENABLE_V  0x1
1023 #define DPORT_SPI_DECRYPT_ENABLE_S  12
1024 /* DPORT_SPI_ENCRYPT_ENABLE : R/W ;bitpos:[8] ;default: 1'b0 ; */
1025 /*description: */
1026 #define DPORT_SPI_ENCRYPT_ENABLE  (BIT(8))
1027 #define DPORT_SPI_ENCRYPT_ENABLE_M  (BIT(8))
1028 #define DPORT_SPI_ENCRYPT_ENABLE_V  0x1
1029 #define DPORT_SPI_ENCRYPT_ENABLE_S  8
1030 /* DPORT_SLAVE_SPI_MASK_APP : R/W ;bitpos:[4] ;default: 1'b0 ; */
1031 /*description: */
1032 #define DPORT_SLAVE_SPI_MASK_APP  (BIT(4))
1033 #define DPORT_SLAVE_SPI_MASK_APP_M  (BIT(4))
1034 #define DPORT_SLAVE_SPI_MASK_APP_V  0x1
1035 #define DPORT_SLAVE_SPI_MASK_APP_S  4
1036 /* DPORT_SLAVE_SPI_MASK_PRO : R/W ;bitpos:[0] ;default: 1'b0 ; */
1037 /*description: */
1038 #define DPORT_SLAVE_SPI_MASK_PRO  (BIT(0))
1039 #define DPORT_SLAVE_SPI_MASK_PRO_M  (BIT(0))
1040 #define DPORT_SLAVE_SPI_MASK_PRO_V  0x1
1041 #define DPORT_SLAVE_SPI_MASK_PRO_S  0
1042 
1043 #define DPORT_WIFI_CLK_EN_REG          (DR_REG_DPORT_BASE + 0x0CC)
1044 /* DPORT_WIFI_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'hfffce030 ; */
1045 /*description: */
1046 #define DPORT_WIFI_CLK_EN  0xFFFFFFFF
1047 #define DPORT_WIFI_CLK_EN_M  ((DPORT_WIFI_CLK_EN_V)<<(DPORT_WIFI_CLK_EN_S))
1048 #define DPORT_WIFI_CLK_EN_V  0xFFFFFFFF
1049 #define DPORT_WIFI_CLK_EN_S  0
1050 
1051 /* Mask for all Wifi clock bits - 1, 2, 10 */
1052 #define DPORT_WIFI_CLK_WIFI_EN  0x00000406
1053 #define DPORT_WIFI_CLK_WIFI_EN_M  ((DPORT_WIFI_CLK_WIFI_EN_V)<<(DPORT_WIFI_CLK_WIFI_EN_S))
1054 #define DPORT_WIFI_CLK_WIFI_EN_V  0x406
1055 #define DPORT_WIFI_CLK_WIFI_EN_S  0
1056 /* Mask for all Bluetooth clock bits - 11, 16, 17 */
1057 #define DPORT_WIFI_CLK_BT_EN  0x61
1058 #define DPORT_WIFI_CLK_BT_EN_M  ((DPORT_WIFI_CLK_BT_EN_V)<<(DPORT_WIFI_CLK_BT_EN_S))
1059 #define DPORT_WIFI_CLK_BT_EN_V  0x61
1060 #define DPORT_WIFI_CLK_BT_EN_S  11
1061 /* Mask for clock bits used by both WIFI and Bluetooth, bit 0, 3, 6, 7, 8, 9 */
1062 #define DPORT_WIFI_CLK_WIFI_BT_COMMON_M 0x000003c9
1063 //bluetooth baseband bit11
1064 #define DPORT_BT_BASEBAND_EN  BIT(11)
1065 //bluetooth LC bit16 and bit17
1066 #define DPORT_BT_LC_EN  (BIT(16)|BIT(17))
1067 
1068 /* Remaining single bit clock masks */
1069 #define DPORT_WIFI_CLK_SDIOSLAVE_EN  BIT(4)
1070 #define DPORT_WIFI_CLK_UNUSED_BIT5  BIT(5)
1071 #define DPORT_WIFI_CLK_UNUSED_BIT12  BIT(12)
1072 #define DPORT_WIFI_CLK_SDIO_HOST_EN  BIT(13)
1073 #define DPORT_WIFI_CLK_EMAC_EN  BIT(14)
1074 #define DPORT_WIFI_CLK_RNG_EN  BIT(15)
1075 
1076 #define DPORT_CORE_RST_EN_REG          (DR_REG_DPORT_BASE + 0x0D0)
1077 /* DPORT_CORE_RST : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
1078 /*description: */
1079 #define DPORT_RW_BTLP_RST (BIT(10))
1080 #define DPORT_RW_BTMAC_RST (BIT(9))
1081 #define DPORT_MACPWR_RST (BIT(8))
1082 #define DPORT_EMAC_RST (BIT(7))
1083 #define DPORT_SDIO_HOST_RST (BIT(6))
1084 #define DPORT_SDIO_RST (BIT(5))
1085 #define DPORT_BTMAC_RST (BIT(4))
1086 #define DPORT_BT_RST (BIT(3))
1087 #define DPORT_MAC_RST (BIT(2))
1088 #define DPORT_FE_RST (BIT(1))
1089 #define DPORT_BB_RST (BIT(0))
1090 
1091 #define DPORT_BT_LPCK_DIV_INT_REG          (DR_REG_DPORT_BASE + 0x0D4)
1092 /* DPORT_BTEXTWAKEUP_REQ : R/W ;bitpos:[12] ;default: 1'b0 ; */
1093 /*description: */
1094 #define DPORT_BTEXTWAKEUP_REQ  (BIT(12))
1095 #define DPORT_BTEXTWAKEUP_REQ_M  (BIT(12))
1096 #define DPORT_BTEXTWAKEUP_REQ_V  0x1
1097 #define DPORT_BTEXTWAKEUP_REQ_S  12
1098 /* DPORT_BT_LPCK_DIV_NUM : R/W ;bitpos:[11:0] ;default: 12'd255 ; */
1099 /*description: */
1100 #define DPORT_BT_LPCK_DIV_NUM  0x00000FFF
1101 #define DPORT_BT_LPCK_DIV_NUM_M  ((DPORT_BT_LPCK_DIV_NUM_V)<<(DPORT_BT_LPCK_DIV_NUM_S))
1102 #define DPORT_BT_LPCK_DIV_NUM_V  0xFFF
1103 #define DPORT_BT_LPCK_DIV_NUM_S  0
1104 
1105 #define DPORT_BT_LPCK_DIV_FRAC_REG          (DR_REG_DPORT_BASE + 0x0D8)
1106 /* DPORT_LPCLK_SEL_XTAL32K : R/W ;bitpos:[27] ;default: 1'b0 ; */
1107 /*description: */
1108 #define DPORT_LPCLK_SEL_XTAL32K  (BIT(27))
1109 #define DPORT_LPCLK_SEL_XTAL32K_M  (BIT(27))
1110 #define DPORT_LPCLK_SEL_XTAL32K_V  0x1
1111 #define DPORT_LPCLK_SEL_XTAL32K_S  27
1112 /* DPORT_LPCLK_SEL_XTAL : R/W ;bitpos:[26] ;default: 1'b0 ; */
1113 /*description: */
1114 #define DPORT_LPCLK_SEL_XTAL  (BIT(26))
1115 #define DPORT_LPCLK_SEL_XTAL_M  (BIT(26))
1116 #define DPORT_LPCLK_SEL_XTAL_V  0x1
1117 #define DPORT_LPCLK_SEL_XTAL_S  26
1118 /* DPORT_LPCLK_SEL_8M : R/W ;bitpos:[25] ;default: 1'b1 ; */
1119 /*description: */
1120 #define DPORT_LPCLK_SEL_8M  (BIT(25))
1121 #define DPORT_LPCLK_SEL_8M_M  (BIT(25))
1122 #define DPORT_LPCLK_SEL_8M_V  0x1
1123 #define DPORT_LPCLK_SEL_8M_S  25
1124 /* DPORT_LPCLK_SEL_RTC_SLOW : R/W ;bitpos:[24] ;default: 1'b0 ; */
1125 /*description: */
1126 #define DPORT_LPCLK_SEL_RTC_SLOW  (BIT(24))
1127 #define DPORT_LPCLK_SEL_RTC_SLOW_M  (BIT(24))
1128 #define DPORT_LPCLK_SEL_RTC_SLOW_V  0x1
1129 #define DPORT_LPCLK_SEL_RTC_SLOW_S  24
1130 /* DPORT_BT_LPCK_DIV_A : R/W ;bitpos:[23:12] ;default: 12'd1 ; */
1131 /*description: */
1132 #define DPORT_BT_LPCK_DIV_A  0x00000FFF
1133 #define DPORT_BT_LPCK_DIV_A_M  ((DPORT_BT_LPCK_DIV_A_V)<<(DPORT_BT_LPCK_DIV_A_S))
1134 #define DPORT_BT_LPCK_DIV_A_V  0xFFF
1135 #define DPORT_BT_LPCK_DIV_A_S  12
1136 /* DPORT_BT_LPCK_DIV_B : R/W ;bitpos:[11:0] ;default: 12'd1 ; */
1137 /*description: */
1138 #define DPORT_BT_LPCK_DIV_B  0x00000FFF
1139 #define DPORT_BT_LPCK_DIV_B_M  ((DPORT_BT_LPCK_DIV_B_V)<<(DPORT_BT_LPCK_DIV_B_S))
1140 #define DPORT_BT_LPCK_DIV_B_V  0xFFF
1141 #define DPORT_BT_LPCK_DIV_B_S  0
1142 
1143 #define DPORT_CPU_INTR_FROM_CPU_0_REG          (DR_REG_DPORT_BASE + 0x0DC)
1144 /* DPORT_CPU_INTR_FROM_CPU_0 : R/W ;bitpos:[0] ;default: 1'b0 ; */
1145 /*description: */
1146 #define DPORT_CPU_INTR_FROM_CPU_0  (BIT(0))
1147 #define DPORT_CPU_INTR_FROM_CPU_0_M  (BIT(0))
1148 #define DPORT_CPU_INTR_FROM_CPU_0_V  0x1
1149 #define DPORT_CPU_INTR_FROM_CPU_0_S  0
1150 
1151 #define DPORT_CPU_INTR_FROM_CPU_1_REG          (DR_REG_DPORT_BASE + 0x0E0)
1152 /* DPORT_CPU_INTR_FROM_CPU_1 : R/W ;bitpos:[0] ;default: 1'b0 ; */
1153 /*description: */
1154 #define DPORT_CPU_INTR_FROM_CPU_1  (BIT(0))
1155 #define DPORT_CPU_INTR_FROM_CPU_1_M  (BIT(0))
1156 #define DPORT_CPU_INTR_FROM_CPU_1_V  0x1
1157 #define DPORT_CPU_INTR_FROM_CPU_1_S  0
1158 
1159 #define SYSTEM_CPU_INTR_FROM_CPU_2_REG          DPORT_CPU_INTR_FROM_CPU_2_REG
1160 #define SYSTEM_CPU_INTR_FROM_CPU_2              DPORT_CPU_INTR_FROM_CPU_2
1161 #define DPORT_CPU_INTR_FROM_CPU_2_REG          (DR_REG_DPORT_BASE + 0x0E4)
1162 /* DPORT_CPU_INTR_FROM_CPU_2 : R/W ;bitpos:[0] ;default: 1'b0 ; */
1163 /*description: */
1164 #define DPORT_CPU_INTR_FROM_CPU_2  (BIT(0))
1165 #define DPORT_CPU_INTR_FROM_CPU_2_M  (BIT(0))
1166 #define DPORT_CPU_INTR_FROM_CPU_2_V  0x1
1167 #define DPORT_CPU_INTR_FROM_CPU_2_S  0
1168 
1169 #define SYSTEM_CPU_INTR_FROM_CPU_3_REG          DPORT_CPU_INTR_FROM_CPU_3_REG
1170 #define SYSTEM_CPU_INTR_FROM_CPU_3              DPORT_CPU_INTR_FROM_CPU_3
1171 #define DPORT_CPU_INTR_FROM_CPU_3_REG          (DR_REG_DPORT_BASE + 0x0E8)
1172 /* DPORT_CPU_INTR_FROM_CPU_3 : R/W ;bitpos:[0] ;default: 1'b0 ; */
1173 /*description: */
1174 #define DPORT_CPU_INTR_FROM_CPU_3  (BIT(0))
1175 #define DPORT_CPU_INTR_FROM_CPU_3_M  (BIT(0))
1176 #define DPORT_CPU_INTR_FROM_CPU_3_V  0x1
1177 #define DPORT_CPU_INTR_FROM_CPU_3_S  0
1178 
1179 #define DPORT_PRO_INTR_STATUS_0_REG          (DR_REG_DPORT_BASE + 0x0EC)
1180 /* DPORT_PRO_INTR_STATUS_0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
1181 /*description: */
1182 #define DPORT_PRO_INTR_STATUS_0  0xFFFFFFFF
1183 #define DPORT_PRO_INTR_STATUS_0_M  ((DPORT_PRO_INTR_STATUS_0_V)<<(DPORT_PRO_INTR_STATUS_0_S))
1184 #define DPORT_PRO_INTR_STATUS_0_V  0xFFFFFFFF
1185 #define DPORT_PRO_INTR_STATUS_0_S  0
1186 
1187 #define DPORT_PRO_INTR_STATUS_1_REG          (DR_REG_DPORT_BASE + 0x0F0)
1188 /* DPORT_PRO_INTR_STATUS_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
1189 /*description: */
1190 #define DPORT_PRO_INTR_STATUS_1  0xFFFFFFFF
1191 #define DPORT_PRO_INTR_STATUS_1_M  ((DPORT_PRO_INTR_STATUS_1_V)<<(DPORT_PRO_INTR_STATUS_1_S))
1192 #define DPORT_PRO_INTR_STATUS_1_V  0xFFFFFFFF
1193 #define DPORT_PRO_INTR_STATUS_1_S  0
1194 
1195 #define DPORT_PRO_INTR_STATUS_2_REG          (DR_REG_DPORT_BASE + 0x0F4)
1196 /* DPORT_PRO_INTR_STATUS_2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
1197 /*description: */
1198 #define DPORT_PRO_INTR_STATUS_2  0xFFFFFFFF
1199 #define DPORT_PRO_INTR_STATUS_2_M  ((DPORT_PRO_INTR_STATUS_2_V)<<(DPORT_PRO_INTR_STATUS_2_S))
1200 #define DPORT_PRO_INTR_STATUS_2_V  0xFFFFFFFF
1201 #define DPORT_PRO_INTR_STATUS_2_S  0
1202 
1203 #define DPORT_APP_INTR_STATUS_0_REG          (DR_REG_DPORT_BASE + 0x0F8)
1204 /* DPORT_APP_INTR_STATUS_0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
1205 /*description: */
1206 #define DPORT_APP_INTR_STATUS_0  0xFFFFFFFF
1207 #define DPORT_APP_INTR_STATUS_0_M  ((DPORT_APP_INTR_STATUS_0_V)<<(DPORT_APP_INTR_STATUS_0_S))
1208 #define DPORT_APP_INTR_STATUS_0_V  0xFFFFFFFF
1209 #define DPORT_APP_INTR_STATUS_0_S  0
1210 
1211 #define DPORT_APP_INTR_STATUS_1_REG          (DR_REG_DPORT_BASE + 0x0FC)
1212 /* DPORT_APP_INTR_STATUS_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
1213 /*description: */
1214 #define DPORT_APP_INTR_STATUS_1  0xFFFFFFFF
1215 #define DPORT_APP_INTR_STATUS_1_M  ((DPORT_APP_INTR_STATUS_1_V)<<(DPORT_APP_INTR_STATUS_1_S))
1216 #define DPORT_APP_INTR_STATUS_1_V  0xFFFFFFFF
1217 #define DPORT_APP_INTR_STATUS_1_S  0
1218 
1219 #define DPORT_APP_INTR_STATUS_2_REG          (DR_REG_DPORT_BASE + 0x100)
1220 /* DPORT_APP_INTR_STATUS_2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
1221 /*description: */
1222 #define DPORT_APP_INTR_STATUS_2  0xFFFFFFFF
1223 #define DPORT_APP_INTR_STATUS_2_M  ((DPORT_APP_INTR_STATUS_2_V)<<(DPORT_APP_INTR_STATUS_2_S))
1224 #define DPORT_APP_INTR_STATUS_2_V  0xFFFFFFFF
1225 #define DPORT_APP_INTR_STATUS_2_S  0
1226 
1227 #define DPORT_PRO_MAC_INTR_MAP_REG          (DR_REG_DPORT_BASE + 0x104)
1228 /* DPORT_PRO_MAC_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
1229 /*description: */
1230 #define DPORT_PRO_MAC_INTR_MAP  0x0000001F
1231 #define DPORT_PRO_MAC_INTR_MAP_M  ((DPORT_PRO_MAC_INTR_MAP_V)<<(DPORT_PRO_MAC_INTR_MAP_S))
1232 #define DPORT_PRO_MAC_INTR_MAP_V  0x1F
1233 #define DPORT_PRO_MAC_INTR_MAP_S  0
1234 
1235 #define DPORT_PRO_MAC_NMI_MAP_REG          (DR_REG_DPORT_BASE + 0x108)
1236 /* DPORT_PRO_MAC_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
1237 /*description: */
1238 #define DPORT_PRO_MAC_NMI_MAP  0x0000001F
1239 #define DPORT_PRO_MAC_NMI_MAP_M  ((DPORT_PRO_MAC_NMI_MAP_V)<<(DPORT_PRO_MAC_NMI_MAP_S))
1240 #define DPORT_PRO_MAC_NMI_MAP_V  0x1F
1241 #define DPORT_PRO_MAC_NMI_MAP_S  0
1242 
1243 #define DPORT_PRO_BB_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x10C)
1244 /* DPORT_PRO_BB_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
1245 /*description: */
1246 #define DPORT_PRO_BB_INT_MAP  0x0000001F
1247 #define DPORT_PRO_BB_INT_MAP_M  ((DPORT_PRO_BB_INT_MAP_V)<<(DPORT_PRO_BB_INT_MAP_S))
1248 #define DPORT_PRO_BB_INT_MAP_V  0x1F
1249 #define DPORT_PRO_BB_INT_MAP_S  0
1250 
1251 #define DPORT_PRO_BT_MAC_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x110)
1252 /* DPORT_PRO_BT_MAC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
1253 /*description: */
1254 #define DPORT_PRO_BT_MAC_INT_MAP  0x0000001F
1255 #define DPORT_PRO_BT_MAC_INT_MAP_M  ((DPORT_PRO_BT_MAC_INT_MAP_V)<<(DPORT_PRO_BT_MAC_INT_MAP_S))
1256 #define DPORT_PRO_BT_MAC_INT_MAP_V  0x1F
1257 #define DPORT_PRO_BT_MAC_INT_MAP_S  0
1258 
1259 #define DPORT_PRO_BT_BB_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x114)
1260 /* DPORT_PRO_BT_BB_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
1261 /*description: */
1262 #define DPORT_PRO_BT_BB_INT_MAP  0x0000001F
1263 #define DPORT_PRO_BT_BB_INT_MAP_M  ((DPORT_PRO_BT_BB_INT_MAP_V)<<(DPORT_PRO_BT_BB_INT_MAP_S))
1264 #define DPORT_PRO_BT_BB_INT_MAP_V  0x1F
1265 #define DPORT_PRO_BT_BB_INT_MAP_S  0
1266 
1267 #define DPORT_PRO_BT_BB_NMI_MAP_REG          (DR_REG_DPORT_BASE + 0x118)
1268 /* DPORT_PRO_BT_BB_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
1269 /*description: */
1270 #define DPORT_PRO_BT_BB_NMI_MAP  0x0000001F
1271 #define DPORT_PRO_BT_BB_NMI_MAP_M  ((DPORT_PRO_BT_BB_NMI_MAP_V)<<(DPORT_PRO_BT_BB_NMI_MAP_S))
1272 #define DPORT_PRO_BT_BB_NMI_MAP_V  0x1F
1273 #define DPORT_PRO_BT_BB_NMI_MAP_S  0
1274 
1275 #define DPORT_PRO_RWBT_IRQ_MAP_REG          (DR_REG_DPORT_BASE + 0x11C)
1276 /* DPORT_PRO_RWBT_IRQ_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
1277 /*description: */
1278 #define DPORT_PRO_RWBT_IRQ_MAP  0x0000001F
1279 #define DPORT_PRO_RWBT_IRQ_MAP_M  ((DPORT_PRO_RWBT_IRQ_MAP_V)<<(DPORT_PRO_RWBT_IRQ_MAP_S))
1280 #define DPORT_PRO_RWBT_IRQ_MAP_V  0x1F
1281 #define DPORT_PRO_RWBT_IRQ_MAP_S  0
1282 
1283 #define DPORT_PRO_RWBLE_IRQ_MAP_REG          (DR_REG_DPORT_BASE + 0x120)
1284 /* DPORT_PRO_RWBLE_IRQ_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
1285 /*description: */
1286 #define DPORT_PRO_RWBLE_IRQ_MAP  0x0000001F
1287 #define DPORT_PRO_RWBLE_IRQ_MAP_M  ((DPORT_PRO_RWBLE_IRQ_MAP_V)<<(DPORT_PRO_RWBLE_IRQ_MAP_S))
1288 #define DPORT_PRO_RWBLE_IRQ_MAP_V  0x1F
1289 #define DPORT_PRO_RWBLE_IRQ_MAP_S  0
1290 
1291 #define DPORT_PRO_RWBT_NMI_MAP_REG          (DR_REG_DPORT_BASE + 0x124)
1292 /* DPORT_PRO_RWBT_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
1293 /*description: */
1294 #define DPORT_PRO_RWBT_NMI_MAP  0x0000001F
1295 #define DPORT_PRO_RWBT_NMI_MAP_M  ((DPORT_PRO_RWBT_NMI_MAP_V)<<(DPORT_PRO_RWBT_NMI_MAP_S))
1296 #define DPORT_PRO_RWBT_NMI_MAP_V  0x1F
1297 #define DPORT_PRO_RWBT_NMI_MAP_S  0
1298 
1299 #define DPORT_PRO_RWBLE_NMI_MAP_REG          (DR_REG_DPORT_BASE + 0x128)
1300 /* DPORT_PRO_RWBLE_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
1301 /*description: */
1302 #define DPORT_PRO_RWBLE_NMI_MAP  0x0000001F
1303 #define DPORT_PRO_RWBLE_NMI_MAP_M  ((DPORT_PRO_RWBLE_NMI_MAP_V)<<(DPORT_PRO_RWBLE_NMI_MAP_S))
1304 #define DPORT_PRO_RWBLE_NMI_MAP_V  0x1F
1305 #define DPORT_PRO_RWBLE_NMI_MAP_S  0
1306 
1307 #define DPORT_PRO_SLC0_INTR_MAP_REG          (DR_REG_DPORT_BASE + 0x12C)
1308 /* DPORT_PRO_SLC0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
1309 /*description: */
1310 #define DPORT_PRO_SLC0_INTR_MAP  0x0000001F
1311 #define DPORT_PRO_SLC0_INTR_MAP_M  ((DPORT_PRO_SLC0_INTR_MAP_V)<<(DPORT_PRO_SLC0_INTR_MAP_S))
1312 #define DPORT_PRO_SLC0_INTR_MAP_V  0x1F
1313 #define DPORT_PRO_SLC0_INTR_MAP_S  0
1314 
1315 #define DPORT_PRO_SLC1_INTR_MAP_REG          (DR_REG_DPORT_BASE + 0x130)
1316 /* DPORT_PRO_SLC1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
1317 /*description: */
1318 #define DPORT_PRO_SLC1_INTR_MAP  0x0000001F
1319 #define DPORT_PRO_SLC1_INTR_MAP_M  ((DPORT_PRO_SLC1_INTR_MAP_V)<<(DPORT_PRO_SLC1_INTR_MAP_S))
1320 #define DPORT_PRO_SLC1_INTR_MAP_V  0x1F
1321 #define DPORT_PRO_SLC1_INTR_MAP_S  0
1322 
1323 #define DPORT_PRO_UHCI0_INTR_MAP_REG          (DR_REG_DPORT_BASE + 0x134)
1324 /* DPORT_PRO_UHCI0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
1325 /*description: */
1326 #define DPORT_PRO_UHCI0_INTR_MAP  0x0000001F
1327 #define DPORT_PRO_UHCI0_INTR_MAP_M  ((DPORT_PRO_UHCI0_INTR_MAP_V)<<(DPORT_PRO_UHCI0_INTR_MAP_S))
1328 #define DPORT_PRO_UHCI0_INTR_MAP_V  0x1F
1329 #define DPORT_PRO_UHCI0_INTR_MAP_S  0
1330 
1331 #define DPORT_PRO_UHCI1_INTR_MAP_REG          (DR_REG_DPORT_BASE + 0x138)
1332 /* DPORT_PRO_UHCI1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
1333 /*description: */
1334 #define DPORT_PRO_UHCI1_INTR_MAP  0x0000001F
1335 #define DPORT_PRO_UHCI1_INTR_MAP_M  ((DPORT_PRO_UHCI1_INTR_MAP_V)<<(DPORT_PRO_UHCI1_INTR_MAP_S))
1336 #define DPORT_PRO_UHCI1_INTR_MAP_V  0x1F
1337 #define DPORT_PRO_UHCI1_INTR_MAP_S  0
1338 
1339 #define DPORT_PRO_TG_T0_LEVEL_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x13C)
1340 /* DPORT_PRO_TG_T0_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
1341 /*description: */
1342 #define DPORT_PRO_TG_T0_LEVEL_INT_MAP  0x0000001F
1343 #define DPORT_PRO_TG_T0_LEVEL_INT_MAP_M  ((DPORT_PRO_TG_T0_LEVEL_INT_MAP_V)<<(DPORT_PRO_TG_T0_LEVEL_INT_MAP_S))
1344 #define DPORT_PRO_TG_T0_LEVEL_INT_MAP_V  0x1F
1345 #define DPORT_PRO_TG_T0_LEVEL_INT_MAP_S  0
1346 
1347 #define DPORT_PRO_TG_T1_LEVEL_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x140)
1348 /* DPORT_PRO_TG_T1_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
1349 /*description: */
1350 #define DPORT_PRO_TG_T1_LEVEL_INT_MAP  0x0000001F
1351 #define DPORT_PRO_TG_T1_LEVEL_INT_MAP_M  ((DPORT_PRO_TG_T1_LEVEL_INT_MAP_V)<<(DPORT_PRO_TG_T1_LEVEL_INT_MAP_S))
1352 #define DPORT_PRO_TG_T1_LEVEL_INT_MAP_V  0x1F
1353 #define DPORT_PRO_TG_T1_LEVEL_INT_MAP_S  0
1354 
1355 #define DPORT_PRO_TG_WDT_LEVEL_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x144)
1356 /* DPORT_PRO_TG_WDT_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
1357 /*description: */
1358 #define DPORT_PRO_TG_WDT_LEVEL_INT_MAP  0x0000001F
1359 #define DPORT_PRO_TG_WDT_LEVEL_INT_MAP_M  ((DPORT_PRO_TG_WDT_LEVEL_INT_MAP_V)<<(DPORT_PRO_TG_WDT_LEVEL_INT_MAP_S))
1360 #define DPORT_PRO_TG_WDT_LEVEL_INT_MAP_V  0x1F
1361 #define DPORT_PRO_TG_WDT_LEVEL_INT_MAP_S  0
1362 
1363 #define DPORT_PRO_TG_LACT_LEVEL_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x148)
1364 /* DPORT_PRO_TG_LACT_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
1365 /*description: */
1366 #define DPORT_PRO_TG_LACT_LEVEL_INT_MAP  0x0000001F
1367 #define DPORT_PRO_TG_LACT_LEVEL_INT_MAP_M  ((DPORT_PRO_TG_LACT_LEVEL_INT_MAP_V)<<(DPORT_PRO_TG_LACT_LEVEL_INT_MAP_S))
1368 #define DPORT_PRO_TG_LACT_LEVEL_INT_MAP_V  0x1F
1369 #define DPORT_PRO_TG_LACT_LEVEL_INT_MAP_S  0
1370 
1371 #define DPORT_PRO_TG1_T0_LEVEL_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x14C)
1372 /* DPORT_PRO_TG1_T0_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
1373 /*description: */
1374 #define DPORT_PRO_TG1_T0_LEVEL_INT_MAP  0x0000001F
1375 #define DPORT_PRO_TG1_T0_LEVEL_INT_MAP_M  ((DPORT_PRO_TG1_T0_LEVEL_INT_MAP_V)<<(DPORT_PRO_TG1_T0_LEVEL_INT_MAP_S))
1376 #define DPORT_PRO_TG1_T0_LEVEL_INT_MAP_V  0x1F
1377 #define DPORT_PRO_TG1_T0_LEVEL_INT_MAP_S  0
1378 
1379 #define DPORT_PRO_TG1_T1_LEVEL_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x150)
1380 /* DPORT_PRO_TG1_T1_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
1381 /*description: */
1382 #define DPORT_PRO_TG1_T1_LEVEL_INT_MAP  0x0000001F
1383 #define DPORT_PRO_TG1_T1_LEVEL_INT_MAP_M  ((DPORT_PRO_TG1_T1_LEVEL_INT_MAP_V)<<(DPORT_PRO_TG1_T1_LEVEL_INT_MAP_S))
1384 #define DPORT_PRO_TG1_T1_LEVEL_INT_MAP_V  0x1F
1385 #define DPORT_PRO_TG1_T1_LEVEL_INT_MAP_S  0
1386 
1387 #define DPORT_PRO_TG1_WDT_LEVEL_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x154)
1388 /* DPORT_PRO_TG1_WDT_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
1389 /*description: */
1390 #define DPORT_PRO_TG1_WDT_LEVEL_INT_MAP  0x0000001F
1391 #define DPORT_PRO_TG1_WDT_LEVEL_INT_MAP_M  ((DPORT_PRO_TG1_WDT_LEVEL_INT_MAP_V)<<(DPORT_PRO_TG1_WDT_LEVEL_INT_MAP_S))
1392 #define DPORT_PRO_TG1_WDT_LEVEL_INT_MAP_V  0x1F
1393 #define DPORT_PRO_TG1_WDT_LEVEL_INT_MAP_S  0
1394 
1395 #define DPORT_PRO_TG1_LACT_LEVEL_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x158)
1396 /* DPORT_PRO_TG1_LACT_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
1397 /*description: */
1398 #define DPORT_PRO_TG1_LACT_LEVEL_INT_MAP  0x0000001F
1399 #define DPORT_PRO_TG1_LACT_LEVEL_INT_MAP_M  ((DPORT_PRO_TG1_LACT_LEVEL_INT_MAP_V)<<(DPORT_PRO_TG1_LACT_LEVEL_INT_MAP_S))
1400 #define DPORT_PRO_TG1_LACT_LEVEL_INT_MAP_V  0x1F
1401 #define DPORT_PRO_TG1_LACT_LEVEL_INT_MAP_S  0
1402 
1403 #define DPORT_PRO_GPIO_INTERRUPT_MAP_REG          (DR_REG_DPORT_BASE + 0x15C)
1404 /* DPORT_PRO_GPIO_INTERRUPT_PRO_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
1405 /*description: */
1406 #define DPORT_PRO_GPIO_INTERRUPT_PRO_MAP  0x0000001F
1407 #define DPORT_PRO_GPIO_INTERRUPT_PRO_MAP_M  ((DPORT_PRO_GPIO_INTERRUPT_PRO_MAP_V)<<(DPORT_PRO_GPIO_INTERRUPT_PRO_MAP_S))
1408 #define DPORT_PRO_GPIO_INTERRUPT_PRO_MAP_V  0x1F
1409 #define DPORT_PRO_GPIO_INTERRUPT_PRO_MAP_S  0
1410 
1411 #define DPORT_PRO_GPIO_INTERRUPT_NMI_MAP_REG          (DR_REG_DPORT_BASE + 0x160)
1412 /* DPORT_PRO_GPIO_INTERRUPT_PRO_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
1413 /*description: */
1414 #define DPORT_PRO_GPIO_INTERRUPT_PRO_NMI_MAP  0x0000001F
1415 #define DPORT_PRO_GPIO_INTERRUPT_PRO_NMI_MAP_M  ((DPORT_PRO_GPIO_INTERRUPT_PRO_NMI_MAP_V)<<(DPORT_PRO_GPIO_INTERRUPT_PRO_NMI_MAP_S))
1416 #define DPORT_PRO_GPIO_INTERRUPT_PRO_NMI_MAP_V  0x1F
1417 #define DPORT_PRO_GPIO_INTERRUPT_PRO_NMI_MAP_S  0
1418 
1419 #define DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_REG          (DR_REG_DPORT_BASE + 0x164)
1420 /* DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
1421 /*description: */
1422 #define DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP  0x0000001F
1423 #define DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_M  ((DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_V)<<(DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_S))
1424 #define DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_V  0x1F
1425 #define DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_S  0
1426 
1427 #define DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_REG          (DR_REG_DPORT_BASE + 0x168)
1428 /* DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
1429 /*description: */
1430 #define DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP  0x0000001F
1431 #define DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_M  ((DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_V)<<(DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_S))
1432 #define DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_V  0x1F
1433 #define DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_S  0
1434 
1435 #define DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_REG          (DR_REG_DPORT_BASE + 0x16C)
1436 /* DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
1437 /*description: */
1438 #define DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP  0x0000001F
1439 #define DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_M  ((DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_V)<<(DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_S))
1440 #define DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_V  0x1F
1441 #define DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_S  0
1442 
1443 #define DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_REG          (DR_REG_DPORT_BASE + 0x170)
1444 /* DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
1445 /*description: */
1446 #define DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP  0x0000001F
1447 #define DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_M  ((DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_V)<<(DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_S))
1448 #define DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_V  0x1F
1449 #define DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_S  0
1450 
1451 #define DPORT_PRO_SPI_INTR_0_MAP_REG          (DR_REG_DPORT_BASE + 0x174)
1452 /* DPORT_PRO_SPI_INTR_0_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
1453 /*description: */
1454 #define DPORT_PRO_SPI_INTR_0_MAP  0x0000001F
1455 #define DPORT_PRO_SPI_INTR_0_MAP_M  ((DPORT_PRO_SPI_INTR_0_MAP_V)<<(DPORT_PRO_SPI_INTR_0_MAP_S))
1456 #define DPORT_PRO_SPI_INTR_0_MAP_V  0x1F
1457 #define DPORT_PRO_SPI_INTR_0_MAP_S  0
1458 
1459 #define DPORT_PRO_SPI_INTR_1_MAP_REG          (DR_REG_DPORT_BASE + 0x178)
1460 /* DPORT_PRO_SPI_INTR_1_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
1461 /*description: */
1462 #define DPORT_PRO_SPI_INTR_1_MAP  0x0000001F
1463 #define DPORT_PRO_SPI_INTR_1_MAP_M  ((DPORT_PRO_SPI_INTR_1_MAP_V)<<(DPORT_PRO_SPI_INTR_1_MAP_S))
1464 #define DPORT_PRO_SPI_INTR_1_MAP_V  0x1F
1465 #define DPORT_PRO_SPI_INTR_1_MAP_S  0
1466 
1467 #define DPORT_PRO_SPI_INTR_2_MAP_REG          (DR_REG_DPORT_BASE + 0x17C)
1468 /* DPORT_PRO_SPI_INTR_2_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
1469 /*description: */
1470 #define DPORT_PRO_SPI_INTR_2_MAP  0x0000001F
1471 #define DPORT_PRO_SPI_INTR_2_MAP_M  ((DPORT_PRO_SPI_INTR_2_MAP_V)<<(DPORT_PRO_SPI_INTR_2_MAP_S))
1472 #define DPORT_PRO_SPI_INTR_2_MAP_V  0x1F
1473 #define DPORT_PRO_SPI_INTR_2_MAP_S  0
1474 
1475 #define DPORT_PRO_SPI_INTR_3_MAP_REG          (DR_REG_DPORT_BASE + 0x180)
1476 /* DPORT_PRO_SPI_INTR_3_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
1477 /*description: */
1478 #define DPORT_PRO_SPI_INTR_3_MAP  0x0000001F
1479 #define DPORT_PRO_SPI_INTR_3_MAP_M  ((DPORT_PRO_SPI_INTR_3_MAP_V)<<(DPORT_PRO_SPI_INTR_3_MAP_S))
1480 #define DPORT_PRO_SPI_INTR_3_MAP_V  0x1F
1481 #define DPORT_PRO_SPI_INTR_3_MAP_S  0
1482 
1483 #define DPORT_PRO_I2S0_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x184)
1484 /* DPORT_PRO_I2S0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
1485 /*description: */
1486 #define DPORT_PRO_I2S0_INT_MAP  0x0000001F
1487 #define DPORT_PRO_I2S0_INT_MAP_M  ((DPORT_PRO_I2S0_INT_MAP_V)<<(DPORT_PRO_I2S0_INT_MAP_S))
1488 #define DPORT_PRO_I2S0_INT_MAP_V  0x1F
1489 #define DPORT_PRO_I2S0_INT_MAP_S  0
1490 
1491 #define DPORT_PRO_I2S1_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x188)
1492 /* DPORT_PRO_I2S1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
1493 /*description: */
1494 #define DPORT_PRO_I2S1_INT_MAP  0x0000001F
1495 #define DPORT_PRO_I2S1_INT_MAP_M  ((DPORT_PRO_I2S1_INT_MAP_V)<<(DPORT_PRO_I2S1_INT_MAP_S))
1496 #define DPORT_PRO_I2S1_INT_MAP_V  0x1F
1497 #define DPORT_PRO_I2S1_INT_MAP_S  0
1498 
1499 #define DPORT_PRO_UART_INTR_MAP_REG          (DR_REG_DPORT_BASE + 0x18C)
1500 /* DPORT_PRO_UART_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
1501 /*description: */
1502 #define DPORT_PRO_UART_INTR_MAP  0x0000001F
1503 #define DPORT_PRO_UART_INTR_MAP_M  ((DPORT_PRO_UART_INTR_MAP_V)<<(DPORT_PRO_UART_INTR_MAP_S))
1504 #define DPORT_PRO_UART_INTR_MAP_V  0x1F
1505 #define DPORT_PRO_UART_INTR_MAP_S  0
1506 
1507 #define DPORT_PRO_UART1_INTR_MAP_REG          (DR_REG_DPORT_BASE + 0x190)
1508 /* DPORT_PRO_UART1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
1509 /*description: */
1510 #define DPORT_PRO_UART1_INTR_MAP  0x0000001F
1511 #define DPORT_PRO_UART1_INTR_MAP_M  ((DPORT_PRO_UART1_INTR_MAP_V)<<(DPORT_PRO_UART1_INTR_MAP_S))
1512 #define DPORT_PRO_UART1_INTR_MAP_V  0x1F
1513 #define DPORT_PRO_UART1_INTR_MAP_S  0
1514 
1515 #define DPORT_PRO_UART2_INTR_MAP_REG          (DR_REG_DPORT_BASE + 0x194)
1516 /* DPORT_PRO_UART2_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
1517 /*description: */
1518 #define DPORT_PRO_UART2_INTR_MAP  0x0000001F
1519 #define DPORT_PRO_UART2_INTR_MAP_M  ((DPORT_PRO_UART2_INTR_MAP_V)<<(DPORT_PRO_UART2_INTR_MAP_S))
1520 #define DPORT_PRO_UART2_INTR_MAP_V  0x1F
1521 #define DPORT_PRO_UART2_INTR_MAP_S  0
1522 
1523 #define DPORT_PRO_SDIO_HOST_INTERRUPT_MAP_REG          (DR_REG_DPORT_BASE + 0x198)
1524 /* DPORT_PRO_SDIO_HOST_INTERRUPT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
1525 /*description: */
1526 #define DPORT_PRO_SDIO_HOST_INTERRUPT_MAP  0x0000001F
1527 #define DPORT_PRO_SDIO_HOST_INTERRUPT_MAP_M  ((DPORT_PRO_SDIO_HOST_INTERRUPT_MAP_V)<<(DPORT_PRO_SDIO_HOST_INTERRUPT_MAP_S))
1528 #define DPORT_PRO_SDIO_HOST_INTERRUPT_MAP_V  0x1F
1529 #define DPORT_PRO_SDIO_HOST_INTERRUPT_MAP_S  0
1530 
1531 #define DPORT_PRO_EMAC_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x19C)
1532 /* DPORT_PRO_EMAC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
1533 /*description: */
1534 #define DPORT_PRO_EMAC_INT_MAP  0x0000001F
1535 #define DPORT_PRO_EMAC_INT_MAP_M  ((DPORT_PRO_EMAC_INT_MAP_V)<<(DPORT_PRO_EMAC_INT_MAP_S))
1536 #define DPORT_PRO_EMAC_INT_MAP_V  0x1F
1537 #define DPORT_PRO_EMAC_INT_MAP_S  0
1538 
1539 #define DPORT_PRO_PWM0_INTR_MAP_REG          (DR_REG_DPORT_BASE + 0x1A0)
1540 /* DPORT_PRO_PWM0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
1541 /*description: */
1542 #define DPORT_PRO_PWM0_INTR_MAP  0x0000001F
1543 #define DPORT_PRO_PWM0_INTR_MAP_M  ((DPORT_PRO_PWM0_INTR_MAP_V)<<(DPORT_PRO_PWM0_INTR_MAP_S))
1544 #define DPORT_PRO_PWM0_INTR_MAP_V  0x1F
1545 #define DPORT_PRO_PWM0_INTR_MAP_S  0
1546 
1547 #define DPORT_PRO_PWM1_INTR_MAP_REG          (DR_REG_DPORT_BASE + 0x1A4)
1548 /* DPORT_PRO_PWM1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
1549 /*description: */
1550 #define DPORT_PRO_PWM1_INTR_MAP  0x0000001F
1551 #define DPORT_PRO_PWM1_INTR_MAP_M  ((DPORT_PRO_PWM1_INTR_MAP_V)<<(DPORT_PRO_PWM1_INTR_MAP_S))
1552 #define DPORT_PRO_PWM1_INTR_MAP_V  0x1F
1553 #define DPORT_PRO_PWM1_INTR_MAP_S  0
1554 
1555 #define DPORT_PRO_PWM2_INTR_MAP_REG          (DR_REG_DPORT_BASE + 0x1A8)
1556 /* DPORT_PRO_PWM2_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
1557 /*description: */
1558 #define DPORT_PRO_PWM2_INTR_MAP  0x0000001F
1559 #define DPORT_PRO_PWM2_INTR_MAP_M  ((DPORT_PRO_PWM2_INTR_MAP_V)<<(DPORT_PRO_PWM2_INTR_MAP_S))
1560 #define DPORT_PRO_PWM2_INTR_MAP_V  0x1F
1561 #define DPORT_PRO_PWM2_INTR_MAP_S  0
1562 
1563 #define DPORT_PRO_PWM3_INTR_MAP_REG          (DR_REG_DPORT_BASE + 0x1AC)
1564 /* DPORT_PRO_PWM3_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
1565 /*description: */
1566 #define DPORT_PRO_PWM3_INTR_MAP  0x0000001F
1567 #define DPORT_PRO_PWM3_INTR_MAP_M  ((DPORT_PRO_PWM3_INTR_MAP_V)<<(DPORT_PRO_PWM3_INTR_MAP_S))
1568 #define DPORT_PRO_PWM3_INTR_MAP_V  0x1F
1569 #define DPORT_PRO_PWM3_INTR_MAP_S  0
1570 
1571 #define DPORT_PRO_LEDC_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x1B0)
1572 /* DPORT_PRO_LEDC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
1573 /*description: */
1574 #define DPORT_PRO_LEDC_INT_MAP  0x0000001F
1575 #define DPORT_PRO_LEDC_INT_MAP_M  ((DPORT_PRO_LEDC_INT_MAP_V)<<(DPORT_PRO_LEDC_INT_MAP_S))
1576 #define DPORT_PRO_LEDC_INT_MAP_V  0x1F
1577 #define DPORT_PRO_LEDC_INT_MAP_S  0
1578 
1579 #define DPORT_PRO_EFUSE_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x1B4)
1580 /* DPORT_PRO_EFUSE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
1581 /*description: */
1582 #define DPORT_PRO_EFUSE_INT_MAP  0x0000001F
1583 #define DPORT_PRO_EFUSE_INT_MAP_M  ((DPORT_PRO_EFUSE_INT_MAP_V)<<(DPORT_PRO_EFUSE_INT_MAP_S))
1584 #define DPORT_PRO_EFUSE_INT_MAP_V  0x1F
1585 #define DPORT_PRO_EFUSE_INT_MAP_S  0
1586 
1587 #define DPORT_PRO_CAN_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x1B8)
1588 /* DPORT_PRO_CAN_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
1589 /*description: */
1590 #define DPORT_PRO_CAN_INT_MAP  0x0000001F
1591 #define DPORT_PRO_CAN_INT_MAP_M  ((DPORT_PRO_CAN_INT_MAP_V)<<(DPORT_PRO_CAN_INT_MAP_S))
1592 #define DPORT_PRO_CAN_INT_MAP_V  0x1F
1593 #define DPORT_PRO_CAN_INT_MAP_S  0
1594 
1595 #define DPORT_PRO_RTC_CORE_INTR_MAP_REG          (DR_REG_DPORT_BASE + 0x1BC)
1596 /* DPORT_PRO_RTC_CORE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
1597 /*description: */
1598 #define DPORT_PRO_RTC_CORE_INTR_MAP  0x0000001F
1599 #define DPORT_PRO_RTC_CORE_INTR_MAP_M  ((DPORT_PRO_RTC_CORE_INTR_MAP_V)<<(DPORT_PRO_RTC_CORE_INTR_MAP_S))
1600 #define DPORT_PRO_RTC_CORE_INTR_MAP_V  0x1F
1601 #define DPORT_PRO_RTC_CORE_INTR_MAP_S  0
1602 
1603 #define DPORT_PRO_RMT_INTR_MAP_REG          (DR_REG_DPORT_BASE + 0x1C0)
1604 /* DPORT_PRO_RMT_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
1605 /*description: */
1606 #define DPORT_PRO_RMT_INTR_MAP  0x0000001F
1607 #define DPORT_PRO_RMT_INTR_MAP_M  ((DPORT_PRO_RMT_INTR_MAP_V)<<(DPORT_PRO_RMT_INTR_MAP_S))
1608 #define DPORT_PRO_RMT_INTR_MAP_V  0x1F
1609 #define DPORT_PRO_RMT_INTR_MAP_S  0
1610 
1611 #define DPORT_PRO_PCNT_INTR_MAP_REG          (DR_REG_DPORT_BASE + 0x1C4)
1612 /* DPORT_PRO_PCNT_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
1613 /*description: */
1614 #define DPORT_PRO_PCNT_INTR_MAP  0x0000001F
1615 #define DPORT_PRO_PCNT_INTR_MAP_M  ((DPORT_PRO_PCNT_INTR_MAP_V)<<(DPORT_PRO_PCNT_INTR_MAP_S))
1616 #define DPORT_PRO_PCNT_INTR_MAP_V  0x1F
1617 #define DPORT_PRO_PCNT_INTR_MAP_S  0
1618 
1619 #define DPORT_PRO_I2C_EXT0_INTR_MAP_REG          (DR_REG_DPORT_BASE + 0x1C8)
1620 /* DPORT_PRO_I2C_EXT0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
1621 /*description: */
1622 #define DPORT_PRO_I2C_EXT0_INTR_MAP  0x0000001F
1623 #define DPORT_PRO_I2C_EXT0_INTR_MAP_M  ((DPORT_PRO_I2C_EXT0_INTR_MAP_V)<<(DPORT_PRO_I2C_EXT0_INTR_MAP_S))
1624 #define DPORT_PRO_I2C_EXT0_INTR_MAP_V  0x1F
1625 #define DPORT_PRO_I2C_EXT0_INTR_MAP_S  0
1626 
1627 #define DPORT_PRO_I2C_EXT1_INTR_MAP_REG          (DR_REG_DPORT_BASE + 0x1CC)
1628 /* DPORT_PRO_I2C_EXT1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
1629 /*description: */
1630 #define DPORT_PRO_I2C_EXT1_INTR_MAP  0x0000001F
1631 #define DPORT_PRO_I2C_EXT1_INTR_MAP_M  ((DPORT_PRO_I2C_EXT1_INTR_MAP_V)<<(DPORT_PRO_I2C_EXT1_INTR_MAP_S))
1632 #define DPORT_PRO_I2C_EXT1_INTR_MAP_V  0x1F
1633 #define DPORT_PRO_I2C_EXT1_INTR_MAP_S  0
1634 
1635 #define DPORT_PRO_RSA_INTR_MAP_REG          (DR_REG_DPORT_BASE + 0x1D0)
1636 /* DPORT_PRO_RSA_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
1637 /*description: */
1638 #define DPORT_PRO_RSA_INTR_MAP  0x0000001F
1639 #define DPORT_PRO_RSA_INTR_MAP_M  ((DPORT_PRO_RSA_INTR_MAP_V)<<(DPORT_PRO_RSA_INTR_MAP_S))
1640 #define DPORT_PRO_RSA_INTR_MAP_V  0x1F
1641 #define DPORT_PRO_RSA_INTR_MAP_S  0
1642 
1643 #define DPORT_PRO_SPI1_DMA_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x1D4)
1644 /* DPORT_PRO_SPI1_DMA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
1645 /*description: */
1646 #define DPORT_PRO_SPI1_DMA_INT_MAP  0x0000001F
1647 #define DPORT_PRO_SPI1_DMA_INT_MAP_M  ((DPORT_PRO_SPI1_DMA_INT_MAP_V)<<(DPORT_PRO_SPI1_DMA_INT_MAP_S))
1648 #define DPORT_PRO_SPI1_DMA_INT_MAP_V  0x1F
1649 #define DPORT_PRO_SPI1_DMA_INT_MAP_S  0
1650 
1651 #define DPORT_PRO_SPI2_DMA_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x1D8)
1652 /* DPORT_PRO_SPI2_DMA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
1653 /*description: */
1654 #define DPORT_PRO_SPI2_DMA_INT_MAP  0x0000001F
1655 #define DPORT_PRO_SPI2_DMA_INT_MAP_M  ((DPORT_PRO_SPI2_DMA_INT_MAP_V)<<(DPORT_PRO_SPI2_DMA_INT_MAP_S))
1656 #define DPORT_PRO_SPI2_DMA_INT_MAP_V  0x1F
1657 #define DPORT_PRO_SPI2_DMA_INT_MAP_S  0
1658 
1659 #define DPORT_PRO_SPI3_DMA_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x1DC)
1660 /* DPORT_PRO_SPI3_DMA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
1661 /*description: */
1662 #define DPORT_PRO_SPI3_DMA_INT_MAP  0x0000001F
1663 #define DPORT_PRO_SPI3_DMA_INT_MAP_M  ((DPORT_PRO_SPI3_DMA_INT_MAP_V)<<(DPORT_PRO_SPI3_DMA_INT_MAP_S))
1664 #define DPORT_PRO_SPI3_DMA_INT_MAP_V  0x1F
1665 #define DPORT_PRO_SPI3_DMA_INT_MAP_S  0
1666 
1667 #define DPORT_PRO_WDG_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x1E0)
1668 /* DPORT_PRO_WDG_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
1669 /*description: */
1670 #define DPORT_PRO_WDG_INT_MAP  0x0000001F
1671 #define DPORT_PRO_WDG_INT_MAP_M  ((DPORT_PRO_WDG_INT_MAP_V)<<(DPORT_PRO_WDG_INT_MAP_S))
1672 #define DPORT_PRO_WDG_INT_MAP_V  0x1F
1673 #define DPORT_PRO_WDG_INT_MAP_S  0
1674 
1675 #define DPORT_PRO_TIMER_INT1_MAP_REG          (DR_REG_DPORT_BASE + 0x1E4)
1676 /* DPORT_PRO_TIMER_INT1_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
1677 /*description: */
1678 #define DPORT_PRO_TIMER_INT1_MAP  0x0000001F
1679 #define DPORT_PRO_TIMER_INT1_MAP_M  ((DPORT_PRO_TIMER_INT1_MAP_V)<<(DPORT_PRO_TIMER_INT1_MAP_S))
1680 #define DPORT_PRO_TIMER_INT1_MAP_V  0x1F
1681 #define DPORT_PRO_TIMER_INT1_MAP_S  0
1682 
1683 #define DPORT_PRO_TIMER_INT2_MAP_REG          (DR_REG_DPORT_BASE + 0x1E8)
1684 /* DPORT_PRO_TIMER_INT2_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
1685 /*description: */
1686 #define DPORT_PRO_TIMER_INT2_MAP  0x0000001F
1687 #define DPORT_PRO_TIMER_INT2_MAP_M  ((DPORT_PRO_TIMER_INT2_MAP_V)<<(DPORT_PRO_TIMER_INT2_MAP_S))
1688 #define DPORT_PRO_TIMER_INT2_MAP_V  0x1F
1689 #define DPORT_PRO_TIMER_INT2_MAP_S  0
1690 
1691 #define DPORT_PRO_TG_T0_EDGE_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x1EC)
1692 /* DPORT_PRO_TG_T0_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
1693 /*description: */
1694 #define DPORT_PRO_TG_T0_EDGE_INT_MAP  0x0000001F
1695 #define DPORT_PRO_TG_T0_EDGE_INT_MAP_M  ((DPORT_PRO_TG_T0_EDGE_INT_MAP_V)<<(DPORT_PRO_TG_T0_EDGE_INT_MAP_S))
1696 #define DPORT_PRO_TG_T0_EDGE_INT_MAP_V  0x1F
1697 #define DPORT_PRO_TG_T0_EDGE_INT_MAP_S  0
1698 
1699 #define DPORT_PRO_TG_T1_EDGE_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x1F0)
1700 /* DPORT_PRO_TG_T1_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
1701 /*description: */
1702 #define DPORT_PRO_TG_T1_EDGE_INT_MAP  0x0000001F
1703 #define DPORT_PRO_TG_T1_EDGE_INT_MAP_M  ((DPORT_PRO_TG_T1_EDGE_INT_MAP_V)<<(DPORT_PRO_TG_T1_EDGE_INT_MAP_S))
1704 #define DPORT_PRO_TG_T1_EDGE_INT_MAP_V  0x1F
1705 #define DPORT_PRO_TG_T1_EDGE_INT_MAP_S  0
1706 
1707 #define DPORT_PRO_TG_WDT_EDGE_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x1F4)
1708 /* DPORT_PRO_TG_WDT_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
1709 /*description: */
1710 #define DPORT_PRO_TG_WDT_EDGE_INT_MAP  0x0000001F
1711 #define DPORT_PRO_TG_WDT_EDGE_INT_MAP_M  ((DPORT_PRO_TG_WDT_EDGE_INT_MAP_V)<<(DPORT_PRO_TG_WDT_EDGE_INT_MAP_S))
1712 #define DPORT_PRO_TG_WDT_EDGE_INT_MAP_V  0x1F
1713 #define DPORT_PRO_TG_WDT_EDGE_INT_MAP_S  0
1714 
1715 #define DPORT_PRO_TG_LACT_EDGE_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x1F8)
1716 /* DPORT_PRO_TG_LACT_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
1717 /*description: */
1718 #define DPORT_PRO_TG_LACT_EDGE_INT_MAP  0x0000001F
1719 #define DPORT_PRO_TG_LACT_EDGE_INT_MAP_M  ((DPORT_PRO_TG_LACT_EDGE_INT_MAP_V)<<(DPORT_PRO_TG_LACT_EDGE_INT_MAP_S))
1720 #define DPORT_PRO_TG_LACT_EDGE_INT_MAP_V  0x1F
1721 #define DPORT_PRO_TG_LACT_EDGE_INT_MAP_S  0
1722 
1723 #define DPORT_PRO_TG1_T0_EDGE_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x1FC)
1724 /* DPORT_PRO_TG1_T0_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
1725 /*description: */
1726 #define DPORT_PRO_TG1_T0_EDGE_INT_MAP  0x0000001F
1727 #define DPORT_PRO_TG1_T0_EDGE_INT_MAP_M  ((DPORT_PRO_TG1_T0_EDGE_INT_MAP_V)<<(DPORT_PRO_TG1_T0_EDGE_INT_MAP_S))
1728 #define DPORT_PRO_TG1_T0_EDGE_INT_MAP_V  0x1F
1729 #define DPORT_PRO_TG1_T0_EDGE_INT_MAP_S  0
1730 
1731 #define DPORT_PRO_TG1_T1_EDGE_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x200)
1732 /* DPORT_PRO_TG1_T1_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
1733 /*description: */
1734 #define DPORT_PRO_TG1_T1_EDGE_INT_MAP  0x0000001F
1735 #define DPORT_PRO_TG1_T1_EDGE_INT_MAP_M  ((DPORT_PRO_TG1_T1_EDGE_INT_MAP_V)<<(DPORT_PRO_TG1_T1_EDGE_INT_MAP_S))
1736 #define DPORT_PRO_TG1_T1_EDGE_INT_MAP_V  0x1F
1737 #define DPORT_PRO_TG1_T1_EDGE_INT_MAP_S  0
1738 
1739 #define DPORT_PRO_TG1_WDT_EDGE_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x204)
1740 /* DPORT_PRO_TG1_WDT_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
1741 /*description: */
1742 #define DPORT_PRO_TG1_WDT_EDGE_INT_MAP  0x0000001F
1743 #define DPORT_PRO_TG1_WDT_EDGE_INT_MAP_M  ((DPORT_PRO_TG1_WDT_EDGE_INT_MAP_V)<<(DPORT_PRO_TG1_WDT_EDGE_INT_MAP_S))
1744 #define DPORT_PRO_TG1_WDT_EDGE_INT_MAP_V  0x1F
1745 #define DPORT_PRO_TG1_WDT_EDGE_INT_MAP_S  0
1746 
1747 #define DPORT_PRO_TG1_LACT_EDGE_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x208)
1748 /* DPORT_PRO_TG1_LACT_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
1749 /*description: */
1750 #define DPORT_PRO_TG1_LACT_EDGE_INT_MAP  0x0000001F
1751 #define DPORT_PRO_TG1_LACT_EDGE_INT_MAP_M  ((DPORT_PRO_TG1_LACT_EDGE_INT_MAP_V)<<(DPORT_PRO_TG1_LACT_EDGE_INT_MAP_S))
1752 #define DPORT_PRO_TG1_LACT_EDGE_INT_MAP_V  0x1F
1753 #define DPORT_PRO_TG1_LACT_EDGE_INT_MAP_S  0
1754 
1755 #define DPORT_PRO_MMU_IA_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x20C)
1756 /* DPORT_PRO_MMU_IA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
1757 /*description: */
1758 #define DPORT_PRO_MMU_IA_INT_MAP  0x0000001F
1759 #define DPORT_PRO_MMU_IA_INT_MAP_M  ((DPORT_PRO_MMU_IA_INT_MAP_V)<<(DPORT_PRO_MMU_IA_INT_MAP_S))
1760 #define DPORT_PRO_MMU_IA_INT_MAP_V  0x1F
1761 #define DPORT_PRO_MMU_IA_INT_MAP_S  0
1762 
1763 #define DPORT_PRO_MPU_IA_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x210)
1764 /* DPORT_PRO_MPU_IA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
1765 /*description: */
1766 #define DPORT_PRO_MPU_IA_INT_MAP  0x0000001F
1767 #define DPORT_PRO_MPU_IA_INT_MAP_M  ((DPORT_PRO_MPU_IA_INT_MAP_V)<<(DPORT_PRO_MPU_IA_INT_MAP_S))
1768 #define DPORT_PRO_MPU_IA_INT_MAP_V  0x1F
1769 #define DPORT_PRO_MPU_IA_INT_MAP_S  0
1770 
1771 #define DPORT_PRO_CACHE_IA_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x214)
1772 /* DPORT_PRO_CACHE_IA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
1773 /*description: */
1774 #define DPORT_PRO_CACHE_IA_INT_MAP  0x0000001F
1775 #define DPORT_PRO_CACHE_IA_INT_MAP_M  ((DPORT_PRO_CACHE_IA_INT_MAP_V)<<(DPORT_PRO_CACHE_IA_INT_MAP_S))
1776 #define DPORT_PRO_CACHE_IA_INT_MAP_V  0x1F
1777 #define DPORT_PRO_CACHE_IA_INT_MAP_S  0
1778 
1779 #define DPORT_APP_MAC_INTR_MAP_REG          (DR_REG_DPORT_BASE + 0x218)
1780 /* DPORT_APP_MAC_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
1781 /*description: */
1782 #define DPORT_APP_MAC_INTR_MAP  0x0000001F
1783 #define DPORT_APP_MAC_INTR_MAP_M  ((DPORT_APP_MAC_INTR_MAP_V)<<(DPORT_APP_MAC_INTR_MAP_S))
1784 #define DPORT_APP_MAC_INTR_MAP_V  0x1F
1785 #define DPORT_APP_MAC_INTR_MAP_S  0
1786 
1787 #define DPORT_APP_MAC_NMI_MAP_REG          (DR_REG_DPORT_BASE + 0x21C)
1788 /* DPORT_APP_MAC_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
1789 /*description: */
1790 #define DPORT_APP_MAC_NMI_MAP  0x0000001F
1791 #define DPORT_APP_MAC_NMI_MAP_M  ((DPORT_APP_MAC_NMI_MAP_V)<<(DPORT_APP_MAC_NMI_MAP_S))
1792 #define DPORT_APP_MAC_NMI_MAP_V  0x1F
1793 #define DPORT_APP_MAC_NMI_MAP_S  0
1794 
1795 #define DPORT_APP_BB_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x220)
1796 /* DPORT_APP_BB_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
1797 /*description: */
1798 #define DPORT_APP_BB_INT_MAP  0x0000001F
1799 #define DPORT_APP_BB_INT_MAP_M  ((DPORT_APP_BB_INT_MAP_V)<<(DPORT_APP_BB_INT_MAP_S))
1800 #define DPORT_APP_BB_INT_MAP_V  0x1F
1801 #define DPORT_APP_BB_INT_MAP_S  0
1802 
1803 #define DPORT_APP_BT_MAC_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x224)
1804 /* DPORT_APP_BT_MAC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
1805 /*description: */
1806 #define DPORT_APP_BT_MAC_INT_MAP  0x0000001F
1807 #define DPORT_APP_BT_MAC_INT_MAP_M  ((DPORT_APP_BT_MAC_INT_MAP_V)<<(DPORT_APP_BT_MAC_INT_MAP_S))
1808 #define DPORT_APP_BT_MAC_INT_MAP_V  0x1F
1809 #define DPORT_APP_BT_MAC_INT_MAP_S  0
1810 
1811 #define DPORT_APP_BT_BB_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x228)
1812 /* DPORT_APP_BT_BB_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
1813 /*description: */
1814 #define DPORT_APP_BT_BB_INT_MAP  0x0000001F
1815 #define DPORT_APP_BT_BB_INT_MAP_M  ((DPORT_APP_BT_BB_INT_MAP_V)<<(DPORT_APP_BT_BB_INT_MAP_S))
1816 #define DPORT_APP_BT_BB_INT_MAP_V  0x1F
1817 #define DPORT_APP_BT_BB_INT_MAP_S  0
1818 
1819 #define DPORT_APP_BT_BB_NMI_MAP_REG          (DR_REG_DPORT_BASE + 0x22C)
1820 /* DPORT_APP_BT_BB_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
1821 /*description: */
1822 #define DPORT_APP_BT_BB_NMI_MAP  0x0000001F
1823 #define DPORT_APP_BT_BB_NMI_MAP_M  ((DPORT_APP_BT_BB_NMI_MAP_V)<<(DPORT_APP_BT_BB_NMI_MAP_S))
1824 #define DPORT_APP_BT_BB_NMI_MAP_V  0x1F
1825 #define DPORT_APP_BT_BB_NMI_MAP_S  0
1826 
1827 #define DPORT_APP_RWBT_IRQ_MAP_REG          (DR_REG_DPORT_BASE + 0x230)
1828 /* DPORT_APP_RWBT_IRQ_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
1829 /*description: */
1830 #define DPORT_APP_RWBT_IRQ_MAP  0x0000001F
1831 #define DPORT_APP_RWBT_IRQ_MAP_M  ((DPORT_APP_RWBT_IRQ_MAP_V)<<(DPORT_APP_RWBT_IRQ_MAP_S))
1832 #define DPORT_APP_RWBT_IRQ_MAP_V  0x1F
1833 #define DPORT_APP_RWBT_IRQ_MAP_S  0
1834 
1835 #define DPORT_APP_RWBLE_IRQ_MAP_REG          (DR_REG_DPORT_BASE + 0x234)
1836 /* DPORT_APP_RWBLE_IRQ_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
1837 /*description: */
1838 #define DPORT_APP_RWBLE_IRQ_MAP  0x0000001F
1839 #define DPORT_APP_RWBLE_IRQ_MAP_M  ((DPORT_APP_RWBLE_IRQ_MAP_V)<<(DPORT_APP_RWBLE_IRQ_MAP_S))
1840 #define DPORT_APP_RWBLE_IRQ_MAP_V  0x1F
1841 #define DPORT_APP_RWBLE_IRQ_MAP_S  0
1842 
1843 #define DPORT_APP_RWBT_NMI_MAP_REG          (DR_REG_DPORT_BASE + 0x238)
1844 /* DPORT_APP_RWBT_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
1845 /*description: */
1846 #define DPORT_APP_RWBT_NMI_MAP  0x0000001F
1847 #define DPORT_APP_RWBT_NMI_MAP_M  ((DPORT_APP_RWBT_NMI_MAP_V)<<(DPORT_APP_RWBT_NMI_MAP_S))
1848 #define DPORT_APP_RWBT_NMI_MAP_V  0x1F
1849 #define DPORT_APP_RWBT_NMI_MAP_S  0
1850 
1851 #define DPORT_APP_RWBLE_NMI_MAP_REG          (DR_REG_DPORT_BASE + 0x23C)
1852 /* DPORT_APP_RWBLE_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
1853 /*description: */
1854 #define DPORT_APP_RWBLE_NMI_MAP  0x0000001F
1855 #define DPORT_APP_RWBLE_NMI_MAP_M  ((DPORT_APP_RWBLE_NMI_MAP_V)<<(DPORT_APP_RWBLE_NMI_MAP_S))
1856 #define DPORT_APP_RWBLE_NMI_MAP_V  0x1F
1857 #define DPORT_APP_RWBLE_NMI_MAP_S  0
1858 
1859 #define DPORT_APP_SLC0_INTR_MAP_REG          (DR_REG_DPORT_BASE + 0x240)
1860 /* DPORT_APP_SLC0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
1861 /*description: */
1862 #define DPORT_APP_SLC0_INTR_MAP  0x0000001F
1863 #define DPORT_APP_SLC0_INTR_MAP_M  ((DPORT_APP_SLC0_INTR_MAP_V)<<(DPORT_APP_SLC0_INTR_MAP_S))
1864 #define DPORT_APP_SLC0_INTR_MAP_V  0x1F
1865 #define DPORT_APP_SLC0_INTR_MAP_S  0
1866 
1867 #define DPORT_APP_SLC1_INTR_MAP_REG          (DR_REG_DPORT_BASE + 0x244)
1868 /* DPORT_APP_SLC1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
1869 /*description: */
1870 #define DPORT_APP_SLC1_INTR_MAP  0x0000001F
1871 #define DPORT_APP_SLC1_INTR_MAP_M  ((DPORT_APP_SLC1_INTR_MAP_V)<<(DPORT_APP_SLC1_INTR_MAP_S))
1872 #define DPORT_APP_SLC1_INTR_MAP_V  0x1F
1873 #define DPORT_APP_SLC1_INTR_MAP_S  0
1874 
1875 #define DPORT_APP_UHCI0_INTR_MAP_REG          (DR_REG_DPORT_BASE + 0x248)
1876 /* DPORT_APP_UHCI0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
1877 /*description: */
1878 #define DPORT_APP_UHCI0_INTR_MAP  0x0000001F
1879 #define DPORT_APP_UHCI0_INTR_MAP_M  ((DPORT_APP_UHCI0_INTR_MAP_V)<<(DPORT_APP_UHCI0_INTR_MAP_S))
1880 #define DPORT_APP_UHCI0_INTR_MAP_V  0x1F
1881 #define DPORT_APP_UHCI0_INTR_MAP_S  0
1882 
1883 #define DPORT_APP_UHCI1_INTR_MAP_REG          (DR_REG_DPORT_BASE + 0x24C)
1884 /* DPORT_APP_UHCI1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
1885 /*description: */
1886 #define DPORT_APP_UHCI1_INTR_MAP  0x0000001F
1887 #define DPORT_APP_UHCI1_INTR_MAP_M  ((DPORT_APP_UHCI1_INTR_MAP_V)<<(DPORT_APP_UHCI1_INTR_MAP_S))
1888 #define DPORT_APP_UHCI1_INTR_MAP_V  0x1F
1889 #define DPORT_APP_UHCI1_INTR_MAP_S  0
1890 
1891 #define DPORT_APP_TG_T0_LEVEL_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x250)
1892 /* DPORT_APP_TG_T0_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
1893 /*description: */
1894 #define DPORT_APP_TG_T0_LEVEL_INT_MAP  0x0000001F
1895 #define DPORT_APP_TG_T0_LEVEL_INT_MAP_M  ((DPORT_APP_TG_T0_LEVEL_INT_MAP_V)<<(DPORT_APP_TG_T0_LEVEL_INT_MAP_S))
1896 #define DPORT_APP_TG_T0_LEVEL_INT_MAP_V  0x1F
1897 #define DPORT_APP_TG_T0_LEVEL_INT_MAP_S  0
1898 
1899 #define DPORT_APP_TG_T1_LEVEL_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x254)
1900 /* DPORT_APP_TG_T1_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
1901 /*description: */
1902 #define DPORT_APP_TG_T1_LEVEL_INT_MAP  0x0000001F
1903 #define DPORT_APP_TG_T1_LEVEL_INT_MAP_M  ((DPORT_APP_TG_T1_LEVEL_INT_MAP_V)<<(DPORT_APP_TG_T1_LEVEL_INT_MAP_S))
1904 #define DPORT_APP_TG_T1_LEVEL_INT_MAP_V  0x1F
1905 #define DPORT_APP_TG_T1_LEVEL_INT_MAP_S  0
1906 
1907 #define DPORT_APP_TG_WDT_LEVEL_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x258)
1908 /* DPORT_APP_TG_WDT_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
1909 /*description: */
1910 #define DPORT_APP_TG_WDT_LEVEL_INT_MAP  0x0000001F
1911 #define DPORT_APP_TG_WDT_LEVEL_INT_MAP_M  ((DPORT_APP_TG_WDT_LEVEL_INT_MAP_V)<<(DPORT_APP_TG_WDT_LEVEL_INT_MAP_S))
1912 #define DPORT_APP_TG_WDT_LEVEL_INT_MAP_V  0x1F
1913 #define DPORT_APP_TG_WDT_LEVEL_INT_MAP_S  0
1914 
1915 #define DPORT_APP_TG_LACT_LEVEL_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x25C)
1916 /* DPORT_APP_TG_LACT_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
1917 /*description: */
1918 #define DPORT_APP_TG_LACT_LEVEL_INT_MAP  0x0000001F
1919 #define DPORT_APP_TG_LACT_LEVEL_INT_MAP_M  ((DPORT_APP_TG_LACT_LEVEL_INT_MAP_V)<<(DPORT_APP_TG_LACT_LEVEL_INT_MAP_S))
1920 #define DPORT_APP_TG_LACT_LEVEL_INT_MAP_V  0x1F
1921 #define DPORT_APP_TG_LACT_LEVEL_INT_MAP_S  0
1922 
1923 #define DPORT_APP_TG1_T0_LEVEL_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x260)
1924 /* DPORT_APP_TG1_T0_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
1925 /*description: */
1926 #define DPORT_APP_TG1_T0_LEVEL_INT_MAP  0x0000001F
1927 #define DPORT_APP_TG1_T0_LEVEL_INT_MAP_M  ((DPORT_APP_TG1_T0_LEVEL_INT_MAP_V)<<(DPORT_APP_TG1_T0_LEVEL_INT_MAP_S))
1928 #define DPORT_APP_TG1_T0_LEVEL_INT_MAP_V  0x1F
1929 #define DPORT_APP_TG1_T0_LEVEL_INT_MAP_S  0
1930 
1931 #define DPORT_APP_TG1_T1_LEVEL_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x264)
1932 /* DPORT_APP_TG1_T1_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
1933 /*description: */
1934 #define DPORT_APP_TG1_T1_LEVEL_INT_MAP  0x0000001F
1935 #define DPORT_APP_TG1_T1_LEVEL_INT_MAP_M  ((DPORT_APP_TG1_T1_LEVEL_INT_MAP_V)<<(DPORT_APP_TG1_T1_LEVEL_INT_MAP_S))
1936 #define DPORT_APP_TG1_T1_LEVEL_INT_MAP_V  0x1F
1937 #define DPORT_APP_TG1_T1_LEVEL_INT_MAP_S  0
1938 
1939 #define DPORT_APP_TG1_WDT_LEVEL_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x268)
1940 /* DPORT_APP_TG1_WDT_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
1941 /*description: */
1942 #define DPORT_APP_TG1_WDT_LEVEL_INT_MAP  0x0000001F
1943 #define DPORT_APP_TG1_WDT_LEVEL_INT_MAP_M  ((DPORT_APP_TG1_WDT_LEVEL_INT_MAP_V)<<(DPORT_APP_TG1_WDT_LEVEL_INT_MAP_S))
1944 #define DPORT_APP_TG1_WDT_LEVEL_INT_MAP_V  0x1F
1945 #define DPORT_APP_TG1_WDT_LEVEL_INT_MAP_S  0
1946 
1947 #define DPORT_APP_TG1_LACT_LEVEL_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x26C)
1948 /* DPORT_APP_TG1_LACT_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
1949 /*description: */
1950 #define DPORT_APP_TG1_LACT_LEVEL_INT_MAP  0x0000001F
1951 #define DPORT_APP_TG1_LACT_LEVEL_INT_MAP_M  ((DPORT_APP_TG1_LACT_LEVEL_INT_MAP_V)<<(DPORT_APP_TG1_LACT_LEVEL_INT_MAP_S))
1952 #define DPORT_APP_TG1_LACT_LEVEL_INT_MAP_V  0x1F
1953 #define DPORT_APP_TG1_LACT_LEVEL_INT_MAP_S  0
1954 
1955 #define DPORT_APP_GPIO_INTERRUPT_MAP_REG          (DR_REG_DPORT_BASE + 0x270)
1956 /* DPORT_APP_GPIO_INTERRUPT_APP_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
1957 /*description: */
1958 #define DPORT_APP_GPIO_INTERRUPT_APP_MAP  0x0000001F
1959 #define DPORT_APP_GPIO_INTERRUPT_APP_MAP_M  ((DPORT_APP_GPIO_INTERRUPT_APP_MAP_V)<<(DPORT_APP_GPIO_INTERRUPT_APP_MAP_S))
1960 #define DPORT_APP_GPIO_INTERRUPT_APP_MAP_V  0x1F
1961 #define DPORT_APP_GPIO_INTERRUPT_APP_MAP_S  0
1962 
1963 #define DPORT_APP_GPIO_INTERRUPT_NMI_MAP_REG          (DR_REG_DPORT_BASE + 0x274)
1964 /* DPORT_APP_GPIO_INTERRUPT_APP_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
1965 /*description: */
1966 #define DPORT_APP_GPIO_INTERRUPT_APP_NMI_MAP  0x0000001F
1967 #define DPORT_APP_GPIO_INTERRUPT_APP_NMI_MAP_M  ((DPORT_APP_GPIO_INTERRUPT_APP_NMI_MAP_V)<<(DPORT_APP_GPIO_INTERRUPT_APP_NMI_MAP_S))
1968 #define DPORT_APP_GPIO_INTERRUPT_APP_NMI_MAP_V  0x1F
1969 #define DPORT_APP_GPIO_INTERRUPT_APP_NMI_MAP_S  0
1970 
1971 #define DPORT_APP_CPU_INTR_FROM_CPU_0_MAP_REG          (DR_REG_DPORT_BASE + 0x278)
1972 /* DPORT_APP_CPU_INTR_FROM_CPU_0_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
1973 /*description: */
1974 #define DPORT_APP_CPU_INTR_FROM_CPU_0_MAP  0x0000001F
1975 #define DPORT_APP_CPU_INTR_FROM_CPU_0_MAP_M  ((DPORT_APP_CPU_INTR_FROM_CPU_0_MAP_V)<<(DPORT_APP_CPU_INTR_FROM_CPU_0_MAP_S))
1976 #define DPORT_APP_CPU_INTR_FROM_CPU_0_MAP_V  0x1F
1977 #define DPORT_APP_CPU_INTR_FROM_CPU_0_MAP_S  0
1978 
1979 #define DPORT_APP_CPU_INTR_FROM_CPU_1_MAP_REG          (DR_REG_DPORT_BASE + 0x27C)
1980 /* DPORT_APP_CPU_INTR_FROM_CPU_1_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
1981 /*description: */
1982 #define DPORT_APP_CPU_INTR_FROM_CPU_1_MAP  0x0000001F
1983 #define DPORT_APP_CPU_INTR_FROM_CPU_1_MAP_M  ((DPORT_APP_CPU_INTR_FROM_CPU_1_MAP_V)<<(DPORT_APP_CPU_INTR_FROM_CPU_1_MAP_S))
1984 #define DPORT_APP_CPU_INTR_FROM_CPU_1_MAP_V  0x1F
1985 #define DPORT_APP_CPU_INTR_FROM_CPU_1_MAP_S  0
1986 
1987 #define DPORT_APP_CPU_INTR_FROM_CPU_2_MAP_REG          (DR_REG_DPORT_BASE + 0x280)
1988 /* DPORT_APP_CPU_INTR_FROM_CPU_2_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
1989 /*description: */
1990 #define DPORT_APP_CPU_INTR_FROM_CPU_2_MAP  0x0000001F
1991 #define DPORT_APP_CPU_INTR_FROM_CPU_2_MAP_M  ((DPORT_APP_CPU_INTR_FROM_CPU_2_MAP_V)<<(DPORT_APP_CPU_INTR_FROM_CPU_2_MAP_S))
1992 #define DPORT_APP_CPU_INTR_FROM_CPU_2_MAP_V  0x1F
1993 #define DPORT_APP_CPU_INTR_FROM_CPU_2_MAP_S  0
1994 
1995 #define DPORT_APP_CPU_INTR_FROM_CPU_3_MAP_REG          (DR_REG_DPORT_BASE + 0x284)
1996 /* DPORT_APP_CPU_INTR_FROM_CPU_3_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
1997 /*description: */
1998 #define DPORT_APP_CPU_INTR_FROM_CPU_3_MAP  0x0000001F
1999 #define DPORT_APP_CPU_INTR_FROM_CPU_3_MAP_M  ((DPORT_APP_CPU_INTR_FROM_CPU_3_MAP_V)<<(DPORT_APP_CPU_INTR_FROM_CPU_3_MAP_S))
2000 #define DPORT_APP_CPU_INTR_FROM_CPU_3_MAP_V  0x1F
2001 #define DPORT_APP_CPU_INTR_FROM_CPU_3_MAP_S  0
2002 
2003 #define DPORT_APP_SPI_INTR_0_MAP_REG          (DR_REG_DPORT_BASE + 0x288)
2004 /* DPORT_APP_SPI_INTR_0_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
2005 /*description: */
2006 #define DPORT_APP_SPI_INTR_0_MAP  0x0000001F
2007 #define DPORT_APP_SPI_INTR_0_MAP_M  ((DPORT_APP_SPI_INTR_0_MAP_V)<<(DPORT_APP_SPI_INTR_0_MAP_S))
2008 #define DPORT_APP_SPI_INTR_0_MAP_V  0x1F
2009 #define DPORT_APP_SPI_INTR_0_MAP_S  0
2010 
2011 #define DPORT_APP_SPI_INTR_1_MAP_REG          (DR_REG_DPORT_BASE + 0x28C)
2012 /* DPORT_APP_SPI_INTR_1_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
2013 /*description: */
2014 #define DPORT_APP_SPI_INTR_1_MAP  0x0000001F
2015 #define DPORT_APP_SPI_INTR_1_MAP_M  ((DPORT_APP_SPI_INTR_1_MAP_V)<<(DPORT_APP_SPI_INTR_1_MAP_S))
2016 #define DPORT_APP_SPI_INTR_1_MAP_V  0x1F
2017 #define DPORT_APP_SPI_INTR_1_MAP_S  0
2018 
2019 #define DPORT_APP_SPI_INTR_2_MAP_REG          (DR_REG_DPORT_BASE + 0x290)
2020 /* DPORT_APP_SPI_INTR_2_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
2021 /*description: */
2022 #define DPORT_APP_SPI_INTR_2_MAP  0x0000001F
2023 #define DPORT_APP_SPI_INTR_2_MAP_M  ((DPORT_APP_SPI_INTR_2_MAP_V)<<(DPORT_APP_SPI_INTR_2_MAP_S))
2024 #define DPORT_APP_SPI_INTR_2_MAP_V  0x1F
2025 #define DPORT_APP_SPI_INTR_2_MAP_S  0
2026 
2027 #define DPORT_APP_SPI_INTR_3_MAP_REG          (DR_REG_DPORT_BASE + 0x294)
2028 /* DPORT_APP_SPI_INTR_3_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
2029 /*description: */
2030 #define DPORT_APP_SPI_INTR_3_MAP  0x0000001F
2031 #define DPORT_APP_SPI_INTR_3_MAP_M  ((DPORT_APP_SPI_INTR_3_MAP_V)<<(DPORT_APP_SPI_INTR_3_MAP_S))
2032 #define DPORT_APP_SPI_INTR_3_MAP_V  0x1F
2033 #define DPORT_APP_SPI_INTR_3_MAP_S  0
2034 
2035 #define DPORT_APP_I2S0_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x298)
2036 /* DPORT_APP_I2S0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
2037 /*description: */
2038 #define DPORT_APP_I2S0_INT_MAP  0x0000001F
2039 #define DPORT_APP_I2S0_INT_MAP_M  ((DPORT_APP_I2S0_INT_MAP_V)<<(DPORT_APP_I2S0_INT_MAP_S))
2040 #define DPORT_APP_I2S0_INT_MAP_V  0x1F
2041 #define DPORT_APP_I2S0_INT_MAP_S  0
2042 
2043 #define DPORT_APP_I2S1_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x29C)
2044 /* DPORT_APP_I2S1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
2045 /*description: */
2046 #define DPORT_APP_I2S1_INT_MAP  0x0000001F
2047 #define DPORT_APP_I2S1_INT_MAP_M  ((DPORT_APP_I2S1_INT_MAP_V)<<(DPORT_APP_I2S1_INT_MAP_S))
2048 #define DPORT_APP_I2S1_INT_MAP_V  0x1F
2049 #define DPORT_APP_I2S1_INT_MAP_S  0
2050 
2051 #define DPORT_APP_UART_INTR_MAP_REG          (DR_REG_DPORT_BASE + 0x2A0)
2052 /* DPORT_APP_UART_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
2053 /*description: */
2054 #define DPORT_APP_UART_INTR_MAP  0x0000001F
2055 #define DPORT_APP_UART_INTR_MAP_M  ((DPORT_APP_UART_INTR_MAP_V)<<(DPORT_APP_UART_INTR_MAP_S))
2056 #define DPORT_APP_UART_INTR_MAP_V  0x1F
2057 #define DPORT_APP_UART_INTR_MAP_S  0
2058 
2059 #define DPORT_APP_UART1_INTR_MAP_REG          (DR_REG_DPORT_BASE + 0x2A4)
2060 /* DPORT_APP_UART1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
2061 /*description: */
2062 #define DPORT_APP_UART1_INTR_MAP  0x0000001F
2063 #define DPORT_APP_UART1_INTR_MAP_M  ((DPORT_APP_UART1_INTR_MAP_V)<<(DPORT_APP_UART1_INTR_MAP_S))
2064 #define DPORT_APP_UART1_INTR_MAP_V  0x1F
2065 #define DPORT_APP_UART1_INTR_MAP_S  0
2066 
2067 #define DPORT_APP_UART2_INTR_MAP_REG          (DR_REG_DPORT_BASE + 0x2A8)
2068 /* DPORT_APP_UART2_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
2069 /*description: */
2070 #define DPORT_APP_UART2_INTR_MAP  0x0000001F
2071 #define DPORT_APP_UART2_INTR_MAP_M  ((DPORT_APP_UART2_INTR_MAP_V)<<(DPORT_APP_UART2_INTR_MAP_S))
2072 #define DPORT_APP_UART2_INTR_MAP_V  0x1F
2073 #define DPORT_APP_UART2_INTR_MAP_S  0
2074 
2075 #define DPORT_APP_SDIO_HOST_INTERRUPT_MAP_REG          (DR_REG_DPORT_BASE + 0x2AC)
2076 /* DPORT_APP_SDIO_HOST_INTERRUPT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
2077 /*description: */
2078 #define DPORT_APP_SDIO_HOST_INTERRUPT_MAP  0x0000001F
2079 #define DPORT_APP_SDIO_HOST_INTERRUPT_MAP_M  ((DPORT_APP_SDIO_HOST_INTERRUPT_MAP_V)<<(DPORT_APP_SDIO_HOST_INTERRUPT_MAP_S))
2080 #define DPORT_APP_SDIO_HOST_INTERRUPT_MAP_V  0x1F
2081 #define DPORT_APP_SDIO_HOST_INTERRUPT_MAP_S  0
2082 
2083 #define DPORT_APP_EMAC_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x2B0)
2084 /* DPORT_APP_EMAC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
2085 /*description: */
2086 #define DPORT_APP_EMAC_INT_MAP  0x0000001F
2087 #define DPORT_APP_EMAC_INT_MAP_M  ((DPORT_APP_EMAC_INT_MAP_V)<<(DPORT_APP_EMAC_INT_MAP_S))
2088 #define DPORT_APP_EMAC_INT_MAP_V  0x1F
2089 #define DPORT_APP_EMAC_INT_MAP_S  0
2090 
2091 #define DPORT_APP_PWM0_INTR_MAP_REG          (DR_REG_DPORT_BASE + 0x2B4)
2092 /* DPORT_APP_PWM0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
2093 /*description: */
2094 #define DPORT_APP_PWM0_INTR_MAP  0x0000001F
2095 #define DPORT_APP_PWM0_INTR_MAP_M  ((DPORT_APP_PWM0_INTR_MAP_V)<<(DPORT_APP_PWM0_INTR_MAP_S))
2096 #define DPORT_APP_PWM0_INTR_MAP_V  0x1F
2097 #define DPORT_APP_PWM0_INTR_MAP_S  0
2098 
2099 #define DPORT_APP_PWM1_INTR_MAP_REG          (DR_REG_DPORT_BASE + 0x2B8)
2100 /* DPORT_APP_PWM1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
2101 /*description: */
2102 #define DPORT_APP_PWM1_INTR_MAP  0x0000001F
2103 #define DPORT_APP_PWM1_INTR_MAP_M  ((DPORT_APP_PWM1_INTR_MAP_V)<<(DPORT_APP_PWM1_INTR_MAP_S))
2104 #define DPORT_APP_PWM1_INTR_MAP_V  0x1F
2105 #define DPORT_APP_PWM1_INTR_MAP_S  0
2106 
2107 #define DPORT_APP_PWM2_INTR_MAP_REG          (DR_REG_DPORT_BASE + 0x2BC)
2108 /* DPORT_APP_PWM2_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
2109 /*description: */
2110 #define DPORT_APP_PWM2_INTR_MAP  0x0000001F
2111 #define DPORT_APP_PWM2_INTR_MAP_M  ((DPORT_APP_PWM2_INTR_MAP_V)<<(DPORT_APP_PWM2_INTR_MAP_S))
2112 #define DPORT_APP_PWM2_INTR_MAP_V  0x1F
2113 #define DPORT_APP_PWM2_INTR_MAP_S  0
2114 
2115 #define DPORT_APP_PWM3_INTR_MAP_REG          (DR_REG_DPORT_BASE + 0x2C0)
2116 /* DPORT_APP_PWM3_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
2117 /*description: */
2118 #define DPORT_APP_PWM3_INTR_MAP  0x0000001F
2119 #define DPORT_APP_PWM3_INTR_MAP_M  ((DPORT_APP_PWM3_INTR_MAP_V)<<(DPORT_APP_PWM3_INTR_MAP_S))
2120 #define DPORT_APP_PWM3_INTR_MAP_V  0x1F
2121 #define DPORT_APP_PWM3_INTR_MAP_S  0
2122 
2123 #define DPORT_APP_LEDC_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x2C4)
2124 /* DPORT_APP_LEDC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
2125 /*description: */
2126 #define DPORT_APP_LEDC_INT_MAP  0x0000001F
2127 #define DPORT_APP_LEDC_INT_MAP_M  ((DPORT_APP_LEDC_INT_MAP_V)<<(DPORT_APP_LEDC_INT_MAP_S))
2128 #define DPORT_APP_LEDC_INT_MAP_V  0x1F
2129 #define DPORT_APP_LEDC_INT_MAP_S  0
2130 
2131 #define DPORT_APP_EFUSE_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x2C8)
2132 /* DPORT_APP_EFUSE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
2133 /*description: */
2134 #define DPORT_APP_EFUSE_INT_MAP  0x0000001F
2135 #define DPORT_APP_EFUSE_INT_MAP_M  ((DPORT_APP_EFUSE_INT_MAP_V)<<(DPORT_APP_EFUSE_INT_MAP_S))
2136 #define DPORT_APP_EFUSE_INT_MAP_V  0x1F
2137 #define DPORT_APP_EFUSE_INT_MAP_S  0
2138 
2139 #define DPORT_APP_CAN_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x2CC)
2140 /* DPORT_APP_CAN_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
2141 /*description: */
2142 #define DPORT_APP_CAN_INT_MAP  0x0000001F
2143 #define DPORT_APP_CAN_INT_MAP_M  ((DPORT_APP_CAN_INT_MAP_V)<<(DPORT_APP_CAN_INT_MAP_S))
2144 #define DPORT_APP_CAN_INT_MAP_V  0x1F
2145 #define DPORT_APP_CAN_INT_MAP_S  0
2146 
2147 #define DPORT_APP_RTC_CORE_INTR_MAP_REG          (DR_REG_DPORT_BASE + 0x2D0)
2148 /* DPORT_APP_RTC_CORE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
2149 /*description: */
2150 #define DPORT_APP_RTC_CORE_INTR_MAP  0x0000001F
2151 #define DPORT_APP_RTC_CORE_INTR_MAP_M  ((DPORT_APP_RTC_CORE_INTR_MAP_V)<<(DPORT_APP_RTC_CORE_INTR_MAP_S))
2152 #define DPORT_APP_RTC_CORE_INTR_MAP_V  0x1F
2153 #define DPORT_APP_RTC_CORE_INTR_MAP_S  0
2154 
2155 #define DPORT_APP_RMT_INTR_MAP_REG          (DR_REG_DPORT_BASE + 0x2D4)
2156 /* DPORT_APP_RMT_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
2157 /*description: */
2158 #define DPORT_APP_RMT_INTR_MAP  0x0000001F
2159 #define DPORT_APP_RMT_INTR_MAP_M  ((DPORT_APP_RMT_INTR_MAP_V)<<(DPORT_APP_RMT_INTR_MAP_S))
2160 #define DPORT_APP_RMT_INTR_MAP_V  0x1F
2161 #define DPORT_APP_RMT_INTR_MAP_S  0
2162 
2163 #define DPORT_APP_PCNT_INTR_MAP_REG          (DR_REG_DPORT_BASE + 0x2D8)
2164 /* DPORT_APP_PCNT_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
2165 /*description: */
2166 #define DPORT_APP_PCNT_INTR_MAP  0x0000001F
2167 #define DPORT_APP_PCNT_INTR_MAP_M  ((DPORT_APP_PCNT_INTR_MAP_V)<<(DPORT_APP_PCNT_INTR_MAP_S))
2168 #define DPORT_APP_PCNT_INTR_MAP_V  0x1F
2169 #define DPORT_APP_PCNT_INTR_MAP_S  0
2170 
2171 #define DPORT_APP_I2C_EXT0_INTR_MAP_REG          (DR_REG_DPORT_BASE + 0x2DC)
2172 /* DPORT_APP_I2C_EXT0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
2173 /*description: */
2174 #define DPORT_APP_I2C_EXT0_INTR_MAP  0x0000001F
2175 #define DPORT_APP_I2C_EXT0_INTR_MAP_M  ((DPORT_APP_I2C_EXT0_INTR_MAP_V)<<(DPORT_APP_I2C_EXT0_INTR_MAP_S))
2176 #define DPORT_APP_I2C_EXT0_INTR_MAP_V  0x1F
2177 #define DPORT_APP_I2C_EXT0_INTR_MAP_S  0
2178 
2179 #define DPORT_APP_I2C_EXT1_INTR_MAP_REG          (DR_REG_DPORT_BASE + 0x2E0)
2180 /* DPORT_APP_I2C_EXT1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
2181 /*description: */
2182 #define DPORT_APP_I2C_EXT1_INTR_MAP  0x0000001F
2183 #define DPORT_APP_I2C_EXT1_INTR_MAP_M  ((DPORT_APP_I2C_EXT1_INTR_MAP_V)<<(DPORT_APP_I2C_EXT1_INTR_MAP_S))
2184 #define DPORT_APP_I2C_EXT1_INTR_MAP_V  0x1F
2185 #define DPORT_APP_I2C_EXT1_INTR_MAP_S  0
2186 
2187 #define DPORT_APP_RSA_INTR_MAP_REG          (DR_REG_DPORT_BASE + 0x2E4)
2188 /* DPORT_APP_RSA_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
2189 /*description: */
2190 #define DPORT_APP_RSA_INTR_MAP  0x0000001F
2191 #define DPORT_APP_RSA_INTR_MAP_M  ((DPORT_APP_RSA_INTR_MAP_V)<<(DPORT_APP_RSA_INTR_MAP_S))
2192 #define DPORT_APP_RSA_INTR_MAP_V  0x1F
2193 #define DPORT_APP_RSA_INTR_MAP_S  0
2194 
2195 #define DPORT_APP_SPI1_DMA_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x2E8)
2196 /* DPORT_APP_SPI1_DMA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
2197 /*description: */
2198 #define DPORT_APP_SPI1_DMA_INT_MAP  0x0000001F
2199 #define DPORT_APP_SPI1_DMA_INT_MAP_M  ((DPORT_APP_SPI1_DMA_INT_MAP_V)<<(DPORT_APP_SPI1_DMA_INT_MAP_S))
2200 #define DPORT_APP_SPI1_DMA_INT_MAP_V  0x1F
2201 #define DPORT_APP_SPI1_DMA_INT_MAP_S  0
2202 
2203 #define DPORT_APP_SPI2_DMA_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x2EC)
2204 /* DPORT_APP_SPI2_DMA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
2205 /*description: */
2206 #define DPORT_APP_SPI2_DMA_INT_MAP  0x0000001F
2207 #define DPORT_APP_SPI2_DMA_INT_MAP_M  ((DPORT_APP_SPI2_DMA_INT_MAP_V)<<(DPORT_APP_SPI2_DMA_INT_MAP_S))
2208 #define DPORT_APP_SPI2_DMA_INT_MAP_V  0x1F
2209 #define DPORT_APP_SPI2_DMA_INT_MAP_S  0
2210 
2211 #define DPORT_APP_SPI3_DMA_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x2F0)
2212 /* DPORT_APP_SPI3_DMA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
2213 /*description: */
2214 #define DPORT_APP_SPI3_DMA_INT_MAP  0x0000001F
2215 #define DPORT_APP_SPI3_DMA_INT_MAP_M  ((DPORT_APP_SPI3_DMA_INT_MAP_V)<<(DPORT_APP_SPI3_DMA_INT_MAP_S))
2216 #define DPORT_APP_SPI3_DMA_INT_MAP_V  0x1F
2217 #define DPORT_APP_SPI3_DMA_INT_MAP_S  0
2218 
2219 #define DPORT_APP_WDG_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x2F4)
2220 /* DPORT_APP_WDG_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
2221 /*description: */
2222 #define DPORT_APP_WDG_INT_MAP  0x0000001F
2223 #define DPORT_APP_WDG_INT_MAP_M  ((DPORT_APP_WDG_INT_MAP_V)<<(DPORT_APP_WDG_INT_MAP_S))
2224 #define DPORT_APP_WDG_INT_MAP_V  0x1F
2225 #define DPORT_APP_WDG_INT_MAP_S  0
2226 
2227 #define DPORT_APP_TIMER_INT1_MAP_REG          (DR_REG_DPORT_BASE + 0x2F8)
2228 /* DPORT_APP_TIMER_INT1_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
2229 /*description: */
2230 #define DPORT_APP_TIMER_INT1_MAP  0x0000001F
2231 #define DPORT_APP_TIMER_INT1_MAP_M  ((DPORT_APP_TIMER_INT1_MAP_V)<<(DPORT_APP_TIMER_INT1_MAP_S))
2232 #define DPORT_APP_TIMER_INT1_MAP_V  0x1F
2233 #define DPORT_APP_TIMER_INT1_MAP_S  0
2234 
2235 #define DPORT_APP_TIMER_INT2_MAP_REG          (DR_REG_DPORT_BASE + 0x2FC)
2236 /* DPORT_APP_TIMER_INT2_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
2237 /*description: */
2238 #define DPORT_APP_TIMER_INT2_MAP  0x0000001F
2239 #define DPORT_APP_TIMER_INT2_MAP_M  ((DPORT_APP_TIMER_INT2_MAP_V)<<(DPORT_APP_TIMER_INT2_MAP_S))
2240 #define DPORT_APP_TIMER_INT2_MAP_V  0x1F
2241 #define DPORT_APP_TIMER_INT2_MAP_S  0
2242 
2243 #define DPORT_APP_TG_T0_EDGE_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x300)
2244 /* DPORT_APP_TG_T0_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
2245 /*description: */
2246 #define DPORT_APP_TG_T0_EDGE_INT_MAP  0x0000001F
2247 #define DPORT_APP_TG_T0_EDGE_INT_MAP_M  ((DPORT_APP_TG_T0_EDGE_INT_MAP_V)<<(DPORT_APP_TG_T0_EDGE_INT_MAP_S))
2248 #define DPORT_APP_TG_T0_EDGE_INT_MAP_V  0x1F
2249 #define DPORT_APP_TG_T0_EDGE_INT_MAP_S  0
2250 
2251 #define DPORT_APP_TG_T1_EDGE_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x304)
2252 /* DPORT_APP_TG_T1_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
2253 /*description: */
2254 #define DPORT_APP_TG_T1_EDGE_INT_MAP  0x0000001F
2255 #define DPORT_APP_TG_T1_EDGE_INT_MAP_M  ((DPORT_APP_TG_T1_EDGE_INT_MAP_V)<<(DPORT_APP_TG_T1_EDGE_INT_MAP_S))
2256 #define DPORT_APP_TG_T1_EDGE_INT_MAP_V  0x1F
2257 #define DPORT_APP_TG_T1_EDGE_INT_MAP_S  0
2258 
2259 #define DPORT_APP_TG_WDT_EDGE_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x308)
2260 /* DPORT_APP_TG_WDT_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
2261 /*description: */
2262 #define DPORT_APP_TG_WDT_EDGE_INT_MAP  0x0000001F
2263 #define DPORT_APP_TG_WDT_EDGE_INT_MAP_M  ((DPORT_APP_TG_WDT_EDGE_INT_MAP_V)<<(DPORT_APP_TG_WDT_EDGE_INT_MAP_S))
2264 #define DPORT_APP_TG_WDT_EDGE_INT_MAP_V  0x1F
2265 #define DPORT_APP_TG_WDT_EDGE_INT_MAP_S  0
2266 
2267 #define DPORT_APP_TG_LACT_EDGE_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x30C)
2268 /* DPORT_APP_TG_LACT_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
2269 /*description: */
2270 #define DPORT_APP_TG_LACT_EDGE_INT_MAP  0x0000001F
2271 #define DPORT_APP_TG_LACT_EDGE_INT_MAP_M  ((DPORT_APP_TG_LACT_EDGE_INT_MAP_V)<<(DPORT_APP_TG_LACT_EDGE_INT_MAP_S))
2272 #define DPORT_APP_TG_LACT_EDGE_INT_MAP_V  0x1F
2273 #define DPORT_APP_TG_LACT_EDGE_INT_MAP_S  0
2274 
2275 #define DPORT_APP_TG1_T0_EDGE_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x310)
2276 /* DPORT_APP_TG1_T0_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
2277 /*description: */
2278 #define DPORT_APP_TG1_T0_EDGE_INT_MAP  0x0000001F
2279 #define DPORT_APP_TG1_T0_EDGE_INT_MAP_M  ((DPORT_APP_TG1_T0_EDGE_INT_MAP_V)<<(DPORT_APP_TG1_T0_EDGE_INT_MAP_S))
2280 #define DPORT_APP_TG1_T0_EDGE_INT_MAP_V  0x1F
2281 #define DPORT_APP_TG1_T0_EDGE_INT_MAP_S  0
2282 
2283 #define DPORT_APP_TG1_T1_EDGE_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x314)
2284 /* DPORT_APP_TG1_T1_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
2285 /*description: */
2286 #define DPORT_APP_TG1_T1_EDGE_INT_MAP  0x0000001F
2287 #define DPORT_APP_TG1_T1_EDGE_INT_MAP_M  ((DPORT_APP_TG1_T1_EDGE_INT_MAP_V)<<(DPORT_APP_TG1_T1_EDGE_INT_MAP_S))
2288 #define DPORT_APP_TG1_T1_EDGE_INT_MAP_V  0x1F
2289 #define DPORT_APP_TG1_T1_EDGE_INT_MAP_S  0
2290 
2291 #define DPORT_APP_TG1_WDT_EDGE_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x318)
2292 /* DPORT_APP_TG1_WDT_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
2293 /*description: */
2294 #define DPORT_APP_TG1_WDT_EDGE_INT_MAP  0x0000001F
2295 #define DPORT_APP_TG1_WDT_EDGE_INT_MAP_M  ((DPORT_APP_TG1_WDT_EDGE_INT_MAP_V)<<(DPORT_APP_TG1_WDT_EDGE_INT_MAP_S))
2296 #define DPORT_APP_TG1_WDT_EDGE_INT_MAP_V  0x1F
2297 #define DPORT_APP_TG1_WDT_EDGE_INT_MAP_S  0
2298 
2299 #define DPORT_APP_TG1_LACT_EDGE_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x31C)
2300 /* DPORT_APP_TG1_LACT_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
2301 /*description: */
2302 #define DPORT_APP_TG1_LACT_EDGE_INT_MAP  0x0000001F
2303 #define DPORT_APP_TG1_LACT_EDGE_INT_MAP_M  ((DPORT_APP_TG1_LACT_EDGE_INT_MAP_V)<<(DPORT_APP_TG1_LACT_EDGE_INT_MAP_S))
2304 #define DPORT_APP_TG1_LACT_EDGE_INT_MAP_V  0x1F
2305 #define DPORT_APP_TG1_LACT_EDGE_INT_MAP_S  0
2306 
2307 #define DPORT_APP_MMU_IA_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x320)
2308 /* DPORT_APP_MMU_IA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
2309 /*description: */
2310 #define DPORT_APP_MMU_IA_INT_MAP  0x0000001F
2311 #define DPORT_APP_MMU_IA_INT_MAP_M  ((DPORT_APP_MMU_IA_INT_MAP_V)<<(DPORT_APP_MMU_IA_INT_MAP_S))
2312 #define DPORT_APP_MMU_IA_INT_MAP_V  0x1F
2313 #define DPORT_APP_MMU_IA_INT_MAP_S  0
2314 
2315 #define DPORT_APP_MPU_IA_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x324)
2316 /* DPORT_APP_MPU_IA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
2317 /*description: */
2318 #define DPORT_APP_MPU_IA_INT_MAP  0x0000001F
2319 #define DPORT_APP_MPU_IA_INT_MAP_M  ((DPORT_APP_MPU_IA_INT_MAP_V)<<(DPORT_APP_MPU_IA_INT_MAP_S))
2320 #define DPORT_APP_MPU_IA_INT_MAP_V  0x1F
2321 #define DPORT_APP_MPU_IA_INT_MAP_S  0
2322 
2323 #define DPORT_APP_CACHE_IA_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x328)
2324 /* DPORT_APP_CACHE_IA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
2325 /*description: */
2326 #define DPORT_APP_CACHE_IA_INT_MAP  0x0000001F
2327 #define DPORT_APP_CACHE_IA_INT_MAP_M  ((DPORT_APP_CACHE_IA_INT_MAP_V)<<(DPORT_APP_CACHE_IA_INT_MAP_S))
2328 #define DPORT_APP_CACHE_IA_INT_MAP_V  0x1F
2329 #define DPORT_APP_CACHE_IA_INT_MAP_S  0
2330 
2331 #define DPORT_AHBLITE_MPU_TABLE_UART_REG          (DR_REG_DPORT_BASE + 0x32C)
2332 /* DPORT_UART_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
2333 /*description: */
2334 #define DPORT_UART_ACCESS_GRANT_CONFIG  0x0000003F
2335 #define DPORT_UART_ACCESS_GRANT_CONFIG_M  ((DPORT_UART_ACCESS_GRANT_CONFIG_V)<<(DPORT_UART_ACCESS_GRANT_CONFIG_S))
2336 #define DPORT_UART_ACCESS_GRANT_CONFIG_V  0x3F
2337 #define DPORT_UART_ACCESS_GRANT_CONFIG_S  0
2338 
2339 #define DPORT_AHBLITE_MPU_TABLE_SPI1_REG          (DR_REG_DPORT_BASE + 0x330)
2340 /* DPORT_SPI1_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
2341 /*description: */
2342 #define DPORT_SPI1_ACCESS_GRANT_CONFIG  0x0000003F
2343 #define DPORT_SPI1_ACCESS_GRANT_CONFIG_M  ((DPORT_SPI1_ACCESS_GRANT_CONFIG_V)<<(DPORT_SPI1_ACCESS_GRANT_CONFIG_S))
2344 #define DPORT_SPI1_ACCESS_GRANT_CONFIG_V  0x3F
2345 #define DPORT_SPI1_ACCESS_GRANT_CONFIG_S  0
2346 
2347 #define DPORT_AHBLITE_MPU_TABLE_SPI0_REG          (DR_REG_DPORT_BASE + 0x334)
2348 /* DPORT_SPI0_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
2349 /*description: */
2350 #define DPORT_SPI0_ACCESS_GRANT_CONFIG  0x0000003F
2351 #define DPORT_SPI0_ACCESS_GRANT_CONFIG_M  ((DPORT_SPI0_ACCESS_GRANT_CONFIG_V)<<(DPORT_SPI0_ACCESS_GRANT_CONFIG_S))
2352 #define DPORT_SPI0_ACCESS_GRANT_CONFIG_V  0x3F
2353 #define DPORT_SPI0_ACCESS_GRANT_CONFIG_S  0
2354 
2355 #define DPORT_AHBLITE_MPU_TABLE_GPIO_REG          (DR_REG_DPORT_BASE + 0x338)
2356 /* DPORT_GPIO_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
2357 /*description: */
2358 #define DPORT_GPIO_ACCESS_GRANT_CONFIG  0x0000003F
2359 #define DPORT_GPIO_ACCESS_GRANT_CONFIG_M  ((DPORT_GPIO_ACCESS_GRANT_CONFIG_V)<<(DPORT_GPIO_ACCESS_GRANT_CONFIG_S))
2360 #define DPORT_GPIO_ACCESS_GRANT_CONFIG_V  0x3F
2361 #define DPORT_GPIO_ACCESS_GRANT_CONFIG_S  0
2362 
2363 #define DPORT_AHBLITE_MPU_TABLE_FE2_REG          (DR_REG_DPORT_BASE + 0x33C)
2364 /* DPORT_FE2_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
2365 /*description: */
2366 #define DPORT_FE2_ACCESS_GRANT_CONFIG  0x0000003F
2367 #define DPORT_FE2_ACCESS_GRANT_CONFIG_M  ((DPORT_FE2_ACCESS_GRANT_CONFIG_V)<<(DPORT_FE2_ACCESS_GRANT_CONFIG_S))
2368 #define DPORT_FE2_ACCESS_GRANT_CONFIG_V  0x3F
2369 #define DPORT_FE2_ACCESS_GRANT_CONFIG_S  0
2370 
2371 #define DPORT_AHBLITE_MPU_TABLE_FE_REG          (DR_REG_DPORT_BASE + 0x340)
2372 /* DPORT_FE_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
2373 /*description: */
2374 #define DPORT_FE_ACCESS_GRANT_CONFIG  0x0000003F
2375 #define DPORT_FE_ACCESS_GRANT_CONFIG_M  ((DPORT_FE_ACCESS_GRANT_CONFIG_V)<<(DPORT_FE_ACCESS_GRANT_CONFIG_S))
2376 #define DPORT_FE_ACCESS_GRANT_CONFIG_V  0x3F
2377 #define DPORT_FE_ACCESS_GRANT_CONFIG_S  0
2378 
2379 #define DPORT_AHBLITE_MPU_TABLE_TIMER_REG          (DR_REG_DPORT_BASE + 0x344)
2380 /* DPORT_TIMER_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
2381 /*description: */
2382 #define DPORT_TIMER_ACCESS_GRANT_CONFIG  0x0000003F
2383 #define DPORT_TIMER_ACCESS_GRANT_CONFIG_M  ((DPORT_TIMER_ACCESS_GRANT_CONFIG_V)<<(DPORT_TIMER_ACCESS_GRANT_CONFIG_S))
2384 #define DPORT_TIMER_ACCESS_GRANT_CONFIG_V  0x3F
2385 #define DPORT_TIMER_ACCESS_GRANT_CONFIG_S  0
2386 
2387 #define DPORT_AHBLITE_MPU_TABLE_RTC_REG          (DR_REG_DPORT_BASE + 0x348)
2388 /* DPORT_RTC_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
2389 /*description: */
2390 #define DPORT_RTC_ACCESS_GRANT_CONFIG  0x0000003F
2391 #define DPORT_RTC_ACCESS_GRANT_CONFIG_M  ((DPORT_RTC_ACCESS_GRANT_CONFIG_V)<<(DPORT_RTC_ACCESS_GRANT_CONFIG_S))
2392 #define DPORT_RTC_ACCESS_GRANT_CONFIG_V  0x3F
2393 #define DPORT_RTC_ACCESS_GRANT_CONFIG_S  0
2394 
2395 #define DPORT_AHBLITE_MPU_TABLE_IO_MUX_REG          (DR_REG_DPORT_BASE + 0x34C)
2396 /* DPORT_IOMUX_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
2397 /*description: */
2398 #define DPORT_IOMUX_ACCESS_GRANT_CONFIG  0x0000003F
2399 #define DPORT_IOMUX_ACCESS_GRANT_CONFIG_M  ((DPORT_IOMUX_ACCESS_GRANT_CONFIG_V)<<(DPORT_IOMUX_ACCESS_GRANT_CONFIG_S))
2400 #define DPORT_IOMUX_ACCESS_GRANT_CONFIG_V  0x3F
2401 #define DPORT_IOMUX_ACCESS_GRANT_CONFIG_S  0
2402 
2403 #define DPORT_AHBLITE_MPU_TABLE_WDG_REG          (DR_REG_DPORT_BASE + 0x350)
2404 /* DPORT_WDG_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
2405 /*description: */
2406 #define DPORT_WDG_ACCESS_GRANT_CONFIG  0x0000003F
2407 #define DPORT_WDG_ACCESS_GRANT_CONFIG_M  ((DPORT_WDG_ACCESS_GRANT_CONFIG_V)<<(DPORT_WDG_ACCESS_GRANT_CONFIG_S))
2408 #define DPORT_WDG_ACCESS_GRANT_CONFIG_V  0x3F
2409 #define DPORT_WDG_ACCESS_GRANT_CONFIG_S  0
2410 
2411 #define DPORT_AHBLITE_MPU_TABLE_HINF_REG          (DR_REG_DPORT_BASE + 0x354)
2412 /* DPORT_HINF_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
2413 /*description: */
2414 #define DPORT_HINF_ACCESS_GRANT_CONFIG  0x0000003F
2415 #define DPORT_HINF_ACCESS_GRANT_CONFIG_M  ((DPORT_HINF_ACCESS_GRANT_CONFIG_V)<<(DPORT_HINF_ACCESS_GRANT_CONFIG_S))
2416 #define DPORT_HINF_ACCESS_GRANT_CONFIG_V  0x3F
2417 #define DPORT_HINF_ACCESS_GRANT_CONFIG_S  0
2418 
2419 #define DPORT_AHBLITE_MPU_TABLE_UHCI1_REG          (DR_REG_DPORT_BASE + 0x358)
2420 /* DPORT_UHCI1_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
2421 /*description: */
2422 #define DPORT_UHCI1_ACCESS_GRANT_CONFIG  0x0000003F
2423 #define DPORT_UHCI1_ACCESS_GRANT_CONFIG_M  ((DPORT_UHCI1_ACCESS_GRANT_CONFIG_V)<<(DPORT_UHCI1_ACCESS_GRANT_CONFIG_S))
2424 #define DPORT_UHCI1_ACCESS_GRANT_CONFIG_V  0x3F
2425 #define DPORT_UHCI1_ACCESS_GRANT_CONFIG_S  0
2426 
2427 #define DPORT_AHBLITE_MPU_TABLE_MISC_REG          (DR_REG_DPORT_BASE + 0x35C)
2428 /* DPORT_MISC_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
2429 /*description: */
2430 #define DPORT_MISC_ACCESS_GRANT_CONFIG  0x0000003F
2431 #define DPORT_MISC_ACCESS_GRANT_CONFIG_M  ((DPORT_MISC_ACCESS_GRANT_CONFIG_V)<<(DPORT_MISC_ACCESS_GRANT_CONFIG_S))
2432 #define DPORT_MISC_ACCESS_GRANT_CONFIG_V  0x3F
2433 #define DPORT_MISC_ACCESS_GRANT_CONFIG_S  0
2434 
2435 #define DPORT_AHBLITE_MPU_TABLE_I2C_REG          (DR_REG_DPORT_BASE + 0x360)
2436 /* DPORT_I2C_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
2437 /*description: */
2438 #define DPORT_I2C_ACCESS_GRANT_CONFIG  0x0000003F
2439 #define DPORT_I2C_ACCESS_GRANT_CONFIG_M  ((DPORT_I2C_ACCESS_GRANT_CONFIG_V)<<(DPORT_I2C_ACCESS_GRANT_CONFIG_S))
2440 #define DPORT_I2C_ACCESS_GRANT_CONFIG_V  0x3F
2441 #define DPORT_I2C_ACCESS_GRANT_CONFIG_S  0
2442 
2443 #define DPORT_AHBLITE_MPU_TABLE_I2S0_REG          (DR_REG_DPORT_BASE + 0x364)
2444 /* DPORT_I2S0_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
2445 /*description: */
2446 #define DPORT_I2S0_ACCESS_GRANT_CONFIG  0x0000003F
2447 #define DPORT_I2S0_ACCESS_GRANT_CONFIG_M  ((DPORT_I2S0_ACCESS_GRANT_CONFIG_V)<<(DPORT_I2S0_ACCESS_GRANT_CONFIG_S))
2448 #define DPORT_I2S0_ACCESS_GRANT_CONFIG_V  0x3F
2449 #define DPORT_I2S0_ACCESS_GRANT_CONFIG_S  0
2450 
2451 #define DPORT_AHBLITE_MPU_TABLE_UART1_REG          (DR_REG_DPORT_BASE + 0x368)
2452 /* DPORT_UART1_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
2453 /*description: */
2454 #define DPORT_UART1_ACCESS_GRANT_CONFIG  0x0000003F
2455 #define DPORT_UART1_ACCESS_GRANT_CONFIG_M  ((DPORT_UART1_ACCESS_GRANT_CONFIG_V)<<(DPORT_UART1_ACCESS_GRANT_CONFIG_S))
2456 #define DPORT_UART1_ACCESS_GRANT_CONFIG_V  0x3F
2457 #define DPORT_UART1_ACCESS_GRANT_CONFIG_S  0
2458 
2459 #define DPORT_AHBLITE_MPU_TABLE_BT_REG          (DR_REG_DPORT_BASE + 0x36C)
2460 /* DPORT_BT_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
2461 /*description: */
2462 #define DPORT_BT_ACCESS_GRANT_CONFIG  0x0000003F
2463 #define DPORT_BT_ACCESS_GRANT_CONFIG_M  ((DPORT_BT_ACCESS_GRANT_CONFIG_V)<<(DPORT_BT_ACCESS_GRANT_CONFIG_S))
2464 #define DPORT_BT_ACCESS_GRANT_CONFIG_V  0x3F
2465 #define DPORT_BT_ACCESS_GRANT_CONFIG_S  0
2466 
2467 #define DPORT_AHBLITE_MPU_TABLE_BT_BUFFER_REG          (DR_REG_DPORT_BASE + 0x370)
2468 /* DPORT_BTBUFFER_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
2469 /*description: */
2470 #define DPORT_BTBUFFER_ACCESS_GRANT_CONFIG  0x0000003F
2471 #define DPORT_BTBUFFER_ACCESS_GRANT_CONFIG_M  ((DPORT_BTBUFFER_ACCESS_GRANT_CONFIG_V)<<(DPORT_BTBUFFER_ACCESS_GRANT_CONFIG_S))
2472 #define DPORT_BTBUFFER_ACCESS_GRANT_CONFIG_V  0x3F
2473 #define DPORT_BTBUFFER_ACCESS_GRANT_CONFIG_S  0
2474 
2475 #define DPORT_AHBLITE_MPU_TABLE_I2C_EXT0_REG          (DR_REG_DPORT_BASE + 0x374)
2476 /* DPORT_I2CEXT0_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
2477 /*description: */
2478 #define DPORT_I2CEXT0_ACCESS_GRANT_CONFIG  0x0000003F
2479 #define DPORT_I2CEXT0_ACCESS_GRANT_CONFIG_M  ((DPORT_I2CEXT0_ACCESS_GRANT_CONFIG_V)<<(DPORT_I2CEXT0_ACCESS_GRANT_CONFIG_S))
2480 #define DPORT_I2CEXT0_ACCESS_GRANT_CONFIG_V  0x3F
2481 #define DPORT_I2CEXT0_ACCESS_GRANT_CONFIG_S  0
2482 
2483 #define DPORT_AHBLITE_MPU_TABLE_UHCI0_REG          (DR_REG_DPORT_BASE + 0x378)
2484 /* DPORT_UHCI0_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
2485 /*description: */
2486 #define DPORT_UHCI0_ACCESS_GRANT_CONFIG  0x0000003F
2487 #define DPORT_UHCI0_ACCESS_GRANT_CONFIG_M  ((DPORT_UHCI0_ACCESS_GRANT_CONFIG_V)<<(DPORT_UHCI0_ACCESS_GRANT_CONFIG_S))
2488 #define DPORT_UHCI0_ACCESS_GRANT_CONFIG_V  0x3F
2489 #define DPORT_UHCI0_ACCESS_GRANT_CONFIG_S  0
2490 
2491 #define DPORT_AHBLITE_MPU_TABLE_SLCHOST_REG          (DR_REG_DPORT_BASE + 0x37C)
2492 /* DPORT_SLCHOST_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
2493 /*description: */
2494 #define DPORT_SLCHOST_ACCESS_GRANT_CONFIG  0x0000003F
2495 #define DPORT_SLCHOST_ACCESS_GRANT_CONFIG_M  ((DPORT_SLCHOST_ACCESS_GRANT_CONFIG_V)<<(DPORT_SLCHOST_ACCESS_GRANT_CONFIG_S))
2496 #define DPORT_SLCHOST_ACCESS_GRANT_CONFIG_V  0x3F
2497 #define DPORT_SLCHOST_ACCESS_GRANT_CONFIG_S  0
2498 
2499 #define DPORT_AHBLITE_MPU_TABLE_RMT_REG          (DR_REG_DPORT_BASE + 0x380)
2500 /* DPORT_RMT_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
2501 /*description: */
2502 #define DPORT_RMT_ACCESS_GRANT_CONFIG  0x0000003F
2503 #define DPORT_RMT_ACCESS_GRANT_CONFIG_M  ((DPORT_RMT_ACCESS_GRANT_CONFIG_V)<<(DPORT_RMT_ACCESS_GRANT_CONFIG_S))
2504 #define DPORT_RMT_ACCESS_GRANT_CONFIG_V  0x3F
2505 #define DPORT_RMT_ACCESS_GRANT_CONFIG_S  0
2506 
2507 #define DPORT_AHBLITE_MPU_TABLE_PCNT_REG          (DR_REG_DPORT_BASE + 0x384)
2508 /* DPORT_PCNT_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
2509 /*description: */
2510 #define DPORT_PCNT_ACCESS_GRANT_CONFIG  0x0000003F
2511 #define DPORT_PCNT_ACCESS_GRANT_CONFIG_M  ((DPORT_PCNT_ACCESS_GRANT_CONFIG_V)<<(DPORT_PCNT_ACCESS_GRANT_CONFIG_S))
2512 #define DPORT_PCNT_ACCESS_GRANT_CONFIG_V  0x3F
2513 #define DPORT_PCNT_ACCESS_GRANT_CONFIG_S  0
2514 
2515 #define DPORT_AHBLITE_MPU_TABLE_SLC_REG          (DR_REG_DPORT_BASE + 0x388)
2516 /* DPORT_SLC_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
2517 /*description: */
2518 #define DPORT_SLC_ACCESS_GRANT_CONFIG  0x0000003F
2519 #define DPORT_SLC_ACCESS_GRANT_CONFIG_M  ((DPORT_SLC_ACCESS_GRANT_CONFIG_V)<<(DPORT_SLC_ACCESS_GRANT_CONFIG_S))
2520 #define DPORT_SLC_ACCESS_GRANT_CONFIG_V  0x3F
2521 #define DPORT_SLC_ACCESS_GRANT_CONFIG_S  0
2522 
2523 #define DPORT_AHBLITE_MPU_TABLE_LEDC_REG          (DR_REG_DPORT_BASE + 0x38C)
2524 /* DPORT_LEDC_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
2525 /*description: */
2526 #define DPORT_LEDC_ACCESS_GRANT_CONFIG  0x0000003F
2527 #define DPORT_LEDC_ACCESS_GRANT_CONFIG_M  ((DPORT_LEDC_ACCESS_GRANT_CONFIG_V)<<(DPORT_LEDC_ACCESS_GRANT_CONFIG_S))
2528 #define DPORT_LEDC_ACCESS_GRANT_CONFIG_V  0x3F
2529 #define DPORT_LEDC_ACCESS_GRANT_CONFIG_S  0
2530 
2531 #define DPORT_AHBLITE_MPU_TABLE_EFUSE_REG          (DR_REG_DPORT_BASE + 0x390)
2532 /* DPORT_EFUSE_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
2533 /*description: */
2534 #define DPORT_EFUSE_ACCESS_GRANT_CONFIG  0x0000003F
2535 #define DPORT_EFUSE_ACCESS_GRANT_CONFIG_M  ((DPORT_EFUSE_ACCESS_GRANT_CONFIG_V)<<(DPORT_EFUSE_ACCESS_GRANT_CONFIG_S))
2536 #define DPORT_EFUSE_ACCESS_GRANT_CONFIG_V  0x3F
2537 #define DPORT_EFUSE_ACCESS_GRANT_CONFIG_S  0
2538 
2539 #define DPORT_AHBLITE_MPU_TABLE_SPI_ENCRYPT_REG          (DR_REG_DPORT_BASE + 0x394)
2540 /* DPORT_SPI_ENCRYPY_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
2541 /*description: */
2542 #define DPORT_SPI_ENCRYPY_ACCESS_GRANT_CONFIG  0x0000003F
2543 #define DPORT_SPI_ENCRYPY_ACCESS_GRANT_CONFIG_M  ((DPORT_SPI_ENCRYPY_ACCESS_GRANT_CONFIG_V)<<(DPORT_SPI_ENCRYPY_ACCESS_GRANT_CONFIG_S))
2544 #define DPORT_SPI_ENCRYPY_ACCESS_GRANT_CONFIG_V  0x3F
2545 #define DPORT_SPI_ENCRYPY_ACCESS_GRANT_CONFIG_S  0
2546 
2547 #define DPORT_AHBLITE_MPU_TABLE_BB_REG          (DR_REG_DPORT_BASE + 0x398)
2548 /* DPORT_BB_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
2549 /*description: */
2550 #define DPORT_BB_ACCESS_GRANT_CONFIG  0x0000003F
2551 #define DPORT_BB_ACCESS_GRANT_CONFIG_M  ((DPORT_BB_ACCESS_GRANT_CONFIG_V)<<(DPORT_BB_ACCESS_GRANT_CONFIG_S))
2552 #define DPORT_BB_ACCESS_GRANT_CONFIG_V  0x3F
2553 #define DPORT_BB_ACCESS_GRANT_CONFIG_S  0
2554 
2555 #define DPORT_AHBLITE_MPU_TABLE_PWM0_REG          (DR_REG_DPORT_BASE + 0x39C)
2556 /* DPORT_PWM0_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
2557 /*description: */
2558 #define DPORT_PWM0_ACCESS_GRANT_CONFIG  0x0000003F
2559 #define DPORT_PWM0_ACCESS_GRANT_CONFIG_M  ((DPORT_PWM0_ACCESS_GRANT_CONFIG_V)<<(DPORT_PWM0_ACCESS_GRANT_CONFIG_S))
2560 #define DPORT_PWM0_ACCESS_GRANT_CONFIG_V  0x3F
2561 #define DPORT_PWM0_ACCESS_GRANT_CONFIG_S  0
2562 
2563 #define DPORT_AHBLITE_MPU_TABLE_TIMERGROUP_REG          (DR_REG_DPORT_BASE + 0x3A0)
2564 /* DPORT_TIMERGROUP_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
2565 /*description: */
2566 #define DPORT_TIMERGROUP_ACCESS_GRANT_CONFIG  0x0000003F
2567 #define DPORT_TIMERGROUP_ACCESS_GRANT_CONFIG_M  ((DPORT_TIMERGROUP_ACCESS_GRANT_CONFIG_V)<<(DPORT_TIMERGROUP_ACCESS_GRANT_CONFIG_S))
2568 #define DPORT_TIMERGROUP_ACCESS_GRANT_CONFIG_V  0x3F
2569 #define DPORT_TIMERGROUP_ACCESS_GRANT_CONFIG_S  0
2570 
2571 #define DPORT_AHBLITE_MPU_TABLE_TIMERGROUP1_REG          (DR_REG_DPORT_BASE + 0x3A4)
2572 /* DPORT_TIMERGROUP1_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
2573 /*description: */
2574 #define DPORT_TIMERGROUP1_ACCESS_GRANT_CONFIG  0x0000003F
2575 #define DPORT_TIMERGROUP1_ACCESS_GRANT_CONFIG_M  ((DPORT_TIMERGROUP1_ACCESS_GRANT_CONFIG_V)<<(DPORT_TIMERGROUP1_ACCESS_GRANT_CONFIG_S))
2576 #define DPORT_TIMERGROUP1_ACCESS_GRANT_CONFIG_V  0x3F
2577 #define DPORT_TIMERGROUP1_ACCESS_GRANT_CONFIG_S  0
2578 
2579 #define DPORT_AHBLITE_MPU_TABLE_SPI2_REG          (DR_REG_DPORT_BASE + 0x3A8)
2580 /* DPORT_SPI2_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
2581 /*description: */
2582 #define DPORT_SPI2_ACCESS_GRANT_CONFIG  0x0000003F
2583 #define DPORT_SPI2_ACCESS_GRANT_CONFIG_M  ((DPORT_SPI2_ACCESS_GRANT_CONFIG_V)<<(DPORT_SPI2_ACCESS_GRANT_CONFIG_S))
2584 #define DPORT_SPI2_ACCESS_GRANT_CONFIG_V  0x3F
2585 #define DPORT_SPI2_ACCESS_GRANT_CONFIG_S  0
2586 
2587 #define DPORT_AHBLITE_MPU_TABLE_SPI3_REG          (DR_REG_DPORT_BASE + 0x3AC)
2588 /* DPORT_SPI3_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
2589 /*description: */
2590 #define DPORT_SPI3_ACCESS_GRANT_CONFIG  0x0000003F
2591 #define DPORT_SPI3_ACCESS_GRANT_CONFIG_M  ((DPORT_SPI3_ACCESS_GRANT_CONFIG_V)<<(DPORT_SPI3_ACCESS_GRANT_CONFIG_S))
2592 #define DPORT_SPI3_ACCESS_GRANT_CONFIG_V  0x3F
2593 #define DPORT_SPI3_ACCESS_GRANT_CONFIG_S  0
2594 
2595 #define DPORT_AHBLITE_MPU_TABLE_APB_CTRL_REG          (DR_REG_DPORT_BASE + 0x3B0)
2596 /* DPORT_APBCTRL_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
2597 /*description: */
2598 #define DPORT_APBCTRL_ACCESS_GRANT_CONFIG  0x0000003F
2599 #define DPORT_APBCTRL_ACCESS_GRANT_CONFIG_M  ((DPORT_APBCTRL_ACCESS_GRANT_CONFIG_V)<<(DPORT_APBCTRL_ACCESS_GRANT_CONFIG_S))
2600 #define DPORT_APBCTRL_ACCESS_GRANT_CONFIG_V  0x3F
2601 #define DPORT_APBCTRL_ACCESS_GRANT_CONFIG_S  0
2602 
2603 #define DPORT_AHBLITE_MPU_TABLE_I2C_EXT1_REG          (DR_REG_DPORT_BASE + 0x3B4)
2604 /* DPORT_I2CEXT1_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
2605 /*description: */
2606 #define DPORT_I2CEXT1_ACCESS_GRANT_CONFIG  0x0000003F
2607 #define DPORT_I2CEXT1_ACCESS_GRANT_CONFIG_M  ((DPORT_I2CEXT1_ACCESS_GRANT_CONFIG_V)<<(DPORT_I2CEXT1_ACCESS_GRANT_CONFIG_S))
2608 #define DPORT_I2CEXT1_ACCESS_GRANT_CONFIG_V  0x3F
2609 #define DPORT_I2CEXT1_ACCESS_GRANT_CONFIG_S  0
2610 
2611 #define DPORT_AHBLITE_MPU_TABLE_SDIO_HOST_REG          (DR_REG_DPORT_BASE + 0x3B8)
2612 /* DPORT_SDIOHOST_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
2613 /*description: */
2614 #define DPORT_SDIOHOST_ACCESS_GRANT_CONFIG  0x0000003F
2615 #define DPORT_SDIOHOST_ACCESS_GRANT_CONFIG_M  ((DPORT_SDIOHOST_ACCESS_GRANT_CONFIG_V)<<(DPORT_SDIOHOST_ACCESS_GRANT_CONFIG_S))
2616 #define DPORT_SDIOHOST_ACCESS_GRANT_CONFIG_V  0x3F
2617 #define DPORT_SDIOHOST_ACCESS_GRANT_CONFIG_S  0
2618 
2619 #define DPORT_AHBLITE_MPU_TABLE_EMAC_REG          (DR_REG_DPORT_BASE + 0x3BC)
2620 /* DPORT_EMAC_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
2621 /*description: */
2622 #define DPORT_EMAC_ACCESS_GRANT_CONFIG  0x0000003F
2623 #define DPORT_EMAC_ACCESS_GRANT_CONFIG_M  ((DPORT_EMAC_ACCESS_GRANT_CONFIG_V)<<(DPORT_EMAC_ACCESS_GRANT_CONFIG_S))
2624 #define DPORT_EMAC_ACCESS_GRANT_CONFIG_V  0x3F
2625 #define DPORT_EMAC_ACCESS_GRANT_CONFIG_S  0
2626 
2627 #define DPORT_AHBLITE_MPU_TABLE_CAN_REG          (DR_REG_DPORT_BASE + 0x3C0)
2628 /* DPORT_CAN_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
2629 /*description: */
2630 #define DPORT_CAN_ACCESS_GRANT_CONFIG  0x0000003F
2631 #define DPORT_CAN_ACCESS_GRANT_CONFIG_M  ((DPORT_CAN_ACCESS_GRANT_CONFIG_V)<<(DPORT_CAN_ACCESS_GRANT_CONFIG_S))
2632 #define DPORT_CAN_ACCESS_GRANT_CONFIG_V  0x3F
2633 #define DPORT_CAN_ACCESS_GRANT_CONFIG_S  0
2634 
2635 #define DPORT_AHBLITE_MPU_TABLE_PWM1_REG          (DR_REG_DPORT_BASE + 0x3C4)
2636 /* DPORT_PWM1_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
2637 /*description: */
2638 #define DPORT_PWM1_ACCESS_GRANT_CONFIG  0x0000003F
2639 #define DPORT_PWM1_ACCESS_GRANT_CONFIG_M  ((DPORT_PWM1_ACCESS_GRANT_CONFIG_V)<<(DPORT_PWM1_ACCESS_GRANT_CONFIG_S))
2640 #define DPORT_PWM1_ACCESS_GRANT_CONFIG_V  0x3F
2641 #define DPORT_PWM1_ACCESS_GRANT_CONFIG_S  0
2642 
2643 #define DPORT_AHBLITE_MPU_TABLE_I2S1_REG          (DR_REG_DPORT_BASE + 0x3C8)
2644 /* DPORT_I2S1_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
2645 /*description: */
2646 #define DPORT_I2S1_ACCESS_GRANT_CONFIG  0x0000003F
2647 #define DPORT_I2S1_ACCESS_GRANT_CONFIG_M  ((DPORT_I2S1_ACCESS_GRANT_CONFIG_V)<<(DPORT_I2S1_ACCESS_GRANT_CONFIG_S))
2648 #define DPORT_I2S1_ACCESS_GRANT_CONFIG_V  0x3F
2649 #define DPORT_I2S1_ACCESS_GRANT_CONFIG_S  0
2650 
2651 #define DPORT_AHBLITE_MPU_TABLE_UART2_REG          (DR_REG_DPORT_BASE + 0x3CC)
2652 /* DPORT_UART2_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
2653 /*description: */
2654 #define DPORT_UART2_ACCESS_GRANT_CONFIG  0x0000003F
2655 #define DPORT_UART2_ACCESS_GRANT_CONFIG_M  ((DPORT_UART2_ACCESS_GRANT_CONFIG_V)<<(DPORT_UART2_ACCESS_GRANT_CONFIG_S))
2656 #define DPORT_UART2_ACCESS_GRANT_CONFIG_V  0x3F
2657 #define DPORT_UART2_ACCESS_GRANT_CONFIG_S  0
2658 
2659 #define DPORT_AHBLITE_MPU_TABLE_PWM2_REG          (DR_REG_DPORT_BASE + 0x3D0)
2660 /* DPORT_PWM2_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
2661 /*description: */
2662 #define DPORT_PWM2_ACCESS_GRANT_CONFIG  0x0000003F
2663 #define DPORT_PWM2_ACCESS_GRANT_CONFIG_M  ((DPORT_PWM2_ACCESS_GRANT_CONFIG_V)<<(DPORT_PWM2_ACCESS_GRANT_CONFIG_S))
2664 #define DPORT_PWM2_ACCESS_GRANT_CONFIG_V  0x3F
2665 #define DPORT_PWM2_ACCESS_GRANT_CONFIG_S  0
2666 
2667 #define DPORT_AHBLITE_MPU_TABLE_PWM3_REG          (DR_REG_DPORT_BASE + 0x3D4)
2668 /* DPORT_PWM3_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
2669 /*description: */
2670 #define DPORT_PWM3_ACCESS_GRANT_CONFIG  0x0000003F
2671 #define DPORT_PWM3_ACCESS_GRANT_CONFIG_M  ((DPORT_PWM3_ACCESS_GRANT_CONFIG_V)<<(DPORT_PWM3_ACCESS_GRANT_CONFIG_S))
2672 #define DPORT_PWM3_ACCESS_GRANT_CONFIG_V  0x3F
2673 #define DPORT_PWM3_ACCESS_GRANT_CONFIG_S  0
2674 
2675 #define DPORT_AHBLITE_MPU_TABLE_RWBT_REG          (DR_REG_DPORT_BASE + 0x3D8)
2676 /* DPORT_RWBT_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
2677 /*description: */
2678 #define DPORT_RWBT_ACCESS_GRANT_CONFIG  0x0000003F
2679 #define DPORT_RWBT_ACCESS_GRANT_CONFIG_M  ((DPORT_RWBT_ACCESS_GRANT_CONFIG_V)<<(DPORT_RWBT_ACCESS_GRANT_CONFIG_S))
2680 #define DPORT_RWBT_ACCESS_GRANT_CONFIG_V  0x3F
2681 #define DPORT_RWBT_ACCESS_GRANT_CONFIG_S  0
2682 
2683 #define DPORT_AHBLITE_MPU_TABLE_BTMAC_REG          (DR_REG_DPORT_BASE + 0x3DC)
2684 /* DPORT_BTMAC_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
2685 /*description: */
2686 #define DPORT_BTMAC_ACCESS_GRANT_CONFIG  0x0000003F
2687 #define DPORT_BTMAC_ACCESS_GRANT_CONFIG_M  ((DPORT_BTMAC_ACCESS_GRANT_CONFIG_V)<<(DPORT_BTMAC_ACCESS_GRANT_CONFIG_S))
2688 #define DPORT_BTMAC_ACCESS_GRANT_CONFIG_V  0x3F
2689 #define DPORT_BTMAC_ACCESS_GRANT_CONFIG_S  0
2690 
2691 #define DPORT_AHBLITE_MPU_TABLE_WIFIMAC_REG          (DR_REG_DPORT_BASE + 0x3E0)
2692 /* DPORT_WIFIMAC_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
2693 /*description: */
2694 #define DPORT_WIFIMAC_ACCESS_GRANT_CONFIG  0x0000003F
2695 #define DPORT_WIFIMAC_ACCESS_GRANT_CONFIG_M  ((DPORT_WIFIMAC_ACCESS_GRANT_CONFIG_V)<<(DPORT_WIFIMAC_ACCESS_GRANT_CONFIG_S))
2696 #define DPORT_WIFIMAC_ACCESS_GRANT_CONFIG_V  0x3F
2697 #define DPORT_WIFIMAC_ACCESS_GRANT_CONFIG_S  0
2698 
2699 #define DPORT_AHBLITE_MPU_TABLE_PWR_REG          (DR_REG_DPORT_BASE + 0x3E4)
2700 /* DPORT_PWR_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
2701 /*description: */
2702 #define DPORT_PWR_ACCESS_GRANT_CONFIG  0x0000003F
2703 #define DPORT_PWR_ACCESS_GRANT_CONFIG_M  ((DPORT_PWR_ACCESS_GRANT_CONFIG_V)<<(DPORT_PWR_ACCESS_GRANT_CONFIG_S))
2704 #define DPORT_PWR_ACCESS_GRANT_CONFIG_V  0x3F
2705 #define DPORT_PWR_ACCESS_GRANT_CONFIG_S  0
2706 
2707 #define DPORT_MEM_ACCESS_DBUG0_REG          (DR_REG_DPORT_BASE + 0x3E8)
2708 /* DPORT_INTERNAL_SRAM_MMU_MULTI_HIT : RO ;bitpos:[29:26] ;default: 4'b0 ; */
2709 /*description: */
2710 #define DPORT_INTERNAL_SRAM_MMU_MULTI_HIT  0x0000000F
2711 #define DPORT_INTERNAL_SRAM_MMU_MULTI_HIT_M  ((DPORT_INTERNAL_SRAM_MMU_MULTI_HIT_V)<<(DPORT_INTERNAL_SRAM_MMU_MULTI_HIT_S))
2712 #define DPORT_INTERNAL_SRAM_MMU_MULTI_HIT_V  0xF
2713 #define DPORT_INTERNAL_SRAM_MMU_MULTI_HIT_S  26
2714 /* DPORT_INTERNAL_SRAM_IA : RO ;bitpos:[25:14] ;default: 12'b0 ; */
2715 /*description: */
2716 #define DPORT_INTERNAL_SRAM_IA  0x00000FFF
2717 #define DPORT_INTERNAL_SRAM_IA_M  ((DPORT_INTERNAL_SRAM_IA_V)<<(DPORT_INTERNAL_SRAM_IA_S))
2718 #define DPORT_INTERNAL_SRAM_IA_V  0xFFF
2719 #define DPORT_INTERNAL_SRAM_IA_S  14
2720 /* DPORT_INTERNAL_SRAM_MMU_AD : RO ;bitpos:[13:10] ;default: 4'b0 ; */
2721 /*description: */
2722 #define DPORT_INTERNAL_SRAM_MMU_AD  0x0000000F
2723 #define DPORT_INTERNAL_SRAM_MMU_AD_M  ((DPORT_INTERNAL_SRAM_MMU_AD_V)<<(DPORT_INTERNAL_SRAM_MMU_AD_S))
2724 #define DPORT_INTERNAL_SRAM_MMU_AD_V  0xF
2725 #define DPORT_INTERNAL_SRAM_MMU_AD_S  10
2726 /* DPORT_SHARE_ROM_IA : RO ;bitpos:[9:6] ;default: 4'b0 ; */
2727 /*description: */
2728 #define DPORT_SHARE_ROM_IA  0x0000000F
2729 #define DPORT_SHARE_ROM_IA_M  ((DPORT_SHARE_ROM_IA_V)<<(DPORT_SHARE_ROM_IA_S))
2730 #define DPORT_SHARE_ROM_IA_V  0xF
2731 #define DPORT_SHARE_ROM_IA_S  6
2732 /* DPORT_SHARE_ROM_MPU_AD : RO ;bitpos:[5:4] ;default: 2'b0 ; */
2733 /*description: */
2734 #define DPORT_SHARE_ROM_MPU_AD  0x00000003
2735 #define DPORT_SHARE_ROM_MPU_AD_M  ((DPORT_SHARE_ROM_MPU_AD_V)<<(DPORT_SHARE_ROM_MPU_AD_S))
2736 #define DPORT_SHARE_ROM_MPU_AD_V  0x3
2737 #define DPORT_SHARE_ROM_MPU_AD_S  4
2738 /* DPORT_APP_ROM_IA : RO ;bitpos:[3] ;default: 1'b0 ; */
2739 /*description: */
2740 #define DPORT_APP_ROM_IA  (BIT(3))
2741 #define DPORT_APP_ROM_IA_M  (BIT(3))
2742 #define DPORT_APP_ROM_IA_V  0x1
2743 #define DPORT_APP_ROM_IA_S  3
2744 /* DPORT_APP_ROM_MPU_AD : RO ;bitpos:[2] ;default: 1'b0 ; */
2745 /*description: */
2746 #define DPORT_APP_ROM_MPU_AD  (BIT(2))
2747 #define DPORT_APP_ROM_MPU_AD_M  (BIT(2))
2748 #define DPORT_APP_ROM_MPU_AD_V  0x1
2749 #define DPORT_APP_ROM_MPU_AD_S  2
2750 /* DPORT_PRO_ROM_IA : RO ;bitpos:[1] ;default: 1'b0 ; */
2751 /*description: */
2752 #define DPORT_PRO_ROM_IA  (BIT(1))
2753 #define DPORT_PRO_ROM_IA_M  (BIT(1))
2754 #define DPORT_PRO_ROM_IA_V  0x1
2755 #define DPORT_PRO_ROM_IA_S  1
2756 /* DPORT_PRO_ROM_MPU_AD : RO ;bitpos:[0] ;default: 1'b0 ; */
2757 /*description: */
2758 #define DPORT_PRO_ROM_MPU_AD  (BIT(0))
2759 #define DPORT_PRO_ROM_MPU_AD_M  (BIT(0))
2760 #define DPORT_PRO_ROM_MPU_AD_V  0x1
2761 #define DPORT_PRO_ROM_MPU_AD_S  0
2762 
2763 #define DPORT_MEM_ACCESS_DBUG1_REG          (DR_REG_DPORT_BASE + 0x3EC)
2764 /* DPORT_AHBLITE_IA : RO ;bitpos:[10] ;default: 1'b0 ; */
2765 /*description: */
2766 #define DPORT_AHBLITE_IA  (BIT(10))
2767 #define DPORT_AHBLITE_IA_M  (BIT(10))
2768 #define DPORT_AHBLITE_IA_V  0x1
2769 #define DPORT_AHBLITE_IA_S  10
2770 /* DPORT_AHBLITE_ACCESS_DENY : RO ;bitpos:[9] ;default: 1'b0 ; */
2771 /*description: */
2772 #define DPORT_AHBLITE_ACCESS_DENY  (BIT(9))
2773 #define DPORT_AHBLITE_ACCESS_DENY_M  (BIT(9))
2774 #define DPORT_AHBLITE_ACCESS_DENY_V  0x1
2775 #define DPORT_AHBLITE_ACCESS_DENY_S  9
2776 /* DPORT_AHB_ACCESS_DENY : RO ;bitpos:[8] ;default: 1'b0 ; */
2777 /*description: */
2778 #define DPORT_AHB_ACCESS_DENY  (BIT(8))
2779 #define DPORT_AHB_ACCESS_DENY_M  (BIT(8))
2780 #define DPORT_AHB_ACCESS_DENY_V  0x1
2781 #define DPORT_AHB_ACCESS_DENY_S  8
2782 /* DPORT_PIDGEN_IA : RO ;bitpos:[7:6] ;default: 2'b0 ; */
2783 /*description: */
2784 #define DPORT_PIDGEN_IA  0x00000003
2785 #define DPORT_PIDGEN_IA_M  ((DPORT_PIDGEN_IA_V)<<(DPORT_PIDGEN_IA_S))
2786 #define DPORT_PIDGEN_IA_V  0x3
2787 #define DPORT_PIDGEN_IA_S  6
2788 /* DPORT_ARB_IA : RO ;bitpos:[5:4] ;default: 2'b0 ; */
2789 /*description: */
2790 #define DPORT_ARB_IA  0x00000003
2791 #define DPORT_ARB_IA_M  ((DPORT_ARB_IA_V)<<(DPORT_ARB_IA_S))
2792 #define DPORT_ARB_IA_V  0x3
2793 #define DPORT_ARB_IA_S  4
2794 /* DPORT_INTERNAL_SRAM_MMU_MISS : RO ;bitpos:[3:0] ;default: 4'b0 ; */
2795 /*description: */
2796 #define DPORT_INTERNAL_SRAM_MMU_MISS  0x0000000F
2797 #define DPORT_INTERNAL_SRAM_MMU_MISS_M  ((DPORT_INTERNAL_SRAM_MMU_MISS_V)<<(DPORT_INTERNAL_SRAM_MMU_MISS_S))
2798 #define DPORT_INTERNAL_SRAM_MMU_MISS_V  0xF
2799 #define DPORT_INTERNAL_SRAM_MMU_MISS_S  0
2800 
2801 #define DPORT_PRO_DCACHE_DBUG0_REG          (DR_REG_DPORT_BASE + 0x3F0)
2802 /* DPORT_PRO_RX_END : RO ;bitpos:[23] ;default: 1'b0 ; */
2803 /*description: */
2804 #define DPORT_PRO_RX_END  (BIT(23))
2805 #define DPORT_PRO_RX_END_M  (BIT(23))
2806 #define DPORT_PRO_RX_END_V  0x1
2807 #define DPORT_PRO_RX_END_S  23
2808 /* DPORT_PRO_SLAVE_WDATA_V : RO ;bitpos:[22] ;default: 1'b0 ; */
2809 /*description: */
2810 #define DPORT_PRO_SLAVE_WDATA_V  (BIT(22))
2811 #define DPORT_PRO_SLAVE_WDATA_V_M  (BIT(22))
2812 #define DPORT_PRO_SLAVE_WDATA_V_V  0x1
2813 #define DPORT_PRO_SLAVE_WDATA_V_S  22
2814 /* DPORT_PRO_SLAVE_WR : RO ;bitpos:[21] ;default: 1'b0 ; */
2815 /*description: */
2816 #define DPORT_PRO_SLAVE_WR  (BIT(21))
2817 #define DPORT_PRO_SLAVE_WR_M  (BIT(21))
2818 #define DPORT_PRO_SLAVE_WR_V  0x1
2819 #define DPORT_PRO_SLAVE_WR_S  21
2820 /* DPORT_PRO_TX_END : RO ;bitpos:[20] ;default: 1'b0 ; */
2821 /*description: */
2822 #define DPORT_PRO_TX_END  (BIT(20))
2823 #define DPORT_PRO_TX_END_M  (BIT(20))
2824 #define DPORT_PRO_TX_END_V  0x1
2825 #define DPORT_PRO_TX_END_S  20
2826 /* DPORT_PRO_WR_BAK_TO_READ : RO ;bitpos:[19] ;default: 1'b0 ; */
2827 /*description: */
2828 #define DPORT_PRO_WR_BAK_TO_READ  (BIT(19))
2829 #define DPORT_PRO_WR_BAK_TO_READ_M  (BIT(19))
2830 #define DPORT_PRO_WR_BAK_TO_READ_V  0x1
2831 #define DPORT_PRO_WR_BAK_TO_READ_S  19
2832 /* DPORT_PRO_CACHE_STATE : RO ;bitpos:[18:7] ;default: 12'b0 ; */
2833 /*description: */
2834 #define DPORT_PRO_CACHE_STATE  0x00000FFF
2835 #define DPORT_PRO_CACHE_STATE_M  ((DPORT_PRO_CACHE_STATE_V)<<(DPORT_PRO_CACHE_STATE_S))
2836 #define DPORT_PRO_CACHE_STATE_V  0xFFF
2837 #define DPORT_PRO_CACHE_STATE_S  7
2838 /* DPORT_PRO_CACHE_IA : RO ;bitpos:[6:1] ;default: 6'b0 ; */
2839 /*description: */
2840 #define DPORT_PRO_CACHE_IA  0x0000003F
2841 #define DPORT_PRO_CACHE_IA_M  ((DPORT_PRO_CACHE_IA_V)<<(DPORT_PRO_CACHE_IA_S))
2842 #define DPORT_PRO_CACHE_IA_V  0x3F
2843 #define DPORT_PRO_CACHE_IA_S  1
2844 /* DPORT_PRO_CACHE_MMU_IA : RO ;bitpos:[0] ;default: 1'b0 ; */
2845 /*description: */
2846 #define DPORT_PRO_CACHE_MMU_IA  (BIT(0))
2847 #define DPORT_PRO_CACHE_MMU_IA_M  (BIT(0))
2848 #define DPORT_PRO_CACHE_MMU_IA_V  0x1
2849 #define DPORT_PRO_CACHE_MMU_IA_S  0
2850 
2851 #define DPORT_PRO_DCACHE_DBUG1_REG          (DR_REG_DPORT_BASE + 0x3F4)
2852 /* DPORT_PRO_CTAG_RAM_RDATA : RO ;bitpos:[31:0] ;default: 32'b0 ; */
2853 /*description: */
2854 #define DPORT_PRO_CTAG_RAM_RDATA  0xFFFFFFFF
2855 #define DPORT_PRO_CTAG_RAM_RDATA_M  ((DPORT_PRO_CTAG_RAM_RDATA_V)<<(DPORT_PRO_CTAG_RAM_RDATA_S))
2856 #define DPORT_PRO_CTAG_RAM_RDATA_V  0xFFFFFFFF
2857 #define DPORT_PRO_CTAG_RAM_RDATA_S  0
2858 
2859 #define DPORT_PRO_DCACHE_DBUG2_REG          (DR_REG_DPORT_BASE + 0x3F8)
2860 /* DPORT_PRO_CACHE_VADDR : RO ;bitpos:[26:0] ;default: 27'b0 ; */
2861 /*description: */
2862 #define DPORT_PRO_CACHE_VADDR  0x07FFFFFF
2863 #define DPORT_PRO_CACHE_VADDR_M  ((DPORT_PRO_CACHE_VADDR_V)<<(DPORT_PRO_CACHE_VADDR_S))
2864 #define DPORT_PRO_CACHE_VADDR_V  0x7FFFFFF
2865 #define DPORT_PRO_CACHE_VADDR_S  0
2866 
2867 #define DPORT_PRO_DCACHE_DBUG3_REG          (DR_REG_DPORT_BASE + 0x3FC)
2868 /* DPORT_PRO_CACHE_IRAM0_PID_ERROR : RO ;bitpos:[15] ;default: 1'b0 ; */
2869 /*description: */
2870 #define DPORT_PRO_CACHE_IRAM0_PID_ERROR  (BIT(15))
2871 #define DPORT_PRO_CACHE_IRAM0_PID_ERROR_M  (BIT(15))
2872 #define DPORT_PRO_CACHE_IRAM0_PID_ERROR_V  0x1
2873 #define DPORT_PRO_CACHE_IRAM0_PID_ERROR_S  15
2874 /* DPORT_PRO_CPU_DISABLED_CACHE_IA : RO ;bitpos:[14:9] ;default: 6'b0 ; */
2875 /*description: */
2876 #define DPORT_PRO_CPU_DISABLED_CACHE_IA  0x0000003F
2877 #define DPORT_PRO_CPU_DISABLED_CACHE_IA_M  ((DPORT_PRO_CPU_DISABLED_CACHE_IA_V)<<(DPORT_PRO_CPU_DISABLED_CACHE_IA_S))
2878 #define DPORT_PRO_CPU_DISABLED_CACHE_IA_V  0x3F
2879 #define DPORT_PRO_CPU_DISABLED_CACHE_IA_S  9
2880 /* This is the contents of DPORT_PRO_CPU_DISABLED_CACHE_IA field expanded */
2881 /* The following bits will be set upon invalid access for different memory
2882  * regions: */
2883 /* Port of the APP CPU cache when cache is used in high/low or odd/even mode */
2884 #define DPORT_PRO_CPU_DISABLED_CACHE_IA_OPPOSITE   BIT(9)
2885 #define DPORT_PRO_CPU_DISABLED_CACHE_IA_OPPOSITE_M BIT(9)
2886 #define DPORT_PRO_CPU_DISABLED_CACHE_IA_OPPOSITE_V 1
2887 #define DPORT_PRO_CPU_DISABLED_CACHE_IA_OPPOSITE_S 9
2888 /* DRAM1: 0x3F80_0000 ~ 0x3FBF_FFFF(R/W) */
2889 #define DPORT_PRO_CPU_DISABLED_CACHE_IA_DRAM1    BIT(10)
2890 #define DPORT_PRO_CPU_DISABLED_CACHE_IA_DRAM1_M  BIT(10)
2891 #define DPORT_PRO_CPU_DISABLED_CACHE_IA_DRAM1_V  1
2892 #define DPORT_PRO_CPU_DISABLED_CACHE_IA_DRAM1_S  10
2893 /* IROM0: 0x4080_0000 ~ 0x40BF_FFFF(RO) */
2894 #define DPORT_PRO_CPU_DISABLED_CACHE_IA_IROM0    BIT(11)
2895 #define DPORT_PRO_CPU_DISABLED_CACHE_IA_IROM0_M  BIT(11)
2896 #define DPORT_PRO_CPU_DISABLED_CACHE_IA_IROM0_V  1
2897 #define DPORT_PRO_CPU_DISABLED_CACHE_IA_IROM0_S  11
2898 /* IRAM1:  0x4040_0000 ~ 0x407F_FFFF(RO) */
2899 #define DPORT_PRO_CPU_DISABLED_CACHE_IA_IRAM1    BIT(12)
2900 #define DPORT_PRO_CPU_DISABLED_CACHE_IA_IRAM1_M  BIT(12)
2901 #define DPORT_PRO_CPU_DISABLED_CACHE_IA_IRAM1_V  1
2902 #define DPORT_PRO_CPU_DISABLED_CACHE_IA_IRAM1_S  12
2903 /* IRAM0: 0x4080_0000 ~ 0x40BF_FFFF(RO) */
2904 #define DPORT_PRO_CPU_DISABLED_CACHE_IA_IRAM0    BIT(13)
2905 #define DPORT_PRO_CPU_DISABLED_CACHE_IA_IRAM0_M  BIT(13)
2906 #define DPORT_PRO_CPU_DISABLED_CACHE_IA_IRAM0_V  1
2907 #define DPORT_PRO_CPU_DISABLED_CACHE_IA_IRAM0_S  13
2908 /* DROM0: 0x3F40_0000 ~ 0x3F7F_FFFF (RO) */
2909 #define DPORT_PRO_CPU_DISABLED_CACHE_IA_DROM0    BIT(14)
2910 #define DPORT_PRO_CPU_DISABLED_CACHE_IA_DROM0_M  BIT(14)
2911 #define DPORT_PRO_CPU_DISABLED_CACHE_IA_DROM0_V  1
2912 #define DPORT_PRO_CPU_DISABLED_CACHE_IA_DROM0_S  14
2913 
2914 /* DPORT_PRO_MMU_RDATA : RO ;bitpos:[8:0] ;default: 9'h0 ; */
2915 /*description: */
2916 #define DPORT_PRO_MMU_RDATA  0x000001FF
2917 #define DPORT_PRO_MMU_RDATA_M  ((DPORT_PRO_MMU_RDATA_V)<<(DPORT_PRO_MMU_RDATA_S))
2918 #define DPORT_PRO_MMU_RDATA_V  0x1FF
2919 #define DPORT_PRO_MMU_RDATA_S  0
2920 
2921 #define DPORT_PRO_DCACHE_DBUG4_REG          (DR_REG_DPORT_BASE + 0x400)
2922 /* DPORT_PRO_DRAM1ADDR0_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */
2923 /*description: */
2924 #define DPORT_PRO_DRAM1ADDR0_IA  0x000FFFFF
2925 #define DPORT_PRO_DRAM1ADDR0_IA_M  ((DPORT_PRO_DRAM1ADDR0_IA_V)<<(DPORT_PRO_DRAM1ADDR0_IA_S))
2926 #define DPORT_PRO_DRAM1ADDR0_IA_V  0xFFFFF
2927 #define DPORT_PRO_DRAM1ADDR0_IA_S  0
2928 
2929 #define DPORT_PRO_DCACHE_DBUG5_REG          (DR_REG_DPORT_BASE + 0x404)
2930 /* DPORT_PRO_DROM0ADDR0_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */
2931 /*description: */
2932 #define DPORT_PRO_DROM0ADDR0_IA  0x000FFFFF
2933 #define DPORT_PRO_DROM0ADDR0_IA_M  ((DPORT_PRO_DROM0ADDR0_IA_V)<<(DPORT_PRO_DROM0ADDR0_IA_S))
2934 #define DPORT_PRO_DROM0ADDR0_IA_V  0xFFFFF
2935 #define DPORT_PRO_DROM0ADDR0_IA_S  0
2936 
2937 #define DPORT_PRO_DCACHE_DBUG6_REG          (DR_REG_DPORT_BASE + 0x408)
2938 /* DPORT_PRO_IRAM0ADDR_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */
2939 /*description: */
2940 #define DPORT_PRO_IRAM0ADDR_IA  0x000FFFFF
2941 #define DPORT_PRO_IRAM0ADDR_IA_M  ((DPORT_PRO_IRAM0ADDR_IA_V)<<(DPORT_PRO_IRAM0ADDR_IA_S))
2942 #define DPORT_PRO_IRAM0ADDR_IA_V  0xFFFFF
2943 #define DPORT_PRO_IRAM0ADDR_IA_S  0
2944 
2945 #define DPORT_PRO_DCACHE_DBUG7_REG          (DR_REG_DPORT_BASE + 0x40C)
2946 /* DPORT_PRO_IRAM1ADDR_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */
2947 /*description: */
2948 #define DPORT_PRO_IRAM1ADDR_IA  0x000FFFFF
2949 #define DPORT_PRO_IRAM1ADDR_IA_M  ((DPORT_PRO_IRAM1ADDR_IA_V)<<(DPORT_PRO_IRAM1ADDR_IA_S))
2950 #define DPORT_PRO_IRAM1ADDR_IA_V  0xFFFFF
2951 #define DPORT_PRO_IRAM1ADDR_IA_S  0
2952 
2953 #define DPORT_PRO_DCACHE_DBUG8_REG          (DR_REG_DPORT_BASE + 0x410)
2954 /* DPORT_PRO_IROM0ADDR_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */
2955 /*description: */
2956 #define DPORT_PRO_IROM0ADDR_IA  0x000FFFFF
2957 #define DPORT_PRO_IROM0ADDR_IA_M  ((DPORT_PRO_IROM0ADDR_IA_V)<<(DPORT_PRO_IROM0ADDR_IA_S))
2958 #define DPORT_PRO_IROM0ADDR_IA_V  0xFFFFF
2959 #define DPORT_PRO_IROM0ADDR_IA_S  0
2960 
2961 #define DPORT_PRO_DCACHE_DBUG9_REG          (DR_REG_DPORT_BASE + 0x414)
2962 /* DPORT_PRO_OPSDRAMADDR_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */
2963 /*description: */
2964 #define DPORT_PRO_OPSDRAMADDR_IA  0x000FFFFF
2965 #define DPORT_PRO_OPSDRAMADDR_IA_M  ((DPORT_PRO_OPSDRAMADDR_IA_V)<<(DPORT_PRO_OPSDRAMADDR_IA_S))
2966 #define DPORT_PRO_OPSDRAMADDR_IA_V  0xFFFFF
2967 #define DPORT_PRO_OPSDRAMADDR_IA_S  0
2968 
2969 #define DPORT_APP_DCACHE_DBUG0_REG          (DR_REG_DPORT_BASE + 0x418)
2970 /* DPORT_APP_RX_END : RO ;bitpos:[23] ;default: 1'b0 ; */
2971 /*description: */
2972 #define DPORT_APP_RX_END  (BIT(23))
2973 #define DPORT_APP_RX_END_M  (BIT(23))
2974 #define DPORT_APP_RX_END_V  0x1
2975 #define DPORT_APP_RX_END_S  23
2976 /* DPORT_APP_SLAVE_WDATA_V : RO ;bitpos:[22] ;default: 1'b0 ; */
2977 /*description: */
2978 #define DPORT_APP_SLAVE_WDATA_V  (BIT(22))
2979 #define DPORT_APP_SLAVE_WDATA_V_M  (BIT(22))
2980 #define DPORT_APP_SLAVE_WDATA_V_V  0x1
2981 #define DPORT_APP_SLAVE_WDATA_V_S  22
2982 /* DPORT_APP_SLAVE_WR : RO ;bitpos:[21] ;default: 1'b0 ; */
2983 /*description: */
2984 #define DPORT_APP_SLAVE_WR  (BIT(21))
2985 #define DPORT_APP_SLAVE_WR_M  (BIT(21))
2986 #define DPORT_APP_SLAVE_WR_V  0x1
2987 #define DPORT_APP_SLAVE_WR_S  21
2988 /* DPORT_APP_TX_END : RO ;bitpos:[20] ;default: 1'b0 ; */
2989 /*description: */
2990 #define DPORT_APP_TX_END  (BIT(20))
2991 #define DPORT_APP_TX_END_M  (BIT(20))
2992 #define DPORT_APP_TX_END_V  0x1
2993 #define DPORT_APP_TX_END_S  20
2994 /* DPORT_APP_WR_BAK_TO_READ : RO ;bitpos:[19] ;default: 1'b0 ; */
2995 /*description: */
2996 #define DPORT_APP_WR_BAK_TO_READ  (BIT(19))
2997 #define DPORT_APP_WR_BAK_TO_READ_M  (BIT(19))
2998 #define DPORT_APP_WR_BAK_TO_READ_V  0x1
2999 #define DPORT_APP_WR_BAK_TO_READ_S  19
3000 /* DPORT_APP_CACHE_STATE : RO ;bitpos:[18:7] ;default: 12'b0 ; */
3001 /*description: */
3002 #define DPORT_APP_CACHE_STATE  0x00000FFF
3003 #define DPORT_APP_CACHE_STATE_M  ((DPORT_APP_CACHE_STATE_V)<<(DPORT_APP_CACHE_STATE_S))
3004 #define DPORT_APP_CACHE_STATE_V  0xFFF
3005 #define DPORT_APP_CACHE_STATE_S  7
3006 /* DPORT_APP_CACHE_IA : RO ;bitpos:[6:1] ;default: 6'b0 ; */
3007 /*description: */
3008 #define DPORT_APP_CACHE_IA  0x0000003F
3009 #define DPORT_APP_CACHE_IA_M  ((DPORT_APP_CACHE_IA_V)<<(DPORT_APP_CACHE_IA_S))
3010 #define DPORT_APP_CACHE_IA_V  0x3F
3011 #define DPORT_APP_CACHE_IA_S  1
3012 /* DPORT_APP_CACHE_MMU_IA : RO ;bitpos:[0] ;default: 1'b0 ; */
3013 /*description: */
3014 #define DPORT_APP_CACHE_MMU_IA  (BIT(0))
3015 #define DPORT_APP_CACHE_MMU_IA_M  (BIT(0))
3016 #define DPORT_APP_CACHE_MMU_IA_V  0x1
3017 #define DPORT_APP_CACHE_MMU_IA_S  0
3018 
3019 #define DPORT_APP_DCACHE_DBUG1_REG          (DR_REG_DPORT_BASE + 0x41C)
3020 /* DPORT_APP_CTAG_RAM_RDATA : RO ;bitpos:[31:0] ;default: 32'b0 ; */
3021 /*description: */
3022 #define DPORT_APP_CTAG_RAM_RDATA  0xFFFFFFFF
3023 #define DPORT_APP_CTAG_RAM_RDATA_M  ((DPORT_APP_CTAG_RAM_RDATA_V)<<(DPORT_APP_CTAG_RAM_RDATA_S))
3024 #define DPORT_APP_CTAG_RAM_RDATA_V  0xFFFFFFFF
3025 #define DPORT_APP_CTAG_RAM_RDATA_S  0
3026 
3027 #define DPORT_APP_DCACHE_DBUG2_REG          (DR_REG_DPORT_BASE + 0x420)
3028 /* DPORT_APP_CACHE_VADDR : RO ;bitpos:[26:0] ;default: 27'b0 ; */
3029 /*description: */
3030 #define DPORT_APP_CACHE_VADDR  0x07FFFFFF
3031 #define DPORT_APP_CACHE_VADDR_M  ((DPORT_APP_CACHE_VADDR_V)<<(DPORT_APP_CACHE_VADDR_S))
3032 #define DPORT_APP_CACHE_VADDR_V  0x7FFFFFF
3033 #define DPORT_APP_CACHE_VADDR_S  0
3034 
3035 #define DPORT_APP_DCACHE_DBUG3_REG          (DR_REG_DPORT_BASE + 0x424)
3036 /* DPORT_APP_CACHE_IRAM0_PID_ERROR : RO ;bitpos:[15] ;default: 1'b0 ; */
3037 /*description: */
3038 #define DPORT_APP_CACHE_IRAM0_PID_ERROR  (BIT(15))
3039 #define DPORT_APP_CACHE_IRAM0_PID_ERROR_M  (BIT(15))
3040 #define DPORT_APP_CACHE_IRAM0_PID_ERROR_V  0x1
3041 #define DPORT_APP_CACHE_IRAM0_PID_ERROR_S  15
3042 /* DPORT_APP_CPU_DISABLED_CACHE_IA : RO ;bitpos:[14:9] ;default: 6'b0 ; */
3043 /*description: */
3044 #define DPORT_APP_CPU_DISABLED_CACHE_IA  0x0000003F
3045 #define DPORT_APP_CPU_DISABLED_CACHE_IA_M  ((DPORT_APP_CPU_DISABLED_CACHE_IA_V)<<(DPORT_APP_CPU_DISABLED_CACHE_IA_S))
3046 #define DPORT_APP_CPU_DISABLED_CACHE_IA_V  0x3F
3047 #define DPORT_APP_CPU_DISABLED_CACHE_IA_S  9
3048 /* This is the contents of DPORT_APP_CPU_DISABLED_CACHE_IA field expanded */
3049 /* The following bits will be set upon invalid access for different memory
3050  * regions: */
3051 /* Port of the PRO CPU cache when cache is used in high/low or odd/even mode */
3052 #define DPORT_APP_CPU_DISABLED_CACHE_IA_OPPOSITE   BIT(9)
3053 #define DPORT_APP_CPU_DISABLED_CACHE_IA_OPPOSITE_M BIT(9)
3054 #define DPORT_APP_CPU_DISABLED_CACHE_IA_OPPOSITE_V 1
3055 #define DPORT_APP_CPU_DISABLED_CACHE_IA_OPPOSITE_S 9
3056 /* DRAM1: 0x3F80_0000 ~ 0x3FBF_FFFF(R/W) */
3057 #define DPORT_APP_CPU_DISABLED_CACHE_IA_DRAM1    BIT(10)
3058 #define DPORT_APP_CPU_DISABLED_CACHE_IA_DRAM1_M  BIT(10)
3059 #define DPORT_APP_CPU_DISABLED_CACHE_IA_DRAM1_V  1
3060 #define DPORT_APP_CPU_DISABLED_CACHE_IA_DRAM1_S  10
3061 /* IROM0: 0x4080_0000 ~ 0x40BF_FFFF(RO) */
3062 #define DPORT_APP_CPU_DISABLED_CACHE_IA_IROM0    BIT(11)
3063 #define DPORT_APP_CPU_DISABLED_CACHE_IA_IROM0_M  BIT(11)
3064 #define DPORT_APP_CPU_DISABLED_CACHE_IA_IROM0_V  1
3065 #define DPORT_APP_CPU_DISABLED_CACHE_IA_IROM0_S  11
3066 /* IRAM1:  0x4040_0000 ~ 0x407F_FFFF(RO) */
3067 #define DPORT_APP_CPU_DISABLED_CACHE_IA_IRAM1    BIT(12)
3068 #define DPORT_APP_CPU_DISABLED_CACHE_IA_IRAM1_M  BIT(12)
3069 #define DPORT_APP_CPU_DISABLED_CACHE_IA_IRAM1_V  1
3070 #define DPORT_APP_CPU_DISABLED_CACHE_IA_IRAM1_S  12
3071 /* IRAM0: 0x4080_0000 ~ 0x40BF_FFFF(RO) */
3072 #define DPORT_APP_CPU_DISABLED_CACHE_IA_IRAM0    BIT(13)
3073 #define DPORT_APP_CPU_DISABLED_CACHE_IA_IRAM0_M  BIT(13)
3074 #define DPORT_APP_CPU_DISABLED_CACHE_IA_IRAM0_V  1
3075 #define DPORT_APP_CPU_DISABLED_CACHE_IA_IRAM0_S  13
3076 /* DROM0: 0x3F40_0000 ~ 0x3F7F_FFFF (RO) */
3077 #define DPORT_APP_CPU_DISABLED_CACHE_IA_DROM0    BIT(14)
3078 #define DPORT_APP_CPU_DISABLED_CACHE_IA_DROM0_M  BIT(14)
3079 #define DPORT_APP_CPU_DISABLED_CACHE_IA_DROM0_V  1
3080 #define DPORT_APP_CPU_DISABLED_CACHE_IA_DROM0_S  14
3081 
3082 /* DPORT_APP_MMU_RDATA : RO ;bitpos:[8:0] ;default: 9'h0 ; */
3083 /*description: */
3084 #define DPORT_APP_MMU_RDATA  0x000001FF
3085 #define DPORT_APP_MMU_RDATA_M  ((DPORT_APP_MMU_RDATA_V)<<(DPORT_APP_MMU_RDATA_S))
3086 #define DPORT_APP_MMU_RDATA_V  0x1FF
3087 #define DPORT_APP_MMU_RDATA_S  0
3088 
3089 #define DPORT_APP_DCACHE_DBUG4_REG          (DR_REG_DPORT_BASE + 0x428)
3090 /* DPORT_APP_DRAM1ADDR0_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */
3091 /*description: */
3092 #define DPORT_APP_DRAM1ADDR0_IA  0x000FFFFF
3093 #define DPORT_APP_DRAM1ADDR0_IA_M  ((DPORT_APP_DRAM1ADDR0_IA_V)<<(DPORT_APP_DRAM1ADDR0_IA_S))
3094 #define DPORT_APP_DRAM1ADDR0_IA_V  0xFFFFF
3095 #define DPORT_APP_DRAM1ADDR0_IA_S  0
3096 
3097 #define DPORT_APP_DCACHE_DBUG5_REG          (DR_REG_DPORT_BASE + 0x42C)
3098 /* DPORT_APP_DROM0ADDR0_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */
3099 /*description: */
3100 #define DPORT_APP_DROM0ADDR0_IA  0x000FFFFF
3101 #define DPORT_APP_DROM0ADDR0_IA_M  ((DPORT_APP_DROM0ADDR0_IA_V)<<(DPORT_APP_DROM0ADDR0_IA_S))
3102 #define DPORT_APP_DROM0ADDR0_IA_V  0xFFFFF
3103 #define DPORT_APP_DROM0ADDR0_IA_S  0
3104 
3105 #define DPORT_APP_DCACHE_DBUG6_REG          (DR_REG_DPORT_BASE + 0x430)
3106 /* DPORT_APP_IRAM0ADDR_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */
3107 /*description: */
3108 #define DPORT_APP_IRAM0ADDR_IA  0x000FFFFF
3109 #define DPORT_APP_IRAM0ADDR_IA_M  ((DPORT_APP_IRAM0ADDR_IA_V)<<(DPORT_APP_IRAM0ADDR_IA_S))
3110 #define DPORT_APP_IRAM0ADDR_IA_V  0xFFFFF
3111 #define DPORT_APP_IRAM0ADDR_IA_S  0
3112 
3113 #define DPORT_APP_DCACHE_DBUG7_REG          (DR_REG_DPORT_BASE + 0x434)
3114 /* DPORT_APP_IRAM1ADDR_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */
3115 /*description: */
3116 #define DPORT_APP_IRAM1ADDR_IA  0x000FFFFF
3117 #define DPORT_APP_IRAM1ADDR_IA_M  ((DPORT_APP_IRAM1ADDR_IA_V)<<(DPORT_APP_IRAM1ADDR_IA_S))
3118 #define DPORT_APP_IRAM1ADDR_IA_V  0xFFFFF
3119 #define DPORT_APP_IRAM1ADDR_IA_S  0
3120 
3121 #define DPORT_APP_DCACHE_DBUG8_REG          (DR_REG_DPORT_BASE + 0x438)
3122 /* DPORT_APP_IROM0ADDR_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */
3123 /*description: */
3124 #define DPORT_APP_IROM0ADDR_IA  0x000FFFFF
3125 #define DPORT_APP_IROM0ADDR_IA_M  ((DPORT_APP_IROM0ADDR_IA_V)<<(DPORT_APP_IROM0ADDR_IA_S))
3126 #define DPORT_APP_IROM0ADDR_IA_V  0xFFFFF
3127 #define DPORT_APP_IROM0ADDR_IA_S  0
3128 
3129 #define DPORT_APP_DCACHE_DBUG9_REG          (DR_REG_DPORT_BASE + 0x43C)
3130 /* DPORT_APP_OPSDRAMADDR_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */
3131 /*description: */
3132 #define DPORT_APP_OPSDRAMADDR_IA  0x000FFFFF
3133 #define DPORT_APP_OPSDRAMADDR_IA_M  ((DPORT_APP_OPSDRAMADDR_IA_V)<<(DPORT_APP_OPSDRAMADDR_IA_S))
3134 #define DPORT_APP_OPSDRAMADDR_IA_V  0xFFFFF
3135 #define DPORT_APP_OPSDRAMADDR_IA_S  0
3136 
3137 #define DPORT_PRO_CPU_RECORD_CTRL_REG          (DR_REG_DPORT_BASE + 0x440)
3138 /* DPORT_PRO_CPU_PDEBUG_ENABLE : R/W ;bitpos:[8] ;default: 1'b1 ; */
3139 /*description: */
3140 #define DPORT_PRO_CPU_PDEBUG_ENABLE  (BIT(8))
3141 #define DPORT_PRO_CPU_PDEBUG_ENABLE_M  (BIT(8))
3142 #define DPORT_PRO_CPU_PDEBUG_ENABLE_V  0x1
3143 #define DPORT_PRO_CPU_PDEBUG_ENABLE_S  8
3144 /* DPORT_PRO_CPU_RECORD_DISABLE : R/W ;bitpos:[4] ;default: 1'b0 ; */
3145 /*description: */
3146 #define DPORT_PRO_CPU_RECORD_DISABLE  (BIT(4))
3147 #define DPORT_PRO_CPU_RECORD_DISABLE_M  (BIT(4))
3148 #define DPORT_PRO_CPU_RECORD_DISABLE_V  0x1
3149 #define DPORT_PRO_CPU_RECORD_DISABLE_S  4
3150 /* DPORT_PRO_CPU_RECORD_ENABLE : R/W ;bitpos:[0] ;default: 1'b0 ; */
3151 /*description: */
3152 #define DPORT_PRO_CPU_RECORD_ENABLE  (BIT(0))
3153 #define DPORT_PRO_CPU_RECORD_ENABLE_M  (BIT(0))
3154 #define DPORT_PRO_CPU_RECORD_ENABLE_V  0x1
3155 #define DPORT_PRO_CPU_RECORD_ENABLE_S  0
3156 
3157 #define DPORT_PRO_CPU_RECORD_STATUS_REG          (DR_REG_DPORT_BASE + 0x444)
3158 /* DPORT_PRO_CPU_RECORDING : RO ;bitpos:[0] ;default: 1'b0 ; */
3159 /*description: */
3160 #define DPORT_PRO_CPU_RECORDING  (BIT(0))
3161 #define DPORT_PRO_CPU_RECORDING_M  (BIT(0))
3162 #define DPORT_PRO_CPU_RECORDING_V  0x1
3163 #define DPORT_PRO_CPU_RECORDING_S  0
3164 
3165 #define DPORT_PRO_CPU_RECORD_PID_REG          (DR_REG_DPORT_BASE + 0x448)
3166 /* DPORT_RECORD_PRO_PID : RO ;bitpos:[2:0] ;default: 3'd0 ; */
3167 /*description: */
3168 #define DPORT_RECORD_PRO_PID  0x00000007
3169 #define DPORT_RECORD_PRO_PID_M  ((DPORT_RECORD_PRO_PID_V)<<(DPORT_RECORD_PRO_PID_S))
3170 #define DPORT_RECORD_PRO_PID_V  0x7
3171 #define DPORT_RECORD_PRO_PID_S  0
3172 
3173 #define DPORT_PRO_CPU_RECORD_PDEBUGINST_REG          (DR_REG_DPORT_BASE + 0x44C)
3174 /* DPORT_RECORD_PRO_PDEBUGINST : RO ;bitpos:[31:0] ;default: 32'b0 ; */
3175 /*description: */
3176 #define DPORT_RECORD_PRO_PDEBUGINST  0xFFFFFFFF
3177 #define DPORT_RECORD_PRO_PDEBUGINST_M  ((DPORT_RECORD_PRO_PDEBUGINST_V)<<(DPORT_RECORD_PRO_PDEBUGINST_S))
3178 #define DPORT_RECORD_PRO_PDEBUGINST_V  0xFFFFFFFF
3179 #define DPORT_RECORD_PRO_PDEBUGINST_S  0
3180 /* register layout:
3181  * SIZE [7..0] 		 : Instructions normally complete in the W stage. The size of the instruction in the W is given
3182  *                	   by this field in number of bytes. If it is 8’b0 in a given cycle the W stage has no completing
3183  *                	   instruction. This is also known as a bubble cycle. Also see DPORT_PRO_CPU_RECORD_PDEBUGSTATUS_REG.
3184  * ISRC [14..12]	 : Instruction source.
3185 ** LOOP [23..20]	 : Loopback status.
3186 ** CINTLEVEL [27..24]: CINTLEVEL.
3187 */
3188 #define DPORT_RECORD_PDEBUGINST_SZ_M  		((DPORT_RECORD_PDEBUGINST_SZ_V)<<(DPORT_RECORD_PDEBUGINST_SZ_S))
3189 #define DPORT_RECORD_PDEBUGINST_SZ_V  		0xFF
3190 #define DPORT_RECORD_PDEBUGINST_SZ_S  		0
3191 #define DPORT_RECORD_PDEBUGINST_SZ(_r_)		(((_r_)>>DPORT_RECORD_PDEBUGINST_SZ_S) & DPORT_RECORD_PDEBUGINST_SZ_V)
3192 #define DPORT_RECORD_PDEBUGINST_ISRC_M  	((DPORT_RECORD_PDEBUGINST_ISRC_V)<<(DPORT_RECORD_PDEBUGINST_ISRC_S))
3193 #define DPORT_RECORD_PDEBUGINST_ISRC_V  	0x07
3194 #define DPORT_RECORD_PDEBUGINST_ISRC_S  	12
3195 #define DPORT_RECORD_PDEBUGINST_ISRC(_r_)	(((_r_)>>DPORT_RECORD_PDEBUGINST_ISRC_S) & DPORT_RECORD_PDEBUGINST_ISRC_V)
3196 // #define DPORT_RECORD_PDEBUGINST_LOOP_M  	((DPORT_RECORD_PDEBUGINST_LOOP_V)<<(DPORT_RECORD_PDEBUGINST_LOOP_S))
3197 // #define DPORT_RECORD_PDEBUGINST_LOOP_V  	0x0F
3198 // #define DPORT_RECORD_PDEBUGINST_LOOP_S  	20
3199 // #define DPORT_RECORD_PDEBUGINST_LOOP(_r_)	(((_r_)>>DPORT_RECORD_PDEBUGINST_LOOP_S) & DPORT_RECORD_PDEBUGINST_LOOP_V)
3200 #define DPORT_RECORD_PDEBUGINST_LOOP_REP 	(BIT(20)) /* loopback will occur */
3201 #define DPORT_RECORD_PDEBUGINST_LOOP		(BIT(21)) /* last inst of loop */
3202 #define DPORT_RECORD_PDEBUGINST_CINTL_M  	((DPORT_RECORD_PDEBUGINST_CINTL_V)<<(DPORT_RECORD_PDEBUGINST_CINTL_S))
3203 #define DPORT_RECORD_PDEBUGINST_CINTL_V  	0x0F
3204 #define DPORT_RECORD_PDEBUGINST_CINTL_S  	24
3205 #define DPORT_RECORD_PDEBUGINST_CINTL(_r_)	(((_r_)>>DPORT_RECORD_PDEBUGINST_CINTL_S) & DPORT_RECORD_PDEBUGINST_CINTL_V)
3206 
3207 #define DPORT_PRO_CPU_RECORD_PDEBUGSTATUS_REG          (DR_REG_DPORT_BASE + 0x450)
3208 /* DPORT_RECORD_PRO_PDEBUGSTATUS : RO ;bitpos:[7:0] ;default: 8'b0 ; */
3209 /*description: */
3210 #define DPORT_RECORD_PRO_PDEBUGSTATUS  0x000000FF
3211 #define DPORT_RECORD_PRO_PDEBUGSTATUS_M  ((DPORT_RECORD_PRO_PDEBUGSTATUS_V)<<(DPORT_RECORD_PRO_PDEBUGSTATUS_S))
3212 #define DPORT_RECORD_PRO_PDEBUGSTATUS_V  0xFF
3213 #define DPORT_RECORD_PRO_PDEBUGSTATUS_S  0
3214 /* register layout:
3215  * BBCAUSE [5..0]: Indicates cause for bubble cycle. See below for posible values. When DPORT_RECORD_PDEBUGINST_SZ == 0
3216  * INSNTYPE[5..0]: Indicates type of instruction retiring in the W stage. See below for posible values. When DPORT_RECORD_PDEBUGINST_SZ > 0
3217 */
3218 #define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_M  		((DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_V)<<(DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_S))
3219 #define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_V  		0x3F
3220 #define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_S  		0
3221 #define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE(_r_)		(((_r_)>>DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_S) & DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_V)
3222 #define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_PSO		0x00 /* Power shut off */
3223 #define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_DEP		0x02 /* Register dependency or resource conflict. See DPORT_XXX_CPU_RECORD_PDEBUGDATA_REG for extra info. */
3224 #define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_CTL		0x04 /* Control transfer bubble */
3225 #define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_ICM		0x08 /* I-cache miss (incl uncached miss) */
3226 #define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_DCM		0x0C /* D-cache miss (excl uncached miss) */
3227 #define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_EXC0		0x10 /* Exception or interrupt (W stage). See DPORT_XXX_CPU_RECORD_PDEBUGDATA_REG for extra info.
3228 															The virtual address of the instruction that was killed appears on DPORT_PRO_CPU_RECORD_PDEBUGPC_REG[31:0] */
3229 #define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_EXC1		0x11 /* Exception or interrupt (W+1 stage). See DPORT_XXX_CPU_RECORD_PDEBUGDATA_REG for extra info. */
3230 #define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_RPL		0x14 /* Instruction replay (other). DPORT_XXX_CPU_RECORD_PDEBUGDATA_REG has the PC of the replaying instruction. */
3231 #define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_ITLB		0x18 /* HW ITLB refill. The refill address and data are available on
3232 															DPORT_PRO_CPU_RECORD_PDEBUGLS0ADDR_REG and DPORT_PRO_CPU_RECORD_PDEBUGLS0DATA_REG. */
3233 #define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_ITLBM		0x1A /* ITLB miss */
3234 #define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_DTLB		0x1C /* HW DTLB refill. The refill address and data are available on
3235 															DPORT_PRO_CPU_RECORD_PDEBUGLS0ADDR_REG and DPORT_PRO_CPU_RECORD_PDEBUGLS0DATA_REG. */
3236 #define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_DTLBM		0x1E /* DTLB miss */
3237 #define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_STALL		0x20 /* Stall . The cause of the global stall is further classified in the DPORT_XXX_CPU_RECORD_PDEBUGDATA_REG. */
3238 #define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_HWMEC		0x24 /* HW-corrected memory error */
3239 #define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_WAITI		0x28 /* WAITI mode */
3240 #define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_OTHER		0x3C /* all other bubbles */
3241 #define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_M  		((DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_V)<<(DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_S))
3242 #define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_V  		0x3F
3243 #define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_S  		0
3244 #define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE(_r_)		(((_r_)>>DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_S) & DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_V)
3245 #define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_JX		0x00 /* JX */
3246 #define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_CALLX	0x04 /* CALLX */
3247 #define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_CRET		0x08 /* All call returns */
3248 #define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_ERET		0x0C /* All exception returns */
3249 #define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_B		0x10 /* Branch taken or loop not taken */
3250 #define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_J		0x14 /* J */
3251 #define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_CALL		0x18 /* CALL */
3252 #define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_BN		0x1C /* Branch not taken */
3253 #define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_LOOP		0x20 /* Loop instruction (taken) */
3254 #define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_S32C1I	0x24 /* S32C1I. The address and load data (before the conditional store) are available on the LS signals*/
3255 #define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_WXSR2LB	0x28 /* WSR/XSR to LBEGIN */
3256 #define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_WSR2MMID	0x2C /* WSR to MMID */
3257 #define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_RWXSR	0x30 /* RSR or WSR (except MMID and LBEGIN) or XSR (except LBEGIN) */
3258 #define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_RWER		0x34 /* RER or WER */
3259 #define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_DEF		0x3C /* Default */
3260 
3261 #define DPORT_PRO_CPU_RECORD_PDEBUGDATA_REG          (DR_REG_DPORT_BASE + 0x454)
3262 /* DPORT_RECORD_PRO_PDEBUGDATA : RO ;bitpos:[31:0] ;default: 32'b0 ; */
3263 /*description: */
3264 #define DPORT_RECORD_PRO_PDEBUGDATA  0xFFFFFFFF
3265 #define DPORT_RECORD_PRO_PDEBUGDATA_M  ((DPORT_RECORD_PRO_PDEBUGDATA_V)<<(DPORT_RECORD_PRO_PDEBUGDATA_S))
3266 #define DPORT_RECORD_PRO_PDEBUGDATA_V  0xFFFFFFFF
3267 #define DPORT_RECORD_PRO_PDEBUGDATA_S  0
3268 /* register layout when bubble cycke cause is DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_DEP:
3269  *
3270  * HALT [17]: HALT instruction (TX only)
3271  * MEMW [16]: MEMW, EXTW or EXCW instruction dependency
3272  * REG  [12]: register dependencies or resource (e.g.TIE ports) conflicts
3273  * STR  [11]: store release (instruction) dependency
3274  * LSU  [8] : various LSU dependencies (MHT access, prefetch, cache access insts, s32c1i, etc)
3275  * OTHER[0] : all other hold dependencies resulting from data or resource dependencies
3276 */
3277 #define DPORT_RECORD_PDEBUGDATA_DEP_HALT  	(BIT(17))
3278 #define DPORT_RECORD_PDEBUGDATA_DEP_MEMW  	(BIT(16))
3279 #define DPORT_RECORD_PDEBUGDATA_DEP_REG  	(BIT(12))
3280 #define DPORT_RECORD_PDEBUGDATA_DEP_STR  	(BIT(11))
3281 #define DPORT_RECORD_PDEBUGDATA_DEP_LSU  	(BIT(8))
3282 #define DPORT_RECORD_PDEBUGDATA_DEP_OTHER	(BIT(0))
3283 /* register layout when bubble cycke cause is DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_EXCn:
3284  *
3285  * EXCCAUSE[21..16]: Processor exception cause
3286  * EXCVEC  [4..0]  : Encoded Exception Vector
3287 */
3288 #define DPORT_RECORD_PDEBUGDATA_EXCCAUSE_M  	((DPORT_RECORD_PDEBUGDATA_EXCCAUSE_V)<<(DPORT_RECORD_PDEBUGDATA_EXCCAUSE_S))
3289 #define DPORT_RECORD_PDEBUGDATA_EXCCAUSE_V  	0x3F
3290 #define DPORT_RECORD_PDEBUGDATA_EXCCAUSE_S  	16
3291 #define DPORT_RECORD_PDEBUGDATA_EXCCAUSE(_r_)	(((_r_)>>DPORT_RECORD_PDEBUGDATA_EXCCAUSE_S) & DPORT_RECORD_PDEBUGDATA_EXCCAUSE_V)
3292 #define DPORT_RECORD_PDEBUGDATA_EXCVEC_M  		((DPORT_RECORD_PDEBUGDATA_EXCCAUSE_V)<<(DPORT_RECORD_PDEBUGDATA_EXCCAUSE_S))
3293 #define DPORT_RECORD_PDEBUGDATA_EXCVEC_V  		0x1F
3294 #define DPORT_RECORD_PDEBUGDATA_EXCVEC_S  		0
3295 #define DPORT_RECORD_PDEBUGDATA_EXCVEC(_r_)		(((_r_)>>DPORT_RECORD_PDEBUGDATA_EXCCAUSE_S) & DPORT_RECORD_PDEBUGDATA_EXCCAUSE_V)
3296 #define DPORT_RECORD_PDEBUGDATA_EXCVEC_NONE		0x00 /* no vector */
3297 #define DPORT_RECORD_PDEBUGDATA_EXCVEC_RST		0x01 /* Reset */
3298 #define DPORT_RECORD_PDEBUGDATA_EXCVEC_DBG		0x02 /* Debug (repl corresp level “n”) */
3299 #define DPORT_RECORD_PDEBUGDATA_EXCVEC_NMI		0x03 /* NMI (repl corresp level “n”) */
3300 #define DPORT_RECORD_PDEBUGDATA_EXCVEC_USR		0x04 /* User */
3301 #define DPORT_RECORD_PDEBUGDATA_EXCVEC_KRNL		0x05 /* Kernel */
3302 #define DPORT_RECORD_PDEBUGDATA_EXCVEC_DBL		0x06 /* Double */
3303 #define DPORT_RECORD_PDEBUGDATA_EXCVEC_EMEM		0x07 /* Memory Error */
3304 #define DPORT_RECORD_PDEBUGDATA_EXCVEC_OVF4		0x0A /* Window Overflow 4 */
3305 #define DPORT_RECORD_PDEBUGDATA_EXCVEC_UNF4		0x0B /* Window Underflow 4 */
3306 #define DPORT_RECORD_PDEBUGDATA_EXCVEC_OVF8		0x0C /* Window Overflow 8 */
3307 #define DPORT_RECORD_PDEBUGDATA_EXCVEC_UNF8		0x0D /* Window Underflow 8 */
3308 #define DPORT_RECORD_PDEBUGDATA_EXCVEC_OVF12	0x0E /* Window Overflow 12 */
3309 #define DPORT_RECORD_PDEBUGDATA_EXCVEC_UNF12	0x0F /* Window Underflow 12 */
3310 #define DPORT_RECORD_PDEBUGDATA_EXCVEC_INT2		0x10 /* Int Level 2 (n/a if debug/NMI) */
3311 #define DPORT_RECORD_PDEBUGDATA_EXCVEC_INT3		0x11 /* Int Level 3 (n/a if debug/NMI) */
3312 #define DPORT_RECORD_PDEBUGDATA_EXCVEC_INT4		0x12 /* Int Level 4 (n/a if debug/NMI) */
3313 #define DPORT_RECORD_PDEBUGDATA_EXCVEC_INT5		0x13 /* Int Level 5 (n/a if debug/NMI) */
3314 #define DPORT_RECORD_PDEBUGDATA_EXCVEC_INT6		0x14 /* Int Level 6 (n/a if debug/NMI) */
3315 /* register layout when bubble cycke cause is DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_STALL:
3316  *
3317  * ITERDIV[19]  : Iterative divide stall.
3318  * ITERMUL[18]  : Iterative multiply stall.
3319  * BANKCONFL[16]: Bank-conflict stall.
3320  * BPLOAD[15]  	: Bypass load stall.
3321  * LSPROC[14]  	: Load/store miss-processing stall.
3322  * L32R[13]	   	: FastL32R stall.
3323  * BPIFETCH[12]	: Bypass I fetch stall.
3324  * RUNSTALL[10]	: RunStall.
3325  * TIE[9] 	   	: TIE port stall.
3326  * IPIF[8]	   	: Instruction RAM inbound-PIF stall.
3327  * IRAMBUSY[7] 	: Instruction RAM/ROM busy stall.
3328  * ICM[6] 	   	: I-cache-miss stall.
3329  * LSU[4]      	: The LSU will stall the pipeline under various local memory access conflict situations.
3330  * DCM[3] 	   	: D-cache-miss stall.
3331  * BUFFCONFL[2]	: Store buffer conflict stall.
3332  * BUFF[1] 	   	: Store buffer full stall.
3333 */
3334 #define DPORT_RECORD_PDEBUGDATA_STALL_ITERDIV	(BIT(19))
3335 #define DPORT_RECORD_PDEBUGDATA_STALL_ITERMUL	(BIT(18))
3336 #define DPORT_RECORD_PDEBUGDATA_STALL_BANKCONFL	(BIT(16))
3337 #define DPORT_RECORD_PDEBUGDATA_STALL_BPLOAD	(BIT(15))
3338 #define DPORT_RECORD_PDEBUGDATA_STALL_LSPROC	(BIT(14))
3339 #define DPORT_RECORD_PDEBUGDATA_STALL_L32R		(BIT(13))
3340 #define DPORT_RECORD_PDEBUGDATA_STALL_BPIFETCH	(BIT(12))
3341 #define DPORT_RECORD_PDEBUGDATA_STALL_RUN		(BIT(10))
3342 #define DPORT_RECORD_PDEBUGDATA_STALL_TIE		(BIT(9))
3343 #define DPORT_RECORD_PDEBUGDATA_STALL_IPIF		(BIT(8))
3344 #define DPORT_RECORD_PDEBUGDATA_STALL_IRAMBUSY	(BIT(7))
3345 #define DPORT_RECORD_PDEBUGDATA_STALL_ICM		(BIT(6))
3346 #define DPORT_RECORD_PDEBUGDATA_STALL_LSU		(BIT(4))
3347 #define DPORT_RECORD_PDEBUGDATA_STALL_DCM		(BIT(3))
3348 #define DPORT_RECORD_PDEBUGDATA_STALL_BUFFCONFL	(BIT(2))
3349 #define DPORT_RECORD_PDEBUGDATA_STALL_BUFF		(BIT(1))
3350 /* register layout for DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_RWXSR:
3351  *
3352  * XSR[10]		: XSR Instruction
3353  * WSR[9]		: WSR Instruction
3354  * RSR[8]		: RSR Instruction
3355  * SR[7..0] : Special Register Number
3356 */
3357 #define DPORT_RECORD_PDEBUGDATA_INSNTYPE_XSR		(BIT(10))
3358 #define DPORT_RECORD_PDEBUGDATA_INSNTYPE_WSR		(BIT(9))
3359 #define DPORT_RECORD_PDEBUGDATA_INSNTYPE_RSR		(BIT(8))
3360 #define DPORT_RECORD_PDEBUGDATA_INSNTYPE_SR_M  		((DPORT_RECORD_PDEBUGDATA_INSNTYPE_SR_V)<<(DPORT_RECORD_PDEBUGDATA_INSNTYPE_SR_S))
3361 #define DPORT_RECORD_PDEBUGDATA_INSNTYPE_SR_V  		0xFF
3362 #define DPORT_RECORD_PDEBUGDATA_INSNTYPE_SR_S  		0
3363 #define DPORT_RECORD_PDEBUGDATA_INSNTYPE_SR(_r_)	(((_r_)>>DPORT_RECORD_PDEBUGDATA_INSNTYPE_SR_S) & DPORT_RECORD_PDEBUGDATA_INSNTYPE_SR_V)
3364 /* register layout for DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_RWER:
3365  *
3366  * ER[13..2]: ER Address
3367  * WER[1]	: WER Instruction
3368  * RER[0]	: RER Instruction
3369 */
3370 #define DPORT_RECORD_PDEBUGDATA_INSNTYPE_ER_M  		((DPORT_RECORD_PDEBUGDATA_INSNTYPE_ER_V)<<(DPORT_RECORD_PDEBUGDATA_INSNTYPE_ER_S))
3371 #define DPORT_RECORD_PDEBUGDATA_INSNTYPE_ER_V  		0xFFF
3372 #define DPORT_RECORD_PDEBUGDATA_INSNTYPE_ER_S  		2
3373 #define DPORT_RECORD_PDEBUGDATA_INSNTYPE_ER(_r_)	(((_r_)>>DPORT_RECORD_PDEBUGDATA_INSNTYPE_ER_S) & DPORT_RECORD_PDEBUGDATA_INSNTYPE_ER_V)
3374 #define DPORT_RECORD_PDEBUGDATA_INSNTYPE_WER		(BIT(1))
3375 #define DPORT_RECORD_PDEBUGDATA_INSNTYPE_RER		(BIT(0))
3376 
3377 
3378 #define DPORT_PRO_CPU_RECORD_PDEBUGPC_REG          (DR_REG_DPORT_BASE + 0x458)
3379 /* DPORT_RECORD_PRO_PDEBUGPC : RO ;bitpos:[31:0] ;default: 32'b0 ; */
3380 /*description: */
3381 #define DPORT_RECORD_PRO_PDEBUGPC  0xFFFFFFFF
3382 #define DPORT_RECORD_PRO_PDEBUGPC_M  ((DPORT_RECORD_PRO_PDEBUGPC_V)<<(DPORT_RECORD_PRO_PDEBUGPC_S))
3383 #define DPORT_RECORD_PRO_PDEBUGPC_V  0xFFFFFFFF
3384 #define DPORT_RECORD_PRO_PDEBUGPC_S  0
3385 
3386 #define DPORT_PRO_CPU_RECORD_PDEBUGLS0STAT_REG          (DR_REG_DPORT_BASE + 0x45C)
3387 /* DPORT_RECORD_PRO_PDEBUGLS0STAT : RO ;bitpos:[31:0] ;default: 32'b0 ; */
3388 /*description: */
3389 #define DPORT_RECORD_PRO_PDEBUGLS0STAT  0xFFFFFFFF
3390 #define DPORT_RECORD_PRO_PDEBUGLS0STAT_M  ((DPORT_RECORD_PRO_PDEBUGLS0STAT_V)<<(DPORT_RECORD_PRO_PDEBUGLS0STAT_S))
3391 #define DPORT_RECORD_PRO_PDEBUGLS0STAT_V  0xFFFFFFFF
3392 #define DPORT_RECORD_PRO_PDEBUGLS0STAT_S  0
3393 /* register layout:
3394  * TYPE [3..0] 	 : Type of instruction in LS.
3395  * SZ [7..4]	 : Operand size.
3396  * DTLBM [8]	 : Data TLB miss.
3397  * DCM [9]		 : D-cache miss.
3398  * DCH [10]		 : D-cache hit.
3399  * UC [12]		 : Uncached.
3400  * WB [13]		 : Writeback.
3401  * COH [16]	     : Coherency.
3402  * STCOH [18..17]: Coherent state.
3403  * TGT [23..20]  : Local target.
3404 */
3405 #define DPORT_RECORD_PDEBUGLS0STAT_TYPE_M  		((DPORT_RECORD_PDEBUGLS0STAT_TYPE_V)<<(DPORT_RECORD_PDEBUGLS0STAT_TYPE_S))
3406 #define DPORT_RECORD_PDEBUGLS0STAT_TYPE_V  		0x0F
3407 #define DPORT_RECORD_PDEBUGLS0STAT_TYPE_S  		0
3408 #define DPORT_RECORD_PDEBUGLS0STAT_TYPE(_r_)	(((_r_)>>DPORT_RECORD_PDEBUGLS0STAT_TYPE_S) & DPORT_RECORD_PDEBUGLS0STAT_TYPE_V)
3409 #define DPORT_RECORD_PDEBUGLS0STAT_TYPE_NONE	0x00 /* neither */
3410 #define DPORT_RECORD_PDEBUGLS0STAT_TYPE_ITLBR	0x01 /* hw itlb refill */
3411 #define DPORT_RECORD_PDEBUGLS0STAT_TYPE_DTLBR	0x02 /* hw dtlb refill */
3412 #define DPORT_RECORD_PDEBUGLS0STAT_TYPE_LD		0x05 /* load */
3413 #define DPORT_RECORD_PDEBUGLS0STAT_TYPE_STR		0x06 /* store */
3414 #define DPORT_RECORD_PDEBUGLS0STAT_TYPE_L32R	0x08 /* l32r */
3415 #define DPORT_RECORD_PDEBUGLS0STAT_TYPE_S32CLI1	0x0A /* s32ci1 */
3416 #define DPORT_RECORD_PDEBUGLS0STAT_TYPE_CTI		0x0C /* cache test inst */
3417 #define DPORT_RECORD_PDEBUGLS0STAT_TYPE_RWXSR	0x0E /* rsr/wsr/xsr */
3418 #define DPORT_RECORD_PDEBUGLS0STAT_TYPE_RWER	0x0F /* rer/wer */
3419 #define DPORT_RECORD_PDEBUGLS0STAT_SZ_M  		((DPORT_RECORD_PDEBUGLS0STAT_SZ_V)<<(DPORT_RECORD_PDEBUGLS0STAT_SZ_S))
3420 #define DPORT_RECORD_PDEBUGLS0STAT_SZ_V  		0x0F
3421 #define DPORT_RECORD_PDEBUGLS0STAT_SZ_S  		4
3422 #define DPORT_RECORD_PDEBUGLS0STAT_SZ(_r_)		(((_r_)>>DPORT_RECORD_PDEBUGLS0STAT_SZ_S) & DPORT_RECORD_PDEBUGLS0STAT_SZ_V)
3423 #define DPORT_RECORD_PDEBUGLS0STAT_SZB(_r_)		((8<<DPORT_RECORD_PDEBUGLS0STAT_SZ(_r_))/8) // in bytes
3424 #define DPORT_RECORD_PDEBUGLS0STAT_DTLBM		(BIT(8))
3425 #define DPORT_RECORD_PDEBUGLS0STAT_DCM			(BIT(9))
3426 #define DPORT_RECORD_PDEBUGLS0STAT_DCH			(BIT(10))
3427 #define DPORT_RECORD_PDEBUGLS0STAT_UC			(BIT(12))
3428 #define DPORT_RECORD_PDEBUGLS0STAT_WB			(BIT(13))
3429 #define DPORT_RECORD_PDEBUGLS0STAT_COH			(BIT(16))
3430 #define DPORT_RECORD_PDEBUGLS0STAT_STCOH_M  	((DPORT_RECORD_PDEBUGLS0STAT_STCOH_V)<<(DPORT_RECORD_PDEBUGLS0STAT_STCOH_S))
3431 #define DPORT_RECORD_PDEBUGLS0STAT_STCOH_V  	0x03
3432 #define DPORT_RECORD_PDEBUGLS0STAT_STCOH_S  	17
3433 #define DPORT_RECORD_PDEBUGLS0STAT_STCOH(_r_)	(((_r_)>>DPORT_RECORD_PDEBUGLS0STAT_STCOH_S) & DPORT_RECORD_PDEBUGLS0STAT_STCOH_V)
3434 #define DPORT_RECORD_PDEBUGLS0STAT_STCOH_NONE  	0x0 /* neither shared nor exclusive nor modified */
3435 #define DPORT_RECORD_PDEBUGLS0STAT_STCOH_SHARED	0x1 /* shared */
3436 #define DPORT_RECORD_PDEBUGLS0STAT_STCOH_EXCL  	0x2 /* exclusive */
3437 #define DPORT_RECORD_PDEBUGLS0STAT_STCOH_MOD  	0x3 /* modified */
3438 #define DPORT_RECORD_PDEBUGLS0STAT_TGT_M  		((DPORT_RECORD_PDEBUGLS0STAT_TGT_V)<<(DPORT_RECORD_PDEBUGLS0STAT_TGT_S))
3439 #define DPORT_RECORD_PDEBUGLS0STAT_TGT_V  		0x0F
3440 #define DPORT_RECORD_PDEBUGLS0STAT_TGT_S  		20
3441 #define DPORT_RECORD_PDEBUGLS0STAT_TGT(_r_)		(((_r_)>>DPORT_RECORD_PDEBUGLS0STAT_TGT_S) & DPORT_RECORD_PDEBUGLS0STAT_TGT_V)
3442 #define DPORT_RECORD_PDEBUGLS0STAT_TGT_EXT  	0x0 /* not to local memory */
3443 #define DPORT_RECORD_PDEBUGLS0STAT_TGT_IRAM0	0x2 /* 001x: InstRAM (0/1) */
3444 #define DPORT_RECORD_PDEBUGLS0STAT_TGT_IRAM1	0x3 /* 001x: InstRAM (0/1) */
3445 #define DPORT_RECORD_PDEBUGLS0STAT_TGT_IROM0  	0x4 /* 010x: InstROM (0/1) */
3446 #define DPORT_RECORD_PDEBUGLS0STAT_TGT_IROM1  	0x5 /* 010x: InstROM (0/1) */
3447 #define DPORT_RECORD_PDEBUGLS0STAT_TGT_DRAM0  	0x0A /* 101x: DataRAM (0/1) */
3448 #define DPORT_RECORD_PDEBUGLS0STAT_TGT_DRAM1  	0x0B /* 101x: DataRAM (0/1) */
3449 #define DPORT_RECORD_PDEBUGLS0STAT_TGT_DROM0  	0xE /* 111x: DataROM (0/1) */
3450 #define DPORT_RECORD_PDEBUGLS0STAT_TGT_DROM1  	0xF /* 111x: DataROM (0/1) */
3451 // #define DPORT_RECORD_PDEBUGLS0STAT_TGT_IRAM(_t_)	(((_t_)&0xE)=0x2) /* 001x: InstRAM (0/1) */
3452 // #define DPORT_RECORD_PDEBUGLS0STAT_TGT_IROM(_t_)  	(((_t_)&0xE)=0x4) /* 010x: InstROM (0/1) */
3453 // #define DPORT_RECORD_PDEBUGLS0STAT_TGT_DRAM(_t_)  	(((_t_)&0xE)=0x2) /* 101x: DataRAM (0/1) */
3454 // #define DPORT_RECORD_PDEBUGLS0STAT_TGT_DROM(_t_)  	(((_t_)&0xE)=0x2) /* 111x: DataROM (0/1) */
3455 
3456 #define DPORT_PRO_CPU_RECORD_PDEBUGLS0ADDR_REG          (DR_REG_DPORT_BASE + 0x460)
3457 /* DPORT_RECORD_PRO_PDEBUGLS0ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
3458 /*description: */
3459 #define DPORT_RECORD_PRO_PDEBUGLS0ADDR  0xFFFFFFFF
3460 #define DPORT_RECORD_PRO_PDEBUGLS0ADDR_M  ((DPORT_RECORD_PRO_PDEBUGLS0ADDR_V)<<(DPORT_RECORD_PRO_PDEBUGLS0ADDR_S))
3461 #define DPORT_RECORD_PRO_PDEBUGLS0ADDR_V  0xFFFFFFFF
3462 #define DPORT_RECORD_PRO_PDEBUGLS0ADDR_S  0
3463 
3464 #define DPORT_PRO_CPU_RECORD_PDEBUGLS0DATA_REG          (DR_REG_DPORT_BASE + 0x464)
3465 /* DPORT_RECORD_PRO_PDEBUGLS0DATA : RO ;bitpos:[31:0] ;default: 32'b0 ; */
3466 /*description: */
3467 #define DPORT_RECORD_PRO_PDEBUGLS0DATA  0xFFFFFFFF
3468 #define DPORT_RECORD_PRO_PDEBUGLS0DATA_M  ((DPORT_RECORD_PRO_PDEBUGLS0DATA_V)<<(DPORT_RECORD_PRO_PDEBUGLS0DATA_S))
3469 #define DPORT_RECORD_PRO_PDEBUGLS0DATA_V  0xFFFFFFFF
3470 #define DPORT_RECORD_PRO_PDEBUGLS0DATA_S  0
3471 
3472 #define DPORT_APP_CPU_RECORD_CTRL_REG          (DR_REG_DPORT_BASE + 0x468)
3473 /* DPORT_APP_CPU_PDEBUG_ENABLE : R/W ;bitpos:[8] ;default: 1'b1 ; */
3474 /*description: */
3475 #define DPORT_APP_CPU_PDEBUG_ENABLE  (BIT(8))
3476 #define DPORT_APP_CPU_PDEBUG_ENABLE_M  (BIT(8))
3477 #define DPORT_APP_CPU_PDEBUG_ENABLE_V  0x1
3478 #define DPORT_APP_CPU_PDEBUG_ENABLE_S  8
3479 /* DPORT_APP_CPU_RECORD_DISABLE : R/W ;bitpos:[4] ;default: 1'b0 ; */
3480 /*description: */
3481 #define DPORT_APP_CPU_RECORD_DISABLE  (BIT(4))
3482 #define DPORT_APP_CPU_RECORD_DISABLE_M  (BIT(4))
3483 #define DPORT_APP_CPU_RECORD_DISABLE_V  0x1
3484 #define DPORT_APP_CPU_RECORD_DISABLE_S  4
3485 /* DPORT_APP_CPU_RECORD_ENABLE : R/W ;bitpos:[0] ;default: 1'b0 ; */
3486 /*description: */
3487 #define DPORT_APP_CPU_RECORD_ENABLE  (BIT(0))
3488 #define DPORT_APP_CPU_RECORD_ENABLE_M  (BIT(0))
3489 #define DPORT_APP_CPU_RECORD_ENABLE_V  0x1
3490 #define DPORT_APP_CPU_RECORD_ENABLE_S  0
3491 
3492 #define DPORT_APP_CPU_RECORD_STATUS_REG          (DR_REG_DPORT_BASE + 0x46C)
3493 /* DPORT_APP_CPU_RECORDING : RO ;bitpos:[0] ;default: 1'b0 ; */
3494 /*description: */
3495 #define DPORT_APP_CPU_RECORDING  (BIT(0))
3496 #define DPORT_APP_CPU_RECORDING_M  (BIT(0))
3497 #define DPORT_APP_CPU_RECORDING_V  0x1
3498 #define DPORT_APP_CPU_RECORDING_S  0
3499 
3500 #define DPORT_APP_CPU_RECORD_PID_REG          (DR_REG_DPORT_BASE + 0x470)
3501 /* DPORT_RECORD_APP_PID : RO ;bitpos:[2:0] ;default: 3'd0 ; */
3502 /*description: */
3503 #define DPORT_RECORD_APP_PID  0x00000007
3504 #define DPORT_RECORD_APP_PID_M  ((DPORT_RECORD_APP_PID_V)<<(DPORT_RECORD_APP_PID_S))
3505 #define DPORT_RECORD_APP_PID_V  0x7
3506 #define DPORT_RECORD_APP_PID_S  0
3507 
3508 #define DPORT_APP_CPU_RECORD_PDEBUGINST_REG          (DR_REG_DPORT_BASE + 0x474)
3509 /* DPORT_RECORD_APP_PDEBUGINST : RO ;bitpos:[31:0] ;default: 32'b0 ; */
3510 /*description: */
3511 #define DPORT_RECORD_APP_PDEBUGINST  0xFFFFFFFF
3512 #define DPORT_RECORD_APP_PDEBUGINST_M  ((DPORT_RECORD_APP_PDEBUGINST_V)<<(DPORT_RECORD_APP_PDEBUGINST_S))
3513 #define DPORT_RECORD_APP_PDEBUGINST_V  0xFFFFFFFF
3514 #define DPORT_RECORD_APP_PDEBUGINST_S  0
3515 
3516 #define DPORT_APP_CPU_RECORD_PDEBUGSTATUS_REG          (DR_REG_DPORT_BASE + 0x478)
3517 /* DPORT_RECORD_APP_PDEBUGSTATUS : RO ;bitpos:[7:0] ;default: 8'b0 ; */
3518 /*description: */
3519 #define DPORT_RECORD_APP_PDEBUGSTATUS  0x000000FF
3520 #define DPORT_RECORD_APP_PDEBUGSTATUS_M  ((DPORT_RECORD_APP_PDEBUGSTATUS_V)<<(DPORT_RECORD_APP_PDEBUGSTATUS_S))
3521 #define DPORT_RECORD_APP_PDEBUGSTATUS_V  0xFF
3522 #define DPORT_RECORD_APP_PDEBUGSTATUS_S  0
3523 
3524 #define DPORT_APP_CPU_RECORD_PDEBUGDATA_REG          (DR_REG_DPORT_BASE + 0x47C)
3525 /* DPORT_RECORD_APP_PDEBUGDATA : RO ;bitpos:[31:0] ;default: 32'b0 ; */
3526 /*description: */
3527 #define DPORT_RECORD_APP_PDEBUGDATA  0xFFFFFFFF
3528 #define DPORT_RECORD_APP_PDEBUGDATA_M  ((DPORT_RECORD_APP_PDEBUGDATA_V)<<(DPORT_RECORD_APP_PDEBUGDATA_S))
3529 #define DPORT_RECORD_APP_PDEBUGDATA_V  0xFFFFFFFF
3530 #define DPORT_RECORD_APP_PDEBUGDATA_S  0
3531 
3532 #define DPORT_APP_CPU_RECORD_PDEBUGPC_REG          (DR_REG_DPORT_BASE + 0x480)
3533 /* DPORT_RECORD_APP_PDEBUGPC : RO ;bitpos:[31:0] ;default: 32'b0 ; */
3534 /*description: */
3535 #define DPORT_RECORD_APP_PDEBUGPC  0xFFFFFFFF
3536 #define DPORT_RECORD_APP_PDEBUGPC_M  ((DPORT_RECORD_APP_PDEBUGPC_V)<<(DPORT_RECORD_APP_PDEBUGPC_S))
3537 #define DPORT_RECORD_APP_PDEBUGPC_V  0xFFFFFFFF
3538 #define DPORT_RECORD_APP_PDEBUGPC_S  0
3539 
3540 #define DPORT_APP_CPU_RECORD_PDEBUGLS0STAT_REG          (DR_REG_DPORT_BASE + 0x484)
3541 /* DPORT_RECORD_APP_PDEBUGLS0STAT : RO ;bitpos:[31:0] ;default: 32'b0 ; */
3542 /*description: */
3543 #define DPORT_RECORD_APP_PDEBUGLS0STAT  0xFFFFFFFF
3544 #define DPORT_RECORD_APP_PDEBUGLS0STAT_M  ((DPORT_RECORD_APP_PDEBUGLS0STAT_V)<<(DPORT_RECORD_APP_PDEBUGLS0STAT_S))
3545 #define DPORT_RECORD_APP_PDEBUGLS0STAT_V  0xFFFFFFFF
3546 #define DPORT_RECORD_APP_PDEBUGLS0STAT_S  0
3547 
3548 #define DPORT_APP_CPU_RECORD_PDEBUGLS0ADDR_REG          (DR_REG_DPORT_BASE + 0x488)
3549 /* DPORT_RECORD_APP_PDEBUGLS0ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
3550 /*description: */
3551 #define DPORT_RECORD_APP_PDEBUGLS0ADDR  0xFFFFFFFF
3552 #define DPORT_RECORD_APP_PDEBUGLS0ADDR_M  ((DPORT_RECORD_APP_PDEBUGLS0ADDR_V)<<(DPORT_RECORD_APP_PDEBUGLS0ADDR_S))
3553 #define DPORT_RECORD_APP_PDEBUGLS0ADDR_V  0xFFFFFFFF
3554 #define DPORT_RECORD_APP_PDEBUGLS0ADDR_S  0
3555 
3556 #define DPORT_APP_CPU_RECORD_PDEBUGLS0DATA_REG          (DR_REG_DPORT_BASE + 0x48C)
3557 /* DPORT_RECORD_APP_PDEBUGLS0DATA : RO ;bitpos:[31:0] ;default: 32'b0 ; */
3558 /*description: */
3559 #define DPORT_RECORD_APP_PDEBUGLS0DATA  0xFFFFFFFF
3560 #define DPORT_RECORD_APP_PDEBUGLS0DATA_M  ((DPORT_RECORD_APP_PDEBUGLS0DATA_V)<<(DPORT_RECORD_APP_PDEBUGLS0DATA_S))
3561 #define DPORT_RECORD_APP_PDEBUGLS0DATA_V  0xFFFFFFFF
3562 #define DPORT_RECORD_APP_PDEBUGLS0DATA_S  0
3563 
3564 #define DPORT_RSA_PD_CTRL_REG          (DR_REG_DPORT_BASE + 0x490)
3565 /* DPORT_RSA_PD : R/W ;bitpos:[0] ;default: 1'b0 ; */
3566 /*description: */
3567 #define DPORT_RSA_PD  (BIT(0))
3568 #define DPORT_RSA_PD_M  (BIT(0))
3569 #define DPORT_RSA_PD_V  0x1
3570 #define DPORT_RSA_PD_S  0
3571 
3572 #define DPORT_ROM_MPU_TABLE0_REG          (DR_REG_DPORT_BASE + 0x494)
3573 /* DPORT_ROM_MPU_TABLE0 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */
3574 /*description: */
3575 #define DPORT_ROM_MPU_TABLE0  0x00000003
3576 #define DPORT_ROM_MPU_TABLE0_M  ((DPORT_ROM_MPU_TABLE0_V)<<(DPORT_ROM_MPU_TABLE0_S))
3577 #define DPORT_ROM_MPU_TABLE0_V  0x3
3578 #define DPORT_ROM_MPU_TABLE0_S  0
3579 
3580 #define DPORT_ROM_MPU_TABLE1_REG          (DR_REG_DPORT_BASE + 0x498)
3581 /* DPORT_ROM_MPU_TABLE1 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */
3582 /*description: */
3583 #define DPORT_ROM_MPU_TABLE1  0x00000003
3584 #define DPORT_ROM_MPU_TABLE1_M  ((DPORT_ROM_MPU_TABLE1_V)<<(DPORT_ROM_MPU_TABLE1_S))
3585 #define DPORT_ROM_MPU_TABLE1_V  0x3
3586 #define DPORT_ROM_MPU_TABLE1_S  0
3587 
3588 #define DPORT_ROM_MPU_TABLE2_REG          (DR_REG_DPORT_BASE + 0x49C)
3589 /* DPORT_ROM_MPU_TABLE2 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */
3590 /*description: */
3591 #define DPORT_ROM_MPU_TABLE2  0x00000003
3592 #define DPORT_ROM_MPU_TABLE2_M  ((DPORT_ROM_MPU_TABLE2_V)<<(DPORT_ROM_MPU_TABLE2_S))
3593 #define DPORT_ROM_MPU_TABLE2_V  0x3
3594 #define DPORT_ROM_MPU_TABLE2_S  0
3595 
3596 #define DPORT_ROM_MPU_TABLE3_REG          (DR_REG_DPORT_BASE + 0x4A0)
3597 /* DPORT_ROM_MPU_TABLE3 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */
3598 /*description: */
3599 #define DPORT_ROM_MPU_TABLE3  0x00000003
3600 #define DPORT_ROM_MPU_TABLE3_M  ((DPORT_ROM_MPU_TABLE3_V)<<(DPORT_ROM_MPU_TABLE3_S))
3601 #define DPORT_ROM_MPU_TABLE3_V  0x3
3602 #define DPORT_ROM_MPU_TABLE3_S  0
3603 
3604 #define DPORT_SHROM_MPU_TABLE0_REG          (DR_REG_DPORT_BASE + 0x4A4)
3605 /* DPORT_SHROM_MPU_TABLE0 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */
3606 /*description: */
3607 #define DPORT_SHROM_MPU_TABLE0  0x00000003
3608 #define DPORT_SHROM_MPU_TABLE0_M  ((DPORT_SHROM_MPU_TABLE0_V)<<(DPORT_SHROM_MPU_TABLE0_S))
3609 #define DPORT_SHROM_MPU_TABLE0_V  0x3
3610 #define DPORT_SHROM_MPU_TABLE0_S  0
3611 
3612 #define DPORT_SHROM_MPU_TABLE1_REG          (DR_REG_DPORT_BASE + 0x4A8)
3613 /* DPORT_SHROM_MPU_TABLE1 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */
3614 /*description: */
3615 #define DPORT_SHROM_MPU_TABLE1  0x00000003
3616 #define DPORT_SHROM_MPU_TABLE1_M  ((DPORT_SHROM_MPU_TABLE1_V)<<(DPORT_SHROM_MPU_TABLE1_S))
3617 #define DPORT_SHROM_MPU_TABLE1_V  0x3
3618 #define DPORT_SHROM_MPU_TABLE1_S  0
3619 
3620 #define DPORT_SHROM_MPU_TABLE2_REG          (DR_REG_DPORT_BASE + 0x4AC)
3621 /* DPORT_SHROM_MPU_TABLE2 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */
3622 /*description: */
3623 #define DPORT_SHROM_MPU_TABLE2  0x00000003
3624 #define DPORT_SHROM_MPU_TABLE2_M  ((DPORT_SHROM_MPU_TABLE2_V)<<(DPORT_SHROM_MPU_TABLE2_S))
3625 #define DPORT_SHROM_MPU_TABLE2_V  0x3
3626 #define DPORT_SHROM_MPU_TABLE2_S  0
3627 
3628 #define DPORT_SHROM_MPU_TABLE3_REG          (DR_REG_DPORT_BASE + 0x4B0)
3629 /* DPORT_SHROM_MPU_TABLE3 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */
3630 /*description: */
3631 #define DPORT_SHROM_MPU_TABLE3  0x00000003
3632 #define DPORT_SHROM_MPU_TABLE3_M  ((DPORT_SHROM_MPU_TABLE3_V)<<(DPORT_SHROM_MPU_TABLE3_S))
3633 #define DPORT_SHROM_MPU_TABLE3_V  0x3
3634 #define DPORT_SHROM_MPU_TABLE3_S  0
3635 
3636 #define DPORT_SHROM_MPU_TABLE4_REG          (DR_REG_DPORT_BASE + 0x4B4)
3637 /* DPORT_SHROM_MPU_TABLE4 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */
3638 /*description: */
3639 #define DPORT_SHROM_MPU_TABLE4  0x00000003
3640 #define DPORT_SHROM_MPU_TABLE4_M  ((DPORT_SHROM_MPU_TABLE4_V)<<(DPORT_SHROM_MPU_TABLE4_S))
3641 #define DPORT_SHROM_MPU_TABLE4_V  0x3
3642 #define DPORT_SHROM_MPU_TABLE4_S  0
3643 
3644 #define DPORT_SHROM_MPU_TABLE5_REG          (DR_REG_DPORT_BASE + 0x4B8)
3645 /* DPORT_SHROM_MPU_TABLE5 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */
3646 /*description: */
3647 #define DPORT_SHROM_MPU_TABLE5  0x00000003
3648 #define DPORT_SHROM_MPU_TABLE5_M  ((DPORT_SHROM_MPU_TABLE5_V)<<(DPORT_SHROM_MPU_TABLE5_S))
3649 #define DPORT_SHROM_MPU_TABLE5_V  0x3
3650 #define DPORT_SHROM_MPU_TABLE5_S  0
3651 
3652 #define DPORT_SHROM_MPU_TABLE6_REG          (DR_REG_DPORT_BASE + 0x4BC)
3653 /* DPORT_SHROM_MPU_TABLE6 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */
3654 /*description: */
3655 #define DPORT_SHROM_MPU_TABLE6  0x00000003
3656 #define DPORT_SHROM_MPU_TABLE6_M  ((DPORT_SHROM_MPU_TABLE6_V)<<(DPORT_SHROM_MPU_TABLE6_S))
3657 #define DPORT_SHROM_MPU_TABLE6_V  0x3
3658 #define DPORT_SHROM_MPU_TABLE6_S  0
3659 
3660 #define DPORT_SHROM_MPU_TABLE7_REG          (DR_REG_DPORT_BASE + 0x4C0)
3661 /* DPORT_SHROM_MPU_TABLE7 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */
3662 /*description: */
3663 #define DPORT_SHROM_MPU_TABLE7  0x00000003
3664 #define DPORT_SHROM_MPU_TABLE7_M  ((DPORT_SHROM_MPU_TABLE7_V)<<(DPORT_SHROM_MPU_TABLE7_S))
3665 #define DPORT_SHROM_MPU_TABLE7_V  0x3
3666 #define DPORT_SHROM_MPU_TABLE7_S  0
3667 
3668 #define DPORT_SHROM_MPU_TABLE8_REG          (DR_REG_DPORT_BASE + 0x4C4)
3669 /* DPORT_SHROM_MPU_TABLE8 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */
3670 /*description: */
3671 #define DPORT_SHROM_MPU_TABLE8  0x00000003
3672 #define DPORT_SHROM_MPU_TABLE8_M  ((DPORT_SHROM_MPU_TABLE8_V)<<(DPORT_SHROM_MPU_TABLE8_S))
3673 #define DPORT_SHROM_MPU_TABLE8_V  0x3
3674 #define DPORT_SHROM_MPU_TABLE8_S  0
3675 
3676 #define DPORT_SHROM_MPU_TABLE9_REG          (DR_REG_DPORT_BASE + 0x4C8)
3677 /* DPORT_SHROM_MPU_TABLE9 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */
3678 /*description: */
3679 #define DPORT_SHROM_MPU_TABLE9  0x00000003
3680 #define DPORT_SHROM_MPU_TABLE9_M  ((DPORT_SHROM_MPU_TABLE9_V)<<(DPORT_SHROM_MPU_TABLE9_S))
3681 #define DPORT_SHROM_MPU_TABLE9_V  0x3
3682 #define DPORT_SHROM_MPU_TABLE9_S  0
3683 
3684 #define DPORT_SHROM_MPU_TABLE10_REG          (DR_REG_DPORT_BASE + 0x4CC)
3685 /* DPORT_SHROM_MPU_TABLE10 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */
3686 /*description: */
3687 #define DPORT_SHROM_MPU_TABLE10  0x00000003
3688 #define DPORT_SHROM_MPU_TABLE10_M  ((DPORT_SHROM_MPU_TABLE10_V)<<(DPORT_SHROM_MPU_TABLE10_S))
3689 #define DPORT_SHROM_MPU_TABLE10_V  0x3
3690 #define DPORT_SHROM_MPU_TABLE10_S  0
3691 
3692 #define DPORT_SHROM_MPU_TABLE11_REG          (DR_REG_DPORT_BASE + 0x4D0)
3693 /* DPORT_SHROM_MPU_TABLE11 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */
3694 /*description: */
3695 #define DPORT_SHROM_MPU_TABLE11  0x00000003
3696 #define DPORT_SHROM_MPU_TABLE11_M  ((DPORT_SHROM_MPU_TABLE11_V)<<(DPORT_SHROM_MPU_TABLE11_S))
3697 #define DPORT_SHROM_MPU_TABLE11_V  0x3
3698 #define DPORT_SHROM_MPU_TABLE11_S  0
3699 
3700 #define DPORT_SHROM_MPU_TABLE12_REG          (DR_REG_DPORT_BASE + 0x4D4)
3701 /* DPORT_SHROM_MPU_TABLE12 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */
3702 /*description: */
3703 #define DPORT_SHROM_MPU_TABLE12  0x00000003
3704 #define DPORT_SHROM_MPU_TABLE12_M  ((DPORT_SHROM_MPU_TABLE12_V)<<(DPORT_SHROM_MPU_TABLE12_S))
3705 #define DPORT_SHROM_MPU_TABLE12_V  0x3
3706 #define DPORT_SHROM_MPU_TABLE12_S  0
3707 
3708 #define DPORT_SHROM_MPU_TABLE13_REG          (DR_REG_DPORT_BASE + 0x4D8)
3709 /* DPORT_SHROM_MPU_TABLE13 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */
3710 /*description: */
3711 #define DPORT_SHROM_MPU_TABLE13  0x00000003
3712 #define DPORT_SHROM_MPU_TABLE13_M  ((DPORT_SHROM_MPU_TABLE13_V)<<(DPORT_SHROM_MPU_TABLE13_S))
3713 #define DPORT_SHROM_MPU_TABLE13_V  0x3
3714 #define DPORT_SHROM_MPU_TABLE13_S  0
3715 
3716 #define DPORT_SHROM_MPU_TABLE14_REG          (DR_REG_DPORT_BASE + 0x4DC)
3717 /* DPORT_SHROM_MPU_TABLE14 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */
3718 /*description: */
3719 #define DPORT_SHROM_MPU_TABLE14  0x00000003
3720 #define DPORT_SHROM_MPU_TABLE14_M  ((DPORT_SHROM_MPU_TABLE14_V)<<(DPORT_SHROM_MPU_TABLE14_S))
3721 #define DPORT_SHROM_MPU_TABLE14_V  0x3
3722 #define DPORT_SHROM_MPU_TABLE14_S  0
3723 
3724 #define DPORT_SHROM_MPU_TABLE15_REG          (DR_REG_DPORT_BASE + 0x4E0)
3725 /* DPORT_SHROM_MPU_TABLE15 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */
3726 /*description: */
3727 #define DPORT_SHROM_MPU_TABLE15  0x00000003
3728 #define DPORT_SHROM_MPU_TABLE15_M  ((DPORT_SHROM_MPU_TABLE15_V)<<(DPORT_SHROM_MPU_TABLE15_S))
3729 #define DPORT_SHROM_MPU_TABLE15_V  0x3
3730 #define DPORT_SHROM_MPU_TABLE15_S  0
3731 
3732 #define DPORT_SHROM_MPU_TABLE16_REG          (DR_REG_DPORT_BASE + 0x4E4)
3733 /* DPORT_SHROM_MPU_TABLE16 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */
3734 /*description: */
3735 #define DPORT_SHROM_MPU_TABLE16  0x00000003
3736 #define DPORT_SHROM_MPU_TABLE16_M  ((DPORT_SHROM_MPU_TABLE16_V)<<(DPORT_SHROM_MPU_TABLE16_S))
3737 #define DPORT_SHROM_MPU_TABLE16_V  0x3
3738 #define DPORT_SHROM_MPU_TABLE16_S  0
3739 
3740 #define DPORT_SHROM_MPU_TABLE17_REG          (DR_REG_DPORT_BASE + 0x4E8)
3741 /* DPORT_SHROM_MPU_TABLE17 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */
3742 /*description: */
3743 #define DPORT_SHROM_MPU_TABLE17  0x00000003
3744 #define DPORT_SHROM_MPU_TABLE17_M  ((DPORT_SHROM_MPU_TABLE17_V)<<(DPORT_SHROM_MPU_TABLE17_S))
3745 #define DPORT_SHROM_MPU_TABLE17_V  0x3
3746 #define DPORT_SHROM_MPU_TABLE17_S  0
3747 
3748 #define DPORT_SHROM_MPU_TABLE18_REG          (DR_REG_DPORT_BASE + 0x4EC)
3749 /* DPORT_SHROM_MPU_TABLE18 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */
3750 /*description: */
3751 #define DPORT_SHROM_MPU_TABLE18  0x00000003
3752 #define DPORT_SHROM_MPU_TABLE18_M  ((DPORT_SHROM_MPU_TABLE18_V)<<(DPORT_SHROM_MPU_TABLE18_S))
3753 #define DPORT_SHROM_MPU_TABLE18_V  0x3
3754 #define DPORT_SHROM_MPU_TABLE18_S  0
3755 
3756 #define DPORT_SHROM_MPU_TABLE19_REG          (DR_REG_DPORT_BASE + 0x4F0)
3757 /* DPORT_SHROM_MPU_TABLE19 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */
3758 /*description: */
3759 #define DPORT_SHROM_MPU_TABLE19  0x00000003
3760 #define DPORT_SHROM_MPU_TABLE19_M  ((DPORT_SHROM_MPU_TABLE19_V)<<(DPORT_SHROM_MPU_TABLE19_S))
3761 #define DPORT_SHROM_MPU_TABLE19_V  0x3
3762 #define DPORT_SHROM_MPU_TABLE19_S  0
3763 
3764 #define DPORT_SHROM_MPU_TABLE20_REG          (DR_REG_DPORT_BASE + 0x4F4)
3765 /* DPORT_SHROM_MPU_TABLE20 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */
3766 /*description: */
3767 #define DPORT_SHROM_MPU_TABLE20  0x00000003
3768 #define DPORT_SHROM_MPU_TABLE20_M  ((DPORT_SHROM_MPU_TABLE20_V)<<(DPORT_SHROM_MPU_TABLE20_S))
3769 #define DPORT_SHROM_MPU_TABLE20_V  0x3
3770 #define DPORT_SHROM_MPU_TABLE20_S  0
3771 
3772 #define DPORT_SHROM_MPU_TABLE21_REG          (DR_REG_DPORT_BASE + 0x4F8)
3773 /* DPORT_SHROM_MPU_TABLE21 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */
3774 /*description: */
3775 #define DPORT_SHROM_MPU_TABLE21  0x00000003
3776 #define DPORT_SHROM_MPU_TABLE21_M  ((DPORT_SHROM_MPU_TABLE21_V)<<(DPORT_SHROM_MPU_TABLE21_S))
3777 #define DPORT_SHROM_MPU_TABLE21_V  0x3
3778 #define DPORT_SHROM_MPU_TABLE21_S  0
3779 
3780 #define DPORT_SHROM_MPU_TABLE22_REG          (DR_REG_DPORT_BASE + 0x4FC)
3781 /* DPORT_SHROM_MPU_TABLE22 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */
3782 /*description: */
3783 #define DPORT_SHROM_MPU_TABLE22  0x00000003
3784 #define DPORT_SHROM_MPU_TABLE22_M  ((DPORT_SHROM_MPU_TABLE22_V)<<(DPORT_SHROM_MPU_TABLE22_S))
3785 #define DPORT_SHROM_MPU_TABLE22_V  0x3
3786 #define DPORT_SHROM_MPU_TABLE22_S  0
3787 
3788 #define DPORT_SHROM_MPU_TABLE23_REG          (DR_REG_DPORT_BASE + 0x500)
3789 /* DPORT_SHROM_MPU_TABLE23 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */
3790 /*description: */
3791 #define DPORT_SHROM_MPU_TABLE23  0x00000003
3792 #define DPORT_SHROM_MPU_TABLE23_M  ((DPORT_SHROM_MPU_TABLE23_V)<<(DPORT_SHROM_MPU_TABLE23_S))
3793 #define DPORT_SHROM_MPU_TABLE23_V  0x3
3794 #define DPORT_SHROM_MPU_TABLE23_S  0
3795 
3796 #define DPORT_IMMU_TABLE0_REG          (DR_REG_DPORT_BASE + 0x504)
3797 /* DPORT_IMMU_TABLE0 : R/W ;bitpos:[6:0] ;default: 7'd0 ; */
3798 /*description: */
3799 #define DPORT_IMMU_TABLE0  0x0000007F
3800 #define DPORT_IMMU_TABLE0_M  ((DPORT_IMMU_TABLE0_V)<<(DPORT_IMMU_TABLE0_S))
3801 #define DPORT_IMMU_TABLE0_V  0x7F
3802 #define DPORT_IMMU_TABLE0_S  0
3803 
3804 #define DPORT_IMMU_TABLE1_REG          (DR_REG_DPORT_BASE + 0x508)
3805 /* DPORT_IMMU_TABLE1 : R/W ;bitpos:[6:0] ;default: 7'd1 ; */
3806 /*description: */
3807 #define DPORT_IMMU_TABLE1  0x0000007F
3808 #define DPORT_IMMU_TABLE1_M  ((DPORT_IMMU_TABLE1_V)<<(DPORT_IMMU_TABLE1_S))
3809 #define DPORT_IMMU_TABLE1_V  0x7F
3810 #define DPORT_IMMU_TABLE1_S  0
3811 
3812 #define DPORT_IMMU_TABLE2_REG          (DR_REG_DPORT_BASE + 0x50C)
3813 /* DPORT_IMMU_TABLE2 : R/W ;bitpos:[6:0] ;default: 7'd2 ; */
3814 /*description: */
3815 #define DPORT_IMMU_TABLE2  0x0000007F
3816 #define DPORT_IMMU_TABLE2_M  ((DPORT_IMMU_TABLE2_V)<<(DPORT_IMMU_TABLE2_S))
3817 #define DPORT_IMMU_TABLE2_V  0x7F
3818 #define DPORT_IMMU_TABLE2_S  0
3819 
3820 #define DPORT_IMMU_TABLE3_REG          (DR_REG_DPORT_BASE + 0x510)
3821 /* DPORT_IMMU_TABLE3 : R/W ;bitpos:[6:0] ;default: 7'd3 ; */
3822 /*description: */
3823 #define DPORT_IMMU_TABLE3  0x0000007F
3824 #define DPORT_IMMU_TABLE3_M  ((DPORT_IMMU_TABLE3_V)<<(DPORT_IMMU_TABLE3_S))
3825 #define DPORT_IMMU_TABLE3_V  0x7F
3826 #define DPORT_IMMU_TABLE3_S  0
3827 
3828 #define DPORT_IMMU_TABLE4_REG          (DR_REG_DPORT_BASE + 0x514)
3829 /* DPORT_IMMU_TABLE4 : R/W ;bitpos:[6:0] ;default: 7'd4 ; */
3830 /*description: */
3831 #define DPORT_IMMU_TABLE4  0x0000007F
3832 #define DPORT_IMMU_TABLE4_M  ((DPORT_IMMU_TABLE4_V)<<(DPORT_IMMU_TABLE4_S))
3833 #define DPORT_IMMU_TABLE4_V  0x7F
3834 #define DPORT_IMMU_TABLE4_S  0
3835 
3836 #define DPORT_IMMU_TABLE5_REG          (DR_REG_DPORT_BASE + 0x518)
3837 /* DPORT_IMMU_TABLE5 : R/W ;bitpos:[6:0] ;default: 7'd5 ; */
3838 /*description: */
3839 #define DPORT_IMMU_TABLE5  0x0000007F
3840 #define DPORT_IMMU_TABLE5_M  ((DPORT_IMMU_TABLE5_V)<<(DPORT_IMMU_TABLE5_S))
3841 #define DPORT_IMMU_TABLE5_V  0x7F
3842 #define DPORT_IMMU_TABLE5_S  0
3843 
3844 #define DPORT_IMMU_TABLE6_REG          (DR_REG_DPORT_BASE + 0x51C)
3845 /* DPORT_IMMU_TABLE6 : R/W ;bitpos:[6:0] ;default: 7'd6 ; */
3846 /*description: */
3847 #define DPORT_IMMU_TABLE6  0x0000007F
3848 #define DPORT_IMMU_TABLE6_M  ((DPORT_IMMU_TABLE6_V)<<(DPORT_IMMU_TABLE6_S))
3849 #define DPORT_IMMU_TABLE6_V  0x7F
3850 #define DPORT_IMMU_TABLE6_S  0
3851 
3852 #define DPORT_IMMU_TABLE7_REG          (DR_REG_DPORT_BASE + 0x520)
3853 /* DPORT_IMMU_TABLE7 : R/W ;bitpos:[6:0] ;default: 7'd7 ; */
3854 /*description: */
3855 #define DPORT_IMMU_TABLE7  0x0000007F
3856 #define DPORT_IMMU_TABLE7_M  ((DPORT_IMMU_TABLE7_V)<<(DPORT_IMMU_TABLE7_S))
3857 #define DPORT_IMMU_TABLE7_V  0x7F
3858 #define DPORT_IMMU_TABLE7_S  0
3859 
3860 #define DPORT_IMMU_TABLE8_REG          (DR_REG_DPORT_BASE + 0x524)
3861 /* DPORT_IMMU_TABLE8 : R/W ;bitpos:[6:0] ;default: 7'd8 ; */
3862 /*description: */
3863 #define DPORT_IMMU_TABLE8  0x0000007F
3864 #define DPORT_IMMU_TABLE8_M  ((DPORT_IMMU_TABLE8_V)<<(DPORT_IMMU_TABLE8_S))
3865 #define DPORT_IMMU_TABLE8_V  0x7F
3866 #define DPORT_IMMU_TABLE8_S  0
3867 
3868 #define DPORT_IMMU_TABLE9_REG          (DR_REG_DPORT_BASE + 0x528)
3869 /* DPORT_IMMU_TABLE9 : R/W ;bitpos:[6:0] ;default: 7'd9 ; */
3870 /*description: */
3871 #define DPORT_IMMU_TABLE9  0x0000007F
3872 #define DPORT_IMMU_TABLE9_M  ((DPORT_IMMU_TABLE9_V)<<(DPORT_IMMU_TABLE9_S))
3873 #define DPORT_IMMU_TABLE9_V  0x7F
3874 #define DPORT_IMMU_TABLE9_S  0
3875 
3876 #define DPORT_IMMU_TABLE10_REG          (DR_REG_DPORT_BASE + 0x52C)
3877 /* DPORT_IMMU_TABLE10 : R/W ;bitpos:[6:0] ;default: 7'd10 ; */
3878 /*description: */
3879 #define DPORT_IMMU_TABLE10  0x0000007F
3880 #define DPORT_IMMU_TABLE10_M  ((DPORT_IMMU_TABLE10_V)<<(DPORT_IMMU_TABLE10_S))
3881 #define DPORT_IMMU_TABLE10_V  0x7F
3882 #define DPORT_IMMU_TABLE10_S  0
3883 
3884 #define DPORT_IMMU_TABLE11_REG          (DR_REG_DPORT_BASE + 0x530)
3885 /* DPORT_IMMU_TABLE11 : R/W ;bitpos:[6:0] ;default: 7'd11 ; */
3886 /*description: */
3887 #define DPORT_IMMU_TABLE11  0x0000007F
3888 #define DPORT_IMMU_TABLE11_M  ((DPORT_IMMU_TABLE11_V)<<(DPORT_IMMU_TABLE11_S))
3889 #define DPORT_IMMU_TABLE11_V  0x7F
3890 #define DPORT_IMMU_TABLE11_S  0
3891 
3892 #define DPORT_IMMU_TABLE12_REG          (DR_REG_DPORT_BASE + 0x534)
3893 /* DPORT_IMMU_TABLE12 : R/W ;bitpos:[6:0] ;default: 7'd12 ; */
3894 /*description: */
3895 #define DPORT_IMMU_TABLE12  0x0000007F
3896 #define DPORT_IMMU_TABLE12_M  ((DPORT_IMMU_TABLE12_V)<<(DPORT_IMMU_TABLE12_S))
3897 #define DPORT_IMMU_TABLE12_V  0x7F
3898 #define DPORT_IMMU_TABLE12_S  0
3899 
3900 #define DPORT_IMMU_TABLE13_REG          (DR_REG_DPORT_BASE + 0x538)
3901 /* DPORT_IMMU_TABLE13 : R/W ;bitpos:[6:0] ;default: 7'd13 ; */
3902 /*description: */
3903 #define DPORT_IMMU_TABLE13  0x0000007F
3904 #define DPORT_IMMU_TABLE13_M  ((DPORT_IMMU_TABLE13_V)<<(DPORT_IMMU_TABLE13_S))
3905 #define DPORT_IMMU_TABLE13_V  0x7F
3906 #define DPORT_IMMU_TABLE13_S  0
3907 
3908 #define DPORT_IMMU_TABLE14_REG          (DR_REG_DPORT_BASE + 0x53C)
3909 /* DPORT_IMMU_TABLE14 : R/W ;bitpos:[6:0] ;default: 7'd14 ; */
3910 /*description: */
3911 #define DPORT_IMMU_TABLE14  0x0000007F
3912 #define DPORT_IMMU_TABLE14_M  ((DPORT_IMMU_TABLE14_V)<<(DPORT_IMMU_TABLE14_S))
3913 #define DPORT_IMMU_TABLE14_V  0x7F
3914 #define DPORT_IMMU_TABLE14_S  0
3915 
3916 #define DPORT_IMMU_TABLE15_REG          (DR_REG_DPORT_BASE + 0x540)
3917 /* DPORT_IMMU_TABLE15 : R/W ;bitpos:[6:0] ;default: 7'd15 ; */
3918 /*description: */
3919 #define DPORT_IMMU_TABLE15  0x0000007F
3920 #define DPORT_IMMU_TABLE15_M  ((DPORT_IMMU_TABLE15_V)<<(DPORT_IMMU_TABLE15_S))
3921 #define DPORT_IMMU_TABLE15_V  0x7F
3922 #define DPORT_IMMU_TABLE15_S  0
3923 
3924 #define DPORT_DMMU_TABLE0_REG          (DR_REG_DPORT_BASE + 0x544)
3925 /* DPORT_DMMU_TABLE0 : R/W ;bitpos:[6:0] ;default: 7'd0 ; */
3926 /*description: */
3927 #define DPORT_DMMU_TABLE0  0x0000007F
3928 #define DPORT_DMMU_TABLE0_M  ((DPORT_DMMU_TABLE0_V)<<(DPORT_DMMU_TABLE0_S))
3929 #define DPORT_DMMU_TABLE0_V  0x7F
3930 #define DPORT_DMMU_TABLE0_S  0
3931 
3932 #define DPORT_DMMU_TABLE1_REG          (DR_REG_DPORT_BASE + 0x548)
3933 /* DPORT_DMMU_TABLE1 : R/W ;bitpos:[6:0] ;default: 7'd1 ; */
3934 /*description: */
3935 #define DPORT_DMMU_TABLE1  0x0000007F
3936 #define DPORT_DMMU_TABLE1_M  ((DPORT_DMMU_TABLE1_V)<<(DPORT_DMMU_TABLE1_S))
3937 #define DPORT_DMMU_TABLE1_V  0x7F
3938 #define DPORT_DMMU_TABLE1_S  0
3939 
3940 #define DPORT_DMMU_TABLE2_REG          (DR_REG_DPORT_BASE + 0x54C)
3941 /* DPORT_DMMU_TABLE2 : R/W ;bitpos:[6:0] ;default: 7'd2 ; */
3942 /*description: */
3943 #define DPORT_DMMU_TABLE2  0x0000007F
3944 #define DPORT_DMMU_TABLE2_M  ((DPORT_DMMU_TABLE2_V)<<(DPORT_DMMU_TABLE2_S))
3945 #define DPORT_DMMU_TABLE2_V  0x7F
3946 #define DPORT_DMMU_TABLE2_S  0
3947 
3948 #define DPORT_DMMU_TABLE3_REG          (DR_REG_DPORT_BASE + 0x550)
3949 /* DPORT_DMMU_TABLE3 : R/W ;bitpos:[6:0] ;default: 7'd3 ; */
3950 /*description: */
3951 #define DPORT_DMMU_TABLE3  0x0000007F
3952 #define DPORT_DMMU_TABLE3_M  ((DPORT_DMMU_TABLE3_V)<<(DPORT_DMMU_TABLE3_S))
3953 #define DPORT_DMMU_TABLE3_V  0x7F
3954 #define DPORT_DMMU_TABLE3_S  0
3955 
3956 #define DPORT_DMMU_TABLE4_REG          (DR_REG_DPORT_BASE + 0x554)
3957 /* DPORT_DMMU_TABLE4 : R/W ;bitpos:[6:0] ;default: 7'd4 ; */
3958 /*description: */
3959 #define DPORT_DMMU_TABLE4  0x0000007F
3960 #define DPORT_DMMU_TABLE4_M  ((DPORT_DMMU_TABLE4_V)<<(DPORT_DMMU_TABLE4_S))
3961 #define DPORT_DMMU_TABLE4_V  0x7F
3962 #define DPORT_DMMU_TABLE4_S  0
3963 
3964 #define DPORT_DMMU_TABLE5_REG          (DR_REG_DPORT_BASE + 0x558)
3965 /* DPORT_DMMU_TABLE5 : R/W ;bitpos:[6:0] ;default: 7'd5 ; */
3966 /*description: */
3967 #define DPORT_DMMU_TABLE5  0x0000007F
3968 #define DPORT_DMMU_TABLE5_M  ((DPORT_DMMU_TABLE5_V)<<(DPORT_DMMU_TABLE5_S))
3969 #define DPORT_DMMU_TABLE5_V  0x7F
3970 #define DPORT_DMMU_TABLE5_S  0
3971 
3972 #define DPORT_DMMU_TABLE6_REG          (DR_REG_DPORT_BASE + 0x55C)
3973 /* DPORT_DMMU_TABLE6 : R/W ;bitpos:[6:0] ;default: 7'd6 ; */
3974 /*description: */
3975 #define DPORT_DMMU_TABLE6  0x0000007F
3976 #define DPORT_DMMU_TABLE6_M  ((DPORT_DMMU_TABLE6_V)<<(DPORT_DMMU_TABLE6_S))
3977 #define DPORT_DMMU_TABLE6_V  0x7F
3978 #define DPORT_DMMU_TABLE6_S  0
3979 
3980 #define DPORT_DMMU_TABLE7_REG          (DR_REG_DPORT_BASE + 0x560)
3981 /* DPORT_DMMU_TABLE7 : R/W ;bitpos:[6:0] ;default: 7'd7 ; */
3982 /*description: */
3983 #define DPORT_DMMU_TABLE7  0x0000007F
3984 #define DPORT_DMMU_TABLE7_M  ((DPORT_DMMU_TABLE7_V)<<(DPORT_DMMU_TABLE7_S))
3985 #define DPORT_DMMU_TABLE7_V  0x7F
3986 #define DPORT_DMMU_TABLE7_S  0
3987 
3988 #define DPORT_DMMU_TABLE8_REG          (DR_REG_DPORT_BASE + 0x564)
3989 /* DPORT_DMMU_TABLE8 : R/W ;bitpos:[6:0] ;default: 7'd8 ; */
3990 /*description: */
3991 #define DPORT_DMMU_TABLE8  0x0000007F
3992 #define DPORT_DMMU_TABLE8_M  ((DPORT_DMMU_TABLE8_V)<<(DPORT_DMMU_TABLE8_S))
3993 #define DPORT_DMMU_TABLE8_V  0x7F
3994 #define DPORT_DMMU_TABLE8_S  0
3995 
3996 #define DPORT_DMMU_TABLE9_REG          (DR_REG_DPORT_BASE + 0x568)
3997 /* DPORT_DMMU_TABLE9 : R/W ;bitpos:[6:0] ;default: 7'd9 ; */
3998 /*description: */
3999 #define DPORT_DMMU_TABLE9  0x0000007F
4000 #define DPORT_DMMU_TABLE9_M  ((DPORT_DMMU_TABLE9_V)<<(DPORT_DMMU_TABLE9_S))
4001 #define DPORT_DMMU_TABLE9_V  0x7F
4002 #define DPORT_DMMU_TABLE9_S  0
4003 
4004 #define DPORT_DMMU_TABLE10_REG          (DR_REG_DPORT_BASE + 0x56C)
4005 /* DPORT_DMMU_TABLE10 : R/W ;bitpos:[6:0] ;default: 7'd10 ; */
4006 /*description: */
4007 #define DPORT_DMMU_TABLE10  0x0000007F
4008 #define DPORT_DMMU_TABLE10_M  ((DPORT_DMMU_TABLE10_V)<<(DPORT_DMMU_TABLE10_S))
4009 #define DPORT_DMMU_TABLE10_V  0x7F
4010 #define DPORT_DMMU_TABLE10_S  0
4011 
4012 #define DPORT_DMMU_TABLE11_REG          (DR_REG_DPORT_BASE + 0x570)
4013 /* DPORT_DMMU_TABLE11 : R/W ;bitpos:[6:0] ;default: 7'd11 ; */
4014 /*description: */
4015 #define DPORT_DMMU_TABLE11  0x0000007F
4016 #define DPORT_DMMU_TABLE11_M  ((DPORT_DMMU_TABLE11_V)<<(DPORT_DMMU_TABLE11_S))
4017 #define DPORT_DMMU_TABLE11_V  0x7F
4018 #define DPORT_DMMU_TABLE11_S  0
4019 
4020 #define DPORT_DMMU_TABLE12_REG          (DR_REG_DPORT_BASE + 0x574)
4021 /* DPORT_DMMU_TABLE12 : R/W ;bitpos:[6:0] ;default: 7'd12 ; */
4022 /*description: */
4023 #define DPORT_DMMU_TABLE12  0x0000007F
4024 #define DPORT_DMMU_TABLE12_M  ((DPORT_DMMU_TABLE12_V)<<(DPORT_DMMU_TABLE12_S))
4025 #define DPORT_DMMU_TABLE12_V  0x7F
4026 #define DPORT_DMMU_TABLE12_S  0
4027 
4028 #define DPORT_DMMU_TABLE13_REG          (DR_REG_DPORT_BASE + 0x578)
4029 /* DPORT_DMMU_TABLE13 : R/W ;bitpos:[6:0] ;default: 7'd13 ; */
4030 /*description: */
4031 #define DPORT_DMMU_TABLE13  0x0000007F
4032 #define DPORT_DMMU_TABLE13_M  ((DPORT_DMMU_TABLE13_V)<<(DPORT_DMMU_TABLE13_S))
4033 #define DPORT_DMMU_TABLE13_V  0x7F
4034 #define DPORT_DMMU_TABLE13_S  0
4035 
4036 #define DPORT_DMMU_TABLE14_REG          (DR_REG_DPORT_BASE + 0x57C)
4037 /* DPORT_DMMU_TABLE14 : R/W ;bitpos:[6:0] ;default: 7'd14 ; */
4038 /*description: */
4039 #define DPORT_DMMU_TABLE14  0x0000007F
4040 #define DPORT_DMMU_TABLE14_M  ((DPORT_DMMU_TABLE14_V)<<(DPORT_DMMU_TABLE14_S))
4041 #define DPORT_DMMU_TABLE14_V  0x7F
4042 #define DPORT_DMMU_TABLE14_S  0
4043 
4044 #define DPORT_DMMU_TABLE15_REG          (DR_REG_DPORT_BASE + 0x580)
4045 /* DPORT_DMMU_TABLE15 : R/W ;bitpos:[6:0] ;default: 7'd15 ; */
4046 /*description: */
4047 #define DPORT_DMMU_TABLE15  0x0000007F
4048 #define DPORT_DMMU_TABLE15_M  ((DPORT_DMMU_TABLE15_V)<<(DPORT_DMMU_TABLE15_S))
4049 #define DPORT_DMMU_TABLE15_V  0x7F
4050 #define DPORT_DMMU_TABLE15_S  0
4051 
4052 #define DPORT_PRO_INTRUSION_CTRL_REG          (DR_REG_DPORT_BASE + 0x584)
4053 /* DPORT_PRO_INTRUSION_RECORD_RESET_N : R/W ;bitpos:[0] ;default: 1'b1 ; */
4054 /*description: */
4055 #define DPORT_PRO_INTRUSION_RECORD_RESET_N  (BIT(0))
4056 #define DPORT_PRO_INTRUSION_RECORD_RESET_N_M  (BIT(0))
4057 #define DPORT_PRO_INTRUSION_RECORD_RESET_N_V  0x1
4058 #define DPORT_PRO_INTRUSION_RECORD_RESET_N_S  0
4059 
4060 #define DPORT_PRO_INTRUSION_STATUS_REG          (DR_REG_DPORT_BASE + 0x588)
4061 /* DPORT_PRO_INTRUSION_RECORD : RO ;bitpos:[3:0] ;default: 4'b0 ; */
4062 /*description: */
4063 #define DPORT_PRO_INTRUSION_RECORD  0x0000000F
4064 #define DPORT_PRO_INTRUSION_RECORD_M  ((DPORT_PRO_INTRUSION_RECORD_V)<<(DPORT_PRO_INTRUSION_RECORD_S))
4065 #define DPORT_PRO_INTRUSION_RECORD_V  0xF
4066 #define DPORT_PRO_INTRUSION_RECORD_S  0
4067 
4068 #define DPORT_APP_INTRUSION_CTRL_REG          (DR_REG_DPORT_BASE + 0x58C)
4069 /* DPORT_APP_INTRUSION_RECORD_RESET_N : R/W ;bitpos:[0] ;default: 1'b1 ; */
4070 /*description: */
4071 #define DPORT_APP_INTRUSION_RECORD_RESET_N  (BIT(0))
4072 #define DPORT_APP_INTRUSION_RECORD_RESET_N_M  (BIT(0))
4073 #define DPORT_APP_INTRUSION_RECORD_RESET_N_V  0x1
4074 #define DPORT_APP_INTRUSION_RECORD_RESET_N_S  0
4075 
4076 #define DPORT_APP_INTRUSION_STATUS_REG          (DR_REG_DPORT_BASE + 0x590)
4077 /* DPORT_APP_INTRUSION_RECORD : RO ;bitpos:[3:0] ;default: 4'b0 ; */
4078 /*description: */
4079 #define DPORT_APP_INTRUSION_RECORD  0x0000000F
4080 #define DPORT_APP_INTRUSION_RECORD_M  ((DPORT_APP_INTRUSION_RECORD_V)<<(DPORT_APP_INTRUSION_RECORD_S))
4081 #define DPORT_APP_INTRUSION_RECORD_V  0xF
4082 #define DPORT_APP_INTRUSION_RECORD_S  0
4083 
4084 #define DPORT_FRONT_END_MEM_PD_REG          (DR_REG_DPORT_BASE + 0x594)
4085 /* DPORT_PBUS_MEM_FORCE_PD : R/W ;bitpos:[3] ;default: 1'b0 ; */
4086 /*description: */
4087 #define DPORT_PBUS_MEM_FORCE_PD  (BIT(3))
4088 #define DPORT_PBUS_MEM_FORCE_PD_M  (BIT(3))
4089 #define DPORT_PBUS_MEM_FORCE_PD_V  0x1
4090 #define DPORT_PBUS_MEM_FORCE_PD_S  3
4091 /* DPORT_PBUS_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */
4092 /*description: */
4093 #define DPORT_PBUS_MEM_FORCE_PU  (BIT(2))
4094 #define DPORT_PBUS_MEM_FORCE_PU_M  (BIT(2))
4095 #define DPORT_PBUS_MEM_FORCE_PU_V  0x1
4096 #define DPORT_PBUS_MEM_FORCE_PU_S  2
4097 /* DPORT_AGC_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */
4098 /*description: */
4099 #define DPORT_AGC_MEM_FORCE_PD  (BIT(1))
4100 #define DPORT_AGC_MEM_FORCE_PD_M  (BIT(1))
4101 #define DPORT_AGC_MEM_FORCE_PD_V  0x1
4102 #define DPORT_AGC_MEM_FORCE_PD_S  1
4103 /* DPORT_AGC_MEM_FORCE_PU : R/W ;bitpos:[0] ;default: 1'b1 ; */
4104 /*description: */
4105 #define DPORT_AGC_MEM_FORCE_PU  (BIT(0))
4106 #define DPORT_AGC_MEM_FORCE_PU_M  (BIT(0))
4107 #define DPORT_AGC_MEM_FORCE_PU_V  0x1
4108 #define DPORT_AGC_MEM_FORCE_PU_S  0
4109 
4110 #define DPORT_MMU_IA_INT_EN_REG          (DR_REG_DPORT_BASE + 0x598)
4111 /* DPORT_MMU_IA_INT_EN : R/W ;bitpos:[23:0] ;default: 24'b0 ; */
4112 /*description: */
4113 #define DPORT_MMU_IA_INT_EN  0x00FFFFFF
4114 #define DPORT_MMU_IA_INT_EN_M  ((DPORT_MMU_IA_INT_EN_V)<<(DPORT_MMU_IA_INT_EN_S))
4115 #define DPORT_MMU_IA_INT_EN_V  0xFFFFFF
4116 #define DPORT_MMU_IA_INT_EN_S  0
4117 
4118 #define DPORT_MPU_IA_INT_EN_REG          (DR_REG_DPORT_BASE + 0x59C)
4119 /* DPORT_MPU_IA_INT_EN : R/W ;bitpos:[16:0] ;default: 17'b0 ; */
4120 /*description: */
4121 #define DPORT_MPU_IA_INT_EN  0x0001FFFF
4122 #define DPORT_MPU_IA_INT_EN_M  ((DPORT_MPU_IA_INT_EN_V)<<(DPORT_MPU_IA_INT_EN_S))
4123 #define DPORT_MPU_IA_INT_EN_V  0x1FFFF
4124 #define DPORT_MPU_IA_INT_EN_S  0
4125 
4126 #define DPORT_CACHE_IA_INT_EN_REG          (DR_REG_DPORT_BASE + 0x5A0)
4127 /* DPORT_CACHE_IA_INT_EN : R/W ;bitpos:[27:0] ;default: 28'b0 ; */
4128 /*description: Interrupt enable bits for various invalid cache access reasons*/
4129 #define DPORT_CACHE_IA_INT_EN  0x0FFFFFFF
4130 #define DPORT_CACHE_IA_INT_EN_M  ((DPORT_CACHE_IA_INT_EN_V)<<(DPORT_CACHE_IA_INT_EN_S))
4131 #define DPORT_CACHE_IA_INT_EN_V  0xFFFFFFF
4132 #define DPORT_CACHE_IA_INT_EN_S  0
4133 /* Contents of DPORT_CACHE_IA_INT_EN field: */
4134 /* DPORT_CACHE_IA_INT_PRO_OPPOSITE : R/W ;bitpos:[19] ;default: 1'b0 ; */
4135 /*description: PRO CPU invalid access to APP CPU cache when cache disabled */
4136 #define DPORT_CACHE_IA_INT_PRO_OPPOSITE    BIT(19)
4137 #define DPORT_CACHE_IA_INT_PRO_OPPOSITE_M  BIT(19)
4138 #define DPORT_CACHE_IA_INT_PRO_OPPOSITE_V  (1)
4139 #define DPORT_CACHE_IA_INT_PRO_OPPOSITE_S  (19)
4140 /* DPORT_CACHE_IA_INT_PRO_DRAM1 : R/W ;bitpos:[18] ;default: 1'b0 ; */
4141 /*description: PRO CPU invalid access to DRAM1 when cache is disabled */
4142 #define DPORT_CACHE_IA_INT_PRO_DRAM1    BIT(18)
4143 #define DPORT_CACHE_IA_INT_PRO_DRAM1_M  BIT(18)
4144 #define DPORT_CACHE_IA_INT_PRO_DRAM1_V  (1)
4145 #define DPORT_CACHE_IA_INT_PRO_DRAM1_S  (18)
4146 /* DPORT_CACHE_IA_INT_PRO_IROM0 : R/W ;bitpos:[17] ;default: 1'b0 ; */
4147 /*description: PRO CPU invalid access to IROM0 when cache is disabled */
4148 #define DPORT_CACHE_IA_INT_PRO_IROM0    BIT(17)
4149 #define DPORT_CACHE_IA_INT_PRO_IROM0_M  BIT(17)
4150 #define DPORT_CACHE_IA_INT_PRO_IROM0_V  (1)
4151 #define DPORT_CACHE_IA_INT_PRO_IROM0_S  (17)
4152 /* DPORT_CACHE_IA_INT_PRO_IRAM1 : R/W ;bitpos:[16] ;default: 1'b0 ; */
4153 /*description: PRO CPU invalid access to IRAM1 when cache is disabled */
4154 #define DPORT_CACHE_IA_INT_PRO_IRAM1    BIT(16)
4155 #define DPORT_CACHE_IA_INT_PRO_IRAM1_M  BIT(16)
4156 #define DPORT_CACHE_IA_INT_PRO_IRAM1_V  (1)
4157 #define DPORT_CACHE_IA_INT_PRO_IRAM1_S  (16)
4158 /* DPORT_CACHE_IA_INT_PRO_IRAM0 : R/W ;bitpos:[15] ;default: 1'b0 ; */
4159 /*description: PRO CPU invalid access to IRAM0 when cache is disabled */
4160 #define DPORT_CACHE_IA_INT_PRO_IRAM0    BIT(15)
4161 #define DPORT_CACHE_IA_INT_PRO_IRAM0_M  BIT(15)
4162 #define DPORT_CACHE_IA_INT_PRO_IRAM0_V  (1)
4163 #define DPORT_CACHE_IA_INT_PRO_IRAM0_S  (15)
4164 /* DPORT_CACHE_IA_INT_PRO_DROM0 : R/W ;bitpos:[14] ;default: 1'b0 ; */
4165 /*description: PRO CPU invalid access to DROM0 when cache is disabled */
4166 #define DPORT_CACHE_IA_INT_PRO_DROM0    BIT(14)
4167 #define DPORT_CACHE_IA_INT_PRO_DROM0_M  BIT(14)
4168 #define DPORT_CACHE_IA_INT_PRO_DROM0_V  (1)
4169 #define DPORT_CACHE_IA_INT_PRO_DROM0_S  (14)
4170 /* DPORT_CACHE_IA_INT_APP_OPPOSITE : R/W ;bitpos:[5] ;default: 1'b0 ; */
4171 /*description: APP CPU invalid access to APP CPU cache when cache disabled */
4172 #define DPORT_CACHE_IA_INT_APP_OPPOSITE    BIT(5)
4173 #define DPORT_CACHE_IA_INT_APP_OPPOSITE_M  BIT(5)
4174 #define DPORT_CACHE_IA_INT_APP_OPPOSITE_V  (1)
4175 #define DPORT_CACHE_IA_INT_APP_OPPOSITE_S  (5)
4176 /* DPORT_CACHE_IA_INT_APP_DRAM1 : R/W ;bitpos:43] ;default: 1'b0 ; */
4177 /*description: APP CPU invalid access to DRAM1 when cache is disabled */
4178 #define DPORT_CACHE_IA_INT_APP_DRAM1    BIT(4)
4179 #define DPORT_CACHE_IA_INT_APP_DRAM1_M  BIT(4)
4180 #define DPORT_CACHE_IA_INT_APP_DRAM1_V  (1)
4181 #define DPORT_CACHE_IA_INT_APP_DRAM1_S  (4)
4182 /* DPORT_CACHE_IA_INT_APP_IROM0 : R/W ;bitpos:[3] ;default: 1'b0 ; */
4183 /*description: APP CPU invalid access to IROM0 when cache is disabled */
4184 #define DPORT_CACHE_IA_INT_APP_IROM0    BIT(3)
4185 #define DPORT_CACHE_IA_INT_APP_IROM0_M  BIT(3)
4186 #define DPORT_CACHE_IA_INT_APP_IROM0_V  (1)
4187 #define DPORT_CACHE_IA_INT_APP_IROM0_S  (3)
4188 /* DPORT_CACHE_IA_INT_APP_IRAM1 : R/W ;bitpos:[2] ;default: 1'b0 ; */
4189 /*description: APP CPU invalid access to IRAM1 when cache is disabled */
4190 #define DPORT_CACHE_IA_INT_APP_IRAM1    BIT(2)
4191 #define DPORT_CACHE_IA_INT_APP_IRAM1_M  BIT(2)
4192 #define DPORT_CACHE_IA_INT_APP_IRAM1_V  (1)
4193 #define DPORT_CACHE_IA_INT_APP_IRAM1_S  (2)
4194 /* DPORT_CACHE_IA_INT_APP_IRAM0 : R/W ;bitpos:[1] ;default: 1'b0 ; */
4195 /*description: APP CPU invalid access to IRAM0 when cache is disabled */
4196 #define DPORT_CACHE_IA_INT_APP_IRAM0    BIT(1)
4197 #define DPORT_CACHE_IA_INT_APP_IRAM0_M  BIT(1)
4198 #define DPORT_CACHE_IA_INT_APP_IRAM0_V  (1)
4199 #define DPORT_CACHE_IA_INT_APP_IRAM0_S  (1)
4200 /* DPORT_CACHE_IA_INT_APP_DROM0 : R/W ;bitpos:[0] ;default: 1'b0 ; */
4201 /*description: APP CPU invalid access to DROM0 when cache is disabled */
4202 #define DPORT_CACHE_IA_INT_APP_DROM0    BIT(0)
4203 #define DPORT_CACHE_IA_INT_APP_DROM0_M  BIT(0)
4204 #define DPORT_CACHE_IA_INT_APP_DROM0_V  (1)
4205 #define DPORT_CACHE_IA_INT_APP_DROM0_S  (0)
4206 
4207 #define DPORT_SECURE_BOOT_CTRL_REG          (DR_REG_DPORT_BASE + 0x5A4)
4208 /* DPORT_SW_BOOTLOADER_SEL : R/W ;bitpos:[0] ;default: 1'b0 ; */
4209 /*description: */
4210 #define DPORT_SW_BOOTLOADER_SEL  (BIT(0))
4211 #define DPORT_SW_BOOTLOADER_SEL_M  (BIT(0))
4212 #define DPORT_SW_BOOTLOADER_SEL_V  0x1
4213 #define DPORT_SW_BOOTLOADER_SEL_S  0
4214 
4215 #define DPORT_SPI_DMA_CHAN_SEL_REG          (DR_REG_DPORT_BASE + 0x5A8)
4216 /* DPORT_SPI3_DMA_CHAN_SEL : R/W ;bitpos:[5:4] ;default: 2'b00 ; */
4217 /*description: */
4218 #define DPORT_SPI3_DMA_CHAN_SEL  0x00000003
4219 #define DPORT_SPI3_DMA_CHAN_SEL_M  ((DPORT_SPI3_DMA_CHAN_SEL_V)<<(DPORT_SPI3_DMA_CHAN_SEL_S))
4220 #define DPORT_SPI3_DMA_CHAN_SEL_V  0x3
4221 #define DPORT_SPI3_DMA_CHAN_SEL_S  4
4222 /* DPORT_SPI2_DMA_CHAN_SEL : R/W ;bitpos:[3:2] ;default: 2'b00 ; */
4223 /*description: */
4224 #define DPORT_SPI2_DMA_CHAN_SEL  0x00000003
4225 #define DPORT_SPI2_DMA_CHAN_SEL_M  ((DPORT_SPI2_DMA_CHAN_SEL_V)<<(DPORT_SPI2_DMA_CHAN_SEL_S))
4226 #define DPORT_SPI2_DMA_CHAN_SEL_V  0x3
4227 #define DPORT_SPI2_DMA_CHAN_SEL_S  2
4228 /* DPORT_SPI1_DMA_CHAN_SEL : R/W ;bitpos:[1:0] ;default: 2'b00 ; */
4229 /*description: */
4230 #define DPORT_SPI1_DMA_CHAN_SEL  0x00000003
4231 #define DPORT_SPI1_DMA_CHAN_SEL_M  ((DPORT_SPI1_DMA_CHAN_SEL_V)<<(DPORT_SPI1_DMA_CHAN_SEL_S))
4232 #define DPORT_SPI1_DMA_CHAN_SEL_V  0x3
4233 #define DPORT_SPI1_DMA_CHAN_SEL_S  0
4234 
4235 #define DPORT_PRO_VECBASE_CTRL_REG          (DR_REG_DPORT_BASE + 0x5AC)
4236 /* DPORT_PRO_OUT_VECBASE_SEL : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
4237 /*description: */
4238 #define DPORT_PRO_OUT_VECBASE_SEL  0x00000003
4239 #define DPORT_PRO_OUT_VECBASE_SEL_M  ((DPORT_PRO_OUT_VECBASE_SEL_V)<<(DPORT_PRO_OUT_VECBASE_SEL_S))
4240 #define DPORT_PRO_OUT_VECBASE_SEL_V  0x3
4241 #define DPORT_PRO_OUT_VECBASE_SEL_S  0
4242 
4243 #define DPORT_PRO_VECBASE_SET_REG          (DR_REG_DPORT_BASE + 0x5B0)
4244 /* DPORT_PRO_OUT_VECBASE_REG : R/W ;bitpos:[21:0] ;default: 22'b0 ; */
4245 /*description: */
4246 #define DPORT_PRO_OUT_VECBASE_REG  0x003FFFFF
4247 #define DPORT_PRO_OUT_VECBASE_REG_M  ((DPORT_PRO_OUT_VECBASE_REG_V)<<(DPORT_PRO_OUT_VECBASE_REG_S))
4248 #define DPORT_PRO_OUT_VECBASE_REG_V  0x3FFFFF
4249 #define DPORT_PRO_OUT_VECBASE_REG_S  0
4250 
4251 #define DPORT_APP_VECBASE_CTRL_REG          (DR_REG_DPORT_BASE + 0x5B4)
4252 /* DPORT_APP_OUT_VECBASE_SEL : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
4253 /*description: */
4254 #define DPORT_APP_OUT_VECBASE_SEL  0x00000003
4255 #define DPORT_APP_OUT_VECBASE_SEL_M  ((DPORT_APP_OUT_VECBASE_SEL_V)<<(DPORT_APP_OUT_VECBASE_SEL_S))
4256 #define DPORT_APP_OUT_VECBASE_SEL_V  0x3
4257 #define DPORT_APP_OUT_VECBASE_SEL_S  0
4258 
4259 #define DPORT_APP_VECBASE_SET_REG          (DR_REG_DPORT_BASE + 0x5B8)
4260 /* DPORT_APP_OUT_VECBASE_REG : R/W ;bitpos:[21:0] ;default: 22'b0 ; */
4261 /*description: */
4262 #define DPORT_APP_OUT_VECBASE_REG  0x003FFFFF
4263 #define DPORT_APP_OUT_VECBASE_REG_M  ((DPORT_APP_OUT_VECBASE_REG_V)<<(DPORT_APP_OUT_VECBASE_REG_S))
4264 #define DPORT_APP_OUT_VECBASE_REG_V  0x3FFFFF
4265 #define DPORT_APP_OUT_VECBASE_REG_S  0
4266 
4267 #define DPORT_DATE_REG          (DR_REG_DPORT_BASE + 0xFFC)
4268 /* DPORT_DATE : R/W ;bitpos:[27:0] ;default: 28'h1605190 ; */
4269 /*description: */
4270 #define DPORT_DATE  0x0FFFFFFF
4271 #define DPORT_DATE_M  ((DPORT_DATE_V)<<(DPORT_DATE_S))
4272 #define DPORT_DATE_V  0xFFFFFFF
4273 #define DPORT_DATE_S  0
4274 #define DPORT_DPORT_DATE_VERSION 0x1605190
4275 
4276 /* Flash MMU table for PRO CPU */
4277 #define DPORT_PRO_FLASH_MMU_TABLE ((volatile uint32_t*) 0x3FF10000)
4278 
4279 /* Flash MMU table for APP CPU */
4280 #define DPORT_APP_FLASH_MMU_TABLE ((volatile uint32_t*) 0x3FF12000)
4281 
4282 #define DPORT_FLASH_MMU_TABLE_SIZE 0x100
4283 
4284 #define DPORT_FLASH_MMU_TABLE_INVALID_VAL 0x100
4285 
4286 #define DPORT_MMU_ADDRESS_MASK 0xff
4287 
4288 #define TRACEMEM_MUX_PROBLK0_APPBLK1    0
4289 #define TRACEMEM_MUX_BLK0_ONLY          1
4290 #define TRACEMEM_MUX_BLK1_ONLY          2
4291 #define TRACEMEM_MUX_PROBLK1_APPBLK0    3
4292 
4293 #endif /*_SOC_DPORT_REG_H_ */
4294