Searched refs:APB_SARADC_SAR_CLK_DIV (Results 1 – 6 of 6) sorted by relevance
34 REG_SET_FIELD(APB_SARADC_CTRL_REG, APB_SARADC_SAR_CLK_DIV, 1); in bootloader_random_enable()
41 …REG_SET_FIELD(APB_SARADC_CTRL_REG, APB_SARADC_SAR_CLK_DIV, 3); // SAR clock divider has to be at l… in bootloader_random_enable()
75 #define APB_SARADC_SAR_CLK_DIV 0x000000FF macro
49 #define APB_SARADC_SAR_CLK_DIV 0x000000FF macro
76 #define APB_SARADC_SAR_CLK_DIV 0x000000FF macro