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Searched refs:APB_SARADC_SAR_CLK_DIV (Results 1 – 6 of 6) sorted by relevance

/hal_espressif-3.4.0/components/bootloader_support/src/
Dbootloader_random_esp32c3.c34 REG_SET_FIELD(APB_SARADC_CTRL_REG, APB_SARADC_SAR_CLK_DIV, 1); in bootloader_random_enable()
Dbootloader_random_esp32s3.c41 …REG_SET_FIELD(APB_SARADC_CTRL_REG, APB_SARADC_SAR_CLK_DIV, 3); // SAR clock divider has to be at l… in bootloader_random_enable()
/hal_espressif-3.4.0/components/soc/esp32s2/include/soc/
Dapb_saradc_reg.h75 #define APB_SARADC_SAR_CLK_DIV 0x000000FF macro
/hal_espressif-3.4.0/components/soc/esp32c3/include/soc/
Dapb_saradc_reg.h49 #define APB_SARADC_SAR_CLK_DIV 0x000000FF macro
/hal_espressif-3.4.0/components/soc/esp32s3/include/soc/
Dapb_saradc_reg.h76 #define APB_SARADC_SAR_CLK_DIV 0x000000FF macro
/hal_espressif-3.4.0/components/soc/esp32h2/include/soc/
Dapb_saradc_reg.h49 #define APB_SARADC_SAR_CLK_DIV 0x000000FF macro